2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/acpi.h>
24 /* Deal with broken BIOS'es that neglect to enable passive release,
25 which can cause problems in combination with the 82441FX/PPro MTRRs */
26 static void __devinit quirk_passive_release(struct pci_dev *dev)
28 struct pci_dev *d = NULL;
31 /* We have to make sure a particular bit is set in the PIIX3
32 ISA bridge, so we have to go out and find it. */
33 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
34 pci_read_config_byte(d, 0x82, &dlc);
36 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
38 pci_write_config_byte(d, 0x82, dlc);
42 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
44 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
45 but VIA don't answer queries. If you happen to have good contacts at VIA
46 ask them for me please -- Alan
48 This appears to be BIOS not version dependent. So presumably there is a
50 int isa_dma_bridge_buggy; /* Exported */
52 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
54 if (!isa_dma_bridge_buggy) {
55 isa_dma_bridge_buggy=1;
56 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
60 * Its not totally clear which chipsets are the problematic ones
61 * We know 82C586 and 82C596 variants are affected.
63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
69 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
74 * Chipsets where PCI->PCI transfers vanish or hang
76 static void __devinit quirk_nopcipci(struct pci_dev *dev)
78 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
79 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
80 pci_pci_problems |= PCIPCI_FAIL;
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
84 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
87 * Triton requires workarounds to be used by the drivers
89 static void __devinit quirk_triton(struct pci_dev *dev)
91 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
92 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
93 pci_pci_problems |= PCIPCI_TRITON;
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
99 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
102 * VIA Apollo KT133 needs PCI latency patch
103 * Made according to a windows driver based patch by George E. Breese
104 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
105 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
106 * the info on which Mr Breese based his work.
108 * Updated based on further information from the site and also on
109 * information provided by VIA
111 static void __devinit quirk_vialatency(struct pci_dev *dev)
116 /* Ok we have a potential problem chipset here. Now see if we have
117 a buggy southbridge */
119 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
121 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
122 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
123 /* Check for buggy part revisions */
124 if (rev < 0x40 || rev > 0x42)
127 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
128 if (p==NULL) /* No problem parts */
130 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
131 /* Check for buggy part revisions */
132 if (rev < 0x10 || rev > 0x12)
137 * Ok we have the problem. Now set the PCI master grant to
138 * occur every master grant. The apparent bug is that under high
139 * PCI load (quite common in Linux of course) you can get data
140 * loss when the CPU is held off the bus for 3 bus master requests
141 * This happens to include the IDE controllers....
143 * VIA only apply this fix when an SB Live! is present but under
144 * both Linux and Windows this isnt enough, and we have seen
145 * corruption without SB Live! but with things like 3 UDMA IDE
146 * controllers. So we ignore that bit of the VIA recommendation..
149 pci_read_config_byte(dev, 0x76, &busarb);
150 /* Set bit 4 and bi 5 of byte 76 to 0x01
151 "Master priority rotation on every PCI master grant */
154 pci_write_config_byte(dev, 0x76, busarb);
155 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
161 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
164 * VIA Apollo VP3 needs ETBF on BT848/878
166 static void __devinit quirk_viaetbf(struct pci_dev *dev)
168 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
169 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
170 pci_pci_problems |= PCIPCI_VIAETBF;
173 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
175 static void __devinit quirk_vsfx(struct pci_dev *dev)
177 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
178 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
179 pci_pci_problems |= PCIPCI_VSFX;
182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
185 * Ali Magik requires workarounds to be used by the drivers
186 * that DMA to AGP space. Latency must be set to 0xA and triton
187 * workaround applied too
188 * [Info kindly provided by ALi]
190 static void __init quirk_alimagik(struct pci_dev *dev)
192 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
193 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
194 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
198 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
201 * Natoma has some interesting boundary conditions with Zoran stuff
204 static void __devinit quirk_natoma(struct pci_dev *dev)
206 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
207 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
208 pci_pci_problems |= PCIPCI_NATOMA;
211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
219 * This chip can cause PCI parity errors if config register 0xA0 is read
220 * while DMAs are occurring.
222 static void __devinit quirk_citrine(struct pci_dev *dev)
224 dev->cfg_size = 0xA0;
226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
229 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
230 * If it's needed, re-allocate the region.
232 static void __devinit quirk_s3_64M(struct pci_dev *dev)
234 struct resource *r = &dev->resource[0];
236 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
242 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
244 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
248 struct resource *res = dev->resource + nr;
250 res->name = pci_name(dev);
252 res->end = region + size - 1;
253 res->flags = IORESOURCE_IO;
254 pci_claim_resource(dev, nr);
259 * ATI Northbridge setups MCE the processor if you even
260 * read somewhere between 0x3b0->0x3bb or read 0x3d3
262 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
264 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
265 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
266 request_region(0x3b0, 0x0C, "RadeonIGP");
267 request_region(0x3d3, 0x01, "RadeonIGP");
269 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
272 * Let's make the southbridge information explicit instead
273 * of having to worry about people probing the ACPI areas,
274 * for example.. (Yes, it happens, and if you read the wrong
275 * ACPI register it will put the machine to sleep with no
276 * way of waking it up again. Bummer).
278 * ALI M7101: Two IO regions pointed to by words at
279 * 0xE0 (64 bytes of ACPI registers)
280 * 0xE2 (32 bytes of SMB registers)
282 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
286 pci_read_config_word(dev, 0xE0, ®ion);
287 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
288 pci_read_config_word(dev, 0xE2, ®ion);
289 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
294 * PIIX4 ACPI: Two IO regions pointed to by longwords at
295 * 0x40 (64 bytes of ACPI registers)
296 * 0x90 (32 bytes of SMB registers)
298 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
302 pci_read_config_dword(dev, 0x40, ®ion);
303 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
304 pci_read_config_dword(dev, 0x90, ®ion);
305 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
310 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
311 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
312 * 0x58 (64 bytes of GPIO I/O space)
314 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
318 pci_read_config_dword(dev, 0x40, ®ion);
319 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
321 pci_read_config_dword(dev, 0x58, ®ion);
322 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
336 * VIA ACPI: One IO region pointed to by longword at
337 * 0x48 or 0x20 (256 bytes of ACPI registers)
339 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
344 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
346 pci_read_config_dword(dev, 0x48, ®ion);
347 region &= PCI_BASE_ADDRESS_IO_MASK;
348 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
351 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
354 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
355 * 0x48 (256 bytes of ACPI registers)
356 * 0x70 (128 bytes of hardware monitoring register)
357 * 0x90 (16 bytes of SMB registers)
359 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
364 quirk_vt82c586_acpi(dev);
366 pci_read_config_word(dev, 0x70, &hm);
367 hm &= PCI_BASE_ADDRESS_IO_MASK;
368 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
370 pci_read_config_dword(dev, 0x90, &smb);
371 smb &= PCI_BASE_ADDRESS_IO_MASK;
372 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
374 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
377 #ifdef CONFIG_X86_IO_APIC
379 #include <asm/io_apic.h>
382 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
383 * devices to the external APIC.
385 * TODO: When we have device-specific interrupt routers,
386 * this code will go away from quirks.
388 static void __devinit quirk_via_ioapic(struct pci_dev *dev)
393 tmp = 0; /* nothing routed to external APIC */
395 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
397 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
398 tmp == 0 ? "Disa" : "Ena");
400 /* Offset 0x58: External APIC IRQ output control */
401 pci_write_config_byte (dev, 0x58, tmp);
403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
406 * The AMD io apic can hang the box when an apic irq is masked.
407 * We check all revs >= B0 (yet not in the pre production!) as the bug
408 * is currently marked NoFix
410 * We have multiple reports of hangs with this chipset that went away with
411 * noapic specified. For the moment we assume its the errata. We may be wrong
412 * of course. However the advice is demonstrably good even if so..
414 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
418 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
420 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
421 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
426 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
428 if (dev->devfn == 0 && dev->bus->number == 0)
431 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
435 #define AMD8131_revA0 0x01
436 #define AMD8131_revB0 0x11
437 #define AMD8131_MISC 0x40
438 #define AMD8131_NIOAMODE_BIT 0
439 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
441 unsigned char revid, tmp;
444 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
449 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
450 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
451 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
452 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
453 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
454 pci_write_config_byte( dev, AMD8131_MISC, tmp);
457 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
459 #endif /* CONFIG_X86_IO_APIC */
463 * FIXME: it is questionable that quirk_via_acpi
464 * is needed. It shows up as an ISA bridge, and does not
465 * support the PCI_INTERRUPT_LINE register at all. Therefore
466 * it seems like setting the pci_dev's 'irq' to the
467 * value of the ACPI SCI interrupt is only done for convenience.
470 static void __devinit quirk_via_acpi(struct pci_dev *d)
473 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
476 pci_read_config_byte(d, 0x42, &irq);
478 if (irq && (irq != 2))
481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
485 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
486 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
487 * when written, it makes an internal connection to the PIC.
488 * For these devices, this register is defined to be 4 bits wide.
489 * Normally this is fine. However for IO-APIC motherboards, or
490 * non-x86 architectures (yes Via exists on PPC among other places),
491 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
492 * interrupts delivered properly.
494 static void quirk_via_irq(struct pci_dev *dev)
498 new_irq = dev->irq & 0xf;
499 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
500 if (new_irq != irq) {
501 printk(KERN_INFO "PCI: Via IRQ fixup for %s, from %d to %d\n",
502 pci_name(dev), irq, new_irq);
503 udelay(15); /* unknown if delay really needed */
504 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
507 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_irq);
510 * PIIX3 USB: We have to disable USB interrupts that are
511 * hardwired to PIRQD# and may be shared with an
514 * Legacy Support Register (LEGSUP):
515 * bit13: USB PIRQ Enable (USBPIRQDEN),
516 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
518 * We mask out all r/wc bits, too.
520 static void __devinit quirk_piix3_usb(struct pci_dev *dev)
524 pci_read_config_word(dev, 0xc0, &legsup);
526 pci_write_config_word(dev, 0xc0, legsup);
528 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
529 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
532 * VIA VT82C598 has its device ID settable and many BIOSes
533 * set it to the ID of VT82C597 for backward compatibility.
534 * We need to switch it off to be able to recognize the real
537 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
539 pci_write_config_byte(dev, 0xfc, 0);
540 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
542 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
545 * CardBus controllers have a legacy base address that enables them
546 * to respond as i82365 pcmcia controllers. We don't want them to
547 * do this even if the Linux CardBus driver is not loaded, because
548 * the Linux i82365 driver does not (and should not) handle CardBus.
550 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
552 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
554 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
556 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
559 * Following the PCI ordering rules is optional on the AMD762. I'm not
560 * sure what the designers were smoking but let's not inhale...
562 * To be fair to AMD, it follows the spec by default, its BIOS people
565 static void __devinit quirk_amd_ordering(struct pci_dev *dev)
568 pci_read_config_dword(dev, 0x4C, &pcic);
571 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
572 pci_write_config_dword(dev, 0x4C, pcic);
573 pci_read_config_dword(dev, 0x84, &pcic);
574 pcic |= (1<<23); /* Required in this mode */
575 pci_write_config_dword(dev, 0x84, pcic);
578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
581 * DreamWorks provided workaround for Dunord I-3000 problem
583 * This card decodes and responds to addresses not apparently
584 * assigned to it. We force a larger allocation to ensure that
585 * nothing gets put too close to it.
587 static void __devinit quirk_dunord ( struct pci_dev * dev )
589 struct resource *r = &dev->resource [1];
593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
596 * i82380FB mobile docking controller: its PCI-to-PCI bridge
597 * is subtractive decoding (transparent), and does indicate this
598 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
601 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
603 dev->transparent = 1;
605 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
606 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
609 * Common misconfiguration of the MediaGX/Geode PCI master that will
610 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
611 * datasheets found at http://www.national.com/ds/GX for info on what
612 * these bits do. <christer@weinigel.se>
614 static void __init quirk_mediagx_master(struct pci_dev *dev)
617 pci_read_config_byte(dev, 0x41, ®);
620 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
621 pci_write_config_byte(dev, 0x41, reg);
624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
627 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
628 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
629 * secondary channels respectively). If the device reports Compatible mode
630 * but does use BAR0-3 for address decoding, we assume that firmware has
631 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
632 * Exceptions (if they exist) must be handled in chip/architecture specific
635 * Note: for non x86 people. You may need an arch specific quirk to handle
636 * moving IDE devices to native mode as well. Some plug in card devices power
637 * up in compatible mode and assume the BIOS will adjust them.
639 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
640 * we do now ? We don't want is pci_enable_device to come along
641 * and assign new resources. Both approaches work for that.
643 static void __devinit quirk_ide_bases(struct pci_dev *dev)
645 struct resource *res;
646 int first_bar = 2, last_bar = 0;
648 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
651 res = &dev->resource[0];
653 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
654 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
655 res[0].start = res[0].end = res[0].flags = 0;
656 res[1].start = res[1].end = res[1].flags = 0;
661 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
662 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
663 res[2].start = res[2].end = res[2].flags = 0;
664 res[3].start = res[3].end = res[3].flags = 0;
671 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
672 first_bar, last_bar, pci_name(dev));
674 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
677 * Ensure C0 rev restreaming is off. This is normally done by
678 * the BIOS but in the odd case it is not the results are corruption
679 * hence the presence of a Linux check
681 static void __init quirk_disable_pxb(struct pci_dev *pdev)
686 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
687 if (rev != 0x04) /* Only C0 requires this */
689 pci_read_config_word(pdev, 0x40, &config);
690 if (config & (1<<6)) {
692 pci_write_config_word(pdev, 0x40, config);
693 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
696 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
700 * Serverworks CSB5 IDE does not fully support native mode
702 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
705 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
709 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
710 /* need to re-assign BARs for compat mode */
711 quirk_ide_bases(pdev);
714 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
717 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
719 static void __init quirk_ide_samemode(struct pci_dev *pdev)
723 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
725 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
726 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
729 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
730 /* need to re-assign BARs for compat mode */
731 quirk_ide_bases(pdev);
734 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
736 /* This was originally an Alpha specific thing, but it really fits here.
737 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
739 static void __init quirk_eisa_bridge(struct pci_dev *dev)
741 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
743 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
746 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
747 * is not activated. The myth is that Asus said that they do not want the
748 * users to be irritated by just another PCI Device in the Win98 device
749 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
750 * package 2.7.0 for details)
752 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
753 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
754 * becomes necessary to do this tweak in two steps -- I've chosen the Host
757 static int __initdata asus_hides_smbus = 0;
759 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
761 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
762 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
763 switch(dev->subsystem_device) {
764 case 0x8070: /* P4B */
765 case 0x8088: /* P4B533 */
766 case 0x1626: /* L3C notebook */
767 asus_hides_smbus = 1;
769 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
770 switch(dev->subsystem_device) {
771 case 0x80b1: /* P4GE-V */
772 case 0x80b2: /* P4PE */
773 case 0x8093: /* P4B533-V */
774 asus_hides_smbus = 1;
776 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
777 switch(dev->subsystem_device) {
778 case 0x8030: /* P4T533 */
779 asus_hides_smbus = 1;
781 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
782 switch (dev->subsystem_device) {
783 case 0x8070: /* P4G8X Deluxe */
784 asus_hides_smbus = 1;
786 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
787 switch (dev->subsystem_device) {
788 case 0x1751: /* M2N notebook */
789 case 0x1821: /* M5N notebook */
790 asus_hides_smbus = 1;
792 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
793 switch (dev->subsystem_device) {
794 case 0x184b: /* W1N notebook */
795 case 0x186a: /* M6Ne notebook */
796 asus_hides_smbus = 1;
798 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
799 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
800 switch(dev->subsystem_device) {
801 case 0x088C: /* HP Compaq nc8000 */
802 case 0x0890: /* HP Compaq nc6000 */
803 asus_hides_smbus = 1;
805 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
806 switch (dev->subsystem_device) {
807 case 0x12bc: /* HP D330L */
808 asus_hides_smbus = 1;
810 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
811 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
812 switch(dev->subsystem_device) {
813 case 0x0001: /* Toshiba Satellite A40 */
814 asus_hides_smbus = 1;
816 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
817 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
818 switch(dev->subsystem_device) {
819 case 0xC00C: /* Samsung P35 notebook */
820 asus_hides_smbus = 1;
824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
832 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
836 if (likely(!asus_hides_smbus))
839 pci_read_config_word(dev, 0xF2, &val);
841 pci_write_config_word(dev, 0xF2, val & (~0x8));
842 pci_read_config_word(dev, 0xF2, &val);
844 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
846 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
849 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
856 * SiS 96x south bridge: BIOS typically hides SMBus device...
858 static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
861 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
862 pci_read_config_byte(dev, 0x77, &val);
863 pci_write_config_byte(dev, 0x77, val & ~0x10);
864 pci_read_config_byte(dev, 0x77, &val);
868 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
869 #define UHCI_USBCMD 0 /* command register */
870 #define UHCI_USBSTS 2 /* status register */
871 #define UHCI_USBINTR 4 /* interrupt register */
872 #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
873 #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
874 #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
875 #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
876 #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
878 #define OHCI_CONTROL 0x04
879 #define OHCI_CMDSTATUS 0x08
880 #define OHCI_INTRSTATUS 0x0c
881 #define OHCI_INTRENABLE 0x10
882 #define OHCI_INTRDISABLE 0x14
883 #define OHCI_OCR (1 << 3) /* ownership change request */
884 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
885 #define OHCI_INTR_OC (1 << 30) /* ownership change */
887 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
888 #define EHCI_USBCMD 0 /* command register */
889 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
890 #define EHCI_USBSTS 4 /* status register */
891 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
892 #define EHCI_USBINTR 8 /* interrupt register */
893 #define EHCI_USBLEGSUP 0 /* legacy support register */
894 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
895 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
896 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
897 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
899 int usb_early_handoff __devinitdata = 0;
900 static int __init usb_handoff_early(char *str)
902 usb_early_handoff = 1;
905 __setup("usb-handoff", usb_handoff_early);
907 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
909 unsigned long base = 0;
910 int wait_time, delta;
914 for (i = 0; i < PCI_ROM_RESOURCE; i++)
915 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
916 base = pci_resource_start(pdev, i);
926 sts = inw(base + UHCI_USBSTS);
927 val = inw(base + UHCI_USBCMD);
928 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
929 outw(val, base + UHCI_USBCMD);
932 * wait while it stops if it was running
934 if ((sts & UHCI_USBSTS_HALTED) == 0)
940 outw(0x1f, base + UHCI_USBSTS);
943 val = inw(base + UHCI_USBSTS);
944 if (val & UHCI_USBSTS_HALTED)
946 } while (wait_time > 0);
950 * disable interrupts & legacy support
952 outw(0, base + UHCI_USBINTR);
953 outw(0x1f, base + UHCI_USBSTS);
954 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
956 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
960 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
965 base = ioremap_nocache(pci_resource_start(pdev, 0),
966 pci_resource_len(pdev, 0));
967 if (base == NULL) return;
969 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
970 wait_time = 500; /* 0.5 seconds */
971 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
972 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
973 while (wait_time > 0 &&
974 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
983 writel(~(u32)0, base + OHCI_INTRDISABLE);
984 writel(~(u32)0, base + OHCI_INTRSTATUS);
989 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
991 int wait_time, delta;
992 void __iomem *base, *op_reg_base;
993 u32 hcc_params, val, temp;
996 base = ioremap_nocache(pci_resource_start(pdev, 0),
997 pci_resource_len(pdev, 0));
998 if (base == NULL) return;
1000 cap_length = readb(base);
1001 op_reg_base = base + cap_length;
1002 hcc_params = readl(base + EHCI_HCC_PARAMS);
1003 hcc_params = (hcc_params >> 8) & 0xff;
1005 pci_read_config_dword(pdev,
1006 hcc_params + EHCI_USBLEGSUP,
1008 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
1010 * Ok, BIOS is in smm mode, try to hand off...
1012 pci_read_config_dword(pdev,
1013 hcc_params + EHCI_USBLEGCTLSTS,
1015 pci_write_config_dword(pdev,
1016 hcc_params + EHCI_USBLEGCTLSTS,
1017 temp | EHCI_USBLEGCTLSTS_SOOE);
1018 val |= EHCI_USBLEGSUP_OS;
1019 pci_write_config_dword(pdev,
1020 hcc_params + EHCI_USBLEGSUP,
1027 pci_read_config_dword(pdev,
1028 hcc_params + EHCI_USBLEGSUP,
1030 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
1033 * well, possibly buggy BIOS...
1035 printk(KERN_WARNING "EHCI early BIOS handoff "
1036 "failed (BIOS bug ?)\n");
1037 pci_write_config_dword(pdev,
1038 hcc_params + EHCI_USBLEGSUP,
1040 pci_write_config_dword(pdev,
1041 hcc_params + EHCI_USBLEGCTLSTS,
1048 * halt EHCI & disable its interrupts in any case
1050 val = readl(op_reg_base + EHCI_USBSTS);
1051 if ((val & EHCI_USBSTS_HALTED) == 0) {
1052 val = readl(op_reg_base + EHCI_USBCMD);
1053 val &= ~EHCI_USBCMD_RUN;
1054 writel(val, op_reg_base + EHCI_USBCMD);
1059 writel(0x3f, op_reg_base + EHCI_USBSTS);
1062 val = readl(op_reg_base + EHCI_USBSTS);
1063 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
1066 } while (wait_time > 0);
1068 writel(0, op_reg_base + EHCI_USBINTR);
1069 writel(0x3f, op_reg_base + EHCI_USBSTS);
1078 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
1080 if (!usb_early_handoff)
1083 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
1084 quirk_usb_handoff_uhci(pdev);
1085 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
1086 quirk_usb_handoff_ohci(pdev);
1087 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
1088 quirk_usb_disable_ehci(pdev);
1093 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1096 * ... This is further complicated by the fact that some SiS96x south
1097 * bridges pretend to be 85C503/5513 instead. In that case see if we
1098 * spotted a compatible north bridge to make sure.
1099 * (pci_find_device doesn't work yet)
1101 * We can also enable the sis96x bit in the discovery register..
1103 static int __devinitdata sis_96x_compatible = 0;
1105 #define SIS_DETECT_REGISTER 0x40
1107 static void __init quirk_sis_503(struct pci_dev *dev)
1112 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1113 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1114 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1115 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1116 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1120 /* Make people aware that we changed the config.. */
1121 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1124 * Ok, it now shows up as a 96x.. The 96x quirks are after
1125 * the 503 quirk in the quirk table, so they'll automatically
1126 * run and enable things like the SMBus device
1128 dev->device = devid;
1131 static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1133 sis_96x_compatible = 1;
1135 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1142 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1144 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1149 #ifdef CONFIG_X86_IO_APIC
1150 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1154 if ((pdev->class >> 8) != 0xff00)
1157 /* the first BAR is the location of the IO APIC...we must
1158 * not touch this (and it's already covered by the fixmap), so
1159 * forcibly insert it into the resource tree */
1160 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1161 insert_resource(&iomem_resource, &pdev->resource[0]);
1163 /* The next five BARs all seem to be rubbish, so just clean
1165 for (i=1; i < 6; i++) {
1166 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1170 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1173 #ifdef CONFIG_SCSI_SATA
1174 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1180 * Narrow down to Intel SATA PCI devices.
1182 switch (pdev->device) {
1183 /* PCI ids taken from drivers/scsi/ata_piix.c */
1193 case 0x2680: /* ESB2 */
1201 /* we do not handle this PCI device */
1206 * Read combined mode register.
1208 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1211 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1212 if (tmp == 0x4) /* bits 10x */
1213 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1214 else if (tmp == 0x6) /* bits 11x */
1215 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1217 return; /* not in combined mode */
1219 WARN_ON((ich != 6) && (ich != 7));
1220 tmp &= 0x3; /* interesting bits 1:0 */
1222 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1223 else if (tmp & (1 << 1))
1224 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1226 return; /* not in combined mode */
1230 * Read programming interface register.
1231 * (Tells us if it's legacy or native mode)
1233 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1235 /* if SATA port is in native mode, we're ok. */
1239 /* SATA port is in legacy mode. Reserve port so that
1240 * IDE driver does not attempt to use it. If request_region
1241 * fails, it will be obvious at boot time, so we don't bother
1242 * checking return values.
1244 if (comb == (1 << 0))
1245 request_region(0x1f0, 8, "libata"); /* port 0 */
1247 request_region(0x170, 8, "libata"); /* port 1 */
1249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1250 #endif /* CONFIG_SCSI_SATA */
1255 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1259 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1263 static void __devinit quirk_netmos(struct pci_dev *dev)
1265 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1266 unsigned int num_serial = dev->subsystem_device & 0xf;
1269 * These Netmos parts are multiport serial devices with optional
1270 * parallel ports. Even when parallel ports are present, they
1271 * are identified as class SERIAL, which means the serial driver
1272 * will claim them. To prevent this, mark them as class OTHER.
1273 * These combo devices should be claimed by parport_serial.
1275 * The subdevice ID is of the form 0x00PS, where <P> is the number
1276 * of parallel ports and <S> is the number of serial ports.
1278 switch (dev->device) {
1279 case PCI_DEVICE_ID_NETMOS_9735:
1280 case PCI_DEVICE_ID_NETMOS_9745:
1281 case PCI_DEVICE_ID_NETMOS_9835:
1282 case PCI_DEVICE_ID_NETMOS_9845:
1283 case PCI_DEVICE_ID_NETMOS_9855:
1284 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1286 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1287 "%u serial); changing class SERIAL to OTHER "
1288 "(use parport_serial)\n",
1289 dev->device, num_parallel, num_serial);
1290 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1291 (dev->class & 0xff);
1295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1297 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1300 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1301 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1302 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1309 extern struct pci_fixup __start_pci_fixups_early[];
1310 extern struct pci_fixup __end_pci_fixups_early[];
1311 extern struct pci_fixup __start_pci_fixups_header[];
1312 extern struct pci_fixup __end_pci_fixups_header[];
1313 extern struct pci_fixup __start_pci_fixups_final[];
1314 extern struct pci_fixup __end_pci_fixups_final[];
1315 extern struct pci_fixup __start_pci_fixups_enable[];
1316 extern struct pci_fixup __end_pci_fixups_enable[];
1319 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1321 struct pci_fixup *start, *end;
1324 case pci_fixup_early:
1325 start = __start_pci_fixups_early;
1326 end = __end_pci_fixups_early;
1329 case pci_fixup_header:
1330 start = __start_pci_fixups_header;
1331 end = __end_pci_fixups_header;
1334 case pci_fixup_final:
1335 start = __start_pci_fixups_final;
1336 end = __end_pci_fixups_final;
1339 case pci_fixup_enable:
1340 start = __start_pci_fixups_enable;
1341 end = __end_pci_fixups_enable;
1345 /* stupid compiler warning, you would think with an enum... */
1348 pci_do_fixups(dev, start, end);
1351 EXPORT_SYMBOL(pcie_mch_quirk);
1352 #ifdef CONFIG_HOTPLUG
1353 EXPORT_SYMBOL(pci_fixup_device);