2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
10 * The bridge optimization stuff has been removed. If you really
11 * have a silly BIOS which is unable to set your host bridge right,
12 * use the PowerTweak utility (see http://powertweak.sourceforge.net).
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/init.h>
20 #include <linux/delay.h>
23 /* Deal with broken BIOS'es that neglect to enable passive release,
24 which can cause problems in combination with the 82441FX/PPro MTRRs */
25 static void __devinit quirk_passive_release(struct pci_dev *dev)
27 struct pci_dev *d = NULL;
30 /* We have to make sure a particular bit is set in the PIIX3
31 ISA bridge, so we have to go out and find it. */
32 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
33 pci_read_config_byte(d, 0x82, &dlc);
35 printk(KERN_ERR "PCI: PIIX3: Enabling Passive Release on %s\n", pci_name(d));
37 pci_write_config_byte(d, 0x82, dlc);
41 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release );
43 /* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
44 but VIA don't answer queries. If you happen to have good contacts at VIA
45 ask them for me please -- Alan
47 This appears to be BIOS not version dependent. So presumably there is a
49 int isa_dma_bridge_buggy; /* Exported */
51 static void __devinit quirk_isa_dma_hangs(struct pci_dev *dev)
53 if (!isa_dma_bridge_buggy) {
54 isa_dma_bridge_buggy=1;
55 printk(KERN_INFO "Activating ISA DMA hang workarounds.\n");
59 * Its not totally clear which chipsets are the problematic ones
60 * We know 82C586 and 82C596 variants are affected.
62 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs );
63 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs );
64 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs );
65 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs );
66 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs );
67 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs );
68 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs );
73 * Chipsets where PCI->PCI transfers vanish or hang
75 static void __devinit quirk_nopcipci(struct pci_dev *dev)
77 if ((pci_pci_problems & PCIPCI_FAIL)==0) {
78 printk(KERN_INFO "Disabling direct PCI/PCI transfers.\n");
79 pci_pci_problems |= PCIPCI_FAIL;
82 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci );
83 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci );
86 * Triton requires workarounds to be used by the drivers
88 static void __devinit quirk_triton(struct pci_dev *dev)
90 if ((pci_pci_problems&PCIPCI_TRITON)==0) {
91 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
92 pci_pci_problems |= PCIPCI_TRITON;
95 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton );
96 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton );
97 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton );
98 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton );
101 * VIA Apollo KT133 needs PCI latency patch
102 * Made according to a windows driver based patch by George E. Breese
103 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
104 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
105 * the info on which Mr Breese based his work.
107 * Updated based on further information from the site and also on
108 * information provided by VIA
110 static void __devinit quirk_vialatency(struct pci_dev *dev)
115 /* Ok we have a potential problem chipset here. Now see if we have
116 a buggy southbridge */
118 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
120 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
121 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
122 /* Check for buggy part revisions */
123 if (rev < 0x40 || rev > 0x42)
126 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
127 if (p==NULL) /* No problem parts */
129 pci_read_config_byte(p, PCI_CLASS_REVISION, &rev);
130 /* Check for buggy part revisions */
131 if (rev < 0x10 || rev > 0x12)
136 * Ok we have the problem. Now set the PCI master grant to
137 * occur every master grant. The apparent bug is that under high
138 * PCI load (quite common in Linux of course) you can get data
139 * loss when the CPU is held off the bus for 3 bus master requests
140 * This happens to include the IDE controllers....
142 * VIA only apply this fix when an SB Live! is present but under
143 * both Linux and Windows this isnt enough, and we have seen
144 * corruption without SB Live! but with things like 3 UDMA IDE
145 * controllers. So we ignore that bit of the VIA recommendation..
148 pci_read_config_byte(dev, 0x76, &busarb);
149 /* Set bit 4 and bi 5 of byte 76 to 0x01
150 "Master priority rotation on every PCI master grant */
153 pci_write_config_byte(dev, 0x76, busarb);
154 printk(KERN_INFO "Applying VIA southbridge workaround.\n");
158 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency );
159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency );
160 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency );
163 * VIA Apollo VP3 needs ETBF on BT848/878
165 static void __devinit quirk_viaetbf(struct pci_dev *dev)
167 if ((pci_pci_problems&PCIPCI_VIAETBF)==0) {
168 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
169 pci_pci_problems |= PCIPCI_VIAETBF;
172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf );
174 static void __devinit quirk_vsfx(struct pci_dev *dev)
176 if ((pci_pci_problems&PCIPCI_VSFX)==0) {
177 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
178 pci_pci_problems |= PCIPCI_VSFX;
181 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx );
184 * Ali Magik requires workarounds to be used by the drivers
185 * that DMA to AGP space. Latency must be set to 0xA and triton
186 * workaround applied too
187 * [Info kindly provided by ALi]
189 static void __init quirk_alimagik(struct pci_dev *dev)
191 if ((pci_pci_problems&PCIPCI_ALIMAGIK)==0) {
192 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
193 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
196 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik );
197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik );
200 * Natoma has some interesting boundary conditions with Zoran stuff
203 static void __devinit quirk_natoma(struct pci_dev *dev)
205 if ((pci_pci_problems&PCIPCI_NATOMA)==0) {
206 printk(KERN_INFO "Limiting direct PCI/PCI transfers.\n");
207 pci_pci_problems |= PCIPCI_NATOMA;
210 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma );
211 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma );
212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma );
213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma );
214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma );
215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma );
218 * This chip can cause PCI parity errors if config register 0xA0 is read
219 * while DMAs are occurring.
221 static void __devinit quirk_citrine(struct pci_dev *dev)
223 dev->cfg_size = 0xA0;
225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine );
228 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
229 * If it's needed, re-allocate the region.
231 static void __devinit quirk_s3_64M(struct pci_dev *dev)
233 struct resource *r = &dev->resource[0];
235 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M );
241 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M );
243 static void __devinit quirk_io_region(struct pci_dev *dev, unsigned region, unsigned size, int nr)
247 struct resource *res = dev->resource + nr;
249 res->name = pci_name(dev);
251 res->end = region + size - 1;
252 res->flags = IORESOURCE_IO;
253 pci_claim_resource(dev, nr);
258 * ATI Northbridge setups MCE the processor if you even
259 * read somewhere between 0x3b0->0x3bb or read 0x3d3
261 static void __devinit quirk_ati_exploding_mce(struct pci_dev *dev)
263 printk(KERN_INFO "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb.\n");
264 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
265 request_region(0x3b0, 0x0C, "RadeonIGP");
266 request_region(0x3d3, 0x01, "RadeonIGP");
268 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce );
271 * Let's make the southbridge information explicit instead
272 * of having to worry about people probing the ACPI areas,
273 * for example.. (Yes, it happens, and if you read the wrong
274 * ACPI register it will put the machine to sleep with no
275 * way of waking it up again. Bummer).
277 * ALI M7101: Two IO regions pointed to by words at
278 * 0xE0 (64 bytes of ACPI registers)
279 * 0xE2 (32 bytes of SMB registers)
281 static void __devinit quirk_ali7101_acpi(struct pci_dev *dev)
285 pci_read_config_word(dev, 0xE0, ®ion);
286 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
287 pci_read_config_word(dev, 0xE2, ®ion);
288 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi );
293 * PIIX4 ACPI: Two IO regions pointed to by longwords at
294 * 0x40 (64 bytes of ACPI registers)
295 * 0x90 (32 bytes of SMB registers)
297 static void __devinit quirk_piix4_acpi(struct pci_dev *dev)
301 pci_read_config_dword(dev, 0x40, ®ion);
302 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES);
303 pci_read_config_dword(dev, 0x90, ®ion);
304 quirk_io_region(dev, region, 32, PCI_BRIDGE_RESOURCES+1);
306 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi );
309 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
310 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
311 * 0x58 (64 bytes of GPIO I/O space)
313 static void __devinit quirk_ich4_lpc_acpi(struct pci_dev *dev)
317 pci_read_config_dword(dev, 0x40, ®ion);
318 quirk_io_region(dev, region, 128, PCI_BRIDGE_RESOURCES);
320 pci_read_config_dword(dev, 0x58, ®ion);
321 quirk_io_region(dev, region, 64, PCI_BRIDGE_RESOURCES+1);
323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi );
324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi );
325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi );
326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi );
327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi );
328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi );
329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi );
330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi );
331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi );
332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi );
335 * VIA ACPI: One IO region pointed to by longword at
336 * 0x48 or 0x20 (256 bytes of ACPI registers)
338 static void __devinit quirk_vt82c586_acpi(struct pci_dev *dev)
343 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rev);
345 pci_read_config_dword(dev, 0x48, ®ion);
346 region &= PCI_BASE_ADDRESS_IO_MASK;
347 quirk_io_region(dev, region, 256, PCI_BRIDGE_RESOURCES);
350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi );
353 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
354 * 0x48 (256 bytes of ACPI registers)
355 * 0x70 (128 bytes of hardware monitoring register)
356 * 0x90 (16 bytes of SMB registers)
358 static void __devinit quirk_vt82c686_acpi(struct pci_dev *dev)
363 quirk_vt82c586_acpi(dev);
365 pci_read_config_word(dev, 0x70, &hm);
366 hm &= PCI_BASE_ADDRESS_IO_MASK;
367 quirk_io_region(dev, hm, 128, PCI_BRIDGE_RESOURCES + 1);
369 pci_read_config_dword(dev, 0x90, &smb);
370 smb &= PCI_BASE_ADDRESS_IO_MASK;
371 quirk_io_region(dev, smb, 16, PCI_BRIDGE_RESOURCES + 2);
373 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi );
376 #ifdef CONFIG_X86_IO_APIC
378 #include <asm/io_apic.h>
381 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
382 * devices to the external APIC.
384 * TODO: When we have device-specific interrupt routers,
385 * this code will go away from quirks.
387 static void __devinit quirk_via_ioapic(struct pci_dev *dev)
392 tmp = 0; /* nothing routed to external APIC */
394 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
396 printk(KERN_INFO "PCI: %sbling Via external APIC routing\n",
397 tmp == 0 ? "Disa" : "Ena");
399 /* Offset 0x58: External APIC IRQ output control */
400 pci_write_config_byte (dev, 0x58, tmp);
402 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic );
405 * The AMD io apic can hang the box when an apic irq is masked.
406 * We check all revs >= B0 (yet not in the pre production!) as the bug
407 * is currently marked NoFix
409 * We have multiple reports of hangs with this chipset that went away with
410 * noapic specified. For the moment we assume its the errata. We may be wrong
411 * of course. However the advice is demonstrably good even if so..
413 static void __devinit quirk_amd_ioapic(struct pci_dev *dev)
417 pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
419 printk(KERN_WARNING "I/O APIC: AMD Errata #22 may be present. In the event of instability try\n");
420 printk(KERN_WARNING " : booting with the \"noapic\" option.\n");
423 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic );
425 static void __init quirk_ioapic_rmw(struct pci_dev *dev)
427 if (dev->devfn == 0 && dev->bus->number == 0)
430 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_ANY_ID, quirk_ioapic_rmw );
434 #define AMD8131_revA0 0x01
435 #define AMD8131_revB0 0x11
436 #define AMD8131_MISC 0x40
437 #define AMD8131_NIOAMODE_BIT 0
438 static void __init quirk_amd_8131_ioapic(struct pci_dev *dev)
440 unsigned char revid, tmp;
443 printk(KERN_WARNING "PCI: MSI quirk detected. pci_msi_quirk set.\n");
448 pci_read_config_byte(dev, PCI_REVISION_ID, &revid);
449 if (revid == AMD8131_revA0 || revid == AMD8131_revB0) {
450 printk(KERN_INFO "Fixing up AMD8131 IOAPIC mode\n");
451 pci_read_config_byte( dev, AMD8131_MISC, &tmp);
452 tmp &= ~(1 << AMD8131_NIOAMODE_BIT);
453 pci_write_config_byte( dev, AMD8131_MISC, tmp);
456 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_APIC, quirk_amd_8131_ioapic );
458 #endif /* CONFIG_X86_IO_APIC */
462 * Via 686A/B: The PCI_INTERRUPT_LINE register for the on-chip
463 * devices, USB0/1, AC97, MC97, and ACPI, has an unusual feature:
464 * when written, it makes an internal connection to the PIC.
465 * For these devices, this register is defined to be 4 bits wide.
466 * Normally this is fine. However for IO-APIC motherboards, or
467 * non-x86 architectures (yes Via exists on PPC among other places),
468 * we must mask the PCI_INTERRUPT_LINE value versus 0xf to get
469 * interrupts delivered properly.
471 * TODO: When we have device-specific interrupt routers,
472 * quirk_via_irqpic will go away from quirks.
476 * FIXME: it is questionable that quirk_via_acpi
477 * is needed. It shows up as an ISA bridge, and does not
478 * support the PCI_INTERRUPT_LINE register at all. Therefore
479 * it seems like setting the pci_dev's 'irq' to the
480 * value of the ACPI SCI interrupt is only done for convenience.
483 static void __devinit quirk_via_acpi(struct pci_dev *d)
486 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
489 pci_read_config_byte(d, 0x42, &irq);
491 if (irq && (irq != 2))
494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi );
495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi );
498 * PIIX3 USB: We have to disable USB interrupts that are
499 * hardwired to PIRQD# and may be shared with an
502 * Legacy Support Register (LEGSUP):
503 * bit13: USB PIRQ Enable (USBPIRQDEN),
504 * bit4: Trap/SMI On IRQ Enable (USBSMIEN).
506 * We mask out all r/wc bits, too.
508 static void __devinit quirk_piix3_usb(struct pci_dev *dev)
512 pci_read_config_word(dev, 0xc0, &legsup);
514 pci_write_config_word(dev, 0xc0, legsup);
516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_2, quirk_piix3_usb );
517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_2, quirk_piix3_usb );
520 * VIA VT82C598 has its device ID settable and many BIOSes
521 * set it to the ID of VT82C597 for backward compatibility.
522 * We need to switch it off to be able to recognize the real
525 static void __devinit quirk_vt82c598_id(struct pci_dev *dev)
527 pci_write_config_byte(dev, 0xfc, 0);
528 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
530 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id );
533 * CardBus controllers have a legacy base address that enables them
534 * to respond as i82365 pcmcia controllers. We don't want them to
535 * do this even if the Linux CardBus driver is not loaded, because
536 * the Linux i82365 driver does not (and should not) handle CardBus.
538 static void __devinit quirk_cardbus_legacy(struct pci_dev *dev)
540 if ((PCI_CLASS_BRIDGE_CARDBUS << 8) ^ dev->class)
542 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
544 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, quirk_cardbus_legacy);
547 * Following the PCI ordering rules is optional on the AMD762. I'm not
548 * sure what the designers were smoking but let's not inhale...
550 * To be fair to AMD, it follows the spec by default, its BIOS people
553 static void __devinit quirk_amd_ordering(struct pci_dev *dev)
556 pci_read_config_dword(dev, 0x4C, &pcic);
559 printk(KERN_WARNING "BIOS failed to enable PCI standards compliance, fixing this error.\n");
560 pci_write_config_dword(dev, 0x4C, pcic);
561 pci_read_config_dword(dev, 0x84, &pcic);
562 pcic |= (1<<23); /* Required in this mode */
563 pci_write_config_dword(dev, 0x84, pcic);
566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering );
569 * DreamWorks provided workaround for Dunord I-3000 problem
571 * This card decodes and responds to addresses not apparently
572 * assigned to it. We force a larger allocation to ensure that
573 * nothing gets put too close to it.
575 static void __devinit quirk_dunord ( struct pci_dev * dev )
577 struct resource *r = &dev->resource [1];
581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord );
584 * i82380FB mobile docking controller: its PCI-to-PCI bridge
585 * is subtractive decoding (transparent), and does indicate this
586 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
589 static void __devinit quirk_transparent_bridge(struct pci_dev *dev)
591 dev->transparent = 1;
593 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge );
594 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge );
597 * Common misconfiguration of the MediaGX/Geode PCI master that will
598 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
599 * datasheets found at http://www.national.com/ds/GX for info on what
600 * these bits do. <christer@weinigel.se>
602 static void __init quirk_mediagx_master(struct pci_dev *dev)
605 pci_read_config_byte(dev, 0x41, ®);
608 printk(KERN_INFO "PCI: Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", reg);
609 pci_write_config_byte(dev, 0x41, reg);
612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master );
615 * As per PCI spec, ignore base address registers 0-3 of the IDE controllers
616 * running in Compatible mode (bits 0 and 2 in the ProgIf for primary and
617 * secondary channels respectively). If the device reports Compatible mode
618 * but does use BAR0-3 for address decoding, we assume that firmware has
619 * programmed these BARs with standard values (0x1f0,0x3f4 and 0x170,0x374).
620 * Exceptions (if they exist) must be handled in chip/architecture specific
623 * Note: for non x86 people. You may need an arch specific quirk to handle
624 * moving IDE devices to native mode as well. Some plug in card devices power
625 * up in compatible mode and assume the BIOS will adjust them.
627 * Q: should we load the 0x1f0,0x3f4 into the registers or zap them as
628 * we do now ? We don't want is pci_enable_device to come along
629 * and assign new resources. Both approaches work for that.
631 static void __devinit quirk_ide_bases(struct pci_dev *dev)
633 struct resource *res;
634 int first_bar = 2, last_bar = 0;
636 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
639 res = &dev->resource[0];
641 /* primary channel: ProgIf bit 0, BAR0, BAR1 */
642 if (!(dev->class & 1) && (res[0].flags || res[1].flags)) {
643 res[0].start = res[0].end = res[0].flags = 0;
644 res[1].start = res[1].end = res[1].flags = 0;
649 /* secondary channel: ProgIf bit 2, BAR2, BAR3 */
650 if (!(dev->class & 4) && (res[2].flags || res[3].flags)) {
651 res[2].start = res[2].end = res[2].flags = 0;
652 res[3].start = res[3].end = res[3].flags = 0;
659 printk(KERN_INFO "PCI: Ignoring BAR%d-%d of IDE controller %s\n",
660 first_bar, last_bar, pci_name(dev));
662 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_ide_bases);
665 * Ensure C0 rev restreaming is off. This is normally done by
666 * the BIOS but in the odd case it is not the results are corruption
667 * hence the presence of a Linux check
669 static void __init quirk_disable_pxb(struct pci_dev *pdev)
674 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
675 if (rev != 0x04) /* Only C0 requires this */
677 pci_read_config_word(pdev, 0x40, &config);
678 if (config & (1<<6)) {
680 pci_write_config_word(pdev, 0x40, config);
681 printk(KERN_INFO "PCI: C0 revision 450NX. Disabling PCI restreaming.\n");
684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb );
687 * VIA northbridges care about PCI_INTERRUPT_LINE
689 int via_interrupt_line_quirk;
691 static void __devinit quirk_via_bridge(struct pci_dev *pdev)
693 if(pdev->devfn == 0) {
694 printk(KERN_INFO "PCI: Via IRQ fixup\n");
695 via_interrupt_line_quirk = 1;
698 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_bridge );
701 * Serverworks CSB5 IDE does not fully support native mode
703 static void __devinit quirk_svwks_csb5ide(struct pci_dev *pdev)
706 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
710 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
711 /* need to re-assign BARs for compat mode */
712 quirk_ide_bases(pdev);
715 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide );
718 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
720 static void __init quirk_ide_samemode(struct pci_dev *pdev)
724 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
726 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
727 printk(KERN_INFO "PCI: IDE mode mismatch; forcing legacy mode\n");
730 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
731 /* need to re-assign BARs for compat mode */
732 quirk_ide_bases(pdev);
735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
737 /* This was originally an Alpha specific thing, but it really fits here.
738 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
740 static void __init quirk_eisa_bridge(struct pci_dev *dev)
742 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
744 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge );
747 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
748 * is not activated. The myth is that Asus said that they do not want the
749 * users to be irritated by just another PCI Device in the Win98 device
750 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
751 * package 2.7.0 for details)
753 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
754 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
755 * becomes necessary to do this tweak in two steps -- I've chosen the Host
758 static int __initdata asus_hides_smbus = 0;
760 static void __init asus_hides_smbus_hostbridge(struct pci_dev *dev)
762 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
763 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
764 switch(dev->subsystem_device) {
765 case 0x8070: /* P4B */
766 case 0x8088: /* P4B533 */
767 case 0x1626: /* L3C notebook */
768 asus_hides_smbus = 1;
770 if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
771 switch(dev->subsystem_device) {
772 case 0x80b1: /* P4GE-V */
773 case 0x80b2: /* P4PE */
774 case 0x8093: /* P4B533-V */
775 asus_hides_smbus = 1;
777 if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
778 switch(dev->subsystem_device) {
779 case 0x8030: /* P4T533 */
780 asus_hides_smbus = 1;
782 if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
783 switch (dev->subsystem_device) {
784 case 0x8070: /* P4G8X Deluxe */
785 asus_hides_smbus = 1;
787 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
788 switch (dev->subsystem_device) {
789 case 0x1751: /* M2N notebook */
790 case 0x1821: /* M5N notebook */
791 asus_hides_smbus = 1;
793 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
794 switch (dev->subsystem_device) {
795 case 0x184b: /* W1N notebook */
796 case 0x186a: /* M6Ne notebook */
797 asus_hides_smbus = 1;
799 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
800 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
801 switch(dev->subsystem_device) {
802 case 0x088C: /* HP Compaq nc8000 */
803 case 0x0890: /* HP Compaq nc6000 */
804 asus_hides_smbus = 1;
806 if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
807 switch (dev->subsystem_device) {
808 case 0x12bc: /* HP D330L */
809 asus_hides_smbus = 1;
811 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_TOSHIBA)) {
812 if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
813 switch(dev->subsystem_device) {
814 case 0x0001: /* Toshiba Satellite A40 */
815 asus_hides_smbus = 1;
817 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
818 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
819 switch(dev->subsystem_device) {
820 case 0xC00C: /* Samsung P35 notebook */
821 asus_hides_smbus = 1;
825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge );
826 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge );
827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge );
828 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge );
829 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge );
830 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge );
831 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge );
833 static void __init asus_hides_smbus_lpc(struct pci_dev *dev)
837 if (likely(!asus_hides_smbus))
840 pci_read_config_word(dev, 0xF2, &val);
842 pci_write_config_word(dev, 0xF2, val & (~0x8));
843 pci_read_config_word(dev, 0xF2, &val);
845 printk(KERN_INFO "PCI: i801 SMBus device continues to play 'hide and seek'! 0x%x\n", val);
847 printk(KERN_INFO "PCI: Enabled i801 SMBus device\n");
850 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc );
851 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc );
852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc );
853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc );
854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc );
857 * SiS 96x south bridge: BIOS typically hides SMBus device...
859 static void __init quirk_sis_96x_smbus(struct pci_dev *dev)
862 printk(KERN_INFO "Enabling SiS 96x SMBus.\n");
863 pci_read_config_byte(dev, 0x77, &val);
864 pci_write_config_byte(dev, 0x77, val & ~0x10);
865 pci_read_config_byte(dev, 0x77, &val);
869 #define UHCI_USBLEGSUP 0xc0 /* legacy support */
870 #define UHCI_USBCMD 0 /* command register */
871 #define UHCI_USBSTS 2 /* status register */
872 #define UHCI_USBINTR 4 /* interrupt register */
873 #define UHCI_USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
874 #define UHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
875 #define UHCI_USBCMD_GRESET (1 << 2) /* Global reset */
876 #define UHCI_USBCMD_CONFIGURE (1 << 6) /* config semaphore */
877 #define UHCI_USBSTS_HALTED (1 << 5) /* HCHalted bit */
879 #define OHCI_CONTROL 0x04
880 #define OHCI_CMDSTATUS 0x08
881 #define OHCI_INTRSTATUS 0x0c
882 #define OHCI_INTRENABLE 0x10
883 #define OHCI_INTRDISABLE 0x14
884 #define OHCI_OCR (1 << 3) /* ownership change request */
885 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
886 #define OHCI_INTR_OC (1 << 30) /* ownership change */
888 #define EHCI_HCC_PARAMS 0x08 /* extended capabilities */
889 #define EHCI_USBCMD 0 /* command register */
890 #define EHCI_USBCMD_RUN (1 << 0) /* RUN/STOP bit */
891 #define EHCI_USBSTS 4 /* status register */
892 #define EHCI_USBSTS_HALTED (1 << 12) /* HCHalted bit */
893 #define EHCI_USBINTR 8 /* interrupt register */
894 #define EHCI_USBLEGSUP 0 /* legacy support register */
895 #define EHCI_USBLEGSUP_BIOS (1 << 16) /* BIOS semaphore */
896 #define EHCI_USBLEGSUP_OS (1 << 24) /* OS semaphore */
897 #define EHCI_USBLEGCTLSTS 4 /* legacy control/status */
898 #define EHCI_USBLEGCTLSTS_SOOE (1 << 13) /* SMI on ownership change */
900 int usb_early_handoff __devinitdata = 0;
901 static int __init usb_handoff_early(char *str)
903 usb_early_handoff = 1;
906 __setup("usb-handoff", usb_handoff_early);
908 static void __devinit quirk_usb_handoff_uhci(struct pci_dev *pdev)
910 unsigned long base = 0;
911 int wait_time, delta;
915 for (i = 0; i < PCI_ROM_RESOURCE; i++)
916 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
917 base = pci_resource_start(pdev, i);
927 sts = inw(base + UHCI_USBSTS);
928 val = inw(base + UHCI_USBCMD);
929 val &= ~(u16)(UHCI_USBCMD_RUN | UHCI_USBCMD_CONFIGURE);
930 outw(val, base + UHCI_USBCMD);
933 * wait while it stops if it was running
935 if ((sts & UHCI_USBSTS_HALTED) == 0)
941 outw(0x1f, base + UHCI_USBSTS);
944 val = inw(base + UHCI_USBSTS);
945 if (val & UHCI_USBSTS_HALTED)
947 } while (wait_time > 0);
951 * disable interrupts & legacy support
953 outw(0, base + UHCI_USBINTR);
954 outw(0x1f, base + UHCI_USBSTS);
955 pci_read_config_word(pdev, UHCI_USBLEGSUP, &val);
957 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_DEFAULT);
961 static void __devinit quirk_usb_handoff_ohci(struct pci_dev *pdev)
966 base = ioremap_nocache(pci_resource_start(pdev, 0),
967 pci_resource_len(pdev, 0));
968 if (base == NULL) return;
970 if (readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
971 wait_time = 500; /* 0.5 seconds */
972 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
973 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
974 while (wait_time > 0 &&
975 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
984 writel(~(u32)0, base + OHCI_INTRDISABLE);
985 writel(~(u32)0, base + OHCI_INTRSTATUS);
990 static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
992 int wait_time, delta;
993 void __iomem *base, *op_reg_base;
994 u32 hcc_params, val, temp;
997 base = ioremap_nocache(pci_resource_start(pdev, 0),
998 pci_resource_len(pdev, 0));
999 if (base == NULL) return;
1001 cap_length = readb(base);
1002 op_reg_base = base + cap_length;
1003 hcc_params = readl(base + EHCI_HCC_PARAMS);
1004 hcc_params = (hcc_params >> 8) & 0xff;
1006 pci_read_config_dword(pdev,
1007 hcc_params + EHCI_USBLEGSUP,
1009 if (((val & 0xff) == 1) && (val & EHCI_USBLEGSUP_BIOS)) {
1011 * Ok, BIOS is in smm mode, try to hand off...
1013 pci_read_config_dword(pdev,
1014 hcc_params + EHCI_USBLEGCTLSTS,
1016 pci_write_config_dword(pdev,
1017 hcc_params + EHCI_USBLEGCTLSTS,
1018 temp | EHCI_USBLEGCTLSTS_SOOE);
1019 val |= EHCI_USBLEGSUP_OS;
1020 pci_write_config_dword(pdev,
1021 hcc_params + EHCI_USBLEGSUP,
1028 pci_read_config_dword(pdev,
1029 hcc_params + EHCI_USBLEGSUP,
1031 } while (wait_time && (val & EHCI_USBLEGSUP_BIOS));
1034 * well, possibly buggy BIOS...
1036 printk(KERN_WARNING "EHCI early BIOS handoff "
1037 "failed (BIOS bug ?)\n");
1038 pci_write_config_dword(pdev,
1039 hcc_params + EHCI_USBLEGSUP,
1041 pci_write_config_dword(pdev,
1042 hcc_params + EHCI_USBLEGCTLSTS,
1049 * halt EHCI & disable its interrupts in any case
1051 val = readl(op_reg_base + EHCI_USBSTS);
1052 if ((val & EHCI_USBSTS_HALTED) == 0) {
1053 val = readl(op_reg_base + EHCI_USBCMD);
1054 val &= ~EHCI_USBCMD_RUN;
1055 writel(val, op_reg_base + EHCI_USBCMD);
1060 writel(0x3f, op_reg_base + EHCI_USBSTS);
1063 val = readl(op_reg_base + EHCI_USBSTS);
1064 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
1067 } while (wait_time > 0);
1069 writel(0, op_reg_base + EHCI_USBINTR);
1070 writel(0x3f, op_reg_base + EHCI_USBSTS);
1079 static void __devinit quirk_usb_early_handoff(struct pci_dev *pdev)
1081 if (!usb_early_handoff)
1084 if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x00)) { /* UHCI */
1085 quirk_usb_handoff_uhci(pdev);
1086 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x10)) { /* OHCI */
1087 quirk_usb_handoff_ohci(pdev);
1088 } else if (pdev->class == ((PCI_CLASS_SERIAL_USB << 8) | 0x20)) { /* EHCI */
1089 quirk_usb_disable_ehci(pdev);
1094 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, quirk_usb_early_handoff);
1097 * ... This is further complicated by the fact that some SiS96x south
1098 * bridges pretend to be 85C503/5513 instead. In that case see if we
1099 * spotted a compatible north bridge to make sure.
1100 * (pci_find_device doesn't work yet)
1102 * We can also enable the sis96x bit in the discovery register..
1104 static int __devinitdata sis_96x_compatible = 0;
1106 #define SIS_DETECT_REGISTER 0x40
1108 static void __init quirk_sis_503(struct pci_dev *dev)
1113 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1114 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1115 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1116 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1117 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1121 /* Make people aware that we changed the config.. */
1122 printk(KERN_WARNING "Uncovering SIS%x that hid as a SIS503 (compatible=%d)\n", devid, sis_96x_compatible);
1125 * Ok, it now shows up as a 96x.. The 96x quirks are after
1126 * the 503 quirk in the quirk table, so they'll automatically
1127 * run and enable things like the SMBus device
1129 dev->device = devid;
1132 static void __init quirk_sis_96x_compatible(struct pci_dev *dev)
1134 sis_96x_compatible = 1;
1136 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_645, quirk_sis_96x_compatible );
1137 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_646, quirk_sis_96x_compatible );
1138 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_648, quirk_sis_96x_compatible );
1139 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_650, quirk_sis_96x_compatible );
1140 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_651, quirk_sis_96x_compatible );
1141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_735, quirk_sis_96x_compatible );
1143 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503 );
1145 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus );
1146 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus );
1147 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus );
1148 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus );
1150 #ifdef CONFIG_X86_IO_APIC
1151 static void __init quirk_alder_ioapic(struct pci_dev *pdev)
1155 if ((pdev->class >> 8) != 0xff00)
1158 /* the first BAR is the location of the IO APIC...we must
1159 * not touch this (and it's already covered by the fixmap), so
1160 * forcibly insert it into the resource tree */
1161 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1162 insert_resource(&iomem_resource, &pdev->resource[0]);
1164 /* The next five BARs all seem to be rubbish, so just clean
1166 for (i=1; i < 6; i++) {
1167 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1171 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic );
1174 #ifdef CONFIG_SCSI_SATA
1175 static void __devinit quirk_intel_ide_combined(struct pci_dev *pdev)
1181 * Narrow down to Intel SATA PCI devices.
1183 switch (pdev->device) {
1184 /* PCI ids taken from drivers/scsi/ata_piix.c */
1194 case 0x2680: /* ESB2 */
1202 /* we do not handle this PCI device */
1207 * Read combined mode register.
1209 pci_read_config_byte(pdev, 0x90, &tmp); /* combined mode reg */
1212 tmp &= 0x6; /* interesting bits 2:1, PATA primary/secondary */
1213 if (tmp == 0x4) /* bits 10x */
1214 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1215 else if (tmp == 0x6) /* bits 11x */
1216 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1218 return; /* not in combined mode */
1220 WARN_ON((ich != 6) && (ich != 7));
1221 tmp &= 0x3; /* interesting bits 1:0 */
1223 comb = (1 << 2); /* PATA port 0, SATA port 1 */
1224 else if (tmp & (1 << 1))
1225 comb = (1 << 0); /* SATA port 0, PATA port 1 */
1227 return; /* not in combined mode */
1231 * Read programming interface register.
1232 * (Tells us if it's legacy or native mode)
1234 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1236 /* if SATA port is in native mode, we're ok. */
1240 /* SATA port is in legacy mode. Reserve port so that
1241 * IDE driver does not attempt to use it. If request_region
1242 * fails, it will be obvious at boot time, so we don't bother
1243 * checking return values.
1245 if (comb == (1 << 0))
1246 request_region(0x1f0, 8, "libata"); /* port 0 */
1248 request_region(0x170, 8, "libata"); /* port 1 */
1250 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_ide_combined );
1251 #endif /* CONFIG_SCSI_SATA */
1256 static void __devinit quirk_pcie_mch(struct pci_dev *pdev)
1260 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch );
1261 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch );
1262 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch );
1264 static void __devinit quirk_netmos(struct pci_dev *dev)
1266 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1267 unsigned int num_serial = dev->subsystem_device & 0xf;
1270 * These Netmos parts are multiport serial devices with optional
1271 * parallel ports. Even when parallel ports are present, they
1272 * are identified as class SERIAL, which means the serial driver
1273 * will claim them. To prevent this, mark them as class OTHER.
1274 * These combo devices should be claimed by parport_serial.
1276 * The subdevice ID is of the form 0x00PS, where <P> is the number
1277 * of parallel ports and <S> is the number of serial ports.
1279 switch (dev->device) {
1280 case PCI_DEVICE_ID_NETMOS_9735:
1281 case PCI_DEVICE_ID_NETMOS_9745:
1282 case PCI_DEVICE_ID_NETMOS_9835:
1283 case PCI_DEVICE_ID_NETMOS_9845:
1284 case PCI_DEVICE_ID_NETMOS_9855:
1285 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_SERIAL &&
1287 printk(KERN_INFO "PCI: Netmos %04x (%u parallel, "
1288 "%u serial); changing class SERIAL to OTHER "
1289 "(use parport_serial)\n",
1290 dev->device, num_parallel, num_serial);
1291 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1292 (dev->class & 0xff);
1296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, quirk_netmos);
1298 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, struct pci_fixup *end)
1301 if ((f->vendor == dev->vendor || f->vendor == (u16) PCI_ANY_ID) &&
1302 (f->device == dev->device || f->device == (u16) PCI_ANY_ID)) {
1303 pr_debug("PCI: Calling quirk %p for %s\n", f->hook, pci_name(dev));
1310 extern struct pci_fixup __start_pci_fixups_early[];
1311 extern struct pci_fixup __end_pci_fixups_early[];
1312 extern struct pci_fixup __start_pci_fixups_header[];
1313 extern struct pci_fixup __end_pci_fixups_header[];
1314 extern struct pci_fixup __start_pci_fixups_final[];
1315 extern struct pci_fixup __end_pci_fixups_final[];
1316 extern struct pci_fixup __start_pci_fixups_enable[];
1317 extern struct pci_fixup __end_pci_fixups_enable[];
1320 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
1322 struct pci_fixup *start, *end;
1325 case pci_fixup_early:
1326 start = __start_pci_fixups_early;
1327 end = __end_pci_fixups_early;
1330 case pci_fixup_header:
1331 start = __start_pci_fixups_header;
1332 end = __end_pci_fixups_header;
1335 case pci_fixup_final:
1336 start = __start_pci_fixups_final;
1337 end = __end_pci_fixups_final;
1340 case pci_fixup_enable:
1341 start = __start_pci_fixups_enable;
1342 end = __end_pci_fixups_enable;
1346 /* stupid compiler warning, you would think with an enum... */
1349 pci_do_fixups(dev, start, end);
1352 EXPORT_SYMBOL(pcie_mch_quirk);
1353 #ifdef CONFIG_HOTPLUG
1354 EXPORT_SYMBOL(pci_fixup_device);