2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
15 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
16 #define CARDBUS_RESERVE_BUSNR 3
17 #define PCI_CFG_SPACE_SIZE 256
18 #define PCI_CFG_SPACE_EXP_SIZE 4096
20 /* Ugh. Need to stop exporting this to modules. */
21 LIST_HEAD(pci_root_buses);
22 EXPORT_SYMBOL(pci_root_buses);
25 static int find_anything(struct device *dev, void *data)
31 * Some device drivers need know if pci is initiated.
32 * Basically, we think pci is not initiated when there
33 * is no device to be found on the pci_bus_type.
35 int no_pci_devices(void)
40 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
41 no_devices = (dev == NULL);
45 EXPORT_SYMBOL(no_pci_devices);
47 #ifdef HAVE_PCI_LEGACY
49 * pci_create_legacy_files - create legacy I/O port and memory files
50 * @b: bus to create files under
52 * Some platforms allow access to legacy I/O port and ISA memory space on
53 * a per-bus basis. This routine creates the files and ties them into
54 * their associated read, write and mmap files from pci-sysfs.c
56 static void pci_create_legacy_files(struct pci_bus *b)
58 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
61 b->legacy_io->attr.name = "legacy_io";
62 b->legacy_io->size = 0xffff;
63 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
64 b->legacy_io->read = pci_read_legacy_io;
65 b->legacy_io->write = pci_write_legacy_io;
66 device_create_bin_file(&b->dev, b->legacy_io);
68 /* Allocated above after the legacy_io struct */
69 b->legacy_mem = b->legacy_io + 1;
70 b->legacy_mem->attr.name = "legacy_mem";
71 b->legacy_mem->size = 1024*1024;
72 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
73 b->legacy_mem->mmap = pci_mmap_legacy_mem;
74 device_create_bin_file(&b->dev, b->legacy_mem);
78 void pci_remove_legacy_files(struct pci_bus *b)
81 device_remove_bin_file(&b->dev, b->legacy_io);
82 device_remove_bin_file(&b->dev, b->legacy_mem);
83 kfree(b->legacy_io); /* both are allocated here */
86 #else /* !HAVE_PCI_LEGACY */
87 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
88 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
89 #endif /* HAVE_PCI_LEGACY */
92 * PCI Bus Class Devices
94 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
96 struct device_attribute *attr,
102 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
104 cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask):
105 cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
111 static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
112 struct device_attribute *attr,
115 return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
118 static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
119 struct device_attribute *attr,
122 return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
125 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
126 DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
131 static void release_pcibus_dev(struct device *dev)
133 struct pci_bus *pci_bus = to_pci_bus(dev);
136 put_device(pci_bus->bridge);
140 static struct class pcibus_class = {
142 .dev_release = &release_pcibus_dev,
145 static int __init pcibus_class_init(void)
147 return class_register(&pcibus_class);
149 postcore_initcall(pcibus_class_init);
152 * Translate the low bits of the PCI base
153 * to the resource type
155 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
157 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
158 return IORESOURCE_IO;
160 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
161 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
163 return IORESOURCE_MEM;
167 * Find the extent of a PCI decode..
169 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
171 u32 size = mask & maxbase; /* Find the significant bits */
175 /* Get the lowest of them to find the decode size, and
176 from that the extent. */
177 size = (size & ~(size-1)) - 1;
179 /* base == maxbase can be valid only if the BAR has
180 already been programmed with all 1s. */
181 if (base == maxbase && ((base | size) & mask) != mask)
187 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
189 u64 size = mask & maxbase; /* Find the significant bits */
193 /* Get the lowest of them to find the decode size, and
194 from that the extent. */
195 size = (size & ~(size-1)) - 1;
197 /* base == maxbase can be valid only if the BAR has
198 already been programmed with all 1s. */
199 if (base == maxbase && ((base | size) & mask) != mask)
205 static inline int is_64bit_memory(u32 mask)
207 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
208 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
213 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
215 unsigned int pos, reg, next;
217 struct resource *res;
219 for(pos=0; pos<howmany; pos = next) {
225 res = &dev->resource[pos];
226 res->name = pci_name(dev);
227 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
228 pci_read_config_dword(dev, reg, &l);
229 pci_write_config_dword(dev, reg, ~0);
230 pci_read_config_dword(dev, reg, &sz);
231 pci_write_config_dword(dev, reg, l);
232 if (!sz || sz == 0xffffffff)
237 if ((l & PCI_BASE_ADDRESS_SPACE) ==
238 PCI_BASE_ADDRESS_SPACE_MEMORY) {
239 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
241 * For 64bit prefetchable memory sz could be 0, if the
242 * real size is bigger than 4G, so we need to check
245 if (!is_64bit_memory(l) && !sz)
247 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
248 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
250 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
253 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
254 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
256 res->end = res->start + (unsigned long) sz;
257 res->flags |= pci_calc_resource_flags(l) | IORESOURCE_SIZEALIGN;
258 if (is_64bit_memory(l)) {
261 pci_read_config_dword(dev, reg+4, &lhi);
262 pci_write_config_dword(dev, reg+4, ~0);
263 pci_read_config_dword(dev, reg+4, &szhi);
264 pci_write_config_dword(dev, reg+4, lhi);
265 sz64 = ((u64)szhi << 32) | raw_sz;
266 l64 = ((u64)lhi << 32) | l;
267 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
269 #if BITS_PER_LONG == 64
276 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
277 res->end = res->start + sz64;
278 printk(KERN_INFO "PCI: %s reg %x 64bit mmio: [%llx, %llx]\n", pci_name(dev), reg, res->start, res->end);
280 if (sz64 > 0x100000000ULL) {
281 dev_err(&dev->dev, "BAR %d: can't handle 64-bit"
286 /* 64-bit wide address, treat as disabled */
287 pci_write_config_dword(dev, reg,
288 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
289 pci_write_config_dword(dev, reg+4, 0);
295 printk(KERN_INFO "PCI: %s reg %x %s: [%llx, %llx]\n", pci_name(dev), reg, (res->flags & IORESOURCE_IO)? "io port":"32bit mmio", res->start, res->end);
299 dev->rom_base_reg = rom;
300 res = &dev->resource[PCI_ROM_RESOURCE];
301 res->name = pci_name(dev);
302 pci_read_config_dword(dev, rom, &l);
303 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
304 pci_read_config_dword(dev, rom, &sz);
305 pci_write_config_dword(dev, rom, l);
308 if (sz && sz != 0xffffffff) {
309 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
311 res->flags = (l & IORESOURCE_ROM_ENABLE) |
312 IORESOURCE_MEM | IORESOURCE_PREFETCH |
313 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
314 IORESOURCE_SIZEALIGN;
315 res->start = l & PCI_ROM_ADDRESS_MASK;
316 res->end = res->start + (unsigned long) sz;
322 void __devinit pci_read_bridge_bases(struct pci_bus *child)
324 struct pci_dev *dev = child->self;
325 u8 io_base_lo, io_limit_lo;
326 u16 mem_base_lo, mem_limit_lo;
327 unsigned long base, limit;
328 struct resource *res;
331 if (!dev) /* It's a host bus, nothing to read */
334 if (dev->transparent) {
335 dev_info(&dev->dev, "transparent bridge\n");
336 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
337 child->resource[i] = child->parent->resource[i - 3];
341 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
343 res = child->resource[0];
344 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
345 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
346 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
347 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
349 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
350 u16 io_base_hi, io_limit_hi;
351 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
352 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
353 base |= (io_base_hi << 16);
354 limit |= (io_limit_hi << 16);
358 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
362 res->end = limit + 0xfff;
363 printk(KERN_INFO "PCI: bridge %s io port: [%llx, %llx]\n", pci_name(dev), res->start, res->end);
366 res = child->resource[1];
367 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
368 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
369 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
370 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
372 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
374 res->end = limit + 0xfffff;
375 printk(KERN_INFO "PCI: bridge %s 32bit mmio: [%llx, %llx]\n", pci_name(dev), res->start, res->end);
378 res = child->resource[2];
379 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
380 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
381 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
382 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
384 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
385 u32 mem_base_hi, mem_limit_hi;
386 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
387 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
390 * Some bridges set the base > limit by default, and some
391 * (broken) BIOSes do not initialize them. If we find
392 * this, just assume they are not being used.
394 if (mem_base_hi <= mem_limit_hi) {
395 #if BITS_PER_LONG == 64
396 base |= ((long) mem_base_hi) << 32;
397 limit |= ((long) mem_limit_hi) << 32;
399 if (mem_base_hi || mem_limit_hi) {
400 dev_err(&dev->dev, "can't handle 64-bit "
401 "address space for bridge\n");
408 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
410 res->end = limit + 0xfffff;
411 printk(KERN_INFO "PCI: bridge %s %sbit mmio pref: [%llx, %llx]\n", pci_name(dev), (res->flags & PCI_PREF_RANGE_TYPE_64)?"64":"32",res->start, res->end);
415 static struct pci_bus * pci_alloc_bus(void)
419 b = kzalloc(sizeof(*b), GFP_KERNEL);
421 INIT_LIST_HEAD(&b->node);
422 INIT_LIST_HEAD(&b->children);
423 INIT_LIST_HEAD(&b->devices);
424 INIT_LIST_HEAD(&b->slots);
429 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
430 struct pci_dev *bridge, int busnr)
432 struct pci_bus *child;
436 * Allocate a new bus, and inherit stuff from the parent..
438 child = pci_alloc_bus();
442 child->self = bridge;
443 child->parent = parent;
444 child->ops = parent->ops;
445 child->sysdata = parent->sysdata;
446 child->bus_flags = parent->bus_flags;
447 child->bridge = get_device(&bridge->dev);
449 /* initialize some portions of the bus device, but don't register it
450 * now as the parent is not properly set up yet. This device will get
451 * registered later in pci_bus_add_devices()
453 child->dev.class = &pcibus_class;
454 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
457 * Set up the primary, secondary and subordinate
460 child->number = child->secondary = busnr;
461 child->primary = parent->secondary;
462 child->subordinate = 0xff;
464 /* Set up default resource pointers and names.. */
465 for (i = 0; i < 4; i++) {
466 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
467 child->resource[i]->name = child->name;
469 bridge->subordinate = child;
474 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
476 struct pci_bus *child;
478 child = pci_alloc_child_bus(parent, dev, busnr);
480 down_write(&pci_bus_sem);
481 list_add_tail(&child->node, &parent->children);
482 up_write(&pci_bus_sem);
487 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
489 struct pci_bus *parent = child->parent;
491 /* Attempts to fix that up are really dangerous unless
492 we're going to re-assign all bus numbers. */
493 if (!pcibios_assign_all_busses())
496 while (parent->parent && parent->subordinate < max) {
497 parent->subordinate = max;
498 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
499 parent = parent->parent;
504 * If it's a bridge, configure it and scan the bus behind it.
505 * For CardBus bridges, we don't scan behind as the devices will
506 * be handled by the bridge driver itself.
508 * We need to process bridges in two passes -- first we scan those
509 * already configured by the BIOS and after we are done with all of
510 * them, we proceed to assigning numbers to the remaining buses in
511 * order to avoid overlaps between old and new bus numbers.
513 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
515 struct pci_bus *child;
516 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
520 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
522 dev_dbg(&dev->dev, "scanning behind bridge, config %06x, pass %d\n",
523 buses & 0xffffff, pass);
525 /* Disable MasterAbortMode during probing to avoid reporting
526 of bus errors (in some architectures) */
527 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
528 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
529 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
531 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
532 unsigned int cmax, busnr;
534 * Bus already configured by firmware, process it in the first
535 * pass and just note the configuration.
539 busnr = (buses >> 8) & 0xFF;
542 * If we already got to this bus through a different bridge,
543 * ignore it. This can happen with the i450NX chipset.
545 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
546 dev_info(&dev->dev, "bus %04x:%02x already known\n",
547 pci_domain_nr(bus), busnr);
551 child = pci_add_new_bus(bus, dev, busnr);
554 child->primary = buses & 0xFF;
555 child->subordinate = (buses >> 16) & 0xFF;
556 child->bridge_ctl = bctl;
558 cmax = pci_scan_child_bus(child);
561 if (child->subordinate > max)
562 max = child->subordinate;
565 * We need to assign a number to this bus which we always
566 * do in the second pass.
569 if (pcibios_assign_all_busses())
570 /* Temporarily disable forwarding of the
571 configuration cycles on all bridges in
572 this bus segment to avoid possible
573 conflicts in the second pass between two
574 bridges programmed with overlapping
576 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
582 pci_write_config_word(dev, PCI_STATUS, 0xffff);
584 /* Prevent assigning a bus number that already exists.
585 * This can happen when a bridge is hot-plugged */
586 if (pci_find_bus(pci_domain_nr(bus), max+1))
588 child = pci_add_new_bus(bus, dev, ++max);
589 buses = (buses & 0xff000000)
590 | ((unsigned int)(child->primary) << 0)
591 | ((unsigned int)(child->secondary) << 8)
592 | ((unsigned int)(child->subordinate) << 16);
595 * yenta.c forces a secondary latency timer of 176.
596 * Copy that behaviour here.
599 buses &= ~0xff000000;
600 buses |= CARDBUS_LATENCY_TIMER << 24;
604 * We need to blast all three values with a single write.
606 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
609 child->bridge_ctl = bctl;
611 * Adjust subordinate busnr in parent buses.
612 * We do this before scanning for children because
613 * some devices may not be detected if the bios
616 pci_fixup_parent_subordinate_busnr(child, max);
617 /* Now we can scan all subordinate buses... */
618 max = pci_scan_child_bus(child);
620 * now fix it up again since we have found
621 * the real value of max.
623 pci_fixup_parent_subordinate_busnr(child, max);
626 * For CardBus bridges, we leave 4 bus numbers
627 * as cards with a PCI-to-PCI bridge can be
630 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
631 struct pci_bus *parent = bus;
632 if (pci_find_bus(pci_domain_nr(bus),
635 while (parent->parent) {
636 if ((!pcibios_assign_all_busses()) &&
637 (parent->subordinate > max) &&
638 (parent->subordinate <= max+i)) {
641 parent = parent->parent;
645 * Often, there are two cardbus bridges
646 * -- try to leave one valid bus number
654 pci_fixup_parent_subordinate_busnr(child, max);
657 * Set the subordinate bus number to its real value.
659 child->subordinate = max;
660 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
664 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
665 pci_domain_nr(bus), child->number);
667 /* Has only triggered on CardBus, fixup is in yenta_socket */
668 while (bus->parent) {
669 if ((child->subordinate > bus->subordinate) ||
670 (child->number > bus->subordinate) ||
671 (child->number < bus->number) ||
672 (child->subordinate < bus->number)) {
673 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
674 "hidden behind%s bridge #%02x (-#%02x)\n",
675 child->number, child->subordinate,
676 (bus->number > child->subordinate &&
677 bus->subordinate < child->number) ?
678 "wholly" : "partially",
679 bus->self->transparent ? " transparent" : "",
680 bus->number, bus->subordinate);
686 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
692 * Read interrupt line and base address registers.
693 * The architecture-dependent code can tweak these, of course.
695 static void pci_read_irq(struct pci_dev *dev)
699 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
702 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
706 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
709 * pci_setup_device - fill in class and map information of a device
710 * @dev: the device structure to fill
712 * Initialize the device structure with information about the device's
713 * vendor,class,memory and IO-space addresses,IRQ lines etc.
714 * Called at initialisation of the PCI subsystem and by CardBus services.
715 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
718 static int pci_setup_device(struct pci_dev * dev)
722 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
723 dev->bus->number, PCI_SLOT(dev->devfn),
724 PCI_FUNC(dev->devfn));
726 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
727 dev->revision = class & 0xff;
728 class >>= 8; /* upper 3 bytes */
732 dev_dbg(&dev->dev, "found [%04x/%04x] class %06x header type %02x\n",
733 dev->vendor, dev->device, class, dev->hdr_type);
735 /* "Unknown power state" */
736 dev->current_state = PCI_UNKNOWN;
738 /* Early fixups, before probing the BARs */
739 pci_fixup_device(pci_fixup_early, dev);
740 class = dev->class >> 8;
742 switch (dev->hdr_type) { /* header type */
743 case PCI_HEADER_TYPE_NORMAL: /* standard header */
744 if (class == PCI_CLASS_BRIDGE_PCI)
747 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
748 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
749 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
752 * Do the ugly legacy mode stuff here rather than broken chip
753 * quirk code. Legacy mode ATA controllers have fixed
754 * addresses. These are not always echoed in BAR0-3, and
755 * BAR0-3 in a few cases contain junk!
757 if (class == PCI_CLASS_STORAGE_IDE) {
759 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
760 if ((progif & 1) == 0) {
761 dev->resource[0].start = 0x1F0;
762 dev->resource[0].end = 0x1F7;
763 dev->resource[0].flags = LEGACY_IO_RESOURCE;
764 dev->resource[1].start = 0x3F6;
765 dev->resource[1].end = 0x3F6;
766 dev->resource[1].flags = LEGACY_IO_RESOURCE;
768 if ((progif & 4) == 0) {
769 dev->resource[2].start = 0x170;
770 dev->resource[2].end = 0x177;
771 dev->resource[2].flags = LEGACY_IO_RESOURCE;
772 dev->resource[3].start = 0x376;
773 dev->resource[3].end = 0x376;
774 dev->resource[3].flags = LEGACY_IO_RESOURCE;
779 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
780 if (class != PCI_CLASS_BRIDGE_PCI)
782 /* The PCI-to-PCI bridge spec requires that subtractive
783 decoding (i.e. transparent) bridge must have programming
784 interface code of 0x01. */
786 dev->transparent = ((dev->class & 0xff) == 1);
787 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
790 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
791 if (class != PCI_CLASS_BRIDGE_CARDBUS)
794 pci_read_bases(dev, 1, 0);
795 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
796 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
799 default: /* unknown header */
800 dev_err(&dev->dev, "unknown header type %02x, "
801 "ignoring device\n", dev->hdr_type);
805 dev_err(&dev->dev, "ignoring class %02x (doesn't match header "
806 "type %02x)\n", class, dev->hdr_type);
807 dev->class = PCI_CLASS_NOT_DEFINED;
810 /* We found a fine healthy device, go go go... */
815 * pci_release_dev - free a pci device structure when all users of it are finished.
816 * @dev: device that's been disconnected
818 * Will be called only by the device core when all users of this pci device are
821 static void pci_release_dev(struct device *dev)
823 struct pci_dev *pci_dev;
825 pci_dev = to_pci_dev(dev);
826 pci_vpd_release(pci_dev);
830 static void set_pcie_port_type(struct pci_dev *pdev)
835 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
839 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
840 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
844 * pci_cfg_space_size - get the configuration space size of the PCI device.
847 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
848 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
849 * access it. Maybe we don't have a way to generate extended config space
850 * accesses, or the device is behind a reverse Express bridge. So we try
851 * reading the dword at 0x100 which must either be 0 or a valid extended
854 int pci_cfg_space_size_ext(struct pci_dev *dev)
858 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
860 if (status == 0xffffffff)
863 return PCI_CFG_SPACE_EXP_SIZE;
866 return PCI_CFG_SPACE_SIZE;
869 int pci_cfg_space_size(struct pci_dev *dev)
874 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
876 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
880 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
881 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
885 return pci_cfg_space_size_ext(dev);
888 return PCI_CFG_SPACE_SIZE;
891 static void pci_release_bus_bridge_dev(struct device *dev)
896 struct pci_dev *alloc_pci_dev(void)
900 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
904 INIT_LIST_HEAD(&dev->bus_list);
906 pci_msi_init_pci_dev(dev);
910 EXPORT_SYMBOL(alloc_pci_dev);
913 * Read the config data for a PCI device, sanity-check it
914 * and fill in the dev structure...
916 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
923 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
926 /* some broken boards return 0 or ~0 if a slot is empty: */
927 if (l == 0xffffffff || l == 0x00000000 ||
928 l == 0x0000ffff || l == 0xffff0000)
931 /* Configuration request Retry Status */
932 while (l == 0xffff0001) {
935 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
937 /* Card hasn't responded in 60 seconds? Must be stuck. */
938 if (delay > 60 * 1000) {
939 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
940 "responding\n", pci_domain_nr(bus),
941 bus->number, PCI_SLOT(devfn),
947 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
950 dev = alloc_pci_dev();
955 dev->sysdata = bus->sysdata;
956 dev->dev.parent = bus->bridge;
957 dev->dev.bus = &pci_bus_type;
959 dev->hdr_type = hdr_type & 0x7f;
960 dev->multifunction = !!(hdr_type & 0x80);
961 dev->vendor = l & 0xffff;
962 dev->device = (l >> 16) & 0xffff;
963 dev->cfg_size = pci_cfg_space_size(dev);
964 dev->error_state = pci_channel_io_normal;
965 set_pcie_port_type(dev);
967 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
968 set this higher, assuming the system even supports it. */
969 dev->dma_mask = 0xffffffff;
970 if (pci_setup_device(dev) < 0) {
975 pci_vpd_pci22_init(dev);
980 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
982 device_initialize(&dev->dev);
983 dev->dev.release = pci_release_dev;
986 dev->dev.dma_mask = &dev->dma_mask;
987 dev->dev.dma_parms = &dev->dma_parms;
988 dev->dev.coherent_dma_mask = 0xffffffffull;
990 pci_set_dma_max_seg_size(dev, 65536);
991 pci_set_dma_seg_boundary(dev, 0xffffffff);
993 /* Fix up broken headers */
994 pci_fixup_device(pci_fixup_header, dev);
996 /* Initialize power management of the device */
1000 * Add the device to our list of discovered devices
1001 * and the bus list for fixup functions, etc.
1003 down_write(&pci_bus_sem);
1004 list_add_tail(&dev->bus_list, &bus->devices);
1005 up_write(&pci_bus_sem);
1008 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1010 struct pci_dev *dev;
1012 dev = pci_scan_device(bus, devfn);
1016 pci_device_add(dev, bus);
1020 EXPORT_SYMBOL(pci_scan_single_device);
1023 * pci_scan_slot - scan a PCI slot on a bus for devices.
1024 * @bus: PCI bus to scan
1025 * @devfn: slot number to scan (must have zero function.)
1027 * Scan a PCI slot on the specified PCI bus for devices, adding
1028 * discovered devices to the @bus->devices list. New devices
1029 * will not have is_added set.
1031 int pci_scan_slot(struct pci_bus *bus, int devfn)
1036 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
1038 for (func = 0; func < 8; func++, devfn++) {
1039 struct pci_dev *dev;
1041 dev = pci_scan_single_device(bus, devfn);
1046 * If this is a single function device,
1047 * don't scan past the first function.
1049 if (!dev->multifunction) {
1051 dev->multifunction = 1;
1057 if (func == 0 && !scan_all_fns)
1063 pcie_aspm_init_link_state(bus->self);
1068 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1070 unsigned int devfn, pass, max = bus->secondary;
1071 struct pci_dev *dev;
1073 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1075 /* Go find them, Rover! */
1076 for (devfn = 0; devfn < 0x100; devfn += 8)
1077 pci_scan_slot(bus, devfn);
1080 * After performing arch-dependent fixup of the bus, look behind
1081 * all PCI-to-PCI bridges on this bus.
1083 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1084 pcibios_fixup_bus(bus);
1085 for (pass=0; pass < 2; pass++)
1086 list_for_each_entry(dev, &bus->devices, bus_list) {
1087 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1088 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1089 max = pci_scan_bridge(bus, dev, max, pass);
1093 * We've scanned the bus and so we know all about what's on
1094 * the other side of any bridges that may be on this bus plus
1097 * Return how far we've got finding sub-buses.
1099 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1100 pci_domain_nr(bus), bus->number, max);
1104 void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
1108 struct pci_bus * pci_create_bus(struct device *parent,
1109 int bus, struct pci_ops *ops, void *sysdata)
1115 b = pci_alloc_bus();
1119 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1125 b->sysdata = sysdata;
1128 if (pci_find_bus(pci_domain_nr(b), bus)) {
1129 /* If we already got to this bus through a different bridge, ignore it */
1130 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1134 down_write(&pci_bus_sem);
1135 list_add_tail(&b->node, &pci_root_buses);
1136 up_write(&pci_bus_sem);
1138 memset(dev, 0, sizeof(*dev));
1139 dev->parent = parent;
1140 dev->release = pci_release_bus_bridge_dev;
1141 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1142 error = device_register(dev);
1145 b->bridge = get_device(dev);
1148 set_dev_node(b->bridge, pcibus_to_node(b));
1150 b->dev.class = &pcibus_class;
1151 b->dev.parent = b->bridge;
1152 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1153 error = device_register(&b->dev);
1155 goto class_dev_reg_err;
1156 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1158 goto dev_create_file_err;
1160 /* Create legacy_io and legacy_mem files for this bus */
1161 pci_create_legacy_files(b);
1163 b->number = b->secondary = bus;
1164 b->resource[0] = &ioport_resource;
1165 b->resource[1] = &iomem_resource;
1167 set_pci_bus_resources_arch_default(b);
1171 dev_create_file_err:
1172 device_unregister(&b->dev);
1174 device_unregister(dev);
1176 down_write(&pci_bus_sem);
1178 up_write(&pci_bus_sem);
1185 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1186 int bus, struct pci_ops *ops, void *sysdata)
1190 b = pci_create_bus(parent, bus, ops, sysdata);
1192 b->subordinate = pci_scan_child_bus(b);
1195 EXPORT_SYMBOL(pci_scan_bus_parented);
1197 #ifdef CONFIG_HOTPLUG
1198 EXPORT_SYMBOL(pci_add_new_bus);
1199 EXPORT_SYMBOL(pci_scan_slot);
1200 EXPORT_SYMBOL(pci_scan_bridge);
1201 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1204 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1206 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1207 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1209 if (a->bus->number < b->bus->number) return -1;
1210 else if (a->bus->number > b->bus->number) return 1;
1212 if (a->devfn < b->devfn) return -1;
1213 else if (a->devfn > b->devfn) return 1;
1219 * Yes, this forcably breaks the klist abstraction temporarily. It
1220 * just wants to sort the klist, not change reference counts and
1221 * take/drop locks rapidly in the process. It does all this while
1222 * holding the lock for the list, so objects can't otherwise be
1223 * added/removed while we're swizzling.
1225 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1227 struct list_head *pos;
1228 struct klist_node *n;
1232 list_for_each(pos, list) {
1233 n = container_of(pos, struct klist_node, n_node);
1234 dev = container_of(n, struct device, knode_bus);
1235 b = to_pci_dev(dev);
1236 if (pci_sort_bf_cmp(a, b) <= 0) {
1237 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1241 list_move_tail(&a->dev.knode_bus.n_node, list);
1244 void __init pci_sort_breadthfirst(void)
1246 LIST_HEAD(sorted_devices);
1247 struct list_head *pos, *tmp;
1248 struct klist_node *n;
1250 struct pci_dev *pdev;
1251 struct klist *device_klist;
1253 device_klist = bus_get_device_klist(&pci_bus_type);
1255 spin_lock(&device_klist->k_lock);
1256 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1257 n = container_of(pos, struct klist_node, n_node);
1258 dev = container_of(n, struct device, knode_bus);
1259 pdev = to_pci_dev(dev);
1260 pci_insertion_sort_klist(pdev, &sorted_devices);
1262 list_splice(&sorted_devices, &device_klist->k_list);
1263 spin_unlock(&device_klist->k_lock);