2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/string.h>
19 #include <asm/dma.h> /* isa_dma_bridge_buggy */
25 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
26 * @bus: pointer to PCI bus structure to search
28 * Given a PCI bus, returns the highest PCI bus number present in the set
29 * including the given PCI bus and its list of child PCI buses.
31 unsigned char __devinit
32 pci_bus_max_busnr(struct pci_bus* bus)
34 struct list_head *tmp;
38 list_for_each(tmp, &bus->children) {
39 n = pci_bus_max_busnr(pci_bus_b(tmp));
47 * pci_max_busnr - returns maximum PCI bus number
49 * Returns the highest PCI bus number present in the system global list of
52 unsigned char __devinit
55 struct pci_bus *bus = NULL;
59 while ((bus = pci_find_next_bus(bus)) != NULL) {
60 n = pci_bus_max_busnr(bus);
69 static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, u8 pos, int cap)
75 pci_bus_read_config_byte(bus, devfn, pos, &pos);
79 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID,
85 pos += PCI_CAP_LIST_NEXT;
90 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
92 return __pci_find_next_cap(dev->bus, dev->devfn,
93 pos + PCI_CAP_LIST_NEXT, cap);
95 EXPORT_SYMBOL_GPL(pci_find_next_capability);
97 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
102 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
103 if (!(status & PCI_STATUS_CAP_LIST))
107 case PCI_HEADER_TYPE_NORMAL:
108 case PCI_HEADER_TYPE_BRIDGE:
109 pos = PCI_CAPABILITY_LIST;
111 case PCI_HEADER_TYPE_CARDBUS:
112 pos = PCI_CB_CAPABILITY_LIST;
117 return __pci_find_next_cap(bus, devfn, pos, cap);
121 * pci_find_capability - query for devices' capabilities
122 * @dev: PCI device to query
123 * @cap: capability code
125 * Tell if a device supports a given PCI capability.
126 * Returns the address of the requested capability structure within the
127 * device's PCI configuration space or 0 in case the device does not
128 * support it. Possible values for @cap:
130 * %PCI_CAP_ID_PM Power Management
131 * %PCI_CAP_ID_AGP Accelerated Graphics Port
132 * %PCI_CAP_ID_VPD Vital Product Data
133 * %PCI_CAP_ID_SLOTID Slot Identification
134 * %PCI_CAP_ID_MSI Message Signalled Interrupts
135 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
136 * %PCI_CAP_ID_PCIX PCI-X
137 * %PCI_CAP_ID_EXP PCI Express
139 int pci_find_capability(struct pci_dev *dev, int cap)
141 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
145 * pci_bus_find_capability - query for devices' capabilities
146 * @bus: the PCI bus to query
147 * @devfn: PCI device to query
148 * @cap: capability code
150 * Like pci_find_capability() but works for pci devices that do not have a
151 * pci_dev structure set up yet.
153 * Returns the address of the requested capability structure within the
154 * device's PCI configuration space or 0 in case the device does not
157 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
161 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
163 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
168 * pci_find_ext_capability - Find an extended capability
169 * @dev: PCI device to query
170 * @cap: capability code
172 * Returns the address of the requested extended capability structure
173 * within the device's PCI configuration space or 0 if the device does
174 * not support it. Possible values for @cap:
176 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
177 * %PCI_EXT_CAP_ID_VC Virtual Channel
178 * %PCI_EXT_CAP_ID_DSN Device Serial Number
179 * %PCI_EXT_CAP_ID_PWR Power Budgeting
181 int pci_find_ext_capability(struct pci_dev *dev, int cap)
184 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
187 if (dev->cfg_size <= 256)
190 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
194 * If we have no capabilities, this is indicated by cap ID,
195 * cap version and next pointer all being 0.
201 if (PCI_EXT_CAP_ID(header) == cap)
204 pos = PCI_EXT_CAP_NEXT(header);
208 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
217 * pci_find_parent_resource - return resource region of parent bus of given region
218 * @dev: PCI device structure contains resources to be searched
219 * @res: child resource record for which parent is sought
221 * For given resource region of given device, return the resource
222 * region of parent bus the given region is contained in or where
223 * it should be allocated from.
226 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
228 const struct pci_bus *bus = dev->bus;
230 struct resource *best = NULL;
232 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
233 struct resource *r = bus->resource[i];
236 if (res->start && !(res->start >= r->start && res->end <= r->end))
237 continue; /* Not contained */
238 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
239 continue; /* Wrong type */
240 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
241 return r; /* Exact match */
242 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
243 best = r; /* Approximating prefetchable by non-prefetchable */
249 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
250 * @dev: PCI device to have its BARs restored
252 * Restore the BAR values for a given device, so as to make it
253 * accessible by its driver.
256 pci_restore_bars(struct pci_dev *dev)
260 switch (dev->hdr_type) {
261 case PCI_HEADER_TYPE_NORMAL:
264 case PCI_HEADER_TYPE_BRIDGE:
267 case PCI_HEADER_TYPE_CARDBUS:
271 /* Should never get here, but just in case... */
275 for (i = 0; i < numres; i ++)
276 pci_update_resource(dev, &dev->resource[i], i);
279 int (*platform_pci_set_power_state)(struct pci_dev *dev, pci_power_t t);
282 * pci_set_power_state - Set the power state of a PCI device
283 * @dev: PCI device to be suspended
284 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
286 * Transition a device to a new power state, using the Power Management
287 * Capabilities in the device's config space.
290 * -EINVAL if trying to enter a lower state than we're already in.
291 * 0 if we're already in the requested state.
292 * -EIO if device does not support PCI PM.
293 * 0 if we can successfully change the power state.
296 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
298 int pm, need_restore = 0;
301 /* bound the state we're entering */
302 if (state > PCI_D3hot)
305 /* Validate current state:
306 * Can enter D0 from any state, but if we can only go deeper
307 * to sleep if we're already in a low power state
309 if (state != PCI_D0 && dev->current_state > state)
311 else if (dev->current_state == state)
312 return 0; /* we're already there */
314 /* find PCI PM capability in list */
315 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
317 /* abort if the device doesn't support PM capabilities */
321 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
322 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
324 "PCI: %s has unsupported PM cap regs version (%u)\n",
325 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
329 /* check if this device supports the desired state */
330 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
332 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
335 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
337 /* If we're (effectively) in D3, force entire word to 0.
338 * This doesn't affect PME_Status, disables PME_En, and
339 * sets PowerState to 0.
341 switch (dev->current_state) {
345 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
348 case PCI_UNKNOWN: /* Boot-up */
349 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
350 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
352 /* Fall-through: force to D0 */
358 /* enter specified state */
359 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
361 /* Mandatory power management transition delays */
362 /* see PCI PM 1.1 5.6.1 table 18 */
363 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
365 else if (state == PCI_D2 || dev->current_state == PCI_D2)
369 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
370 * Firmware method after natice method ?
372 if (platform_pci_set_power_state)
373 platform_pci_set_power_state(dev, state);
375 dev->current_state = state;
377 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
378 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
379 * from D3hot to D0 _may_ perform an internal reset, thereby
380 * going to "D0 Uninitialized" rather than "D0 Initialized".
381 * For example, at least some versions of the 3c905B and the
382 * 3c556B exhibit this behaviour.
384 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
385 * devices in a D3hot state at boot. Consequently, we need to
386 * restore at least the BARs so that the device will be
387 * accessible to its driver.
390 pci_restore_bars(dev);
395 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state);
398 * pci_choose_state - Choose the power state of a PCI device
399 * @dev: PCI device to be suspended
400 * @state: target sleep state for the whole system. This is the value
401 * that is passed to suspend() function.
403 * Returns PCI power state suitable for given device and given system
407 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
411 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
414 if (platform_pci_choose_state) {
415 ret = platform_pci_choose_state(dev, state);
420 switch (state.event) {
423 case PM_EVENT_FREEZE:
424 case PM_EVENT_SUSPEND:
427 printk("They asked me for state %d\n", state.event);
433 EXPORT_SYMBOL(pci_choose_state);
436 * pci_save_state - save the PCI configuration space of a device before suspending
437 * @dev: - PCI device that we're dealing with
440 pci_save_state(struct pci_dev *dev)
443 /* XXX: 100% dword access ok here? */
444 for (i = 0; i < 16; i++)
445 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
450 * pci_restore_state - Restore the saved state of a PCI device
451 * @dev: - PCI device that we're dealing with
454 pci_restore_state(struct pci_dev *dev)
458 for (i = 0; i < 16; i++)
459 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]);
464 * pci_enable_device_bars - Initialize some of a device for use
465 * @dev: PCI device to be initialized
466 * @bars: bitmask of BAR's that must be configured
468 * Initialize device before it's used by a driver. Ask low-level code
469 * to enable selected I/O and memory resources. Wake up the device if it
470 * was suspended. Beware, this function can fail.
474 pci_enable_device_bars(struct pci_dev *dev, int bars)
478 err = pci_set_power_state(dev, PCI_D0);
479 if (err < 0 && err != -EIO)
481 err = pcibios_enable_device(dev, bars);
488 * pci_enable_device - Initialize device before it's used by a driver.
489 * @dev: PCI device to be initialized
491 * Initialize device before it's used by a driver. Ask low-level code
492 * to enable I/O and memory. Wake up the device if it was suspended.
493 * Beware, this function can fail.
496 pci_enable_device(struct pci_dev *dev)
498 int err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1);
501 pci_fixup_device(pci_fixup_enable, dev);
507 * pcibios_disable_device - disable arch specific PCI resources for device dev
508 * @dev: the PCI device to disable
510 * Disables architecture specific PCI resources for the device. This
511 * is the default implementation. Architecture implementations can
514 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
517 * pci_disable_device - Disable PCI device after use
518 * @dev: PCI device to be disabled
520 * Signal to the system that the PCI device is not in use by the system
521 * anymore. This only involves disabling PCI bus-mastering, if active.
524 pci_disable_device(struct pci_dev *dev)
528 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
529 if (pci_command & PCI_COMMAND_MASTER) {
530 pci_command &= ~PCI_COMMAND_MASTER;
531 pci_write_config_word(dev, PCI_COMMAND, pci_command);
533 dev->is_busmaster = 0;
535 pcibios_disable_device(dev);
540 * pci_enable_wake - enable device to generate PME# when suspended
541 * @dev: - PCI device to operate on
542 * @state: - Current state of device.
543 * @enable: - Flag to enable or disable generation
545 * Set the bits in the device's PM Capabilities to generate PME# when
546 * the system is suspended.
548 * -EIO is returned if device doesn't have PM Capabilities.
549 * -EINVAL is returned if device supports it, but can't generate wake events.
550 * 0 if operation is successful.
553 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
558 /* find PCI PM capability in list */
559 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
561 /* If device doesn't support PM Capabilities, but request is to disable
562 * wake events, it's a nop; otherwise fail */
564 return enable ? -EIO : 0;
566 /* Check device's ability to generate PME# */
567 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
569 value &= PCI_PM_CAP_PME_MASK;
570 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
572 /* Check if it can generate PME# from requested state. */
573 if (!value || !(value & (1 << state)))
574 return enable ? -EINVAL : 0;
576 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
578 /* Clear PME_Status by writing 1 to it and enable PME# */
579 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
582 value &= ~PCI_PM_CTRL_PME_ENABLE;
584 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
590 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
598 while (dev->bus->self) {
599 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
600 dev = dev->bus->self;
607 * pci_release_region - Release a PCI bar
608 * @pdev: PCI device whose resources were previously reserved by pci_request_region
609 * @bar: BAR to release
611 * Releases the PCI I/O and memory resources previously reserved by a
612 * successful call to pci_request_region. Call this function only
613 * after all use of the PCI regions has ceased.
615 void pci_release_region(struct pci_dev *pdev, int bar)
617 if (pci_resource_len(pdev, bar) == 0)
619 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
620 release_region(pci_resource_start(pdev, bar),
621 pci_resource_len(pdev, bar));
622 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
623 release_mem_region(pci_resource_start(pdev, bar),
624 pci_resource_len(pdev, bar));
628 * pci_request_region - Reserved PCI I/O and memory resource
629 * @pdev: PCI device whose resources are to be reserved
630 * @bar: BAR to be reserved
631 * @res_name: Name to be associated with resource.
633 * Mark the PCI region associated with PCI device @pdev BR @bar as
634 * being reserved by owner @res_name. Do not access any
635 * address inside the PCI regions unless this call returns
638 * Returns 0 on success, or %EBUSY on error. A warning
639 * message is also printed on failure.
641 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name)
643 if (pci_resource_len(pdev, bar) == 0)
646 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
647 if (!request_region(pci_resource_start(pdev, bar),
648 pci_resource_len(pdev, bar), res_name))
651 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
652 if (!request_mem_region(pci_resource_start(pdev, bar),
653 pci_resource_len(pdev, bar), res_name))
660 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
661 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
662 bar + 1, /* PCI BAR # */
663 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
670 * pci_release_regions - Release reserved PCI I/O and memory resources
671 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
673 * Releases all PCI I/O and memory resources previously reserved by a
674 * successful call to pci_request_regions. Call this function only
675 * after all use of the PCI regions has ceased.
678 void pci_release_regions(struct pci_dev *pdev)
682 for (i = 0; i < 6; i++)
683 pci_release_region(pdev, i);
687 * pci_request_regions - Reserved PCI I/O and memory resources
688 * @pdev: PCI device whose resources are to be reserved
689 * @res_name: Name to be associated with resource.
691 * Mark all PCI regions associated with PCI device @pdev as
692 * being reserved by owner @res_name. Do not access any
693 * address inside the PCI regions unless this call returns
696 * Returns 0 on success, or %EBUSY on error. A warning
697 * message is also printed on failure.
699 int pci_request_regions(struct pci_dev *pdev, char *res_name)
703 for (i = 0; i < 6; i++)
704 if(pci_request_region(pdev, i, res_name))
710 pci_release_region(pdev, i);
716 * pci_set_master - enables bus-mastering for device dev
717 * @dev: the PCI device to enable
719 * Enables bus-mastering on the device and calls pcibios_set_master()
720 * to do the needed arch specific settings.
723 pci_set_master(struct pci_dev *dev)
727 pci_read_config_word(dev, PCI_COMMAND, &cmd);
728 if (! (cmd & PCI_COMMAND_MASTER)) {
729 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
730 cmd |= PCI_COMMAND_MASTER;
731 pci_write_config_word(dev, PCI_COMMAND, cmd);
733 dev->is_busmaster = 1;
734 pcibios_set_master(dev);
737 #ifndef HAVE_ARCH_PCI_MWI
738 /* This can be overridden by arch code. */
739 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
742 * pci_generic_prep_mwi - helper function for pci_set_mwi
743 * @dev: the PCI device for which MWI is enabled
745 * Helper function for generic implementation of pcibios_prep_mwi
746 * function. Originally copied from drivers/net/acenic.c.
747 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
749 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
752 pci_generic_prep_mwi(struct pci_dev *dev)
756 if (!pci_cache_line_size)
757 return -EINVAL; /* The system doesn't support MWI. */
759 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
760 equal to or multiple of the right value. */
761 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
762 if (cacheline_size >= pci_cache_line_size &&
763 (cacheline_size % pci_cache_line_size) == 0)
766 /* Write the correct value. */
767 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
769 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
770 if (cacheline_size == pci_cache_line_size)
773 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
774 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
778 #endif /* !HAVE_ARCH_PCI_MWI */
781 * pci_set_mwi - enables memory-write-invalidate PCI transaction
782 * @dev: the PCI device for which MWI is enabled
784 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
785 * and then calls @pcibios_set_mwi to do the needed arch specific
786 * operations or a generic mwi-prep function.
788 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
791 pci_set_mwi(struct pci_dev *dev)
796 #ifdef HAVE_ARCH_PCI_MWI
797 rc = pcibios_prep_mwi(dev);
799 rc = pci_generic_prep_mwi(dev);
805 pci_read_config_word(dev, PCI_COMMAND, &cmd);
806 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
807 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
808 cmd |= PCI_COMMAND_INVALIDATE;
809 pci_write_config_word(dev, PCI_COMMAND, cmd);
816 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
817 * @dev: the PCI device to disable
819 * Disables PCI Memory-Write-Invalidate transaction on the device
822 pci_clear_mwi(struct pci_dev *dev)
826 pci_read_config_word(dev, PCI_COMMAND, &cmd);
827 if (cmd & PCI_COMMAND_INVALIDATE) {
828 cmd &= ~PCI_COMMAND_INVALIDATE;
829 pci_write_config_word(dev, PCI_COMMAND, cmd);
834 * pci_intx - enables/disables PCI INTx for device dev
835 * @pdev: the PCI device to operate on
836 * @enable: boolean: whether to enable or disable PCI INTx
838 * Enables/disables PCI INTx for device dev
841 pci_intx(struct pci_dev *pdev, int enable)
843 u16 pci_command, new;
845 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
848 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
850 new = pci_command | PCI_COMMAND_INTX_DISABLE;
853 if (new != pci_command) {
854 pci_write_config_word(pdev, PCI_COMMAND, new);
858 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
860 * These can be overridden by arch-specific implementations
863 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
865 if (!pci_dma_supported(dev, mask))
868 dev->dma_mask = mask;
874 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
876 if (!pci_dma_supported(dev, mask))
879 dev->dev.coherent_dma_mask = mask;
885 static int __devinit pci_init(void)
887 struct pci_dev *dev = NULL;
889 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
890 pci_fixup_device(pci_fixup_final, dev);
895 static int __devinit pci_setup(char *str)
898 char *k = strchr(str, ',');
901 if (*str && (str = pcibios_setup(str)) && *str) {
902 /* PCI layer options should be handled here */
903 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
910 device_initcall(pci_init);
912 __setup("pci=", pci_setup);
914 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
915 /* FIXME: Some boxes have multiple ISA bridges! */
916 struct pci_dev *isa_bridge;
917 EXPORT_SYMBOL(isa_bridge);
920 EXPORT_SYMBOL_GPL(pci_restore_bars);
921 EXPORT_SYMBOL(pci_enable_device_bars);
922 EXPORT_SYMBOL(pci_enable_device);
923 EXPORT_SYMBOL(pci_disable_device);
924 EXPORT_SYMBOL(pci_find_capability);
925 EXPORT_SYMBOL(pci_bus_find_capability);
926 EXPORT_SYMBOL(pci_release_regions);
927 EXPORT_SYMBOL(pci_request_regions);
928 EXPORT_SYMBOL(pci_release_region);
929 EXPORT_SYMBOL(pci_request_region);
930 EXPORT_SYMBOL(pci_set_master);
931 EXPORT_SYMBOL(pci_set_mwi);
932 EXPORT_SYMBOL(pci_clear_mwi);
933 EXPORT_SYMBOL_GPL(pci_intx);
934 EXPORT_SYMBOL(pci_set_dma_mask);
935 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
936 EXPORT_SYMBOL(pci_assign_resource);
937 EXPORT_SYMBOL(pci_find_parent_resource);
939 EXPORT_SYMBOL(pci_set_power_state);
940 EXPORT_SYMBOL(pci_save_state);
941 EXPORT_SYMBOL(pci_restore_state);
942 EXPORT_SYMBOL(pci_enable_wake);
946 EXPORT_SYMBOL(isa_dma_bridge_buggy);
947 EXPORT_SYMBOL(pci_pci_problems);