2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
24 * @bus: pointer to PCI bus structure to search
26 * Given a PCI bus, returns the highest PCI bus number present in the set
27 * including the given PCI bus and its list of child PCI buses.
29 unsigned char __devinit
30 pci_bus_max_busnr(struct pci_bus* bus)
32 struct list_head *tmp;
36 list_for_each(tmp, &bus->children) {
37 n = pci_bus_max_busnr(pci_bus_b(tmp));
45 * pci_max_busnr - returns maximum PCI bus number
47 * Returns the highest PCI bus number present in the system global list of
50 unsigned char __devinit
53 struct pci_bus *bus = NULL;
57 while ((bus = pci_find_next_bus(bus)) != NULL) {
58 n = pci_bus_max_busnr(bus);
65 static int __pci_bus_find_cap(struct pci_bus *bus, unsigned int devfn, u8 hdr_type, int cap)
71 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
72 if (!(status & PCI_STATUS_CAP_LIST))
76 case PCI_HEADER_TYPE_NORMAL:
77 case PCI_HEADER_TYPE_BRIDGE:
78 pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos);
80 case PCI_HEADER_TYPE_CARDBUS:
81 pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos);
86 while (ttl-- && pos >= 0x40) {
88 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id);
93 pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos);
99 * pci_find_capability - query for devices' capabilities
100 * @dev: PCI device to query
101 * @cap: capability code
103 * Tell if a device supports a given PCI capability.
104 * Returns the address of the requested capability structure within the
105 * device's PCI configuration space or 0 in case the device does not
106 * support it. Possible values for @cap:
108 * %PCI_CAP_ID_PM Power Management
109 * %PCI_CAP_ID_AGP Accelerated Graphics Port
110 * %PCI_CAP_ID_VPD Vital Product Data
111 * %PCI_CAP_ID_SLOTID Slot Identification
112 * %PCI_CAP_ID_MSI Message Signalled Interrupts
113 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
114 * %PCI_CAP_ID_PCIX PCI-X
115 * %PCI_CAP_ID_EXP PCI Express
117 int pci_find_capability(struct pci_dev *dev, int cap)
119 return __pci_bus_find_cap(dev->bus, dev->devfn, dev->hdr_type, cap);
123 * pci_bus_find_capability - query for devices' capabilities
124 * @bus: the PCI bus to query
125 * @devfn: PCI device to query
126 * @cap: capability code
128 * Like pci_find_capability() but works for pci devices that do not have a
129 * pci_dev structure set up yet.
131 * Returns the address of the requested capability structure within the
132 * device's PCI configuration space or 0 in case the device does not
135 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
139 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
141 return __pci_bus_find_cap(bus, devfn, hdr_type & 0x7f, cap);
145 * pci_find_ext_capability - Find an extended capability
146 * @dev: PCI device to query
147 * @cap: capability code
149 * Returns the address of the requested extended capability structure
150 * within the device's PCI configuration space or 0 if the device does
151 * not support it. Possible values for @cap:
153 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
154 * %PCI_EXT_CAP_ID_VC Virtual Channel
155 * %PCI_EXT_CAP_ID_DSN Device Serial Number
156 * %PCI_EXT_CAP_ID_PWR Power Budgeting
158 int pci_find_ext_capability(struct pci_dev *dev, int cap)
161 int ttl = 480; /* 3840 bytes, minimum 8 bytes per capability */
164 if (dev->cfg_size <= 256)
167 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
171 * If we have no capabilities, this is indicated by cap ID,
172 * cap version and next pointer all being 0.
178 if (PCI_EXT_CAP_ID(header) == cap)
181 pos = PCI_EXT_CAP_NEXT(header);
185 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
193 * pci_find_parent_resource - return resource region of parent bus of given region
194 * @dev: PCI device structure contains resources to be searched
195 * @res: child resource record for which parent is sought
197 * For given resource region of given device, return the resource
198 * region of parent bus the given region is contained in or where
199 * it should be allocated from.
202 pci_find_parent_resource(const struct pci_dev *dev, struct resource *res)
204 const struct pci_bus *bus = dev->bus;
206 struct resource *best = NULL;
208 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
209 struct resource *r = bus->resource[i];
212 if (res->start && !(res->start >= r->start && res->end <= r->end))
213 continue; /* Not contained */
214 if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
215 continue; /* Wrong type */
216 if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
217 return r; /* Exact match */
218 if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
219 best = r; /* Approximating prefetchable by non-prefetchable */
225 * pci_set_power_state - Set the power state of a PCI device
226 * @dev: PCI device to be suspended
227 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
229 * Transition a device to a new power state, using the Power Management
230 * Capabilities in the device's config space.
233 * -EINVAL if trying to enter a lower state than we're already in.
234 * 0 if we're already in the requested state.
235 * -EIO if device does not support PCI PM.
236 * 0 if we can successfully change the power state.
240 pci_set_power_state(struct pci_dev *dev, pci_power_t state)
245 /* bound the state we're entering */
246 if (state > PCI_D3hot)
249 /* Validate current state:
250 * Can enter D0 from any state, but if we can only go deeper
251 * to sleep if we're already in a low power state
253 if (state != PCI_D0 && dev->current_state > state)
255 else if (dev->current_state == state)
256 return 0; /* we're already there */
258 /* find PCI PM capability in list */
259 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
261 /* abort if the device doesn't support PM capabilities */
265 pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc);
266 if ((pmc & PCI_PM_CAP_VER_MASK) > 2) {
268 "PCI: %s has unsupported PM cap regs version (%u)\n",
269 pci_name(dev), pmc & PCI_PM_CAP_VER_MASK);
273 /* check if this device supports the desired state */
274 if (state == PCI_D1 || state == PCI_D2) {
275 if (state == PCI_D1 && !(pmc & PCI_PM_CAP_D1))
277 else if (state == PCI_D2 && !(pmc & PCI_PM_CAP_D2))
281 /* If we're in D3, force entire word to 0.
282 * This doesn't affect PME_Status, disables PME_En, and
283 * sets PowerState to 0.
285 if (dev->current_state >= PCI_D3hot)
288 pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr);
289 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
293 /* enter specified state */
294 pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr);
296 /* Mandatory power management transition delays */
297 /* see PCI PM 1.1 5.6.1 table 18 */
298 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
300 else if (state == PCI_D2 || dev->current_state == PCI_D2)
302 dev->current_state = state;
307 int (*platform_pci_choose_state)(struct pci_dev *dev, pm_message_t state) = NULL;
310 * pci_choose_state - Choose the power state of a PCI device
311 * @dev: PCI device to be suspended
312 * @state: target sleep state for the whole system. This is the value
313 * that is passed to suspend() function.
315 * Returns PCI power state suitable for given device and given system
319 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
323 if (!pci_find_capability(dev, PCI_CAP_ID_PM))
326 if (platform_pci_choose_state) {
327 ret = platform_pci_choose_state(dev, state);
332 case 0: return PCI_D0;
333 case 3: return PCI_D3hot;
335 printk("They asked me for state %d\n", state);
341 EXPORT_SYMBOL(pci_choose_state);
344 * pci_save_state - save the PCI configuration space of a device before suspending
345 * @dev: - PCI device that we're dealing with
346 * @buffer: - buffer to hold config space context
348 * @buffer must be large enough to hold the entire PCI 2.2 config space
352 pci_save_state(struct pci_dev *dev)
355 /* XXX: 100% dword access ok here? */
356 for (i = 0; i < 16; i++)
357 pci_read_config_dword(dev, i * 4,&dev->saved_config_space[i]);
362 * pci_restore_state - Restore the saved state of a PCI device
363 * @dev: - PCI device that we're dealing with
364 * @buffer: - saved PCI config space
368 pci_restore_state(struct pci_dev *dev)
372 for (i = 0; i < 16; i++)
373 pci_write_config_dword(dev,i * 4, dev->saved_config_space[i]);
378 * pci_enable_device_bars - Initialize some of a device for use
379 * @dev: PCI device to be initialized
380 * @bars: bitmask of BAR's that must be configured
382 * Initialize device before it's used by a driver. Ask low-level code
383 * to enable selected I/O and memory resources. Wake up the device if it
384 * was suspended. Beware, this function can fail.
388 pci_enable_device_bars(struct pci_dev *dev, int bars)
392 pci_set_power_state(dev, PCI_D0);
393 if ((err = pcibios_enable_device(dev, bars)) < 0)
399 * pci_enable_device - Initialize device before it's used by a driver.
400 * @dev: PCI device to be initialized
402 * Initialize device before it's used by a driver. Ask low-level code
403 * to enable I/O and memory. Wake up the device if it was suspended.
404 * Beware, this function can fail.
407 pci_enable_device(struct pci_dev *dev)
411 if ((err = pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1)))
413 pci_fixup_device(pci_fixup_enable, dev);
419 * pcibios_disable_device - disable arch specific PCI resources for device dev
420 * @dev: the PCI device to disable
422 * Disables architecture specific PCI resources for the device. This
423 * is the default implementation. Architecture implementations can
426 void __attribute__ ((weak)) pcibios_disable_device (struct pci_dev *dev) {}
429 * pci_disable_device - Disable PCI device after use
430 * @dev: PCI device to be disabled
432 * Signal to the system that the PCI device is not in use by the system
433 * anymore. This only involves disabling PCI bus-mastering, if active.
436 pci_disable_device(struct pci_dev *dev)
440 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
441 if (pci_command & PCI_COMMAND_MASTER) {
442 pci_command &= ~PCI_COMMAND_MASTER;
443 pci_write_config_word(dev, PCI_COMMAND, pci_command);
445 dev->is_busmaster = 0;
447 pcibios_disable_device(dev);
452 * pci_enable_wake - enable device to generate PME# when suspended
453 * @dev: - PCI device to operate on
454 * @state: - Current state of device.
455 * @enable: - Flag to enable or disable generation
457 * Set the bits in the device's PM Capabilities to generate PME# when
458 * the system is suspended.
460 * -EIO is returned if device doesn't have PM Capabilities.
461 * -EINVAL is returned if device supports it, but can't generate wake events.
462 * 0 if operation is successful.
465 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable)
470 /* find PCI PM capability in list */
471 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
473 /* If device doesn't support PM Capabilities, but request is to disable
474 * wake events, it's a nop; otherwise fail */
476 return enable ? -EIO : 0;
478 /* Check device's ability to generate PME# */
479 pci_read_config_word(dev,pm+PCI_PM_PMC,&value);
481 value &= PCI_PM_CAP_PME_MASK;
482 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
484 /* Check if it can generate PME# from requested state. */
485 if (!value || !(value & (1 << state)))
486 return enable ? -EINVAL : 0;
488 pci_read_config_word(dev, pm + PCI_PM_CTRL, &value);
490 /* Clear PME_Status by writing 1 to it and enable PME# */
491 value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
494 value &= ~PCI_PM_CTRL_PME_ENABLE;
496 pci_write_config_word(dev, pm + PCI_PM_CTRL, value);
502 pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
506 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
510 while (dev->bus->self) {
511 pin = (pin + PCI_SLOT(dev->devfn)) % 4;
512 dev = dev->bus->self;
519 * pci_release_region - Release a PCI bar
520 * @pdev: PCI device whose resources were previously reserved by pci_request_region
521 * @bar: BAR to release
523 * Releases the PCI I/O and memory resources previously reserved by a
524 * successful call to pci_request_region. Call this function only
525 * after all use of the PCI regions has ceased.
527 void pci_release_region(struct pci_dev *pdev, int bar)
529 if (pci_resource_len(pdev, bar) == 0)
531 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
532 release_region(pci_resource_start(pdev, bar),
533 pci_resource_len(pdev, bar));
534 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
535 release_mem_region(pci_resource_start(pdev, bar),
536 pci_resource_len(pdev, bar));
540 * pci_request_region - Reserved PCI I/O and memory resource
541 * @pdev: PCI device whose resources are to be reserved
542 * @bar: BAR to be reserved
543 * @res_name: Name to be associated with resource.
545 * Mark the PCI region associated with PCI device @pdev BR @bar as
546 * being reserved by owner @res_name. Do not access any
547 * address inside the PCI regions unless this call returns
550 * Returns 0 on success, or %EBUSY on error. A warning
551 * message is also printed on failure.
553 int pci_request_region(struct pci_dev *pdev, int bar, char *res_name)
555 if (pci_resource_len(pdev, bar) == 0)
558 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
559 if (!request_region(pci_resource_start(pdev, bar),
560 pci_resource_len(pdev, bar), res_name))
563 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
564 if (!request_mem_region(pci_resource_start(pdev, bar),
565 pci_resource_len(pdev, bar), res_name))
572 printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
573 pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem",
574 bar + 1, /* PCI BAR # */
575 pci_resource_len(pdev, bar), pci_resource_start(pdev, bar),
582 * pci_release_regions - Release reserved PCI I/O and memory resources
583 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
585 * Releases all PCI I/O and memory resources previously reserved by a
586 * successful call to pci_request_regions. Call this function only
587 * after all use of the PCI regions has ceased.
590 void pci_release_regions(struct pci_dev *pdev)
594 for (i = 0; i < 6; i++)
595 pci_release_region(pdev, i);
599 * pci_request_regions - Reserved PCI I/O and memory resources
600 * @pdev: PCI device whose resources are to be reserved
601 * @res_name: Name to be associated with resource.
603 * Mark all PCI regions associated with PCI device @pdev as
604 * being reserved by owner @res_name. Do not access any
605 * address inside the PCI regions unless this call returns
608 * Returns 0 on success, or %EBUSY on error. A warning
609 * message is also printed on failure.
611 int pci_request_regions(struct pci_dev *pdev, char *res_name)
615 for (i = 0; i < 6; i++)
616 if(pci_request_region(pdev, i, res_name))
622 pci_release_region(pdev, i);
628 * pci_set_master - enables bus-mastering for device dev
629 * @dev: the PCI device to enable
631 * Enables bus-mastering on the device and calls pcibios_set_master()
632 * to do the needed arch specific settings.
635 pci_set_master(struct pci_dev *dev)
639 pci_read_config_word(dev, PCI_COMMAND, &cmd);
640 if (! (cmd & PCI_COMMAND_MASTER)) {
641 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev));
642 cmd |= PCI_COMMAND_MASTER;
643 pci_write_config_word(dev, PCI_COMMAND, cmd);
645 dev->is_busmaster = 1;
646 pcibios_set_master(dev);
649 #ifndef HAVE_ARCH_PCI_MWI
650 /* This can be overridden by arch code. */
651 u8 pci_cache_line_size = L1_CACHE_BYTES >> 2;
654 * pci_generic_prep_mwi - helper function for pci_set_mwi
655 * @dev: the PCI device for which MWI is enabled
657 * Helper function for generic implementation of pcibios_prep_mwi
658 * function. Originally copied from drivers/net/acenic.c.
659 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
661 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
664 pci_generic_prep_mwi(struct pci_dev *dev)
668 if (!pci_cache_line_size)
669 return -EINVAL; /* The system doesn't support MWI. */
671 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
672 equal to or multiple of the right value. */
673 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
674 if (cacheline_size >= pci_cache_line_size &&
675 (cacheline_size % pci_cache_line_size) == 0)
678 /* Write the correct value. */
679 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
681 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
682 if (cacheline_size == pci_cache_line_size)
685 printk(KERN_DEBUG "PCI: cache line size of %d is not supported "
686 "by device %s\n", pci_cache_line_size << 2, pci_name(dev));
690 #endif /* !HAVE_ARCH_PCI_MWI */
693 * pci_set_mwi - enables memory-write-invalidate PCI transaction
694 * @dev: the PCI device for which MWI is enabled
696 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
697 * and then calls @pcibios_set_mwi to do the needed arch specific
698 * operations or a generic mwi-prep function.
700 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
703 pci_set_mwi(struct pci_dev *dev)
708 #ifdef HAVE_ARCH_PCI_MWI
709 rc = pcibios_prep_mwi(dev);
711 rc = pci_generic_prep_mwi(dev);
717 pci_read_config_word(dev, PCI_COMMAND, &cmd);
718 if (! (cmd & PCI_COMMAND_INVALIDATE)) {
719 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev));
720 cmd |= PCI_COMMAND_INVALIDATE;
721 pci_write_config_word(dev, PCI_COMMAND, cmd);
728 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
729 * @dev: the PCI device to disable
731 * Disables PCI Memory-Write-Invalidate transaction on the device
734 pci_clear_mwi(struct pci_dev *dev)
738 pci_read_config_word(dev, PCI_COMMAND, &cmd);
739 if (cmd & PCI_COMMAND_INVALIDATE) {
740 cmd &= ~PCI_COMMAND_INVALIDATE;
741 pci_write_config_word(dev, PCI_COMMAND, cmd);
745 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
747 * These can be overridden by arch-specific implementations
750 pci_set_dma_mask(struct pci_dev *dev, u64 mask)
752 if (!pci_dma_supported(dev, mask))
755 dev->dma_mask = mask;
761 pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask)
763 if (!pci_dma_supported(dev, mask))
766 dev->dev.coherent_dma_mask = mask;
772 static int __devinit pci_init(void)
774 struct pci_dev *dev = NULL;
776 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
777 pci_fixup_device(pci_fixup_final, dev);
782 static int __devinit pci_setup(char *str)
785 char *k = strchr(str, ',');
788 if (*str && (str = pcibios_setup(str)) && *str) {
789 /* PCI layer options should be handled here */
790 printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
797 device_initcall(pci_init);
799 __setup("pci=", pci_setup);
801 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
802 /* FIXME: Some boxes have multiple ISA bridges! */
803 struct pci_dev *isa_bridge;
804 EXPORT_SYMBOL(isa_bridge);
807 EXPORT_SYMBOL(pci_enable_device_bars);
808 EXPORT_SYMBOL(pci_enable_device);
809 EXPORT_SYMBOL(pci_disable_device);
810 EXPORT_SYMBOL(pci_max_busnr);
811 EXPORT_SYMBOL(pci_bus_max_busnr);
812 EXPORT_SYMBOL(pci_find_capability);
813 EXPORT_SYMBOL(pci_bus_find_capability);
814 EXPORT_SYMBOL(pci_release_regions);
815 EXPORT_SYMBOL(pci_request_regions);
816 EXPORT_SYMBOL(pci_release_region);
817 EXPORT_SYMBOL(pci_request_region);
818 EXPORT_SYMBOL(pci_set_master);
819 EXPORT_SYMBOL(pci_set_mwi);
820 EXPORT_SYMBOL(pci_clear_mwi);
821 EXPORT_SYMBOL(pci_set_dma_mask);
822 EXPORT_SYMBOL(pci_set_consistent_dma_mask);
823 EXPORT_SYMBOL(pci_assign_resource);
824 EXPORT_SYMBOL(pci_find_parent_resource);
826 EXPORT_SYMBOL(pci_set_power_state);
827 EXPORT_SYMBOL(pci_save_state);
828 EXPORT_SYMBOL(pci_restore_state);
829 EXPORT_SYMBOL(pci_enable_wake);
833 EXPORT_SYMBOL(isa_dma_bridge_buggy);
834 EXPORT_SYMBOL(pci_pci_problems);