3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
20 #include <asm/errno.h>
27 static DEFINE_SPINLOCK(msi_lock);
28 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
29 static struct kmem_cache* msi_cachep;
31 static int pci_msi_enable = 1;
33 static int msi_cache_init(void)
35 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
36 0, SLAB_HWCACHE_ALIGN, NULL, NULL);
43 static void msi_set_mask_bit(unsigned int irq, int flag)
45 struct msi_desc *entry;
47 entry = msi_desc[irq];
48 BUG_ON(!entry || !entry->dev);
49 switch (entry->msi_attrib.type) {
51 if (entry->msi_attrib.maskbit) {
55 pos = (long)entry->mask_base;
56 pci_read_config_dword(entry->dev, pos, &mask_bits);
59 pci_write_config_dword(entry->dev, pos, mask_bits);
64 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
65 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
66 writel(flag, entry->mask_base + offset);
75 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
77 struct msi_desc *entry = get_irq_data(irq);
78 switch(entry->msi_attrib.type) {
81 struct pci_dev *dev = entry->dev;
82 int pos = entry->msi_attrib.pos;
85 pci_read_config_dword(dev, msi_lower_address_reg(pos),
87 if (entry->msi_attrib.is_64) {
88 pci_read_config_dword(dev, msi_upper_address_reg(pos),
90 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
93 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
101 base = entry->mask_base +
102 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
104 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
105 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
106 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
114 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
116 struct msi_desc *entry = get_irq_data(irq);
117 switch (entry->msi_attrib.type) {
120 struct pci_dev *dev = entry->dev;
121 int pos = entry->msi_attrib.pos;
123 pci_write_config_dword(dev, msi_lower_address_reg(pos),
125 if (entry->msi_attrib.is_64) {
126 pci_write_config_dword(dev, msi_upper_address_reg(pos),
128 pci_write_config_word(dev, msi_data_reg(pos, 1),
131 pci_write_config_word(dev, msi_data_reg(pos, 0),
136 case PCI_CAP_ID_MSIX:
139 base = entry->mask_base +
140 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
142 writel(msg->address_lo,
143 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
144 writel(msg->address_hi,
145 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
146 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
154 void mask_msi_irq(unsigned int irq)
156 msi_set_mask_bit(irq, 1);
159 void unmask_msi_irq(unsigned int irq)
161 msi_set_mask_bit(irq, 0);
164 static int msi_free_irq(struct pci_dev* dev, int irq);
166 static int msi_init(void)
168 static int status = -ENOMEM;
173 status = msi_cache_init();
176 printk(KERN_WARNING "PCI: MSI cache init failed\n");
183 static struct msi_desc* alloc_msi_entry(void)
185 struct msi_desc *entry;
187 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
191 entry->link.tail = entry->link.head = 0; /* single message */
197 static void attach_msi_entry(struct msi_desc *entry, int irq)
201 spin_lock_irqsave(&msi_lock, flags);
202 msi_desc[irq] = entry;
203 spin_unlock_irqrestore(&msi_lock, flags);
206 static int create_msi_irq(void)
208 struct msi_desc *entry;
211 entry = alloc_msi_entry();
217 kmem_cache_free(msi_cachep, entry);
221 set_irq_data(irq, entry);
226 static void destroy_msi_irq(unsigned int irq)
228 struct msi_desc *entry;
230 entry = get_irq_data(irq);
231 set_irq_chip(irq, NULL);
232 set_irq_data(irq, NULL);
234 kmem_cache_free(msi_cachep, entry);
237 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
241 pci_read_config_word(dev, msi_control_reg(pos), &control);
242 if (type == PCI_CAP_ID_MSI) {
243 /* Set enabled bits to single MSI & enable MSI_enable bit */
244 msi_enable(control, 1);
245 pci_write_config_word(dev, msi_control_reg(pos), control);
246 dev->msi_enabled = 1;
248 msix_enable(control);
249 pci_write_config_word(dev, msi_control_reg(pos), control);
250 dev->msix_enabled = 1;
253 pci_intx(dev, 0); /* disable intx */
256 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
260 pci_read_config_word(dev, msi_control_reg(pos), &control);
261 if (type == PCI_CAP_ID_MSI) {
262 /* Set enabled bits to single MSI & enable MSI_enable bit */
263 msi_disable(control);
264 pci_write_config_word(dev, msi_control_reg(pos), control);
265 dev->msi_enabled = 0;
267 msix_disable(control);
268 pci_write_config_word(dev, msi_control_reg(pos), control);
269 dev->msix_enabled = 0;
272 pci_intx(dev, 1); /* enable intx */
275 static int msi_lookup_irq(struct pci_dev *dev, int type)
280 spin_lock_irqsave(&msi_lock, flags);
281 for (irq = 0; irq < NR_IRQS; irq++) {
282 if (!msi_desc[irq] || msi_desc[irq]->dev != dev ||
283 msi_desc[irq]->msi_attrib.type != type ||
284 msi_desc[irq]->msi_attrib.default_irq != dev->irq)
286 spin_unlock_irqrestore(&msi_lock, flags);
287 /* This pre-assigned MSI irq for this device
288 already exists. Override dev->irq with this irq */
292 spin_unlock_irqrestore(&msi_lock, flags);
297 void pci_scan_msi_device(struct pci_dev *dev)
304 int pci_save_msi_state(struct pci_dev *dev)
308 struct pci_cap_saved_state *save_state;
311 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
312 if (pos <= 0 || dev->no_msi)
315 pci_read_config_word(dev, msi_control_reg(pos), &control);
316 if (!(control & PCI_MSI_FLAGS_ENABLE))
319 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
322 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
325 cap = &save_state->data[0];
327 pci_read_config_dword(dev, pos, &cap[i++]);
328 control = cap[0] >> 16;
329 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
330 if (control & PCI_MSI_FLAGS_64BIT) {
331 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
332 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
334 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
335 if (control & PCI_MSI_FLAGS_MASKBIT)
336 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
337 save_state->cap_nr = PCI_CAP_ID_MSI;
338 pci_add_saved_cap(dev, save_state);
342 void pci_restore_msi_state(struct pci_dev *dev)
346 struct pci_cap_saved_state *save_state;
349 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
350 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
351 if (!save_state || pos <= 0)
353 cap = &save_state->data[0];
355 control = cap[i++] >> 16;
356 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
357 if (control & PCI_MSI_FLAGS_64BIT) {
358 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
359 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
361 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
362 if (control & PCI_MSI_FLAGS_MASKBIT)
363 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
364 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
365 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
366 pci_remove_saved_cap(save_state);
370 int pci_save_msix_state(struct pci_dev *dev)
374 int irq, head, tail = 0;
376 struct pci_cap_saved_state *save_state;
378 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
379 if (pos <= 0 || dev->no_msi)
382 /* save the capability */
383 pci_read_config_word(dev, msi_control_reg(pos), &control);
384 if (!(control & PCI_MSIX_FLAGS_ENABLE))
386 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
389 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
392 *((u16 *)&save_state->data[0]) = control;
396 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
401 irq = head = dev->irq;
402 while (head != tail) {
403 struct msi_desc *entry;
405 entry = msi_desc[irq];
406 read_msi_msg(irq, &entry->msg_save);
408 tail = msi_desc[irq]->link.tail;
413 save_state->cap_nr = PCI_CAP_ID_MSIX;
414 pci_add_saved_cap(dev, save_state);
418 void pci_restore_msix_state(struct pci_dev *dev)
422 int irq, head, tail = 0;
423 struct msi_desc *entry;
425 struct pci_cap_saved_state *save_state;
427 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
430 save = *((u16 *)&save_state->data[0]);
431 pci_remove_saved_cap(save_state);
434 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
438 /* route the table */
440 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX))
442 irq = head = dev->irq;
443 while (head != tail) {
444 entry = msi_desc[irq];
445 write_msi_msg(irq, &entry->msg_save);
447 tail = msi_desc[irq]->link.tail;
452 pci_write_config_word(dev, msi_control_reg(pos), save);
453 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
455 #endif /* CONFIG_PM */
458 * msi_capability_init - configure device's MSI capability structure
459 * @dev: pointer to the pci_dev data structure of MSI device function
461 * Setup the MSI capability structure of device function with a single
462 * MSI irq, regardless of device function is capable of handling
463 * multiple messages. A return of zero indicates the successful setup
464 * of an entry zero with the new MSI irq or non-zero for otherwise.
466 static int msi_capability_init(struct pci_dev *dev)
469 struct msi_desc *entry;
473 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
474 pci_read_config_word(dev, msi_control_reg(pos), &control);
475 /* MSI Entry Initialization */
476 irq = create_msi_irq();
480 entry = get_irq_data(irq);
481 entry->link.head = irq;
482 entry->link.tail = irq;
483 entry->msi_attrib.type = PCI_CAP_ID_MSI;
484 entry->msi_attrib.is_64 = is_64bit_address(control);
485 entry->msi_attrib.entry_nr = 0;
486 entry->msi_attrib.maskbit = is_mask_bit_support(control);
487 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
488 entry->msi_attrib.pos = pos;
489 if (is_mask_bit_support(control)) {
490 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
491 is_64bit_address(control));
494 if (entry->msi_attrib.maskbit) {
495 unsigned int maskbits, temp;
496 /* All MSIs are unmasked by default, Mask them all */
497 pci_read_config_dword(dev,
498 msi_mask_bits_reg(pos, is_64bit_address(control)),
500 temp = (1 << multi_msi_capable(control));
501 temp = ((temp - 1) & ~temp);
503 pci_write_config_dword(dev,
504 msi_mask_bits_reg(pos, is_64bit_address(control)),
507 /* Configure MSI capability structure */
508 status = arch_setup_msi_irq(irq, dev);
510 destroy_msi_irq(irq);
514 attach_msi_entry(entry, irq);
515 /* Set MSI enabled bits */
516 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
523 * msix_capability_init - configure device's MSI-X capability
524 * @dev: pointer to the pci_dev data structure of MSI-X device function
525 * @entries: pointer to an array of struct msix_entry entries
526 * @nvec: number of @entries
528 * Setup the MSI-X capability structure of device function with a
529 * single MSI-X irq. A return of zero indicates the successful setup of
530 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
532 static int msix_capability_init(struct pci_dev *dev,
533 struct msix_entry *entries, int nvec)
535 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
537 int irq, pos, i, j, nr_entries, temp = 0;
538 unsigned long phys_addr;
544 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
545 /* Request & Map MSI-X table region */
546 pci_read_config_word(dev, msi_control_reg(pos), &control);
547 nr_entries = multi_msix_capable(control);
549 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
550 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
551 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
552 phys_addr = pci_resource_start (dev, bir) + table_offset;
553 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
557 /* MSI-X Table Initialization */
558 for (i = 0; i < nvec; i++) {
559 irq = create_msi_irq();
563 entry = get_irq_data(irq);
564 j = entries[i].entry;
565 entries[i].vector = irq;
566 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
567 entry->msi_attrib.is_64 = 1;
568 entry->msi_attrib.entry_nr = j;
569 entry->msi_attrib.maskbit = 1;
570 entry->msi_attrib.default_irq = dev->irq;
571 entry->msi_attrib.pos = pos;
573 entry->mask_base = base;
575 entry->link.head = irq;
576 entry->link.tail = irq;
579 entry->link.head = temp;
580 entry->link.tail = tail->link.tail;
581 tail->link.tail = irq;
582 head->link.head = irq;
586 /* Configure MSI-X capability structure */
587 status = arch_setup_msi_irq(irq, dev);
589 destroy_msi_irq(irq);
593 attach_msi_entry(entry, irq);
598 for (; i >= 0; i--) {
599 irq = (entries + i)->vector;
600 msi_free_irq(dev, irq);
601 (entries + i)->vector = 0;
603 /* If we had some success report the number of irqs
604 * we succeeded in setting up.
610 /* Set MSI-X enabled bits */
611 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
617 * pci_msi_supported - check whether MSI may be enabled on device
618 * @dev: pointer to the pci_dev data structure of MSI device function
620 * Look at global flags, the device itself, and its parent busses
621 * to return 0 if MSI are supported for the device.
624 int pci_msi_supported(struct pci_dev * dev)
628 /* MSI must be globally enabled and supported by the device */
629 if (!pci_msi_enable || !dev || dev->no_msi)
632 /* Any bridge which does NOT route MSI transactions from it's
633 * secondary bus to it's primary bus must set NO_MSI flag on
634 * the secondary pci_bus.
635 * We expect only arch-specific PCI host bus controller driver
636 * or quirks for specific PCI bridges to be setting NO_MSI.
638 for (bus = dev->bus; bus; bus = bus->parent)
639 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
646 * pci_enable_msi - configure device's MSI capability structure
647 * @dev: pointer to the pci_dev data structure of MSI device function
649 * Setup the MSI capability structure of device function with
650 * a single MSI irq upon its software driver call to request for
651 * MSI mode enabled on its hardware device function. A return of zero
652 * indicates the successful setup of an entry zero with the new MSI
653 * irq or non-zero for otherwise.
655 int pci_enable_msi(struct pci_dev* dev)
657 int pos, temp, status;
659 if (pci_msi_supported(dev) < 0)
668 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
672 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI));
674 /* Check whether driver already requested for MSI-X irqs */
675 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
676 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
677 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
678 "Device already has MSI-X irq assigned\n",
683 status = msi_capability_init(dev);
687 void pci_disable_msi(struct pci_dev* dev)
689 struct msi_desc *entry;
690 int pos, default_irq;
699 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
703 pci_read_config_word(dev, msi_control_reg(pos), &control);
704 if (!(control & PCI_MSI_FLAGS_ENABLE))
707 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
709 spin_lock_irqsave(&msi_lock, flags);
710 entry = msi_desc[dev->irq];
711 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
712 spin_unlock_irqrestore(&msi_lock, flags);
715 if (irq_has_action(dev->irq)) {
716 spin_unlock_irqrestore(&msi_lock, flags);
717 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
718 "free_irq() on MSI irq %d\n",
719 pci_name(dev), dev->irq);
720 BUG_ON(irq_has_action(dev->irq));
722 default_irq = entry->msi_attrib.default_irq;
723 spin_unlock_irqrestore(&msi_lock, flags);
724 msi_free_irq(dev, dev->irq);
726 /* Restore dev->irq to its default pin-assertion irq */
727 dev->irq = default_irq;
731 static int msi_free_irq(struct pci_dev* dev, int irq)
733 struct msi_desc *entry;
734 int head, entry_nr, type;
738 arch_teardown_msi_irq(irq);
740 spin_lock_irqsave(&msi_lock, flags);
741 entry = msi_desc[irq];
742 if (!entry || entry->dev != dev) {
743 spin_unlock_irqrestore(&msi_lock, flags);
746 type = entry->msi_attrib.type;
747 entry_nr = entry->msi_attrib.entry_nr;
748 head = entry->link.head;
749 base = entry->mask_base;
750 msi_desc[entry->link.head]->link.tail = entry->link.tail;
751 msi_desc[entry->link.tail]->link.head = entry->link.head;
753 msi_desc[irq] = NULL;
754 spin_unlock_irqrestore(&msi_lock, flags);
756 destroy_msi_irq(irq);
758 if (type == PCI_CAP_ID_MSIX) {
759 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
760 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
770 * pci_enable_msix - configure device's MSI-X capability structure
771 * @dev: pointer to the pci_dev data structure of MSI-X device function
772 * @entries: pointer to an array of MSI-X entries
773 * @nvec: number of MSI-X irqs requested for allocation by device driver
775 * Setup the MSI-X capability structure of device function with the number
776 * of requested irqs upon its software driver call to request for
777 * MSI-X mode enabled on its hardware device function. A return of zero
778 * indicates the successful configuration of MSI-X capability structure
779 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
780 * Or a return of > 0 indicates that driver request is exceeding the number
781 * of irqs available. Driver should use the returned value to re-send
784 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
786 int status, pos, nr_entries;
790 if (!entries || pci_msi_supported(dev) < 0)
797 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
801 pci_read_config_word(dev, msi_control_reg(pos), &control);
802 nr_entries = multi_msix_capable(control);
803 if (nvec > nr_entries)
806 /* Check for any invalid entries */
807 for (i = 0; i < nvec; i++) {
808 if (entries[i].entry >= nr_entries)
809 return -EINVAL; /* invalid entry */
810 for (j = i + 1; j < nvec; j++) {
811 if (entries[i].entry == entries[j].entry)
812 return -EINVAL; /* duplicate entry */
816 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX));
818 /* Check whether driver already requested for MSI irq */
819 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
820 !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
821 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
822 "Device already has an MSI irq assigned\n",
827 status = msix_capability_init(dev, entries, nvec);
831 void pci_disable_msix(struct pci_dev* dev)
841 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
845 pci_read_config_word(dev, msi_control_reg(pos), &control);
846 if (!(control & PCI_MSIX_FLAGS_ENABLE))
849 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
852 if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
853 int irq, head, tail = 0, warning = 0;
856 irq = head = dev->irq;
857 dev->irq = temp; /* Restore pin IRQ */
858 while (head != tail) {
859 spin_lock_irqsave(&msi_lock, flags);
860 tail = msi_desc[irq]->link.tail;
861 spin_unlock_irqrestore(&msi_lock, flags);
862 if (irq_has_action(irq))
864 else if (irq != head) /* Release MSI-X irq */
865 msi_free_irq(dev, irq);
868 msi_free_irq(dev, irq);
870 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
871 "free_irq() on all MSI-X irqs\n",
879 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
880 * @dev: pointer to the pci_dev data structure of MSI(X) device function
882 * Being called during hotplug remove, from which the device function
883 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
884 * allocated for this device function, are reclaimed to unused state,
885 * which may be used later on.
887 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
892 if (!pci_msi_enable || !dev)
895 temp = dev->irq; /* Save IOAPIC IRQ */
896 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
897 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
898 if (irq_has_action(dev->irq)) {
899 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
900 "called without free_irq() on MSI irq %d\n",
901 pci_name(dev), dev->irq);
902 BUG_ON(irq_has_action(dev->irq));
903 } else /* Release MSI irq assigned to this device */
904 msi_free_irq(dev, dev->irq);
905 dev->irq = temp; /* Restore IOAPIC IRQ */
907 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
908 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
909 int irq, head, tail = 0, warning = 0;
910 void __iomem *base = NULL;
912 irq = head = dev->irq;
913 while (head != tail) {
914 spin_lock_irqsave(&msi_lock, flags);
915 tail = msi_desc[irq]->link.tail;
916 base = msi_desc[irq]->mask_base;
917 spin_unlock_irqrestore(&msi_lock, flags);
918 if (irq_has_action(irq))
920 else if (irq != head) /* Release MSI-X irq */
921 msi_free_irq(dev, irq);
924 msi_free_irq(dev, irq);
927 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
928 "called without free_irq() on all MSI-X irqs\n",
932 dev->irq = temp; /* Restore IOAPIC IRQ */
936 void pci_no_msi(void)
941 EXPORT_SYMBOL(pci_enable_msi);
942 EXPORT_SYMBOL(pci_disable_msi);
943 EXPORT_SYMBOL(pci_enable_msix);
944 EXPORT_SYMBOL(pci_disable_msix);