3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
20 #include <asm/errno.h>
27 static DEFINE_SPINLOCK(msi_lock);
28 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
29 static struct kmem_cache* msi_cachep;
31 static int pci_msi_enable = 1;
33 static int msi_cache_init(void)
35 msi_cachep = kmem_cache_create("msi_cache", sizeof(struct msi_desc),
36 0, SLAB_HWCACHE_ALIGN, NULL, NULL);
43 static void msi_set_mask_bit(unsigned int irq, int flag)
45 struct msi_desc *entry;
47 entry = msi_desc[irq];
48 BUG_ON(!entry || !entry->dev);
49 switch (entry->msi_attrib.type) {
51 if (entry->msi_attrib.maskbit) {
55 pos = (long)entry->mask_base;
56 pci_read_config_dword(entry->dev, pos, &mask_bits);
59 pci_write_config_dword(entry->dev, pos, mask_bits);
64 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
65 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
66 writel(flag, entry->mask_base + offset);
75 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
77 struct msi_desc *entry = get_irq_data(irq);
78 switch(entry->msi_attrib.type) {
81 struct pci_dev *dev = entry->dev;
82 int pos = entry->msi_attrib.pos;
85 pci_read_config_dword(dev, msi_lower_address_reg(pos),
87 if (entry->msi_attrib.is_64) {
88 pci_read_config_dword(dev, msi_upper_address_reg(pos),
90 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
93 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
101 base = entry->mask_base +
102 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
104 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
105 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
106 msg->data = readl(base + PCI_MSIX_ENTRY_DATA_OFFSET);
114 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
116 struct msi_desc *entry = get_irq_data(irq);
117 switch (entry->msi_attrib.type) {
120 struct pci_dev *dev = entry->dev;
121 int pos = entry->msi_attrib.pos;
123 pci_write_config_dword(dev, msi_lower_address_reg(pos),
125 if (entry->msi_attrib.is_64) {
126 pci_write_config_dword(dev, msi_upper_address_reg(pos),
128 pci_write_config_word(dev, msi_data_reg(pos, 1),
131 pci_write_config_word(dev, msi_data_reg(pos, 0),
136 case PCI_CAP_ID_MSIX:
139 base = entry->mask_base +
140 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
142 writel(msg->address_lo,
143 base + PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
144 writel(msg->address_hi,
145 base + PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
146 writel(msg->data, base + PCI_MSIX_ENTRY_DATA_OFFSET);
154 void mask_msi_irq(unsigned int irq)
156 msi_set_mask_bit(irq, 1);
159 void unmask_msi_irq(unsigned int irq)
161 msi_set_mask_bit(irq, 0);
164 static int msi_free_irq(struct pci_dev* dev, int irq);
166 static int msi_init(void)
168 static int status = -ENOMEM;
173 status = msi_cache_init();
176 printk(KERN_WARNING "PCI: MSI cache init failed\n");
183 static struct msi_desc* alloc_msi_entry(void)
185 struct msi_desc *entry;
187 entry = kmem_cache_zalloc(msi_cachep, GFP_KERNEL);
191 entry->link.tail = entry->link.head = 0; /* single message */
197 static void attach_msi_entry(struct msi_desc *entry, int irq)
201 spin_lock_irqsave(&msi_lock, flags);
202 msi_desc[irq] = entry;
203 spin_unlock_irqrestore(&msi_lock, flags);
206 static int create_msi_irq(void)
208 struct msi_desc *entry;
211 entry = alloc_msi_entry();
217 kmem_cache_free(msi_cachep, entry);
221 set_irq_data(irq, entry);
226 static void destroy_msi_irq(unsigned int irq)
228 struct msi_desc *entry;
230 entry = get_irq_data(irq);
231 set_irq_chip(irq, NULL);
232 set_irq_data(irq, NULL);
234 kmem_cache_free(msi_cachep, entry);
237 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
241 pci_read_config_word(dev, msi_control_reg(pos), &control);
242 if (type == PCI_CAP_ID_MSI) {
243 /* Set enabled bits to single MSI & enable MSI_enable bit */
244 msi_enable(control, 1);
245 pci_write_config_word(dev, msi_control_reg(pos), control);
246 dev->msi_enabled = 1;
248 msix_enable(control);
249 pci_write_config_word(dev, msi_control_reg(pos), control);
250 dev->msix_enabled = 1;
253 pci_intx(dev, 0); /* disable intx */
256 void disable_msi_mode(struct pci_dev *dev, int pos, int type)
260 pci_read_config_word(dev, msi_control_reg(pos), &control);
261 if (type == PCI_CAP_ID_MSI) {
262 /* Set enabled bits to single MSI & enable MSI_enable bit */
263 msi_disable(control);
264 pci_write_config_word(dev, msi_control_reg(pos), control);
265 dev->msi_enabled = 0;
267 msix_disable(control);
268 pci_write_config_word(dev, msi_control_reg(pos), control);
269 dev->msix_enabled = 0;
272 pci_intx(dev, 1); /* enable intx */
275 static int msi_lookup_irq(struct pci_dev *dev, int type)
280 spin_lock_irqsave(&msi_lock, flags);
281 for (irq = 0; irq < NR_IRQS; irq++) {
282 if (!msi_desc[irq] || msi_desc[irq]->dev != dev ||
283 msi_desc[irq]->msi_attrib.type != type ||
284 msi_desc[irq]->msi_attrib.default_irq != dev->irq)
286 spin_unlock_irqrestore(&msi_lock, flags);
287 /* This pre-assigned MSI irq for this device
288 already exists. Override dev->irq with this irq */
292 spin_unlock_irqrestore(&msi_lock, flags);
298 int pci_save_msi_state(struct pci_dev *dev)
302 struct pci_cap_saved_state *save_state;
305 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
306 if (pos <= 0 || dev->no_msi)
309 pci_read_config_word(dev, msi_control_reg(pos), &control);
310 if (!(control & PCI_MSI_FLAGS_ENABLE))
313 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u32) * 5,
316 printk(KERN_ERR "Out of memory in pci_save_msi_state\n");
319 cap = &save_state->data[0];
321 pci_read_config_dword(dev, pos, &cap[i++]);
322 control = cap[0] >> 16;
323 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, &cap[i++]);
324 if (control & PCI_MSI_FLAGS_64BIT) {
325 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, &cap[i++]);
326 pci_read_config_dword(dev, pos + PCI_MSI_DATA_64, &cap[i++]);
328 pci_read_config_dword(dev, pos + PCI_MSI_DATA_32, &cap[i++]);
329 if (control & PCI_MSI_FLAGS_MASKBIT)
330 pci_read_config_dword(dev, pos + PCI_MSI_MASK_BIT, &cap[i++]);
331 save_state->cap_nr = PCI_CAP_ID_MSI;
332 pci_add_saved_cap(dev, save_state);
336 void pci_restore_msi_state(struct pci_dev *dev)
340 struct pci_cap_saved_state *save_state;
343 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSI);
344 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
345 if (!save_state || pos <= 0)
347 cap = &save_state->data[0];
349 control = cap[i++] >> 16;
350 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO, cap[i++]);
351 if (control & PCI_MSI_FLAGS_64BIT) {
352 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI, cap[i++]);
353 pci_write_config_dword(dev, pos + PCI_MSI_DATA_64, cap[i++]);
355 pci_write_config_dword(dev, pos + PCI_MSI_DATA_32, cap[i++]);
356 if (control & PCI_MSI_FLAGS_MASKBIT)
357 pci_write_config_dword(dev, pos + PCI_MSI_MASK_BIT, cap[i++]);
358 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
359 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
360 pci_remove_saved_cap(save_state);
364 int pci_save_msix_state(struct pci_dev *dev)
368 int irq, head, tail = 0;
370 struct pci_cap_saved_state *save_state;
372 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
373 if (pos <= 0 || dev->no_msi)
376 /* save the capability */
377 pci_read_config_word(dev, msi_control_reg(pos), &control);
378 if (!(control & PCI_MSIX_FLAGS_ENABLE))
380 save_state = kzalloc(sizeof(struct pci_cap_saved_state) + sizeof(u16),
383 printk(KERN_ERR "Out of memory in pci_save_msix_state\n");
386 *((u16 *)&save_state->data[0]) = control;
390 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
395 irq = head = dev->irq;
396 while (head != tail) {
397 struct msi_desc *entry;
399 entry = msi_desc[irq];
400 read_msi_msg(irq, &entry->msg_save);
402 tail = msi_desc[irq]->link.tail;
407 save_state->cap_nr = PCI_CAP_ID_MSIX;
408 pci_add_saved_cap(dev, save_state);
412 void pci_restore_msix_state(struct pci_dev *dev)
416 int irq, head, tail = 0;
417 struct msi_desc *entry;
419 struct pci_cap_saved_state *save_state;
421 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_MSIX);
424 save = *((u16 *)&save_state->data[0]);
425 pci_remove_saved_cap(save_state);
428 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
432 /* route the table */
434 if (msi_lookup_irq(dev, PCI_CAP_ID_MSIX))
436 irq = head = dev->irq;
437 while (head != tail) {
438 entry = msi_desc[irq];
439 write_msi_msg(irq, &entry->msg_save);
441 tail = msi_desc[irq]->link.tail;
446 pci_write_config_word(dev, msi_control_reg(pos), save);
447 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
449 #endif /* CONFIG_PM */
452 * msi_capability_init - configure device's MSI capability structure
453 * @dev: pointer to the pci_dev data structure of MSI device function
455 * Setup the MSI capability structure of device function with a single
456 * MSI irq, regardless of device function is capable of handling
457 * multiple messages. A return of zero indicates the successful setup
458 * of an entry zero with the new MSI irq or non-zero for otherwise.
460 static int msi_capability_init(struct pci_dev *dev)
463 struct msi_desc *entry;
467 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
468 pci_read_config_word(dev, msi_control_reg(pos), &control);
469 /* MSI Entry Initialization */
470 irq = create_msi_irq();
474 entry = get_irq_data(irq);
475 entry->link.head = irq;
476 entry->link.tail = irq;
477 entry->msi_attrib.type = PCI_CAP_ID_MSI;
478 entry->msi_attrib.is_64 = is_64bit_address(control);
479 entry->msi_attrib.entry_nr = 0;
480 entry->msi_attrib.maskbit = is_mask_bit_support(control);
481 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
482 entry->msi_attrib.pos = pos;
483 if (is_mask_bit_support(control)) {
484 entry->mask_base = (void __iomem *)(long)msi_mask_bits_reg(pos,
485 is_64bit_address(control));
488 if (entry->msi_attrib.maskbit) {
489 unsigned int maskbits, temp;
490 /* All MSIs are unmasked by default, Mask them all */
491 pci_read_config_dword(dev,
492 msi_mask_bits_reg(pos, is_64bit_address(control)),
494 temp = (1 << multi_msi_capable(control));
495 temp = ((temp - 1) & ~temp);
497 pci_write_config_dword(dev,
498 msi_mask_bits_reg(pos, is_64bit_address(control)),
501 /* Configure MSI capability structure */
502 status = arch_setup_msi_irq(irq, dev);
504 destroy_msi_irq(irq);
508 attach_msi_entry(entry, irq);
509 /* Set MSI enabled bits */
510 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
517 * msix_capability_init - configure device's MSI-X capability
518 * @dev: pointer to the pci_dev data structure of MSI-X device function
519 * @entries: pointer to an array of struct msix_entry entries
520 * @nvec: number of @entries
522 * Setup the MSI-X capability structure of device function with a
523 * single MSI-X irq. A return of zero indicates the successful setup of
524 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
526 static int msix_capability_init(struct pci_dev *dev,
527 struct msix_entry *entries, int nvec)
529 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
531 int irq, pos, i, j, nr_entries, temp = 0;
532 unsigned long phys_addr;
538 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
539 /* Request & Map MSI-X table region */
540 pci_read_config_word(dev, msi_control_reg(pos), &control);
541 nr_entries = multi_msix_capable(control);
543 pci_read_config_dword(dev, msix_table_offset_reg(pos), &table_offset);
544 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
545 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
546 phys_addr = pci_resource_start (dev, bir) + table_offset;
547 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
551 /* MSI-X Table Initialization */
552 for (i = 0; i < nvec; i++) {
553 irq = create_msi_irq();
557 entry = get_irq_data(irq);
558 j = entries[i].entry;
559 entries[i].vector = irq;
560 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
561 entry->msi_attrib.is_64 = 1;
562 entry->msi_attrib.entry_nr = j;
563 entry->msi_attrib.maskbit = 1;
564 entry->msi_attrib.default_irq = dev->irq;
565 entry->msi_attrib.pos = pos;
567 entry->mask_base = base;
569 entry->link.head = irq;
570 entry->link.tail = irq;
573 entry->link.head = temp;
574 entry->link.tail = tail->link.tail;
575 tail->link.tail = irq;
576 head->link.head = irq;
580 /* Configure MSI-X capability structure */
581 status = arch_setup_msi_irq(irq, dev);
583 destroy_msi_irq(irq);
587 attach_msi_entry(entry, irq);
592 for (; i >= 0; i--) {
593 irq = (entries + i)->vector;
594 msi_free_irq(dev, irq);
595 (entries + i)->vector = 0;
597 /* If we had some success report the number of irqs
598 * we succeeded in setting up.
604 /* Set MSI-X enabled bits */
605 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
611 * pci_msi_supported - check whether MSI may be enabled on device
612 * @dev: pointer to the pci_dev data structure of MSI device function
614 * Look at global flags, the device itself, and its parent busses
615 * to return 0 if MSI are supported for the device.
618 int pci_msi_supported(struct pci_dev * dev)
622 /* MSI must be globally enabled and supported by the device */
623 if (!pci_msi_enable || !dev || dev->no_msi)
626 /* Any bridge which does NOT route MSI transactions from it's
627 * secondary bus to it's primary bus must set NO_MSI flag on
628 * the secondary pci_bus.
629 * We expect only arch-specific PCI host bus controller driver
630 * or quirks for specific PCI bridges to be setting NO_MSI.
632 for (bus = dev->bus; bus; bus = bus->parent)
633 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
640 * pci_enable_msi - configure device's MSI capability structure
641 * @dev: pointer to the pci_dev data structure of MSI device function
643 * Setup the MSI capability structure of device function with
644 * a single MSI irq upon its software driver call to request for
645 * MSI mode enabled on its hardware device function. A return of zero
646 * indicates the successful setup of an entry zero with the new MSI
647 * irq or non-zero for otherwise.
649 int pci_enable_msi(struct pci_dev* dev)
651 int pos, temp, status;
653 if (pci_msi_supported(dev) < 0)
662 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
666 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSI));
668 /* Check whether driver already requested for MSI-X irqs */
669 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
670 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
671 printk(KERN_INFO "PCI: %s: Can't enable MSI. "
672 "Device already has MSI-X irq assigned\n",
677 status = msi_capability_init(dev);
681 void pci_disable_msi(struct pci_dev* dev)
683 struct msi_desc *entry;
684 int pos, default_irq;
693 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
697 pci_read_config_word(dev, msi_control_reg(pos), &control);
698 if (!(control & PCI_MSI_FLAGS_ENABLE))
701 disable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
703 spin_lock_irqsave(&msi_lock, flags);
704 entry = msi_desc[dev->irq];
705 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
706 spin_unlock_irqrestore(&msi_lock, flags);
709 if (irq_has_action(dev->irq)) {
710 spin_unlock_irqrestore(&msi_lock, flags);
711 printk(KERN_WARNING "PCI: %s: pci_disable_msi() called without "
712 "free_irq() on MSI irq %d\n",
713 pci_name(dev), dev->irq);
714 BUG_ON(irq_has_action(dev->irq));
716 default_irq = entry->msi_attrib.default_irq;
717 spin_unlock_irqrestore(&msi_lock, flags);
718 msi_free_irq(dev, dev->irq);
720 /* Restore dev->irq to its default pin-assertion irq */
721 dev->irq = default_irq;
725 static int msi_free_irq(struct pci_dev* dev, int irq)
727 struct msi_desc *entry;
728 int head, entry_nr, type;
732 arch_teardown_msi_irq(irq);
734 spin_lock_irqsave(&msi_lock, flags);
735 entry = msi_desc[irq];
736 if (!entry || entry->dev != dev) {
737 spin_unlock_irqrestore(&msi_lock, flags);
740 type = entry->msi_attrib.type;
741 entry_nr = entry->msi_attrib.entry_nr;
742 head = entry->link.head;
743 base = entry->mask_base;
744 msi_desc[entry->link.head]->link.tail = entry->link.tail;
745 msi_desc[entry->link.tail]->link.head = entry->link.head;
747 msi_desc[irq] = NULL;
748 spin_unlock_irqrestore(&msi_lock, flags);
750 destroy_msi_irq(irq);
752 if (type == PCI_CAP_ID_MSIX) {
753 writel(1, base + entry_nr * PCI_MSIX_ENTRY_SIZE +
754 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
764 * pci_enable_msix - configure device's MSI-X capability structure
765 * @dev: pointer to the pci_dev data structure of MSI-X device function
766 * @entries: pointer to an array of MSI-X entries
767 * @nvec: number of MSI-X irqs requested for allocation by device driver
769 * Setup the MSI-X capability structure of device function with the number
770 * of requested irqs upon its software driver call to request for
771 * MSI-X mode enabled on its hardware device function. A return of zero
772 * indicates the successful configuration of MSI-X capability structure
773 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
774 * Or a return of > 0 indicates that driver request is exceeding the number
775 * of irqs available. Driver should use the returned value to re-send
778 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
780 int status, pos, nr_entries;
784 if (!entries || pci_msi_supported(dev) < 0)
791 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
795 pci_read_config_word(dev, msi_control_reg(pos), &control);
796 nr_entries = multi_msix_capable(control);
797 if (nvec > nr_entries)
800 /* Check for any invalid entries */
801 for (i = 0; i < nvec; i++) {
802 if (entries[i].entry >= nr_entries)
803 return -EINVAL; /* invalid entry */
804 for (j = i + 1; j < nvec; j++) {
805 if (entries[i].entry == entries[j].entry)
806 return -EINVAL; /* duplicate entry */
810 WARN_ON(!msi_lookup_irq(dev, PCI_CAP_ID_MSIX));
812 /* Check whether driver already requested for MSI irq */
813 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
814 !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
815 printk(KERN_INFO "PCI: %s: Can't enable MSI-X. "
816 "Device already has an MSI irq assigned\n",
821 status = msix_capability_init(dev, entries, nvec);
825 void pci_disable_msix(struct pci_dev* dev)
835 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
839 pci_read_config_word(dev, msi_control_reg(pos), &control);
840 if (!(control & PCI_MSIX_FLAGS_ENABLE))
843 disable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
846 if (!msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
847 int irq, head, tail = 0, warning = 0;
850 irq = head = dev->irq;
851 dev->irq = temp; /* Restore pin IRQ */
852 while (head != tail) {
853 spin_lock_irqsave(&msi_lock, flags);
854 tail = msi_desc[irq]->link.tail;
855 spin_unlock_irqrestore(&msi_lock, flags);
856 if (irq_has_action(irq))
858 else if (irq != head) /* Release MSI-X irq */
859 msi_free_irq(dev, irq);
862 msi_free_irq(dev, irq);
864 printk(KERN_WARNING "PCI: %s: pci_disable_msix() called without "
865 "free_irq() on all MSI-X irqs\n",
873 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
874 * @dev: pointer to the pci_dev data structure of MSI(X) device function
876 * Being called during hotplug remove, from which the device function
877 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
878 * allocated for this device function, are reclaimed to unused state,
879 * which may be used later on.
881 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
886 if (!pci_msi_enable || !dev)
889 temp = dev->irq; /* Save IOAPIC IRQ */
890 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
891 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSI)) {
892 if (irq_has_action(dev->irq)) {
893 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
894 "called without free_irq() on MSI irq %d\n",
895 pci_name(dev), dev->irq);
896 BUG_ON(irq_has_action(dev->irq));
897 } else /* Release MSI irq assigned to this device */
898 msi_free_irq(dev, dev->irq);
899 dev->irq = temp; /* Restore IOAPIC IRQ */
901 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
902 if (pos > 0 && !msi_lookup_irq(dev, PCI_CAP_ID_MSIX)) {
903 int irq, head, tail = 0, warning = 0;
904 void __iomem *base = NULL;
906 irq = head = dev->irq;
907 while (head != tail) {
908 spin_lock_irqsave(&msi_lock, flags);
909 tail = msi_desc[irq]->link.tail;
910 base = msi_desc[irq]->mask_base;
911 spin_unlock_irqrestore(&msi_lock, flags);
912 if (irq_has_action(irq))
914 else if (irq != head) /* Release MSI-X irq */
915 msi_free_irq(dev, irq);
918 msi_free_irq(dev, irq);
921 printk(KERN_WARNING "PCI: %s: msi_remove_pci_irq_vectors() "
922 "called without free_irq() on all MSI-X irqs\n",
926 dev->irq = temp; /* Restore IOAPIC IRQ */
930 void pci_no_msi(void)
935 EXPORT_SYMBOL(pci_enable_msi);
936 EXPORT_SYMBOL(pci_disable_msi);
937 EXPORT_SYMBOL(pci_enable_msix);
938 EXPORT_SYMBOL(pci_disable_msix);