2 * Standard PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
39 #define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
40 #define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
41 #define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
42 #define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
43 #define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
44 #define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
45 /* Redefine this flagword to set debug level */
46 #define DEBUG_LEVEL DBG_K_STANDARD
48 #define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
50 #define DBG_PRINT( dbg_flags, args... ) \
52 if ( DEBUG_LEVEL & ( dbg_flags ) ) \
55 len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
56 __FILE__, __LINE__, __FUNCTION__ ); \
57 sprintf( __dbg_str_buf + len, args ); \
58 printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
62 #define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
63 #define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
65 #define DEFINE_DBG_BUFFER
66 #define DBG_ENTER_ROUTINE
67 #define DBG_LEAVE_ROUTINE
70 /* Slot Available Register I field definition */
71 #define SLOT_33MHZ 0x0000001f
72 #define SLOT_66MHZ_PCIX 0x00001f00
73 #define SLOT_100MHZ_PCIX 0x001f0000
74 #define SLOT_133MHZ_PCIX 0x1f000000
76 /* Slot Available Register II field definition */
77 #define SLOT_66MHZ 0x0000001f
78 #define SLOT_66MHZ_PCIX_266 0x00000f00
79 #define SLOT_100MHZ_PCIX_266 0x0000f000
80 #define SLOT_133MHZ_PCIX_266 0x000f0000
81 #define SLOT_66MHZ_PCIX_533 0x00f00000
82 #define SLOT_100MHZ_PCIX_533 0x0f000000
83 #define SLOT_133MHZ_PCIX_533 0xf0000000
85 /* Slot Configuration */
86 #define SLOT_NUM 0x0000001F
87 #define FIRST_DEV_NUM 0x00001F00
88 #define PSN 0x07FF0000
89 #define UPDOWN 0x20000000
90 #define MRLSENSOR 0x40000000
91 #define ATTN_BUTTON 0x80000000
94 * Controller SERR-INT Register
96 #define GLOBAL_INTR_MASK (1 << 0)
97 #define GLOBAL_SERR_MASK (1 << 1)
98 #define COMMAND_INTR_MASK (1 << 2)
99 #define ARBITER_SERR_MASK (1 << 3)
100 #define COMMAND_DETECTED (1 << 16)
101 #define ARBITER_DETECTED (1 << 17)
102 #define SERR_INTR_RSVDZ_MASK 0xfffc0000
105 * Logical Slot Register definitions
107 #define SLOT_REG(i) (SLOT1 + (4 * i))
109 #define SLOT_STATE_SHIFT (0)
110 #define SLOT_STATE_MASK (3 << 0)
111 #define SLOT_STATE_PWRONLY (1)
112 #define SLOT_STATE_ENABLED (2)
113 #define SLOT_STATE_DISABLED (3)
114 #define PWR_LED_STATE_SHIFT (2)
115 #define PWR_LED_STATE_MASK (3 << 2)
116 #define ATN_LED_STATE_SHIFT (4)
117 #define ATN_LED_STATE_MASK (3 << 4)
118 #define ATN_LED_STATE_ON (1)
119 #define ATN_LED_STATE_BLINK (2)
120 #define ATN_LED_STATE_OFF (3)
121 #define POWER_FAULT (1 << 6)
122 #define ATN_BUTTON (1 << 7)
123 #define MRL_SENSOR (1 << 8)
124 #define MHZ66_CAP (1 << 9)
125 #define PRSNT_SHIFT (10)
126 #define PRSNT_MASK (3 << 10)
127 #define PCIX_CAP_SHIFT (12)
128 #define PCIX_CAP_MASK_PI1 (3 << 12)
129 #define PCIX_CAP_MASK_PI2 (7 << 12)
130 #define PRSNT_CHANGE_DETECTED (1 << 16)
131 #define ISO_PFAULT_DETECTED (1 << 17)
132 #define BUTTON_PRESS_DETECTED (1 << 18)
133 #define MRL_CHANGE_DETECTED (1 << 19)
134 #define CON_PFAULT_DETECTED (1 << 20)
135 #define PRSNT_CHANGE_INTR_MASK (1 << 24)
136 #define ISO_PFAULT_INTR_MASK (1 << 25)
137 #define BUTTON_PRESS_INTR_MASK (1 << 26)
138 #define MRL_CHANGE_INTR_MASK (1 << 27)
139 #define CON_PFAULT_INTR_MASK (1 << 28)
140 #define MRL_CHANGE_SERR_MASK (1 << 29)
141 #define CON_PFAULT_SERR_MASK (1 << 30)
142 #define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
144 /* SHPC 'write' operations/commands */
146 /* Slot operation - 0x00h to 0x3Fh */
148 #define NO_CHANGE 0x00
150 /* Slot state - Bits 0 & 1 of controller command register */
151 #define SET_SLOT_PWR 0x01
152 #define SET_SLOT_ENABLE 0x02
153 #define SET_SLOT_DISABLE 0x03
155 /* Power indicator state - Bits 2 & 3 of controller command register*/
156 #define SET_PWR_ON 0x04
157 #define SET_PWR_BLINK 0x08
158 #define SET_PWR_OFF 0x0C
160 /* Attention indicator state - Bits 4 & 5 of controller command register*/
161 #define SET_ATTN_ON 0x010
162 #define SET_ATTN_BLINK 0x020
163 #define SET_ATTN_OFF 0x030
165 /* Set bus speed/mode A - 0x40h to 0x47h */
166 #define SETA_PCI_33MHZ 0x40
167 #define SETA_PCI_66MHZ 0x41
168 #define SETA_PCIX_66MHZ 0x42
169 #define SETA_PCIX_100MHZ 0x43
170 #define SETA_PCIX_133MHZ 0x44
171 #define RESERV_1 0x45
172 #define RESERV_2 0x46
173 #define RESERV_3 0x47
175 /* Set bus speed/mode B - 0x50h to 0x5fh */
176 #define SETB_PCI_33MHZ 0x50
177 #define SETB_PCI_66MHZ 0x51
178 #define SETB_PCIX_66MHZ_PM 0x52
179 #define SETB_PCIX_100MHZ_PM 0x53
180 #define SETB_PCIX_133MHZ_PM 0x54
181 #define SETB_PCIX_66MHZ_EM 0x55
182 #define SETB_PCIX_100MHZ_EM 0x56
183 #define SETB_PCIX_133MHZ_EM 0x57
184 #define SETB_PCIX_66MHZ_266 0x58
185 #define SETB_PCIX_100MHZ_266 0x59
186 #define SETB_PCIX_133MHZ_266 0x5a
187 #define SETB_PCIX_66MHZ_533 0x5b
188 #define SETB_PCIX_100MHZ_533 0x5c
189 #define SETB_PCIX_133MHZ_533 0x5d
192 /* Power-on all slots - 0x48h */
193 #define SET_PWR_ON_ALL 0x48
195 /* Enable all slots - 0x49h */
196 #define SET_ENABLE_ALL 0x49
198 /* SHPC controller command error code */
199 #define SWITCH_OPEN 0x1
200 #define INVALID_CMD 0x2
201 #define INVALID_SPEED_MODE 0x4
203 /* For accessing SHPC Working Register Set */
204 #define DWORD_SELECT 0x2
205 #define DWORD_DATA 0x4
206 #define BASE_OFFSET 0x0
208 /* Field Offset in Logical Slot Register - byte boundary */
209 #define SLOT_EVENT_LATCH 0x2
210 #define SLOT_SERR_INT_MASK 0x3
212 static spinlock_t hpc_event_lock;
214 DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
215 static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
216 static int ctlr_seq_num = 0; /* Controller sequenc # */
217 static spinlock_t list_lock;
219 static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
221 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
223 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
224 static int hpc_check_cmd_status(struct controller *ctrl);
226 static inline u8 shpc_readb(struct controller *ctrl, int reg)
228 return readb(ctrl->hpc_ctlr_handle->creg + reg);
231 static inline void shpc_writeb(struct controller *ctrl, int reg, u8 val)
233 writeb(val, ctrl->hpc_ctlr_handle->creg + reg);
236 static inline u16 shpc_readw(struct controller *ctrl, int reg)
238 return readw(ctrl->hpc_ctlr_handle->creg + reg);
241 static inline void shpc_writew(struct controller *ctrl, int reg, u16 val)
243 writew(val, ctrl->hpc_ctlr_handle->creg + reg);
246 static inline u32 shpc_readl(struct controller *ctrl, int reg)
248 return readl(ctrl->hpc_ctlr_handle->creg + reg);
251 static inline void shpc_writel(struct controller *ctrl, int reg, u32 val)
253 writel(val, ctrl->hpc_ctlr_handle->creg + reg);
256 static inline int shpc_indirect_read(struct controller *ctrl, int index,
260 u32 cap_offset = ctrl->cap_offset;
261 struct pci_dev *pdev = ctrl->pci_dev;
263 rc = pci_write_config_byte(pdev, cap_offset + DWORD_SELECT, index);
266 return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
269 /* This is the interrupt polling timeout function. */
270 static void int_poll_timeout(unsigned long lphp_ctlr)
272 struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
277 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
281 /* Poll for interrupt events. regs == NULL => polling */
282 shpc_isr( 0, (void *)php_ctlr, NULL );
284 init_timer(&php_ctlr->int_poll_timer);
285 if (!shpchp_poll_time)
286 shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
288 start_int_poll_timer(php_ctlr, shpchp_poll_time);
293 /* This function starts the interrupt polling timer. */
294 static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
297 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
301 if ( ( seconds <= 0 ) || ( seconds > 60 ) )
302 seconds = 2; /* Clamp to sane value */
304 php_ctlr->int_poll_timer.function = &int_poll_timeout;
305 php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
306 php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
307 add_timer(&php_ctlr->int_poll_timer);
312 static inline int shpc_wait_cmd(struct controller *ctrl)
315 unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000;
316 unsigned long timeout = msecs_to_jiffies(timeout_msec);
317 int rc = wait_event_interruptible_timeout(ctrl->queue,
318 !ctrl->cmd_busy, timeout);
321 err("Command not completed in %d msec\n", timeout_msec);
324 info("Command was interrupted by a signal\n");
331 static int shpc_write_cmd(struct slot *slot, u8 t_slot, u8 cmd)
333 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
334 struct controller *ctrl = slot->ctrl;
342 mutex_lock(&slot->ctrl->cmd_lock);
345 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
350 for (i = 0; i < 10; i++) {
351 cmd_status = shpc_readw(ctrl, CMD_STATUS);
353 if (!(cmd_status & 0x1))
355 /* Check every 0.1 sec for a total of 1 sec*/
359 cmd_status = shpc_readw(ctrl, CMD_STATUS);
361 if (cmd_status & 0x1) {
362 /* After 1 sec and and the controller is still busy */
363 err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
369 temp_word = (t_slot << 8) | (cmd & 0xFF);
370 dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
372 /* To make sure the Controller Busy bit is 0 before we send out the
375 slot->ctrl->cmd_busy = 1;
376 shpc_writew(ctrl, CMD, temp_word);
379 * Wait for command completion.
381 retval = shpc_wait_cmd(slot->ctrl);
385 cmd_status = hpc_check_cmd_status(slot->ctrl);
387 err("%s: Failed to issued command 0x%x (error code = %d)\n",
388 __FUNCTION__, cmd, cmd_status);
392 mutex_unlock(&slot->ctrl->cmd_lock);
398 static int hpc_check_cmd_status(struct controller *ctrl)
405 if (!ctrl->hpc_ctlr_handle) {
406 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
410 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
412 switch (cmd_status >> 1) {
417 retval = SWITCH_OPEN;
418 err("%s: Switch opened!\n", __FUNCTION__);
421 retval = INVALID_CMD;
422 err("%s: Invalid HPC command!\n", __FUNCTION__);
425 retval = INVALID_SPEED_MODE;
426 err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
437 static int hpc_get_attention_status(struct slot *slot, u8 *status)
439 struct controller *ctrl = slot->ctrl;
445 if (!slot->ctrl->hpc_ctlr_handle) {
446 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
450 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
451 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
454 case ATN_LED_STATE_ON:
455 *status = 1; /* On */
457 case ATN_LED_STATE_BLINK:
458 *status = 2; /* Blink */
460 case ATN_LED_STATE_OFF:
461 *status = 0; /* Off */
464 *status = 0xFF; /* Reserved */
472 static int hpc_get_power_status(struct slot * slot, u8 *status)
474 struct controller *ctrl = slot->ctrl;
480 if (!slot->ctrl->hpc_ctlr_handle) {
481 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
485 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
486 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
489 case SLOT_STATE_PWRONLY:
490 *status = 2; /* Powered only */
492 case SLOT_STATE_ENABLED:
493 *status = 1; /* Enabled */
495 case SLOT_STATE_DISABLED:
496 *status = 0; /* Disabled */
499 *status = 0xFF; /* Reserved */
508 static int hpc_get_latch_status(struct slot *slot, u8 *status)
510 struct controller *ctrl = slot->ctrl;
515 if (!slot->ctrl->hpc_ctlr_handle) {
516 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
520 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
521 *status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
527 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
529 struct controller *ctrl = slot->ctrl;
535 if (!slot->ctrl->hpc_ctlr_handle) {
536 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
540 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
541 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
542 *status = (state != 0x3) ? 1 : 0;
548 static int hpc_get_prog_int(struct slot *slot, u8 *prog_int)
550 struct controller *ctrl = slot->ctrl;
554 if (!slot->ctrl->hpc_ctlr_handle) {
555 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
559 *prog_int = shpc_readb(ctrl, PROG_INTERFACE);
565 static int hpc_get_adapter_speed(struct slot *slot, enum pci_bus_speed *value)
568 struct controller *ctrl = slot->ctrl;
569 u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
570 u8 m66_cap = !!(slot_reg & MHZ66_CAP);
575 if ((retval = hpc_get_prog_int(slot, &pi)))
580 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI1) >> PCIX_CAP_SHIFT;
583 pcix_cap = (slot_reg & PCIX_CAP_MASK_PI2) >> PCIX_CAP_SHIFT;
589 dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
590 __FUNCTION__, slot_reg, pcix_cap, m66_cap);
594 *value = m66_cap ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
597 *value = PCI_SPEED_66MHz_PCIX;
600 *value = PCI_SPEED_133MHz_PCIX;
603 *value = PCI_SPEED_133MHz_PCIX_266;
606 *value = PCI_SPEED_133MHz_PCIX_533;
610 *value = PCI_SPEED_UNKNOWN;
615 dbg("Adapter speed = %d\n", *value);
620 static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
622 struct controller *ctrl = slot->ctrl;
629 if (!slot->ctrl->hpc_ctlr_handle) {
630 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
634 pi = shpc_readb(ctrl, PROG_INTERFACE);
635 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
638 *mode = (sec_bus_status & 0x0100) >> 8;
643 dbg("Mode 1 ECC cap = %d\n", *mode);
649 static int hpc_query_power_fault(struct slot * slot)
651 struct controller *ctrl = slot->ctrl;
656 if (!slot->ctrl->hpc_ctlr_handle) {
657 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
661 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
664 /* Note: Logic 0 => fault */
665 return !(slot_reg & POWER_FAULT);
668 static int hpc_set_attention_status(struct slot *slot, u8 value)
670 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
674 if (!slot->ctrl->hpc_ctlr_handle) {
675 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
679 if (slot->hp_slot >= php_ctlr->num_slots) {
680 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
686 slot_cmd = 0x30; /* OFF */
689 slot_cmd = 0x10; /* ON */
692 slot_cmd = 0x20; /* BLINK */
698 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
704 static void hpc_set_green_led_on(struct slot *slot)
706 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
709 if (!slot->ctrl->hpc_ctlr_handle) {
710 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
714 if (slot->hp_slot >= php_ctlr->num_slots) {
715 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
721 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
726 static void hpc_set_green_led_off(struct slot *slot)
728 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
731 if (!slot->ctrl->hpc_ctlr_handle) {
732 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
736 if (slot->hp_slot >= php_ctlr->num_slots) {
737 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
743 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
748 static void hpc_set_green_led_blink(struct slot *slot)
750 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
753 if (!slot->ctrl->hpc_ctlr_handle) {
754 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
758 if (slot->hp_slot >= php_ctlr->num_slots) {
759 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
765 shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
770 int shpc_get_ctlr_slot_config(struct controller *ctrl,
771 int *num_ctlr_slots, /* number of slots in this HPC */
772 int *first_device_num, /* PCI dev num of the first slot in this SHPC */
773 int *physical_slot_num, /* phy slot num of the first slot in this SHPC */
774 int *updown, /* physical_slot_num increament: 1 or -1 */
781 if (!ctrl->hpc_ctlr_handle) {
782 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
786 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
787 *first_device_num = (slot_config & FIRST_DEV_NUM) >> 8;
788 *num_ctlr_slots = slot_config & SLOT_NUM;
789 *physical_slot_num = (slot_config & PSN) >> 16;
790 *updown = ((slot_config & UPDOWN) >> 29) ? 1 : -1;
792 dbg("%s: physical_slot_num = %x\n", __FUNCTION__, *physical_slot_num);
798 static void hpc_release_ctlr(struct controller *ctrl)
800 struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
801 struct php_ctlr_state_s *p, *p_prev;
803 u32 slot_reg, serr_int;
807 if (!ctrl->hpc_ctlr_handle) {
808 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
813 * Mask event interrupts and SERRs of all slots
815 for (i = 0; i < ctrl->num_slots; i++) {
816 slot_reg = shpc_readl(ctrl, SLOT_REG(i));
817 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
818 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
819 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
820 CON_PFAULT_SERR_MASK);
821 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
822 shpc_writel(ctrl, SLOT_REG(i), slot_reg);
828 * Mask SERR and System Interrut generation
830 serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
831 serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
832 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
833 serr_int &= ~SERR_INTR_RSVDZ_MASK;
834 shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
836 if (shpchp_poll_mode) {
837 del_timer(&php_ctlr->int_poll_timer);
840 free_irq(php_ctlr->irq, ctrl);
842 pci_disable_msi(php_ctlr->pci_dev);
846 if (php_ctlr->pci_dev) {
847 iounmap(php_ctlr->creg);
848 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
849 php_ctlr->pci_dev = NULL;
852 spin_lock(&list_lock);
853 p = php_ctlr_list_head;
858 p_prev->pnext = p->pnext;
860 php_ctlr_list_head = p->pnext;
867 spin_unlock(&list_lock);
872 * If this is the last controller to be released, destroy the
875 if (atomic_dec_and_test(&shpchp_num_controllers))
876 destroy_workqueue(shpchp_wq);
882 static int hpc_power_on_slot(struct slot * slot)
884 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
890 if (!slot->ctrl->hpc_ctlr_handle) {
891 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
895 if (slot->hp_slot >= php_ctlr->num_slots) {
896 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
901 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
904 err("%s: Write command failed!\n", __FUNCTION__);
913 static int hpc_slot_enable(struct slot * slot)
915 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
921 if (!slot->ctrl->hpc_ctlr_handle) {
922 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
926 if (slot->hp_slot >= php_ctlr->num_slots) {
927 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
930 /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
933 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
936 err("%s: Write command failed!\n", __FUNCTION__);
944 static int hpc_slot_disable(struct slot * slot)
946 struct php_ctlr_state_s *php_ctlr = slot->ctrl->hpc_ctlr_handle;
952 if (!slot->ctrl->hpc_ctlr_handle) {
953 err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
957 if (slot->hp_slot >= php_ctlr->num_slots) {
958 err("%s: Invalid HPC slot number!\n", __FUNCTION__);
962 /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
965 retval = shpc_write_cmd(slot, slot->hp_slot, slot_cmd);
968 err("%s: Write command failed!\n", __FUNCTION__);
976 static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
979 struct controller *ctrl = slot->ctrl;
984 pi = shpc_readb(ctrl, PROG_INTERFACE);
985 if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
989 case PCI_SPEED_33MHz:
990 cmd = SETA_PCI_33MHZ;
992 case PCI_SPEED_66MHz:
993 cmd = SETA_PCI_66MHZ;
995 case PCI_SPEED_66MHz_PCIX:
996 cmd = SETA_PCIX_66MHZ;
998 case PCI_SPEED_100MHz_PCIX:
999 cmd = SETA_PCIX_100MHZ;
1001 case PCI_SPEED_133MHz_PCIX:
1002 cmd = SETA_PCIX_133MHZ;
1004 case PCI_SPEED_66MHz_PCIX_ECC:
1005 cmd = SETB_PCIX_66MHZ_EM;
1007 case PCI_SPEED_100MHz_PCIX_ECC:
1008 cmd = SETB_PCIX_100MHZ_EM;
1010 case PCI_SPEED_133MHz_PCIX_ECC:
1011 cmd = SETB_PCIX_133MHZ_EM;
1013 case PCI_SPEED_66MHz_PCIX_266:
1014 cmd = SETB_PCIX_66MHZ_266;
1016 case PCI_SPEED_100MHz_PCIX_266:
1017 cmd = SETB_PCIX_100MHZ_266;
1019 case PCI_SPEED_133MHz_PCIX_266:
1020 cmd = SETB_PCIX_133MHZ_266;
1022 case PCI_SPEED_66MHz_PCIX_533:
1023 cmd = SETB_PCIX_66MHZ_533;
1025 case PCI_SPEED_100MHz_PCIX_533:
1026 cmd = SETB_PCIX_100MHZ_533;
1028 case PCI_SPEED_133MHz_PCIX_533:
1029 cmd = SETB_PCIX_133MHZ_533;
1035 retval = shpc_write_cmd(slot, 0, cmd);
1037 err("%s: Write command failed!\n", __FUNCTION__);
1043 static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
1045 struct controller *ctrl = NULL;
1046 struct php_ctlr_state_s *php_ctlr;
1047 u8 schedule_flag = 0;
1048 u32 temp_dword, intr_loc, intr_loc2;
1054 if (!shpchp_poll_mode) {
1055 ctrl = (struct controller *)dev_id;
1056 php_ctlr = ctrl->hpc_ctlr_handle;
1058 php_ctlr = (struct php_ctlr_state_s *) dev_id;
1059 ctrl = (struct controller *)php_ctlr->callback_instance_id;
1065 if (!php_ctlr || !php_ctlr->creg)
1068 /* Check to see if it was our interrupt */
1069 intr_loc = shpc_readl(ctrl, INTR_LOC);
1073 dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
1075 if(!shpchp_poll_mode) {
1076 /* Mask Global Interrupt Mask - see implementation note on p. 139 */
1077 /* of SHPC spec rev 1.0*/
1078 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1079 temp_dword |= GLOBAL_INTR_MASK;
1080 temp_dword &= ~SERR_INTR_RSVDZ_MASK;
1081 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
1083 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
1084 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1087 if (intr_loc & 0x0001) {
1089 * Command Complete Interrupt Pending
1090 * RO only - clear by writing 1 to the Command Completion
1091 * Detect bit in Controller SERR-INT register
1093 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1094 temp_dword &= ~SERR_INTR_RSVDZ_MASK;
1095 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
1097 wake_up_interruptible(&ctrl->queue);
1100 if ((intr_loc = (intr_loc >> 1)) == 0)
1103 for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
1104 /* To find out which slot has interrupt pending */
1105 if ((intr_loc >> hp_slot) & 0x01) {
1106 temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot));
1107 dbg("%s: Slot %x with intr, slot register = %x\n",
1108 __FUNCTION__, hp_slot, temp_dword);
1109 if ((php_ctlr->switch_change_callback) &&
1110 (temp_dword & MRL_CHANGE_DETECTED))
1111 schedule_flag += php_ctlr->switch_change_callback(
1112 hp_slot, php_ctlr->callback_instance_id);
1113 if ((php_ctlr->attention_button_callback) &&
1114 (temp_dword & BUTTON_PRESS_DETECTED))
1115 schedule_flag += php_ctlr->attention_button_callback(
1116 hp_slot, php_ctlr->callback_instance_id);
1117 if ((php_ctlr->presence_change_callback) &&
1118 (temp_dword & PRSNT_CHANGE_DETECTED))
1119 schedule_flag += php_ctlr->presence_change_callback(
1120 hp_slot , php_ctlr->callback_instance_id);
1121 if ((php_ctlr->power_fault_callback) &&
1122 (temp_dword & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)))
1123 schedule_flag += php_ctlr->power_fault_callback(
1124 hp_slot, php_ctlr->callback_instance_id);
1126 /* Clear all slot events */
1127 temp_dword &= ~SLOT_REG_RSVDZ_MASK;
1128 shpc_writel(ctrl, SLOT_REG(hp_slot), temp_dword);
1130 intr_loc2 = shpc_readl(ctrl, INTR_LOC);
1131 dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
1135 if (!shpchp_poll_mode) {
1136 /* Unmask Global Interrupt Mask */
1137 temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1138 temp_dword &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
1139 shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
1145 static int hpc_get_max_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1148 struct controller *ctrl = slot->ctrl;
1149 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1150 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
1151 u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
1152 u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
1157 if (slot_avail2 & SLOT_133MHZ_PCIX_533)
1158 bus_speed = PCI_SPEED_133MHz_PCIX_533;
1159 else if (slot_avail2 & SLOT_100MHZ_PCIX_533)
1160 bus_speed = PCI_SPEED_100MHz_PCIX_533;
1161 else if (slot_avail2 & SLOT_66MHZ_PCIX_533)
1162 bus_speed = PCI_SPEED_66MHz_PCIX_533;
1163 else if (slot_avail2 & SLOT_133MHZ_PCIX_266)
1164 bus_speed = PCI_SPEED_133MHz_PCIX_266;
1165 else if (slot_avail2 & SLOT_100MHZ_PCIX_266)
1166 bus_speed = PCI_SPEED_100MHz_PCIX_266;
1167 else if (slot_avail2 & SLOT_66MHZ_PCIX_266)
1168 bus_speed = PCI_SPEED_66MHz_PCIX_266;
1171 if (bus_speed == PCI_SPEED_UNKNOWN) {
1172 if (slot_avail1 & SLOT_133MHZ_PCIX)
1173 bus_speed = PCI_SPEED_133MHz_PCIX;
1174 else if (slot_avail1 & SLOT_100MHZ_PCIX)
1175 bus_speed = PCI_SPEED_100MHz_PCIX;
1176 else if (slot_avail1 & SLOT_66MHZ_PCIX)
1177 bus_speed = PCI_SPEED_66MHz_PCIX;
1178 else if (slot_avail2 & SLOT_66MHZ)
1179 bus_speed = PCI_SPEED_66MHz;
1180 else if (slot_avail1 & SLOT_33MHZ)
1181 bus_speed = PCI_SPEED_33MHz;
1187 dbg("Max bus speed = %d\n", bus_speed);
1192 static int hpc_get_cur_bus_speed (struct slot *slot, enum pci_bus_speed *value)
1195 struct controller *ctrl = slot->ctrl;
1196 enum pci_bus_speed bus_speed = PCI_SPEED_UNKNOWN;
1197 u16 sec_bus_reg = shpc_readw(ctrl, SEC_BUS_CONFIG);
1198 u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
1199 u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
1203 if ((pi == 1) && (speed_mode > 4)) {
1204 *value = PCI_SPEED_UNKNOWN;
1208 switch (speed_mode) {
1210 *value = PCI_SPEED_33MHz;
1213 *value = PCI_SPEED_66MHz;
1216 *value = PCI_SPEED_66MHz_PCIX;
1219 *value = PCI_SPEED_100MHz_PCIX;
1222 *value = PCI_SPEED_133MHz_PCIX;
1225 *value = PCI_SPEED_66MHz_PCIX_ECC;
1228 *value = PCI_SPEED_100MHz_PCIX_ECC;
1231 *value = PCI_SPEED_133MHz_PCIX_ECC;
1234 *value = PCI_SPEED_66MHz_PCIX_266;
1237 *value = PCI_SPEED_100MHz_PCIX_266;
1240 *value = PCI_SPEED_133MHz_PCIX_266;
1243 *value = PCI_SPEED_66MHz_PCIX_533;
1246 *value = PCI_SPEED_100MHz_PCIX_533;
1249 *value = PCI_SPEED_133MHz_PCIX_533;
1252 *value = PCI_SPEED_UNKNOWN;
1257 dbg("Current bus speed = %d\n", bus_speed);
1262 static struct hpc_ops shpchp_hpc_ops = {
1263 .power_on_slot = hpc_power_on_slot,
1264 .slot_enable = hpc_slot_enable,
1265 .slot_disable = hpc_slot_disable,
1266 .set_bus_speed_mode = hpc_set_bus_speed_mode,
1267 .set_attention_status = hpc_set_attention_status,
1268 .get_power_status = hpc_get_power_status,
1269 .get_attention_status = hpc_get_attention_status,
1270 .get_latch_status = hpc_get_latch_status,
1271 .get_adapter_status = hpc_get_adapter_status,
1273 .get_max_bus_speed = hpc_get_max_bus_speed,
1274 .get_cur_bus_speed = hpc_get_cur_bus_speed,
1275 .get_adapter_speed = hpc_get_adapter_speed,
1276 .get_mode1_ECC_cap = hpc_get_mode1_ECC_cap,
1277 .get_prog_int = hpc_get_prog_int,
1279 .query_power_fault = hpc_query_power_fault,
1280 .green_led_on = hpc_set_green_led_on,
1281 .green_led_off = hpc_set_green_led_off,
1282 .green_led_blink = hpc_set_green_led_blink,
1284 .release_ctlr = hpc_release_ctlr,
1287 int shpc_init(struct controller * ctrl, struct pci_dev * pdev)
1289 struct php_ctlr_state_s *php_ctlr, *p;
1290 void *instance_id = ctrl;
1291 int rc, num_slots = 0;
1293 static int first = 1;
1294 u32 shpc_base_offset;
1295 u32 tempdword, slot_reg, slot_config;
1300 ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
1302 spin_lock_init(&list_lock);
1303 php_ctlr = kzalloc(sizeof(*php_ctlr), GFP_KERNEL);
1305 if (!php_ctlr) { /* allocate controller state data */
1306 err("%s: HPC controller memory allocation error!\n", __FUNCTION__);
1310 php_ctlr->pci_dev = pdev; /* save pci_dev in context */
1312 if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
1313 PCI_DEVICE_ID_AMD_GOLAM_7450)) {
1314 /* amd shpc driver doesn't use Base Offset; assume 0 */
1315 ctrl->mmio_base = pci_resource_start(pdev, 0);
1316 ctrl->mmio_size = pci_resource_len(pdev, 0);
1318 ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
1319 if (!ctrl->cap_offset) {
1320 err("%s : cap_offset == 0\n", __FUNCTION__);
1321 goto abort_free_ctlr;
1323 dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
1325 rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
1327 err("%s: cannot read base_offset\n", __FUNCTION__);
1328 goto abort_free_ctlr;
1331 rc = shpc_indirect_read(ctrl, 3, &tempdword);
1333 err("%s: cannot read slot config\n", __FUNCTION__);
1334 goto abort_free_ctlr;
1336 num_slots = tempdword & SLOT_NUM;
1337 dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
1339 for (i = 0; i < 9 + num_slots; i++) {
1340 rc = shpc_indirect_read(ctrl, i, &tempdword);
1342 err("%s: cannot read creg (index = %d)\n",
1344 goto abort_free_ctlr;
1346 dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
1351 pci_resource_start(pdev, 0) + shpc_base_offset;
1352 ctrl->mmio_size = 0x24 + 0x4 * num_slots;
1356 spin_lock_init(&hpc_event_lock);
1360 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
1361 pdev->subsystem_device);
1363 if (pci_enable_device(pdev))
1364 goto abort_free_ctlr;
1366 if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
1367 err("%s: cannot reserve MMIO region\n", __FUNCTION__);
1368 goto abort_free_ctlr;
1371 php_ctlr->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
1372 if (!php_ctlr->creg) {
1373 err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
1374 ctrl->mmio_size, ctrl->mmio_base);
1375 release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
1376 goto abort_free_ctlr;
1378 dbg("%s: php_ctlr->creg %p\n", __FUNCTION__, php_ctlr->creg);
1380 mutex_init(&ctrl->crit_sect);
1381 mutex_init(&ctrl->cmd_lock);
1383 /* Setup wait queue */
1384 init_waitqueue_head(&ctrl->queue);
1387 php_ctlr->irq = pdev->irq;
1388 php_ctlr->attention_button_callback = shpchp_handle_attention_button,
1389 php_ctlr->switch_change_callback = shpchp_handle_switch_change;
1390 php_ctlr->presence_change_callback = shpchp_handle_presence_change;
1391 php_ctlr->power_fault_callback = shpchp_handle_power_fault;
1392 php_ctlr->callback_instance_id = instance_id;
1394 ctrl->hpc_ctlr_handle = php_ctlr;
1395 ctrl->hpc_ops = &shpchp_hpc_ops;
1397 /* Return PCI Controller Info */
1398 slot_config = shpc_readl(ctrl, SLOT_CONFIG);
1399 php_ctlr->slot_device_offset = (slot_config & FIRST_DEV_NUM) >> 8;
1400 php_ctlr->num_slots = slot_config & SLOT_NUM;
1401 dbg("%s: slot_device_offset %x\n", __FUNCTION__, php_ctlr->slot_device_offset);
1402 dbg("%s: num_slots %x\n", __FUNCTION__, php_ctlr->num_slots);
1404 /* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
1405 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1406 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1407 tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
1408 COMMAND_INTR_MASK | ARBITER_SERR_MASK);
1409 tempdword &= ~SERR_INTR_RSVDZ_MASK;
1410 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1411 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1412 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1414 /* Mask the MRL sensor SERR Mask of individual slot in
1415 * Slot SERR-INT Mask & clear all the existing event if any
1417 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1418 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1419 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1421 slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1422 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1423 CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
1424 CON_PFAULT_SERR_MASK);
1425 slot_reg &= ~SLOT_REG_RSVDZ_MASK;
1426 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1429 if (shpchp_poll_mode) {/* Install interrupt polling code */
1430 /* Install and start the interrupt polling timer */
1431 init_timer(&php_ctlr->int_poll_timer);
1432 start_int_poll_timer( php_ctlr, 10 ); /* start with 10 second delay */
1434 /* Installs the interrupt handler */
1435 rc = pci_enable_msi(pdev);
1437 info("Can't get msi for the hotplug controller\n");
1438 info("Use INTx for the hotplug controller\n");
1440 php_ctlr->irq = pdev->irq;
1442 rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
1443 dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
1445 err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
1446 goto abort_free_ctlr;
1449 dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
1450 pdev->bus->number, PCI_SLOT(pdev->devfn),
1451 PCI_FUNC(pdev->devfn), pdev->irq);
1452 get_hp_hw_control_from_firmware(pdev);
1454 /* Add this HPC instance into the HPC list */
1455 spin_lock(&list_lock);
1456 if (php_ctlr_list_head == 0) {
1457 php_ctlr_list_head = php_ctlr;
1458 p = php_ctlr_list_head;
1461 p = php_ctlr_list_head;
1466 p->pnext = php_ctlr;
1468 spin_unlock(&list_lock);
1473 * If this is the first controller to be initialized,
1474 * initialize the shpchpd work queue
1476 if (atomic_add_return(1, &shpchp_num_controllers) == 1) {
1477 shpchp_wq = create_singlethread_workqueue("shpchpd");
1483 * Unmask all event interrupts of all slots
1485 for (hp_slot = 0; hp_slot < php_ctlr->num_slots; hp_slot++) {
1486 slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
1487 dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
1489 slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
1490 BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
1491 CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
1492 shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
1494 if (!shpchp_poll_mode) {
1495 /* Unmask all general input interrupts and SERR */
1496 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1497 tempdword &= ~(GLOBAL_INTR_MASK | COMMAND_INTR_MASK |
1498 SERR_INTR_RSVDZ_MASK);
1499 shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
1500 tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
1501 dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
1507 /* We end up here for the many possible ways to fail this API. */