2 * Standard Hot Plug Controller Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
32 #include <linux/types.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/sched.h> /* signal_pending(), struct timer_list */
36 #include <linux/mutex.h>
38 #include "pci_hotplug.h"
41 #define MY_NAME "shpchp"
43 #define MY_NAME THIS_MODULE->name
46 extern int shpchp_poll_mode;
47 extern int shpchp_poll_time;
48 extern int shpchp_debug;
50 /*#define dbg(format, arg...) do { if (shpchp_debug) printk(KERN_DEBUG "%s: " format, MY_NAME , ## arg); } while (0)*/
51 #define dbg(format, arg...) do { if (shpchp_debug) printk("%s: " format, MY_NAME , ## arg); } while (0)
52 #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME , ## arg)
53 #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME , ## arg)
54 #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME , ## arg)
56 #define SLOT_MAGIC 0x67267321
68 struct timer_list task_event;
70 struct controller *ctrl;
71 struct hpc_ops *hpc_ops;
72 struct hotplug_slot *hotplug_slot;
73 struct list_head slot_list;
82 struct controller *next;
83 struct mutex crit_sect; /* critical section mutex */
84 struct php_ctlr_state_s *hpc_ctlr_handle; /* HPC controller handle */
85 int num_slots; /* Number of slots on ctlr */
86 int slot_num_inc; /* 1 or -1 */
87 struct pci_dev *pci_dev;
88 struct pci_bus *pci_bus;
89 struct event_info event_queue[10];
91 struct hpc_ops *hpc_ops;
92 wait_queue_head_t queue; /* sleep & wake process */
97 u8 slot_device_offset;
99 u32 pcix_misc2_reg; /* for amd pogo errata */
100 enum pci_bus_speed speed;
101 u32 first_slot; /* First physical slot number */
102 u8 slot_bus; /* Bus where the slots handled by this controller sit */
104 unsigned long mmio_base;
105 unsigned long mmio_size;
106 volatile int cmd_busy;
109 struct hotplug_params {
116 /* Define AMD SHPC ID */
117 #define PCI_DEVICE_ID_AMD_GOLAM_7450 0x7450
118 #define PCI_DEVICE_ID_AMD_POGO_7458 0x7458
120 /* AMD PCIX bridge registers */
122 #define PCIX_MEM_BASE_LIMIT_OFFSET 0x1C
123 #define PCIX_MISCII_OFFSET 0x48
124 #define PCIX_MISC_BRIDGE_ERRORS_OFFSET 0x80
126 /* AMD PCIX_MISCII masks and offsets */
127 #define PERRNONFATALENABLE_MASK 0x00040000
128 #define PERRFATALENABLE_MASK 0x00080000
129 #define PERRFLOODENABLE_MASK 0x00100000
130 #define SERRNONFATALENABLE_MASK 0x00200000
131 #define SERRFATALENABLE_MASK 0x00400000
133 /* AMD PCIX_MISC_BRIDGE_ERRORS masks and offsets */
134 #define PERR_OBSERVED_MASK 0x00000001
136 /* AMD PCIX_MEM_BASE_LIMIT masks */
137 #define RSE_MASK 0x40000000
139 #define INT_BUTTON_IGNORE 0
140 #define INT_PRESENCE_ON 1
141 #define INT_PRESENCE_OFF 2
142 #define INT_SWITCH_CLOSE 3
143 #define INT_SWITCH_OPEN 4
144 #define INT_POWER_FAULT 5
145 #define INT_POWER_FAULT_CLEAR 6
146 #define INT_BUTTON_PRESS 7
147 #define INT_BUTTON_RELEASE 8
148 #define INT_BUTTON_CANCEL 9
150 #define STATIC_STATE 0
151 #define BLINKINGON_STATE 1
152 #define BLINKINGOFF_STATE 2
153 #define POWERON_STATE 3
154 #define POWEROFF_STATE 4
156 #define PCI_TO_PCI_BRIDGE_CLASS 0x00060400
159 #define INTERLOCK_OPEN 0x00000002
160 #define ADD_NOT_SUPPORTED 0x00000003
161 #define CARD_FUNCTIONING 0x00000005
162 #define ADAPTER_NOT_SAME 0x00000006
163 #define NO_ADAPTER_PRESENT 0x00000009
164 #define NOT_ENOUGH_RESOURCES 0x0000000B
165 #define DEVICE_TYPE_NOT_SUPPORTED 0x0000000C
166 #define WRONG_BUS_FREQUENCY 0x0000000D
167 #define POWER_FAILURE 0x0000000E
169 #define REMOVE_NOT_SUPPORTED 0x00000003
171 #define DISABLE_CARD 1
176 #define msg_initialization_err "Initialization failure, error=%d\n"
177 #define msg_button_on "PCI slot #%d - powering on due to button press.\n"
178 #define msg_button_off "PCI slot #%d - powering off due to button press.\n"
179 #define msg_button_cancel "PCI slot #%d - action canceled due to button press.\n"
181 /* sysfs functions for the hotplug controller info */
182 extern void shpchp_create_ctrl_files (struct controller *ctrl);
184 /* controller functions */
185 extern int shpchp_event_start_thread(void);
186 extern void shpchp_event_stop_thread(void);
187 extern int shpchp_enable_slot(struct slot *slot);
188 extern int shpchp_disable_slot(struct slot *slot);
190 extern u8 shpchp_handle_attention_button(u8 hp_slot, void *inst_id);
191 extern u8 shpchp_handle_switch_change(u8 hp_slot, void *inst_id);
192 extern u8 shpchp_handle_presence_change(u8 hp_slot, void *inst_id);
193 extern u8 shpchp_handle_power_fault(u8 hp_slot, void *inst_id);
196 extern int shpchp_save_config(struct controller *ctrl, int busnumber, int num_ctlr_slots, int first_device_num);
197 extern int shpchp_configure_device(struct slot *p_slot);
198 extern int shpchp_unconfigure_device(struct slot *p_slot);
199 extern void get_hp_hw_control_from_firmware(struct pci_dev *dev);
200 extern void get_hp_params_from_firmware(struct pci_dev *dev,
201 struct hotplug_params *hpp);
202 extern int shpchprm_get_physical_slot_number(struct controller *ctrl,
203 u32 *sun, u8 busnum, u8 devnum);
204 extern void shpchp_remove_ctrl_files(struct controller *ctrl);
207 /* Global variables */
208 extern struct controller *shpchp_ctrl_list;
211 volatile u32 base_offset;
212 volatile u32 slot_avail1;
213 volatile u32 slot_avail2;
214 volatile u32 slot_config;
215 volatile u16 sec_bus_config;
216 volatile u8 msi_ctrl;
217 volatile u8 prog_interface;
219 volatile u16 cmd_status;
220 volatile u32 intr_loc;
221 volatile u32 serr_loc;
222 volatile u32 serr_intr_enable;
235 } __attribute__ ((packed));
237 /* offsets to the controller registers based on the above structure layout */
239 BASE_OFFSET = offsetof(struct ctrl_reg, base_offset),
240 SLOT_AVAIL1 = offsetof(struct ctrl_reg, slot_avail1),
241 SLOT_AVAIL2 = offsetof(struct ctrl_reg, slot_avail2),
242 SLOT_CONFIG = offsetof(struct ctrl_reg, slot_config),
243 SEC_BUS_CONFIG = offsetof(struct ctrl_reg, sec_bus_config),
244 MSI_CTRL = offsetof(struct ctrl_reg, msi_ctrl),
245 PROG_INTERFACE = offsetof(struct ctrl_reg, prog_interface),
246 CMD = offsetof(struct ctrl_reg, cmd),
247 CMD_STATUS = offsetof(struct ctrl_reg, cmd_status),
248 INTR_LOC = offsetof(struct ctrl_reg, intr_loc),
249 SERR_LOC = offsetof(struct ctrl_reg, serr_loc),
250 SERR_INTR_ENABLE = offsetof(struct ctrl_reg, serr_intr_enable),
251 SLOT1 = offsetof(struct ctrl_reg, slot1),
252 SLOT2 = offsetof(struct ctrl_reg, slot2),
253 SLOT3 = offsetof(struct ctrl_reg, slot3),
254 SLOT4 = offsetof(struct ctrl_reg, slot4),
255 SLOT5 = offsetof(struct ctrl_reg, slot5),
256 SLOT6 = offsetof(struct ctrl_reg, slot6),
257 SLOT7 = offsetof(struct ctrl_reg, slot7),
258 SLOT8 = offsetof(struct ctrl_reg, slot8),
259 SLOT9 = offsetof(struct ctrl_reg, slot9),
260 SLOT10 = offsetof(struct ctrl_reg, slot10),
261 SLOT11 = offsetof(struct ctrl_reg, slot11),
262 SLOT12 = offsetof(struct ctrl_reg, slot12),
264 typedef u8(*php_intr_callback_t) (u8 hp_slot, void *instance_id);
265 struct php_ctlr_state_s {
266 struct php_ctlr_state_s *pnext;
267 struct pci_dev *pci_dev;
269 unsigned long flags; /* spinlock's */
270 u32 slot_device_offset;
272 struct timer_list int_poll_timer; /* Added for poll event */
273 php_intr_callback_t attention_button_callback;
274 php_intr_callback_t switch_change_callback;
275 php_intr_callback_t presence_change_callback;
276 php_intr_callback_t power_fault_callback;
277 void *callback_instance_id;
278 void __iomem *creg; /* Ptr to controller register space */
280 /* Inline functions */
283 /* Inline functions to check the sanity of a pointer that is passed to us */
284 static inline int slot_paranoia_check (struct slot *slot, const char *function)
287 dbg("%s - slot == NULL", function);
290 if (slot->magic != SLOT_MAGIC) {
291 dbg("%s - bad magic number for slot", function);
294 if (!slot->hotplug_slot) {
295 dbg("%s - slot->hotplug_slot == NULL!", function);
301 static inline struct slot *get_slot (struct hotplug_slot *hotplug_slot, const char *function)
306 dbg("%s - hotplug_slot == NULL\n", function);
310 slot = (struct slot *)hotplug_slot->private;
311 if (slot_paranoia_check (slot, function))
316 static inline struct slot *shpchp_find_slot (struct controller *ctrl, u8 device)
318 struct slot *p_slot, *tmp_slot = NULL;
325 while (p_slot && (p_slot->device != device)) {
327 p_slot = p_slot->next;
329 if (p_slot == NULL) {
330 err("ERROR: shpchp_find_slot device=0x%x\n", device);
337 static inline int wait_for_ctrl_irq (struct controller *ctrl)
339 DECLARE_WAITQUEUE(wait, current);
342 add_wait_queue(&ctrl->queue, &wait);
344 if (!shpchp_poll_mode) {
345 /* Sleep for up to 1 second */
346 msleep_interruptible(1000);
348 /* Sleep for up to 2 seconds */
349 msleep_interruptible(2000);
351 remove_wait_queue(&ctrl->queue, &wait);
352 if (signal_pending(current))
358 static inline void amd_pogo_errata_save_misc_reg(struct slot *p_slot)
362 /* save MiscII register */
363 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp);
365 p_slot->ctrl->pcix_misc2_reg = pcix_misc2_temp;
367 /* clear SERR/PERR enable bits */
368 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
369 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
370 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
371 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
372 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
373 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
376 static inline void amd_pogo_errata_restore_misc_reg(struct slot *p_slot)
379 u32 pcix_bridge_errors_reg;
380 u32 pcix_mem_base_reg;
384 /* write-one-to-clear Bridge_Errors[ PERR_OBSERVED ] */
385 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, &pcix_bridge_errors_reg);
386 perr_set = pcix_bridge_errors_reg & PERR_OBSERVED_MASK;
388 dbg ("%s W1C: Bridge_Errors[ PERR_OBSERVED = %08X]\n",__FUNCTION__ , perr_set);
390 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISC_BRIDGE_ERRORS_OFFSET, perr_set);
393 /* write-one-to-clear Memory_Base_Limit[ RSE ] */
394 pci_read_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, &pcix_mem_base_reg);
395 rse_set = pcix_mem_base_reg & RSE_MASK;
397 dbg ("%s W1C: Memory_Base_Limit[ RSE ]\n",__FUNCTION__ );
399 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MEM_BASE_LIMIT_OFFSET, rse_set);
401 /* restore MiscII register */
402 pci_read_config_dword( p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, &pcix_misc2_temp );
404 if (p_slot->ctrl->pcix_misc2_reg & SERRFATALENABLE_MASK)
405 pcix_misc2_temp |= SERRFATALENABLE_MASK;
407 pcix_misc2_temp &= ~SERRFATALENABLE_MASK;
409 if (p_slot->ctrl->pcix_misc2_reg & SERRNONFATALENABLE_MASK)
410 pcix_misc2_temp |= SERRNONFATALENABLE_MASK;
412 pcix_misc2_temp &= ~SERRNONFATALENABLE_MASK;
414 if (p_slot->ctrl->pcix_misc2_reg & PERRFLOODENABLE_MASK)
415 pcix_misc2_temp |= PERRFLOODENABLE_MASK;
417 pcix_misc2_temp &= ~PERRFLOODENABLE_MASK;
419 if (p_slot->ctrl->pcix_misc2_reg & PERRFATALENABLE_MASK)
420 pcix_misc2_temp |= PERRFATALENABLE_MASK;
422 pcix_misc2_temp &= ~PERRFATALENABLE_MASK;
424 if (p_slot->ctrl->pcix_misc2_reg & PERRNONFATALENABLE_MASK)
425 pcix_misc2_temp |= PERRNONFATALENABLE_MASK;
427 pcix_misc2_temp &= ~PERRNONFATALENABLE_MASK;
428 pci_write_config_dword(p_slot->ctrl->pci_dev, PCIX_MISCII_OFFSET, pcix_misc2_temp);
437 int shpc_init( struct controller *ctrl, struct pci_dev *pdev);
439 int shpc_get_ctlr_slot_config( struct controller *ctrl,
441 int *first_device_num,
442 int *physical_slot_num,
447 int (*power_on_slot ) (struct slot *slot);
448 int (*slot_enable ) (struct slot *slot);
449 int (*slot_disable ) (struct slot *slot);
450 int (*set_bus_speed_mode) (struct slot *slot, enum pci_bus_speed speed);
451 int (*get_power_status) (struct slot *slot, u8 *status);
452 int (*get_attention_status) (struct slot *slot, u8 *status);
453 int (*set_attention_status) (struct slot *slot, u8 status);
454 int (*get_latch_status) (struct slot *slot, u8 *status);
455 int (*get_adapter_status) (struct slot *slot, u8 *status);
457 int (*get_max_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
458 int (*get_cur_bus_speed) (struct slot *slot, enum pci_bus_speed *speed);
459 int (*get_adapter_speed) (struct slot *slot, enum pci_bus_speed *speed);
460 int (*get_mode1_ECC_cap) (struct slot *slot, u8 *mode);
461 int (*get_prog_int) (struct slot *slot, u8 *prog_int);
463 int (*query_power_fault) (struct slot *slot);
464 void (*green_led_on) (struct slot *slot);
465 void (*green_led_off) (struct slot *slot);
466 void (*green_led_blink) (struct slot *slot);
467 void (*release_ctlr) (struct controller *ctrl);
468 int (*check_cmd_status) (struct controller *ctrl);
471 #endif /* _SHPCHP_H */