2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
61 } __attribute__ ((packed));
63 /* offsets to the controller registers based on the above structure layout */
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
129 /* Link Width Encoding */
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
169 /* Attention indicator and Power indicator states */
171 #define LED_BLINK 0x10
174 /* Power Control Command */
176 #define POWER_OFF 0x0400
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
199 struct controller *ctrl = (struct controller *)data;
201 /* Poll for interrupt events. regs == NULL => polling */
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* default polling interval is 2 sec */
208 start_int_poll_timer(ctrl, pciehp_poll_time);
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
224 static inline int pcie_wait_cmd(struct controller *ctrl)
227 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
228 unsigned long timeout = msecs_to_jiffies(msecs);
231 rc = wait_event_interruptible_timeout(ctrl->queue,
232 !ctrl->cmd_busy, timeout);
234 dbg("Command not completed in 1000 msec\n");
237 info("Command was interrupted by a signal\n");
244 * pcie_write_cmd - Issue controller command
245 * @ctrl: controller to which the command is issued
246 * @cmd: command value written to slot control register
247 * @mask: bitmask of slot control register to be modified
249 static int pcie_write_cmd(struct controller *ctrl, u16 cmd, u16 mask)
255 mutex_lock(&ctrl->ctrl_lock);
257 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
259 err("%s: Cannot read SLOTSTATUS register\n", __func__);
263 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
264 /* After 1 sec and CMD_COMPLETED still not set, just
265 proceed forward to issue the next command according
266 to spec. Just print out the error message */
267 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
271 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
273 err("%s: Cannot read SLOTCTRL register\n", __func__);
278 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
282 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
284 err("%s: Cannot write to SLOTCTRL register\n", __func__);
287 * Wait for command completion.
290 retval = pcie_wait_cmd(ctrl);
292 mutex_unlock(&ctrl->ctrl_lock);
296 static int hpc_check_lnk_status(struct controller *ctrl)
301 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
303 err("%s: Cannot read LNKSTATUS register\n", __func__);
307 dbg("%s: lnk_status = %x\n", __func__, lnk_status);
308 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
309 !(lnk_status & NEG_LINK_WD)) {
310 err("%s : Link Training Error occurs \n", __func__);
318 static int hpc_get_attention_status(struct slot *slot, u8 *status)
320 struct controller *ctrl = slot->ctrl;
325 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
327 err("%s: Cannot read SLOTCTRL register\n", __func__);
331 dbg("%s: SLOTCTRL %x, value read %x\n",
332 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
334 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
336 switch (atten_led_state) {
338 *status = 0xFF; /* Reserved */
341 *status = 1; /* On */
344 *status = 2; /* Blink */
347 *status = 0; /* Off */
357 static int hpc_get_power_status(struct slot *slot, u8 *status)
359 struct controller *ctrl = slot->ctrl;
364 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
366 err("%s: Cannot read SLOTCTRL register\n", __func__);
369 dbg("%s: SLOTCTRL %x value read %x\n",
370 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
372 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
389 static int hpc_get_latch_status(struct slot *slot, u8 *status)
391 struct controller *ctrl = slot->ctrl;
395 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
397 err("%s: Cannot read SLOTSTATUS register\n", __func__);
401 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
406 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
408 struct controller *ctrl = slot->ctrl;
413 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
415 err("%s: Cannot read SLOTSTATUS register\n", __func__);
418 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
419 *status = (card_state == 1) ? 1 : 0;
424 static int hpc_query_power_fault(struct slot *slot)
426 struct controller *ctrl = slot->ctrl;
431 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
433 err("%s: Cannot check for power fault\n", __func__);
436 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
441 static int hpc_get_emi_status(struct slot *slot, u8 *status)
443 struct controller *ctrl = slot->ctrl;
447 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
449 err("%s : Cannot check EMI status\n", __func__);
452 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
457 static int hpc_toggle_emi(struct slot *slot)
465 rc = pcie_write_cmd(slot->ctrl, slot_cmd, cmd_mask);
466 slot->last_emi_toggle = get_seconds();
471 static int hpc_set_attention_status(struct slot *slot, u8 value)
473 struct controller *ctrl = slot->ctrl;
478 cmd_mask = ATTN_LED_CTRL;
480 case 0 : /* turn off */
483 case 1: /* turn on */
486 case 2: /* turn blink */
492 rc = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
493 dbg("%s: SLOTCTRL %x write cmd %x\n",
494 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
499 static void hpc_set_green_led_on(struct slot *slot)
501 struct controller *ctrl = slot->ctrl;
506 cmd_mask = PWR_LED_CTRL;
507 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
508 dbg("%s: SLOTCTRL %x write cmd %x\n",
509 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
512 static void hpc_set_green_led_off(struct slot *slot)
514 struct controller *ctrl = slot->ctrl;
519 cmd_mask = PWR_LED_CTRL;
520 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
521 dbg("%s: SLOTCTRL %x write cmd %x\n",
522 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
525 static void hpc_set_green_led_blink(struct slot *slot)
527 struct controller *ctrl = slot->ctrl;
532 cmd_mask = PWR_LED_CTRL;
533 pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
534 dbg("%s: SLOTCTRL %x write cmd %x\n",
535 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
538 static void hpc_release_ctlr(struct controller *ctrl)
540 if (pciehp_poll_mode)
541 del_timer(&ctrl->poll_timer);
543 free_irq(ctrl->pci_dev->irq, ctrl);
546 * If this is the last controller to be released, destroy the
549 if (atomic_dec_and_test(&pciehp_num_controllers))
550 destroy_workqueue(pciehp_wq);
553 static int hpc_power_on_slot(struct slot * slot)
555 struct controller *ctrl = slot->ctrl;
561 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
563 /* Clear sticky power-fault bit from previous power failures */
564 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
566 err("%s: Cannot read SLOTSTATUS register\n", __func__);
569 slot_status &= PWR_FAULT_DETECTED;
571 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
573 err("%s: Cannot write to SLOTSTATUS register\n",
581 /* Enable detection that we turned off at slot power-off time */
582 if (!pciehp_poll_mode) {
583 slot_cmd |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
585 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
589 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
592 err("%s: Write %x command failed!\n", __func__, slot_cmd);
595 dbg("%s: SLOTCTRL %x write cmd %x\n",
596 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
601 static inline int pcie_mask_bad_dllp(struct controller *ctrl)
603 struct pci_dev *dev = ctrl->pci_dev;
607 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
610 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
611 if (reg & PCI_ERR_COR_BAD_DLLP)
613 reg |= PCI_ERR_COR_BAD_DLLP;
614 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
618 static inline void pcie_unmask_bad_dllp(struct controller *ctrl)
620 struct pci_dev *dev = ctrl->pci_dev;
624 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
627 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®);
628 if (!(reg & PCI_ERR_COR_BAD_DLLP))
630 reg &= ~PCI_ERR_COR_BAD_DLLP;
631 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg);
634 static int hpc_power_off_slot(struct slot * slot)
636 struct controller *ctrl = slot->ctrl;
642 dbg("%s: slot->hp_slot %x\n", __func__, slot->hp_slot);
645 * Set Bad DLLP Mask bit in Correctable Error Mask
646 * Register. This is the workaround against Bad DLLP error
647 * that sometimes happens during turning power off the slot
648 * which conforms to PCI Express 1.0a spec.
650 changed = pcie_mask_bad_dllp(ctrl);
652 slot_cmd = POWER_OFF;
655 * If we get MRL or presence detect interrupts now, the isr
656 * will notice the sticky power-fault bit too and issue power
657 * indicator change commands. This will lead to an endless loop
658 * of command completions, since the power-fault bit remains on
659 * till the slot is powered on again.
661 if (!pciehp_poll_mode) {
662 slot_cmd &= ~(PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
664 cmd_mask |= (PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE |
668 retval = pcie_write_cmd(ctrl, slot_cmd, cmd_mask);
670 err("%s: Write command failed!\n", __func__);
674 dbg("%s: SLOTCTRL %x write cmd %x\n",
675 __func__, ctrl->cap_base + SLOTCTRL, slot_cmd);
678 * After turning power off, we must wait for at least 1 second
679 * before taking any action that relies on power having been
680 * removed from the slot/adapter.
685 pcie_unmask_bad_dllp(ctrl);
690 static irqreturn_t pcie_isr(int irq, void *dev_id)
692 struct controller *ctrl = (struct controller *)dev_id;
693 u16 detected, intr_loc;
696 * In order to guarantee that all interrupt events are
697 * serviced, we need to re-inspect Slot Status register after
698 * clearing what is presumed to be the last pending interrupt.
702 if (pciehp_readw(ctrl, SLOTSTATUS, &detected)) {
703 err("%s: Cannot read SLOTSTATUS\n", __func__);
707 detected &= (ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED |
708 MRL_SENS_CHANGED | PRSN_DETECT_CHANGED |
710 intr_loc |= detected;
713 if (pciehp_writew(ctrl, SLOTSTATUS, detected)) {
714 err("%s: Cannot write to SLOTSTATUS\n", __func__);
719 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
721 /* Check Command Complete Interrupt Pending */
722 if (intr_loc & CMD_COMPLETED) {
725 wake_up_interruptible(&ctrl->queue);
728 /* Check MRL Sensor Changed */
729 if (intr_loc & MRL_SENS_CHANGED)
730 pciehp_handle_switch_change(0, ctrl);
732 /* Check Attention Button Pressed */
733 if (intr_loc & ATTN_BUTTN_PRESSED)
734 pciehp_handle_attention_button(0, ctrl);
736 /* Check Presence Detect Changed */
737 if (intr_loc & PRSN_DETECT_CHANGED)
738 pciehp_handle_presence_change(0, ctrl);
740 /* Check Power Fault Detected */
741 if (intr_loc & PWR_FAULT_DETECTED)
742 pciehp_handle_power_fault(0, ctrl);
747 static int hpc_get_max_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
749 struct controller *ctrl = slot->ctrl;
750 enum pcie_link_speed lnk_speed;
754 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
756 err("%s: Cannot read LNKCAP register\n", __func__);
760 switch (lnk_cap & 0x000F) {
762 lnk_speed = PCIE_2PT5GB;
765 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
770 dbg("Max link speed = %d\n", lnk_speed);
775 static int hpc_get_max_lnk_width(struct slot *slot,
776 enum pcie_link_width *value)
778 struct controller *ctrl = slot->ctrl;
779 enum pcie_link_width lnk_wdth;
783 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
785 err("%s: Cannot read LNKCAP register\n", __func__);
789 switch ((lnk_cap & 0x03F0) >> 4){
791 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
794 lnk_wdth = PCIE_LNK_X1;
797 lnk_wdth = PCIE_LNK_X2;
800 lnk_wdth = PCIE_LNK_X4;
803 lnk_wdth = PCIE_LNK_X8;
806 lnk_wdth = PCIE_LNK_X12;
809 lnk_wdth = PCIE_LNK_X16;
812 lnk_wdth = PCIE_LNK_X32;
815 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
820 dbg("Max link width = %d\n", lnk_wdth);
825 static int hpc_get_cur_lnk_speed(struct slot *slot, enum pci_bus_speed *value)
827 struct controller *ctrl = slot->ctrl;
828 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
832 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
834 err("%s: Cannot read LNKSTATUS register\n", __func__);
838 switch (lnk_status & 0x0F) {
840 lnk_speed = PCIE_2PT5GB;
843 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
848 dbg("Current link speed = %d\n", lnk_speed);
853 static int hpc_get_cur_lnk_width(struct slot *slot,
854 enum pcie_link_width *value)
856 struct controller *ctrl = slot->ctrl;
857 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
861 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
863 err("%s: Cannot read LNKSTATUS register\n", __func__);
867 switch ((lnk_status & 0x03F0) >> 4){
869 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
872 lnk_wdth = PCIE_LNK_X1;
875 lnk_wdth = PCIE_LNK_X2;
878 lnk_wdth = PCIE_LNK_X4;
881 lnk_wdth = PCIE_LNK_X8;
884 lnk_wdth = PCIE_LNK_X12;
887 lnk_wdth = PCIE_LNK_X16;
890 lnk_wdth = PCIE_LNK_X32;
893 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
898 dbg("Current link width = %d\n", lnk_wdth);
903 static struct hpc_ops pciehp_hpc_ops = {
904 .power_on_slot = hpc_power_on_slot,
905 .power_off_slot = hpc_power_off_slot,
906 .set_attention_status = hpc_set_attention_status,
907 .get_power_status = hpc_get_power_status,
908 .get_attention_status = hpc_get_attention_status,
909 .get_latch_status = hpc_get_latch_status,
910 .get_adapter_status = hpc_get_adapter_status,
911 .get_emi_status = hpc_get_emi_status,
912 .toggle_emi = hpc_toggle_emi,
914 .get_max_bus_speed = hpc_get_max_lnk_speed,
915 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
916 .get_max_lnk_width = hpc_get_max_lnk_width,
917 .get_cur_lnk_width = hpc_get_cur_lnk_width,
919 .query_power_fault = hpc_query_power_fault,
920 .green_led_on = hpc_set_green_led_on,
921 .green_led_off = hpc_set_green_led_off,
922 .green_led_blink = hpc_set_green_led_blink,
924 .release_ctlr = hpc_release_ctlr,
925 .check_lnk_status = hpc_check_lnk_status,
929 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
932 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
933 struct pci_dev *pdev = dev;
934 struct pci_bus *parent;
935 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
938 * Per PCI firmware specification, we should run the ACPI _OSC
939 * method to get control of hotplug hardware before using it.
940 * If an _OSC is missing, we look for an OSHP to do the same thing.
941 * To handle different BIOS behavior, we look for _OSC and OSHP
942 * within the scope of the hotplug controller and its parents, upto
943 * the host bridge under which this controller exists.
947 * This hotplug controller was not listed in the ACPI name
948 * space at all. Try to get acpi handle of parent pci bus.
950 if (!pdev || !pdev->bus->parent)
952 parent = pdev->bus->parent;
953 dbg("Could not find %s in acpi namespace, trying parent\n",
956 /* Parent must be a host bridge */
957 handle = acpi_get_pci_rootbridge_handle(
958 pci_domain_nr(parent),
961 handle = DEVICE_ACPI_HANDLE(
962 &(parent->self->dev));
967 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
968 dbg("Trying to get hotplug control for %s \n",
969 (char *)string.pointer);
970 status = pci_osc_control_set(handle,
971 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
972 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
973 if (status == AE_NOT_FOUND)
974 status = acpi_run_oshp(handle);
975 if (ACPI_SUCCESS(status)) {
976 dbg("Gained control for hotplug HW for pci %s (%s)\n",
977 pci_name(dev), (char *)string.pointer);
978 kfree(string.pointer);
981 if (acpi_root_bridge(handle))
984 status = acpi_get_parent(chandle, &handle);
985 if (ACPI_FAILURE(status))
989 err("Cannot get control of hotplug hardware for pci %s\n",
992 kfree(string.pointer);
997 static int pcie_init_hardware_part1(struct controller *ctrl,
998 struct pcie_device *dev)
1000 /* Mask Hot-plug Interrupt Enable */
1001 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE)) {
1002 err("%s: Cannot mask hotplug interrupt enable\n", __func__);
1008 int pcie_init_hardware_part2(struct controller *ctrl, struct pcie_device *dev)
1013 * We need to clear all events before enabling hotplug interrupt
1014 * notification mechanism in order for hotplug controler to
1015 * generate interrupts.
1017 if (pciehp_writew(ctrl, SLOTSTATUS, 0x1f)) {
1018 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1022 cmd = PRSN_DETECT_ENABLE;
1023 if (ATTN_BUTTN(ctrl))
1024 cmd |= ATTN_BUTTN_ENABLE;
1025 if (POWER_CTRL(ctrl))
1026 cmd |= PWR_FAULT_DETECT_ENABLE;
1028 cmd |= MRL_DETECT_ENABLE;
1029 if (!pciehp_poll_mode)
1030 cmd |= HP_INTR_ENABLE;
1032 mask = PRSN_DETECT_ENABLE | ATTN_BUTTN_ENABLE |
1033 PWR_FAULT_DETECT_ENABLE | MRL_DETECT_ENABLE | HP_INTR_ENABLE;
1035 if (pcie_write_cmd(ctrl, cmd, mask)) {
1036 err("%s: Cannot enable software notification\n", __func__);
1041 dbg("Bypassing BIOS check for pciehp use on %s\n",
1042 pci_name(ctrl->pci_dev));
1043 else if (pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev))
1044 goto abort_disable_intr;
1048 /* We end up here for the many possible ways to fail this API. */
1050 if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE))
1051 err("%s : disabling interrupts failed\n", __func__);
1056 int pcie_init(struct controller *ctrl, struct pcie_device *dev)
1062 u16 slot_status, slot_ctrl;
1063 struct pci_dev *pdev;
1066 ctrl->pci_dev = pdev; /* save pci_dev in context */
1068 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1069 __func__, pdev->vendor, pdev->device);
1071 cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1072 if (cap_base == 0) {
1073 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __func__);
1077 ctrl->cap_base = cap_base;
1079 dbg("%s: pcie_cap_base %x\n", __func__, cap_base);
1081 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1083 err("%s: Cannot read CAPREG register\n", __func__);
1086 dbg("%s: CAPREG offset %x cap_reg %x\n",
1087 __func__, ctrl->cap_base + CAPREG, cap_reg);
1089 if (((cap_reg & SLOT_IMPL) == 0) ||
1090 (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1091 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1092 dbg("%s : This is not a root port or the port is not "
1093 "connected to a slot\n", __func__);
1097 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1099 err("%s: Cannot read SLOTCAP register\n", __func__);
1102 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1103 __func__, ctrl->cap_base + SLOTCAP, slot_cap);
1105 if (!(slot_cap & HP_CAP)) {
1106 dbg("%s : This slot is not hot-plug capable\n", __func__);
1109 /* For debugging purpose */
1110 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1112 err("%s: Cannot read SLOTSTATUS register\n", __func__);
1115 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1116 __func__, ctrl->cap_base + SLOTSTATUS, slot_status);
1118 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1120 err("%s: Cannot read SLOTCTRL register\n", __func__);
1123 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1124 __func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1126 for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1127 if (pci_resource_len(pdev, rc) > 0)
1128 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1129 (unsigned long long)pci_resource_start(pdev, rc),
1130 (unsigned long long)pci_resource_len(pdev, rc));
1132 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
1133 pdev->vendor, pdev->device,
1134 pdev->subsystem_vendor, pdev->subsystem_device);
1136 mutex_init(&ctrl->crit_sect);
1137 mutex_init(&ctrl->ctrl_lock);
1139 /* setup wait queue */
1140 init_waitqueue_head(&ctrl->queue);
1142 /* return PCI Controller Info */
1143 ctrl->slot_device_offset = 0;
1144 ctrl->num_slots = 1;
1145 ctrl->first_slot = slot_cap >> 19;
1146 ctrl->slot_cap = slot_cap;
1148 rc = pcie_init_hardware_part1(ctrl, dev);
1152 if (pciehp_poll_mode) {
1153 /* Install interrupt polling timer. Start with 10 sec delay */
1154 init_timer(&ctrl->poll_timer);
1155 start_int_poll_timer(ctrl, 10);
1157 /* Installs the interrupt handler */
1158 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1159 MY_NAME, (void *)ctrl);
1160 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1161 __func__, ctrl->pci_dev->irq,
1162 atomic_read(&pciehp_num_controllers), rc);
1164 err("Can't get irq %d for the hotplug controller\n",
1165 ctrl->pci_dev->irq);
1169 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1170 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1173 * If this is the first controller to be initialized,
1174 * initialize the pciehp work queue
1176 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1177 pciehp_wq = create_singlethread_workqueue("pciehpd");
1180 goto abort_free_irq;
1184 rc = pcie_init_hardware_part2(ctrl, dev);
1186 ctrl->hpc_ops = &pciehp_hpc_ops;
1190 if (pciehp_poll_mode)
1191 del_timer_sync(&ctrl->poll_timer);
1193 free_irq(ctrl->pci_dev->irq, ctrl);