2 * PCI Express PCI Hot Plug Driver
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 * Copyright (C) 2003-2004 Intel Corporation
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
19 * NON INFRINGEMENT. See the GNU General Public License for more
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 * Send feedback to <greg@kroah.com>,<kristen.c.accardi@intel.com>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/types.h>
33 #include <linux/signal.h>
34 #include <linux/jiffies.h>
35 #include <linux/timer.h>
36 #include <linux/pci.h>
37 #include <linux/interrupt.h>
38 #include <linux/time.h>
43 static atomic_t pciehp_num_controllers = ATOMIC_INIT(0);
61 } __attribute__ ((packed));
63 /* offsets to the controller registers based on the above structure layout */
65 PCIECAPID = offsetof(struct ctrl_reg, cap_id),
66 NXTCAPPTR = offsetof(struct ctrl_reg, nxt_ptr),
67 CAPREG = offsetof(struct ctrl_reg, cap_reg),
68 DEVCAP = offsetof(struct ctrl_reg, dev_cap),
69 DEVCTRL = offsetof(struct ctrl_reg, dev_ctrl),
70 DEVSTATUS = offsetof(struct ctrl_reg, dev_status),
71 LNKCAP = offsetof(struct ctrl_reg, lnk_cap),
72 LNKCTRL = offsetof(struct ctrl_reg, lnk_ctrl),
73 LNKSTATUS = offsetof(struct ctrl_reg, lnk_status),
74 SLOTCAP = offsetof(struct ctrl_reg, slot_cap),
75 SLOTCTRL = offsetof(struct ctrl_reg, slot_ctrl),
76 SLOTSTATUS = offsetof(struct ctrl_reg, slot_status),
77 ROOTCTRL = offsetof(struct ctrl_reg, root_ctrl),
78 ROOTSTATUS = offsetof(struct ctrl_reg, root_status),
81 static inline int pciehp_readw(struct controller *ctrl, int reg, u16 *value)
83 struct pci_dev *dev = ctrl->pci_dev;
84 return pci_read_config_word(dev, ctrl->cap_base + reg, value);
87 static inline int pciehp_readl(struct controller *ctrl, int reg, u32 *value)
89 struct pci_dev *dev = ctrl->pci_dev;
90 return pci_read_config_dword(dev, ctrl->cap_base + reg, value);
93 static inline int pciehp_writew(struct controller *ctrl, int reg, u16 value)
95 struct pci_dev *dev = ctrl->pci_dev;
96 return pci_write_config_word(dev, ctrl->cap_base + reg, value);
99 static inline int pciehp_writel(struct controller *ctrl, int reg, u32 value)
101 struct pci_dev *dev = ctrl->pci_dev;
102 return pci_write_config_dword(dev, ctrl->cap_base + reg, value);
105 /* Field definitions in PCI Express Capabilities Register */
106 #define CAP_VER 0x000F
107 #define DEV_PORT_TYPE 0x00F0
108 #define SLOT_IMPL 0x0100
109 #define MSG_NUM 0x3E00
111 /* Device or Port Type */
112 #define NAT_ENDPT 0x00
113 #define LEG_ENDPT 0x01
114 #define ROOT_PORT 0x04
115 #define UP_STREAM 0x05
116 #define DN_STREAM 0x06
117 #define PCIE_PCI_BRDG 0x07
118 #define PCI_PCIE_BRDG 0x10
120 /* Field definitions in Device Capabilities Register */
121 #define DATTN_BUTTN_PRSN 0x1000
122 #define DATTN_LED_PRSN 0x2000
123 #define DPWR_LED_PRSN 0x4000
125 /* Field definitions in Link Capabilities Register */
126 #define MAX_LNK_SPEED 0x000F
127 #define MAX_LNK_WIDTH 0x03F0
129 /* Link Width Encoding */
138 /*Field definitions of Link Status Register */
139 #define LNK_SPEED 0x000F
140 #define NEG_LINK_WD 0x03F0
141 #define LNK_TRN_ERR 0x0400
142 #define LNK_TRN 0x0800
143 #define SLOT_CLK_CONF 0x1000
145 /* Field definitions in Slot Capabilities Register */
146 #define ATTN_BUTTN_PRSN 0x00000001
147 #define PWR_CTRL_PRSN 0x00000002
148 #define MRL_SENS_PRSN 0x00000004
149 #define ATTN_LED_PRSN 0x00000008
150 #define PWR_LED_PRSN 0x00000010
151 #define HP_SUPR_RM_SUP 0x00000020
152 #define HP_CAP 0x00000040
153 #define SLOT_PWR_VALUE 0x000003F8
154 #define SLOT_PWR_LIMIT 0x00000C00
155 #define PSN 0xFFF80000 /* PSN: Physical Slot Number */
157 /* Field definitions in Slot Control Register */
158 #define ATTN_BUTTN_ENABLE 0x0001
159 #define PWR_FAULT_DETECT_ENABLE 0x0002
160 #define MRL_DETECT_ENABLE 0x0004
161 #define PRSN_DETECT_ENABLE 0x0008
162 #define CMD_CMPL_INTR_ENABLE 0x0010
163 #define HP_INTR_ENABLE 0x0020
164 #define ATTN_LED_CTRL 0x00C0
165 #define PWR_LED_CTRL 0x0300
166 #define PWR_CTRL 0x0400
167 #define EMI_CTRL 0x0800
169 /* Attention indicator and Power indicator states */
171 #define LED_BLINK 0x10
174 /* Power Control Command */
176 #define POWER_OFF 0x0400
178 /* EMI Status defines */
179 #define EMI_DISENGAGED 0
180 #define EMI_ENGAGED 1
182 /* Field definitions in Slot Status Register */
183 #define ATTN_BUTTN_PRESSED 0x0001
184 #define PWR_FAULT_DETECTED 0x0002
185 #define MRL_SENS_CHANGED 0x0004
186 #define PRSN_DETECT_CHANGED 0x0008
187 #define CMD_COMPLETED 0x0010
188 #define MRL_STATE 0x0020
189 #define PRSN_STATE 0x0040
190 #define EMI_STATE 0x0080
191 #define EMI_STATUS_BIT 7
193 static irqreturn_t pcie_isr(int irq, void *dev_id);
194 static void start_int_poll_timer(struct controller *ctrl, int sec);
196 /* This is the interrupt polling timeout function. */
197 static void int_poll_timeout(unsigned long data)
199 struct controller *ctrl = (struct controller *)data;
201 /* Poll for interrupt events. regs == NULL => polling */
204 init_timer(&ctrl->poll_timer);
205 if (!pciehp_poll_time)
206 pciehp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
208 start_int_poll_timer(ctrl, pciehp_poll_time);
211 /* This function starts the interrupt polling timer. */
212 static void start_int_poll_timer(struct controller *ctrl, int sec)
214 /* Clamp to sane value */
215 if ((sec <= 0) || (sec > 60))
218 ctrl->poll_timer.function = &int_poll_timeout;
219 ctrl->poll_timer.data = (unsigned long)ctrl;
220 ctrl->poll_timer.expires = jiffies + sec * HZ;
221 add_timer(&ctrl->poll_timer);
224 static inline int pcie_wait_cmd(struct controller *ctrl)
227 unsigned int msecs = pciehp_poll_mode ? 2500 : 1000;
228 unsigned long timeout = msecs_to_jiffies(msecs);
231 rc = wait_event_interruptible_timeout(ctrl->queue,
232 !ctrl->cmd_busy, timeout);
234 dbg("Command not completed in 1000 msec\n");
237 info("Command was interrupted by a signal\n");
244 * pcie_write_cmd - Issue controller command
245 * @slot: slot to which the command is issued
246 * @cmd: command value written to slot control register
247 * @mask: bitmask of slot control register to be modified
249 static int pcie_write_cmd(struct slot *slot, u16 cmd, u16 mask)
251 struct controller *ctrl = slot->ctrl;
257 mutex_lock(&ctrl->ctrl_lock);
259 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
261 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
265 if ((slot_status & CMD_COMPLETED) == CMD_COMPLETED ) {
266 /* After 1 sec and CMD_COMPLETED still not set, just
267 proceed forward to issue the next command according
268 to spec. Just print out the error message */
269 dbg("%s: CMD_COMPLETED not clear after 1 sec.\n",
273 spin_lock_irqsave(&ctrl->lock, flags);
274 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
276 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
277 goto out_spin_unlock;
281 slot_ctrl |= ((cmd & mask) | CMD_CMPL_INTR_ENABLE);
284 retval = pciehp_writew(ctrl, SLOTCTRL, slot_ctrl);
286 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
289 spin_unlock_irqrestore(&ctrl->lock, flags);
292 * Wait for command completion.
295 retval = pcie_wait_cmd(ctrl);
297 mutex_unlock(&ctrl->ctrl_lock);
301 static int hpc_check_lnk_status(struct controller *ctrl)
306 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
308 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
312 dbg("%s: lnk_status = %x\n", __FUNCTION__, lnk_status);
313 if ( (lnk_status & LNK_TRN) || (lnk_status & LNK_TRN_ERR) ||
314 !(lnk_status & NEG_LINK_WD)) {
315 err("%s : Link Training Error occurs \n", __FUNCTION__);
324 static int hpc_get_attention_status(struct slot *slot, u8 *status)
326 struct controller *ctrl = slot->ctrl;
331 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
333 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
337 dbg("%s: SLOTCTRL %x, value read %x\n",
338 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
340 atten_led_state = (slot_ctrl & ATTN_LED_CTRL) >> 6;
342 switch (atten_led_state) {
344 *status = 0xFF; /* Reserved */
347 *status = 1; /* On */
350 *status = 2; /* Blink */
353 *status = 0; /* Off */
363 static int hpc_get_power_status(struct slot *slot, u8 *status)
365 struct controller *ctrl = slot->ctrl;
370 retval = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
372 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
375 dbg("%s: SLOTCTRL %x value read %x\n",
376 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
378 pwr_state = (slot_ctrl & PWR_CTRL) >> 10;
396 static int hpc_get_latch_status(struct slot *slot, u8 *status)
398 struct controller *ctrl = slot->ctrl;
402 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
404 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
408 *status = (((slot_status & MRL_STATE) >> 5) == 0) ? 0 : 1;
413 static int hpc_get_adapter_status(struct slot *slot, u8 *status)
415 struct controller *ctrl = slot->ctrl;
420 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
422 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
425 card_state = (u8)((slot_status & PRSN_STATE) >> 6);
426 *status = (card_state == 1) ? 1 : 0;
431 static int hpc_query_power_fault(struct slot *slot)
433 struct controller *ctrl = slot->ctrl;
438 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
440 err("%s: Cannot check for power fault\n", __FUNCTION__);
443 pwr_fault = (u8)((slot_status & PWR_FAULT_DETECTED) >> 1);
448 static int hpc_get_emi_status(struct slot *slot, u8 *status)
450 struct controller *ctrl = slot->ctrl;
454 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
456 err("%s : Cannot check EMI status\n", __FUNCTION__);
459 *status = (slot_status & EMI_STATE) >> EMI_STATUS_BIT;
464 static int hpc_toggle_emi(struct slot *slot)
472 if (!pciehp_poll_mode) {
473 slot_cmd = slot_cmd | HP_INTR_ENABLE;
474 cmd_mask = cmd_mask | HP_INTR_ENABLE;
477 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
478 slot->last_emi_toggle = get_seconds();
483 static int hpc_set_attention_status(struct slot *slot, u8 value)
485 struct controller *ctrl = slot->ctrl;
490 cmd_mask = ATTN_LED_CTRL;
492 case 0 : /* turn off */
495 case 1: /* turn on */
498 case 2: /* turn blink */
504 if (!pciehp_poll_mode) {
505 slot_cmd = slot_cmd | HP_INTR_ENABLE;
506 cmd_mask = cmd_mask | HP_INTR_ENABLE;
509 rc = pcie_write_cmd(slot, slot_cmd, cmd_mask);
510 dbg("%s: SLOTCTRL %x write cmd %x\n",
511 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
517 static void hpc_set_green_led_on(struct slot *slot)
519 struct controller *ctrl = slot->ctrl;
524 cmd_mask = PWR_LED_CTRL;
525 if (!pciehp_poll_mode) {
526 slot_cmd = slot_cmd | HP_INTR_ENABLE;
527 cmd_mask = cmd_mask | HP_INTR_ENABLE;
530 pcie_write_cmd(slot, slot_cmd, cmd_mask);
532 dbg("%s: SLOTCTRL %x write cmd %x\n",
533 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
536 static void hpc_set_green_led_off(struct slot *slot)
538 struct controller *ctrl = slot->ctrl;
543 cmd_mask = PWR_LED_CTRL;
544 if (!pciehp_poll_mode) {
545 slot_cmd = slot_cmd | HP_INTR_ENABLE;
546 cmd_mask = cmd_mask | HP_INTR_ENABLE;
549 pcie_write_cmd(slot, slot_cmd, cmd_mask);
550 dbg("%s: SLOTCTRL %x write cmd %x\n",
551 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
554 static void hpc_set_green_led_blink(struct slot *slot)
556 struct controller *ctrl = slot->ctrl;
561 cmd_mask = PWR_LED_CTRL;
562 if (!pciehp_poll_mode) {
563 slot_cmd = slot_cmd | HP_INTR_ENABLE;
564 cmd_mask = cmd_mask | HP_INTR_ENABLE;
567 pcie_write_cmd(slot, slot_cmd, cmd_mask);
569 dbg("%s: SLOTCTRL %x write cmd %x\n",
570 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
573 static void hpc_release_ctlr(struct controller *ctrl)
575 if (pciehp_poll_mode)
576 del_timer(&ctrl->poll_timer);
578 free_irq(ctrl->pci_dev->irq, ctrl);
581 * If this is the last controller to be released, destroy the
584 if (atomic_dec_and_test(&pciehp_num_controllers))
585 destroy_workqueue(pciehp_wq);
588 static int hpc_power_on_slot(struct slot * slot)
590 struct controller *ctrl = slot->ctrl;
596 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
598 /* Clear sticky power-fault bit from previous power failures */
599 retval = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
601 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
604 slot_status &= PWR_FAULT_DETECTED;
606 retval = pciehp_writew(ctrl, SLOTSTATUS, slot_status);
608 err("%s: Cannot write to SLOTSTATUS register\n",
616 /* Enable detection that we turned off at slot power-off time */
617 if (!pciehp_poll_mode) {
618 slot_cmd = slot_cmd |
619 PWR_FAULT_DETECT_ENABLE |
623 cmd_mask = cmd_mask |
624 PWR_FAULT_DETECT_ENABLE |
630 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
633 err("%s: Write %x command failed!\n", __FUNCTION__, slot_cmd);
636 dbg("%s: SLOTCTRL %x write cmd %x\n",
637 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
642 static int hpc_power_off_slot(struct slot * slot)
644 struct controller *ctrl = slot->ctrl;
649 dbg("%s: slot->hp_slot %x\n", __FUNCTION__, slot->hp_slot);
651 slot_cmd = POWER_OFF;
654 * If we get MRL or presence detect interrupts now, the isr
655 * will notice the sticky power-fault bit too and issue power
656 * indicator change commands. This will lead to an endless loop
657 * of command completions, since the power-fault bit remains on
658 * till the slot is powered on again.
660 if (!pciehp_poll_mode) {
661 slot_cmd = (slot_cmd &
662 ~PWR_FAULT_DETECT_ENABLE &
664 ~PRSN_DETECT_ENABLE) | HP_INTR_ENABLE;
665 cmd_mask = cmd_mask |
666 PWR_FAULT_DETECT_ENABLE |
672 retval = pcie_write_cmd(slot, slot_cmd, cmd_mask);
674 err("%s: Write command failed!\n", __FUNCTION__);
677 dbg("%s: SLOTCTRL %x write cmd %x\n",
678 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_cmd);
683 static irqreturn_t pcie_isr(int irq, void *dev_id)
685 struct controller *ctrl = (struct controller *)dev_id;
686 u16 slot_status, intr_detect, intr_loc;
688 int hp_slot = 0; /* only 1 slot per PCI Express port */
692 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
694 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
698 intr_detect = ( ATTN_BUTTN_PRESSED | PWR_FAULT_DETECTED | MRL_SENS_CHANGED |
699 PRSN_DETECT_CHANGED | CMD_COMPLETED );
701 intr_loc = slot_status & intr_detect;
703 /* Check to see if it was our interrupt */
707 dbg("%s: intr_loc %x\n", __FUNCTION__, intr_loc);
708 /* Mask Hot-plug Interrupt Enable */
709 if (!pciehp_poll_mode) {
710 spin_lock_irqsave(&ctrl->lock, flags);
711 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
713 err("%s: Cannot read SLOT_CTRL register\n",
715 spin_unlock_irqrestore(&ctrl->lock, flags);
719 dbg("%s: pciehp_readw(SLOTCTRL) with value %x\n",
720 __FUNCTION__, temp_word);
721 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
722 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
724 err("%s: Cannot write to SLOTCTRL register\n",
726 spin_unlock_irqrestore(&ctrl->lock, flags);
729 spin_unlock_irqrestore(&ctrl->lock, flags);
731 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
733 err("%s: Cannot read SLOT_STATUS register\n",
737 dbg("%s: pciehp_readw(SLOTSTATUS) with value %x\n",
738 __FUNCTION__, slot_status);
740 /* Clear command complete interrupt caused by this write */
742 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
744 err("%s: Cannot write to SLOTSTATUS register\n",
750 if (intr_loc & CMD_COMPLETED) {
752 * Command Complete Interrupt Pending
755 wake_up_interruptible(&ctrl->queue);
758 if (intr_loc & MRL_SENS_CHANGED)
759 pciehp_handle_switch_change(hp_slot, ctrl);
761 if (intr_loc & ATTN_BUTTN_PRESSED)
762 pciehp_handle_attention_button(hp_slot, ctrl);
764 if (intr_loc & PRSN_DETECT_CHANGED)
765 pciehp_handle_presence_change(hp_slot, ctrl);
767 if (intr_loc & PWR_FAULT_DETECTED)
768 pciehp_handle_power_fault(hp_slot, ctrl);
770 /* Clear all events after serving them */
772 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
774 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
777 /* Unmask Hot-plug Interrupt Enable */
778 if (!pciehp_poll_mode) {
779 spin_lock_irqsave(&ctrl->lock, flags);
780 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
782 err("%s: Cannot read SLOTCTRL register\n",
784 spin_unlock_irqrestore(&ctrl->lock, flags);
788 dbg("%s: Unmask Hot-plug Interrupt Enable\n", __FUNCTION__);
789 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
791 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
793 err("%s: Cannot write to SLOTCTRL register\n",
795 spin_unlock_irqrestore(&ctrl->lock, flags);
798 spin_unlock_irqrestore(&ctrl->lock, flags);
800 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
802 err("%s: Cannot read SLOT_STATUS register\n",
807 /* Clear command complete interrupt caused by this write */
809 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
811 err("%s: Cannot write to SLOTSTATUS failed\n",
815 dbg("%s: pciehp_writew(SLOTSTATUS) with value %x\n",
816 __FUNCTION__, temp_word);
822 static int hpc_get_max_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
824 struct controller *ctrl = slot->ctrl;
825 enum pcie_link_speed lnk_speed;
829 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
831 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
835 switch (lnk_cap & 0x000F) {
837 lnk_speed = PCIE_2PT5GB;
840 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
845 dbg("Max link speed = %d\n", lnk_speed);
850 static int hpc_get_max_lnk_width (struct slot *slot, enum pcie_link_width *value)
852 struct controller *ctrl = slot->ctrl;
853 enum pcie_link_width lnk_wdth;
857 retval = pciehp_readl(ctrl, LNKCAP, &lnk_cap);
859 err("%s: Cannot read LNKCAP register\n", __FUNCTION__);
863 switch ((lnk_cap & 0x03F0) >> 4){
865 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
868 lnk_wdth = PCIE_LNK_X1;
871 lnk_wdth = PCIE_LNK_X2;
874 lnk_wdth = PCIE_LNK_X4;
877 lnk_wdth = PCIE_LNK_X8;
880 lnk_wdth = PCIE_LNK_X12;
883 lnk_wdth = PCIE_LNK_X16;
886 lnk_wdth = PCIE_LNK_X32;
889 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
894 dbg("Max link width = %d\n", lnk_wdth);
899 static int hpc_get_cur_lnk_speed (struct slot *slot, enum pci_bus_speed *value)
901 struct controller *ctrl = slot->ctrl;
902 enum pcie_link_speed lnk_speed = PCI_SPEED_UNKNOWN;
906 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
908 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
912 switch (lnk_status & 0x0F) {
914 lnk_speed = PCIE_2PT5GB;
917 lnk_speed = PCIE_LNK_SPEED_UNKNOWN;
922 dbg("Current link speed = %d\n", lnk_speed);
927 static int hpc_get_cur_lnk_width (struct slot *slot, enum pcie_link_width *value)
929 struct controller *ctrl = slot->ctrl;
930 enum pcie_link_width lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
934 retval = pciehp_readw(ctrl, LNKSTATUS, &lnk_status);
936 err("%s: Cannot read LNKSTATUS register\n", __FUNCTION__);
940 switch ((lnk_status & 0x03F0) >> 4){
942 lnk_wdth = PCIE_LNK_WIDTH_RESRV;
945 lnk_wdth = PCIE_LNK_X1;
948 lnk_wdth = PCIE_LNK_X2;
951 lnk_wdth = PCIE_LNK_X4;
954 lnk_wdth = PCIE_LNK_X8;
957 lnk_wdth = PCIE_LNK_X12;
960 lnk_wdth = PCIE_LNK_X16;
963 lnk_wdth = PCIE_LNK_X32;
966 lnk_wdth = PCIE_LNK_WIDTH_UNKNOWN;
971 dbg("Current link width = %d\n", lnk_wdth);
976 static struct hpc_ops pciehp_hpc_ops = {
977 .power_on_slot = hpc_power_on_slot,
978 .power_off_slot = hpc_power_off_slot,
979 .set_attention_status = hpc_set_attention_status,
980 .get_power_status = hpc_get_power_status,
981 .get_attention_status = hpc_get_attention_status,
982 .get_latch_status = hpc_get_latch_status,
983 .get_adapter_status = hpc_get_adapter_status,
984 .get_emi_status = hpc_get_emi_status,
985 .toggle_emi = hpc_toggle_emi,
987 .get_max_bus_speed = hpc_get_max_lnk_speed,
988 .get_cur_bus_speed = hpc_get_cur_lnk_speed,
989 .get_max_lnk_width = hpc_get_max_lnk_width,
990 .get_cur_lnk_width = hpc_get_cur_lnk_width,
992 .query_power_fault = hpc_query_power_fault,
993 .green_led_on = hpc_set_green_led_on,
994 .green_led_off = hpc_set_green_led_off,
995 .green_led_blink = hpc_set_green_led_blink,
997 .release_ctlr = hpc_release_ctlr,
998 .check_lnk_status = hpc_check_lnk_status,
1002 int pciehp_acpi_get_hp_hw_control_from_firmware(struct pci_dev *dev)
1005 acpi_handle chandle, handle = DEVICE_ACPI_HANDLE(&(dev->dev));
1006 struct pci_dev *pdev = dev;
1007 struct pci_bus *parent;
1008 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
1011 * Per PCI firmware specification, we should run the ACPI _OSC
1012 * method to get control of hotplug hardware before using it.
1013 * If an _OSC is missing, we look for an OSHP to do the same thing.
1014 * To handle different BIOS behavior, we look for _OSC and OSHP
1015 * within the scope of the hotplug controller and its parents, upto
1016 * the host bridge under which this controller exists.
1020 * This hotplug controller was not listed in the ACPI name
1021 * space at all. Try to get acpi handle of parent pci bus.
1023 if (!pdev || !pdev->bus->parent)
1025 parent = pdev->bus->parent;
1026 dbg("Could not find %s in acpi namespace, trying parent\n",
1029 /* Parent must be a host bridge */
1030 handle = acpi_get_pci_rootbridge_handle(
1031 pci_domain_nr(parent),
1034 handle = DEVICE_ACPI_HANDLE(
1035 &(parent->self->dev));
1036 pdev = parent->self;
1040 acpi_get_name(handle, ACPI_FULL_PATHNAME, &string);
1041 dbg("Trying to get hotplug control for %s \n",
1042 (char *)string.pointer);
1043 status = pci_osc_control_set(handle,
1044 OSC_PCI_EXPRESS_CAP_STRUCTURE_CONTROL |
1045 OSC_PCI_EXPRESS_NATIVE_HP_CONTROL);
1046 if (status == AE_NOT_FOUND)
1047 status = acpi_run_oshp(handle);
1048 if (ACPI_SUCCESS(status)) {
1049 dbg("Gained control for hotplug HW for pci %s (%s)\n",
1050 pci_name(dev), (char *)string.pointer);
1051 kfree(string.pointer);
1054 if (acpi_root_bridge(handle))
1057 status = acpi_get_parent(chandle, &handle);
1058 if (ACPI_FAILURE(status))
1062 err("Cannot get control of hotplug hardware for pci %s\n",
1065 kfree(string.pointer);
1072 int pcie_init(struct controller * ctrl, struct pcie_device *dev)
1077 u16 intr_enable = 0;
1080 u16 slot_status, slot_ctrl;
1081 struct pci_dev *pdev;
1084 ctrl->pci_dev = pdev; /* save pci_dev in context */
1086 dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
1087 __FUNCTION__, pdev->vendor, pdev->device);
1089 if ((cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP)) == 0) {
1090 dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __FUNCTION__);
1091 goto abort_free_ctlr;
1094 ctrl->cap_base = cap_base;
1096 dbg("%s: pcie_cap_base %x\n", __FUNCTION__, cap_base);
1098 rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
1100 err("%s: Cannot read CAPREG register\n", __FUNCTION__);
1101 goto abort_free_ctlr;
1103 dbg("%s: CAPREG offset %x cap_reg %x\n",
1104 __FUNCTION__, ctrl->cap_base + CAPREG, cap_reg);
1106 if (((cap_reg & SLOT_IMPL) == 0) || (((cap_reg & DEV_PORT_TYPE) != 0x0040)
1107 && ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
1108 dbg("%s : This is not a root port or the port is not connected to a slot\n", __FUNCTION__);
1109 goto abort_free_ctlr;
1112 rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
1114 err("%s: Cannot read SLOTCAP register\n", __FUNCTION__);
1115 goto abort_free_ctlr;
1117 dbg("%s: SLOTCAP offset %x slot_cap %x\n",
1118 __FUNCTION__, ctrl->cap_base + SLOTCAP, slot_cap);
1120 if (!(slot_cap & HP_CAP)) {
1121 dbg("%s : This slot is not hot-plug capable\n", __FUNCTION__);
1122 goto abort_free_ctlr;
1124 /* For debugging purpose */
1125 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1127 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1128 goto abort_free_ctlr;
1130 dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
1131 __FUNCTION__, ctrl->cap_base + SLOTSTATUS, slot_status);
1133 rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
1135 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1136 goto abort_free_ctlr;
1138 dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
1139 __FUNCTION__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
1141 for ( rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
1142 if (pci_resource_len(pdev, rc) > 0)
1143 dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
1144 (unsigned long long)pci_resource_start(pdev, rc),
1145 (unsigned long long)pci_resource_len(pdev, rc));
1147 info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device,
1148 pdev->subsystem_vendor, pdev->subsystem_device);
1150 mutex_init(&ctrl->crit_sect);
1151 mutex_init(&ctrl->ctrl_lock);
1152 spin_lock_init(&ctrl->lock);
1154 /* setup wait queue */
1155 init_waitqueue_head(&ctrl->queue);
1157 /* return PCI Controller Info */
1158 ctrl->slot_device_offset = 0;
1159 ctrl->num_slots = 1;
1160 ctrl->first_slot = slot_cap >> 19;
1161 ctrl->ctrlcap = slot_cap & 0x0000007f;
1163 /* Mask Hot-plug Interrupt Enable */
1164 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1166 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1167 goto abort_free_ctlr;
1170 dbg("%s: SLOTCTRL %x value read %x\n",
1171 __FUNCTION__, ctrl->cap_base + SLOTCTRL, temp_word);
1172 temp_word = (temp_word & ~HP_INTR_ENABLE & ~CMD_CMPL_INTR_ENABLE) | 0x00;
1174 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1176 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1177 goto abort_free_ctlr;
1180 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1182 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1183 goto abort_free_ctlr;
1186 temp_word = 0x1F; /* Clear all events */
1187 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1189 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1190 goto abort_free_ctlr;
1193 if (pciehp_poll_mode) {
1194 /* Install interrupt polling timer. Start with 10 sec delay */
1195 init_timer(&ctrl->poll_timer);
1196 start_int_poll_timer(ctrl, 10);
1198 /* Installs the interrupt handler */
1199 rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
1200 MY_NAME, (void *)ctrl);
1201 dbg("%s: request_irq %d for hpc%d (returns %d)\n",
1202 __FUNCTION__, ctrl->pci_dev->irq,
1203 atomic_read(&pciehp_num_controllers), rc);
1205 err("Can't get irq %d for the hotplug controller\n",
1206 ctrl->pci_dev->irq);
1207 goto abort_free_ctlr;
1210 dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
1211 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
1214 * If this is the first controller to be initialized,
1215 * initialize the pciehp work queue
1217 if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
1218 pciehp_wq = create_singlethread_workqueue("pciehpd");
1221 goto abort_free_irq;
1225 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1227 err("%s: Cannot read SLOTCTRL register\n", __FUNCTION__);
1228 goto abort_free_irq;
1231 intr_enable = intr_enable | PRSN_DETECT_ENABLE;
1233 if (ATTN_BUTTN(slot_cap))
1234 intr_enable = intr_enable | ATTN_BUTTN_ENABLE;
1236 if (POWER_CTRL(slot_cap))
1237 intr_enable = intr_enable | PWR_FAULT_DETECT_ENABLE;
1239 if (MRL_SENS(slot_cap))
1240 intr_enable = intr_enable | MRL_DETECT_ENABLE;
1242 temp_word = (temp_word & ~intr_enable) | intr_enable;
1244 if (pciehp_poll_mode) {
1245 temp_word = (temp_word & ~HP_INTR_ENABLE) | 0x0;
1247 temp_word = (temp_word & ~HP_INTR_ENABLE) | HP_INTR_ENABLE;
1250 /* Unmask Hot-plug Interrupt Enable for the interrupt notification mechanism case */
1251 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1253 err("%s: Cannot write to SLOTCTRL register\n", __FUNCTION__);
1254 goto abort_free_irq;
1256 rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
1258 err("%s: Cannot read SLOTSTATUS register\n", __FUNCTION__);
1259 goto abort_disable_intr;
1262 temp_word = 0x1F; /* Clear all events */
1263 rc = pciehp_writew(ctrl, SLOTSTATUS, temp_word);
1265 err("%s: Cannot write to SLOTSTATUS register\n", __FUNCTION__);
1266 goto abort_disable_intr;
1270 dbg("Bypassing BIOS check for pciehp use on %s\n",
1271 pci_name(ctrl->pci_dev));
1273 rc = pciehp_get_hp_hw_control_from_firmware(ctrl->pci_dev);
1275 goto abort_disable_intr;
1278 ctrl->hpc_ops = &pciehp_hpc_ops;
1282 /* We end up here for the many possible ways to fail this API. */
1284 rc = pciehp_readw(ctrl, SLOTCTRL, &temp_word);
1286 temp_word &= ~(intr_enable | HP_INTR_ENABLE);
1287 rc = pciehp_writew(ctrl, SLOTCTRL, temp_word);
1290 err("%s : disabling interrupts failed\n", __FUNCTION__);
1293 if (pciehp_poll_mode)
1294 del_timer_sync(&ctrl->poll_timer);
1296 free_irq(ctrl->pci_dev->irq, ctrl);