3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
28 #include "zd_ieee80211.h"
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
43 void zd_chip_clear(struct zd_chip *chip)
45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_destroy(&chip->mutex);
49 ZD_MEMCLEAR(chip, sizeof(*chip));
52 static int scnprint_mac_oui(struct zd_chip *chip, char *buffer, size_t size)
54 u8 *addr = zd_usb_to_netdev(&chip->usb)->dev_addr;
55 return scnprintf(buffer, size, "%02x-%02x-%02x",
56 addr[0], addr[1], addr[2]);
59 /* Prints an identifier line, which will support debugging. */
60 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
64 i = scnprintf(buffer, size, "zd1211%s chip ",
65 zd_chip_is_zd1211b(chip) ? "b" : "");
66 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
67 i += scnprintf(buffer+i, size-i, " ");
68 i += scnprint_mac_oui(chip, buffer+i, size-i);
69 i += scnprintf(buffer+i, size-i, " ");
70 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
71 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c%c", chip->pa_type,
72 chip->patch_cck_gain ? 'g' : '-',
73 chip->patch_cr157 ? '7' : '-',
74 chip->patch_6m_band_edge ? '6' : '-',
75 chip->new_phy_layout ? 'N' : '-',
76 chip->al2230s_bit ? 'S' : '-');
80 static void print_id(struct zd_chip *chip)
84 scnprint_id(chip, buffer, sizeof(buffer));
85 buffer[sizeof(buffer)-1] = 0;
86 dev_info(zd_chip_dev(chip), "%s\n", buffer);
89 static zd_addr_t inc_addr(zd_addr_t addr)
92 /* Control registers use byte addressing, but everything else uses word
94 if ((a & 0xf000) == CR_START)
101 /* Read a variable number of 32-bit values. Parameter count is not allowed to
102 * exceed USB_MAX_IOREAD32_COUNT.
104 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
109 zd_addr_t *a16 = (zd_addr_t *)NULL;
111 unsigned int count16;
113 if (count > USB_MAX_IOREAD32_COUNT)
116 /* Allocate a single memory block for values and addresses. */
118 a16 = (zd_addr_t *) kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
121 dev_dbg_f(zd_chip_dev(chip),
122 "error ENOMEM in allocation of a16\n");
126 v16 = (u16 *)(a16 + count16);
128 for (i = 0; i < count; i++) {
130 /* We read the high word always first. */
131 a16[j] = inc_addr(addr[i]);
135 r = zd_ioread16v_locked(chip, v16, a16, count16);
137 dev_dbg_f(zd_chip_dev(chip),
138 "error: zd_ioread16v_locked. Error number %d\n", r);
142 for (i = 0; i < count; i++) {
144 values[i] = (v16[j] << 16) | v16[j+1];
152 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
156 struct zd_ioreq16 *ioreqs16;
157 unsigned int count16;
159 ZD_ASSERT(mutex_is_locked(&chip->mutex));
163 if (count > USB_MAX_IOWRITE32_COUNT)
166 /* Allocate a single memory block for values and addresses. */
168 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_KERNEL);
171 dev_dbg_f(zd_chip_dev(chip),
172 "error %d in ioreqs16 allocation\n", r);
176 for (i = 0; i < count; i++) {
178 /* We write the high word always first. */
179 ioreqs16[j].value = ioreqs[i].value >> 16;
180 ioreqs16[j].addr = inc_addr(ioreqs[i].addr);
181 ioreqs16[j+1].value = ioreqs[i].value;
182 ioreqs16[j+1].addr = ioreqs[i].addr;
185 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
188 dev_dbg_f(zd_chip_dev(chip),
189 "error %d in zd_usb_write16v\n", r);
197 int zd_iowrite16a_locked(struct zd_chip *chip,
198 const struct zd_ioreq16 *ioreqs, unsigned int count)
201 unsigned int i, j, t, max;
203 ZD_ASSERT(mutex_is_locked(&chip->mutex));
204 for (i = 0; i < count; i += j + t) {
207 if (max > USB_MAX_IOWRITE16_COUNT)
208 max = USB_MAX_IOWRITE16_COUNT;
209 for (j = 0; j < max; j++) {
210 if (!ioreqs[i+j].addr) {
216 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
218 dev_dbg_f(zd_chip_dev(chip),
219 "error zd_usb_iowrite16v. Error number %d\n",
228 /* Writes a variable number of 32 bit registers. The functions will split
229 * that in several USB requests. A split can be forced by inserting an IO
230 * request with an zero address field.
232 int zd_iowrite32a_locked(struct zd_chip *chip,
233 const struct zd_ioreq32 *ioreqs, unsigned int count)
236 unsigned int i, j, t, max;
238 for (i = 0; i < count; i += j + t) {
241 if (max > USB_MAX_IOWRITE32_COUNT)
242 max = USB_MAX_IOWRITE32_COUNT;
243 for (j = 0; j < max; j++) {
244 if (!ioreqs[i+j].addr) {
250 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
252 dev_dbg_f(zd_chip_dev(chip),
253 "error _zd_iowrite32v_locked."
254 " Error number %d\n", r);
262 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
266 mutex_lock(&chip->mutex);
267 r = zd_ioread16_locked(chip, value, addr);
268 mutex_unlock(&chip->mutex);
272 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
276 mutex_lock(&chip->mutex);
277 r = zd_ioread32_locked(chip, value, addr);
278 mutex_unlock(&chip->mutex);
282 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
286 mutex_lock(&chip->mutex);
287 r = zd_iowrite16_locked(chip, value, addr);
288 mutex_unlock(&chip->mutex);
292 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
296 mutex_lock(&chip->mutex);
297 r = zd_iowrite32_locked(chip, value, addr);
298 mutex_unlock(&chip->mutex);
302 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
303 u32 *values, unsigned int count)
307 mutex_lock(&chip->mutex);
308 r = zd_ioread32v_locked(chip, values, addresses, count);
309 mutex_unlock(&chip->mutex);
313 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
318 mutex_lock(&chip->mutex);
319 r = zd_iowrite32a_locked(chip, ioreqs, count);
320 mutex_unlock(&chip->mutex);
324 static int read_pod(struct zd_chip *chip, u8 *rf_type)
329 ZD_ASSERT(mutex_is_locked(&chip->mutex));
330 r = zd_ioread32_locked(chip, &value, E2P_POD);
333 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
335 /* FIXME: AL2230 handling (Bit 7 in POD) */
336 *rf_type = value & 0x0f;
337 chip->pa_type = (value >> 16) & 0x0f;
338 chip->patch_cck_gain = (value >> 8) & 0x1;
339 chip->patch_cr157 = (value >> 13) & 0x1;
340 chip->patch_6m_band_edge = (value >> 21) & 0x1;
341 chip->new_phy_layout = (value >> 31) & 0x1;
342 chip->al2230s_bit = (value >> 7) & 0x1;
343 chip->link_led = ((value >> 4) & 1) ? LED1 : LED2;
344 chip->supports_tx_led = 1;
345 if (value & (1 << 24)) { /* LED scenario */
346 if (value & (1 << 29))
347 chip->supports_tx_led = 0;
350 dev_dbg_f(zd_chip_dev(chip),
351 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
352 "patch 6M %d new PHY %d link LED%d tx led %d\n",
353 zd_rf_name(*rf_type), *rf_type,
354 chip->pa_type, chip->patch_cck_gain,
355 chip->patch_cr157, chip->patch_6m_band_edge,
356 chip->new_phy_layout,
357 chip->link_led == LED1 ? 1 : 2,
358 chip->supports_tx_led);
363 chip->patch_cck_gain = 0;
364 chip->patch_cr157 = 0;
365 chip->patch_6m_band_edge = 0;
366 chip->new_phy_layout = 0;
370 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
371 * CR_MAC_ADDR_P2 must be overwritten
373 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
376 struct zd_ioreq32 reqs[2] = {
377 [0] = { .addr = CR_MAC_ADDR_P1 },
378 [1] = { .addr = CR_MAC_ADDR_P2 },
381 reqs[0].value = (mac_addr[3] << 24)
382 | (mac_addr[2] << 16)
385 reqs[1].value = (mac_addr[5] << 8)
388 dev_dbg_f(zd_chip_dev(chip),
389 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
391 mutex_lock(&chip->mutex);
392 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
393 mutex_unlock(&chip->mutex);
397 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
402 mutex_lock(&chip->mutex);
403 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
404 mutex_unlock(&chip->mutex);
408 *regdomain = value >> 16;
409 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
414 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
415 zd_addr_t e2p_addr, u32 guard)
421 ZD_ASSERT(mutex_is_locked(&chip->mutex));
423 r = zd_ioread32_locked(chip, &v,
424 (zd_addr_t)((u16)e2p_addr+i/2));
430 values[i++] = v >> 8;
431 values[i++] = v >> 16;
432 values[i++] = v >> 24;
435 for (;i < count; i++)
436 values[i] = v >> (8*(i%3));
441 static int read_pwr_cal_values(struct zd_chip *chip)
443 return read_values(chip, chip->pwr_cal_values,
444 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
448 static int read_pwr_int_values(struct zd_chip *chip)
450 return read_values(chip, chip->pwr_int_values,
451 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
455 static int read_ofdm_cal_values(struct zd_chip *chip)
459 static const zd_addr_t addresses[] = {
465 for (i = 0; i < 3; i++) {
466 r = read_values(chip, chip->ofdm_cal_values[i],
467 E2P_CHANNEL_COUNT, addresses[i], 0);
474 static int read_cal_int_tables(struct zd_chip *chip)
478 r = read_pwr_cal_values(chip);
481 r = read_pwr_int_values(chip);
484 r = read_ofdm_cal_values(chip);
490 /* phy means physical registers */
491 int zd_chip_lock_phy_regs(struct zd_chip *chip)
496 ZD_ASSERT(mutex_is_locked(&chip->mutex));
497 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
499 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
503 dev_dbg_f(zd_chip_dev(chip),
504 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
505 tmp &= ~UNLOCK_PHY_REGS;
507 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
509 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
513 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
518 ZD_ASSERT(mutex_is_locked(&chip->mutex));
519 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
521 dev_err(zd_chip_dev(chip),
522 "error ioread32(CR_REG1): %d\n", r);
526 dev_dbg_f(zd_chip_dev(chip),
527 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
528 tmp |= UNLOCK_PHY_REGS;
530 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
532 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
536 /* CR157 can be optionally patched by the EEPROM for original ZD1211 */
537 static int patch_cr157(struct zd_chip *chip)
542 if (!chip->patch_cr157)
545 r = zd_ioread16_locked(chip, &value, E2P_PHY_REG);
549 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
550 return zd_iowrite32_locked(chip, value >> 8, CR157);
554 * 6M band edge can be optionally overwritten for certain RF's
555 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
556 * bit (for AL2230, AL2230S)
558 static int patch_6m_band_edge(struct zd_chip *chip, u8 channel)
560 ZD_ASSERT(mutex_is_locked(&chip->mutex));
561 if (!chip->patch_6m_band_edge)
564 return zd_rf_patch_6m_band_edge(&chip->rf, channel);
567 /* Generic implementation of 6M band edge patching, used by most RFs via
568 * zd_rf_generic_patch_6m() */
569 int zd_chip_generic_patch_6m_band(struct zd_chip *chip, int channel)
571 struct zd_ioreq16 ioreqs[] = {
572 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
576 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
577 if (channel == 1 || channel == 11)
578 ioreqs[0].value = 0x12;
580 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
581 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
584 static int zd1211_hw_reset_phy(struct zd_chip *chip)
586 static const struct zd_ioreq16 ioreqs[] = {
587 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
588 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
589 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
590 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
591 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
592 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
593 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
594 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
595 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
596 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
597 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
598 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
599 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
600 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
601 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
602 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
603 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
604 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
605 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
606 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
607 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
608 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
609 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
610 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
611 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
612 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
613 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
614 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
615 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
616 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
617 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
618 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
619 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
621 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
622 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
623 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
624 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
625 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
626 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
627 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
628 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
629 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
630 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
631 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
632 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
633 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
634 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
635 { CR125, 0xaa }, { CR127, 0x03 }, { CR128, 0x14 },
636 { CR129, 0x12 }, { CR130, 0x10 }, { CR131, 0x0C },
637 { CR136, 0xdf }, { CR137, 0x40 }, { CR138, 0xa0 },
638 { CR139, 0xb0 }, { CR140, 0x99 }, { CR141, 0x82 },
639 { CR142, 0x54 }, { CR143, 0x1c }, { CR144, 0x6c },
640 { CR147, 0x07 }, { CR148, 0x4c }, { CR149, 0x50 },
641 { CR150, 0x0e }, { CR151, 0x18 }, { CR160, 0xfe },
642 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
643 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
644 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
645 { CR170, 0xba }, { CR171, 0xba },
646 /* Note: CR204 must lead the CR203 */
654 dev_dbg_f(zd_chip_dev(chip), "\n");
656 r = zd_chip_lock_phy_regs(chip);
660 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
664 r = patch_cr157(chip);
666 t = zd_chip_unlock_phy_regs(chip);
673 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
675 static const struct zd_ioreq16 ioreqs[] = {
676 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
677 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
679 /* power control { { CR11, 1 << 6 }, */
681 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
682 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
683 { CR18, 0x0a }, { CR19, 0x48 },
684 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
685 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
686 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
687 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
688 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
689 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
690 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
691 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
692 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
693 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
694 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
695 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
696 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
697 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
698 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
699 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
700 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
701 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
702 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
703 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
704 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
706 { CR95, 0x20 }, /* ZD1211B */
707 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
708 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
709 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
710 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
711 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
712 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
713 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
714 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
715 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
716 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
717 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
718 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
719 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
720 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
721 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
722 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
723 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
724 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
725 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
726 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
727 { CR170, 0xba }, { CR171, 0xba },
728 /* Note: CR204 must lead the CR203 */
736 dev_dbg_f(zd_chip_dev(chip), "\n");
738 r = zd_chip_lock_phy_regs(chip);
742 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
743 t = zd_chip_unlock_phy_regs(chip);
750 static int hw_reset_phy(struct zd_chip *chip)
752 return zd_chip_is_zd1211b(chip) ? zd1211b_hw_reset_phy(chip) :
753 zd1211_hw_reset_phy(chip);
756 static int zd1211_hw_init_hmac(struct zd_chip *chip)
758 static const struct zd_ioreq32 ioreqs[] = {
759 { CR_ZD1211_RETRY_MAX, 0x2 },
760 { CR_RX_THRESHOLD, 0x000c0640 },
763 dev_dbg_f(zd_chip_dev(chip), "\n");
764 ZD_ASSERT(mutex_is_locked(&chip->mutex));
765 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
768 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
770 static const struct zd_ioreq32 ioreqs[] = {
771 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
772 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
773 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
774 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
775 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
776 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
777 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
778 { CR_ZD1211B_TXOP, 0x01800824 },
779 { CR_RX_THRESHOLD, 0x000c0eff, },
782 dev_dbg_f(zd_chip_dev(chip), "\n");
783 ZD_ASSERT(mutex_is_locked(&chip->mutex));
784 return zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
787 static int hw_init_hmac(struct zd_chip *chip)
790 static const struct zd_ioreq32 ioreqs[] = {
791 { CR_ACK_TIMEOUT_EXT, 0x20 },
792 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
793 { CR_SNIFFER_ON, 0 },
794 { CR_RX_FILTER, STA_RX_FILTER },
795 { CR_GROUP_HASH_P1, 0x00 },
796 { CR_GROUP_HASH_P2, 0x80000000 },
798 { CR_ADDA_PWR_DWN, 0x7f },
799 { CR_BCN_PLCP_CFG, 0x00f00401 },
800 { CR_PHY_DELAY, 0x00 },
801 { CR_ACK_TIMEOUT_EXT, 0x80 },
802 { CR_ADDA_PWR_DWN, 0x00 },
803 { CR_ACK_TIME_80211, 0x100 },
804 { CR_RX_PE_DELAY, 0x70 },
805 { CR_PS_CTRL, 0x10000000 },
806 { CR_RTS_CTS_RATE, 0x02030203 },
807 { CR_AFTER_PNP, 0x1 },
808 { CR_WEP_PROTECT, 0x114 },
809 { CR_IFS_VALUE, IFS_VALUE_DEFAULT },
812 ZD_ASSERT(mutex_is_locked(&chip->mutex));
813 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
817 return zd_chip_is_zd1211b(chip) ?
818 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
827 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
830 static const zd_addr_t aw_pt_bi_addr[] =
831 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
834 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
835 ARRAY_SIZE(aw_pt_bi_addr));
837 memset(s, 0, sizeof(*s));
841 s->atim_wnd_period = values[0];
842 s->pre_tbtt = values[1];
843 s->beacon_interval = values[2];
844 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
845 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
849 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
851 struct zd_ioreq32 reqs[3];
853 if (s->beacon_interval <= 5)
854 s->beacon_interval = 5;
855 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
856 s->pre_tbtt = s->beacon_interval - 1;
857 if (s->atim_wnd_period >= s->pre_tbtt)
858 s->atim_wnd_period = s->pre_tbtt - 1;
860 reqs[0].addr = CR_ATIM_WND_PERIOD;
861 reqs[0].value = s->atim_wnd_period;
862 reqs[1].addr = CR_PRE_TBTT;
863 reqs[1].value = s->pre_tbtt;
864 reqs[2].addr = CR_BCN_INTERVAL;
865 reqs[2].value = s->beacon_interval;
867 dev_dbg_f(zd_chip_dev(chip),
868 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
870 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
874 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
879 ZD_ASSERT(mutex_is_locked(&chip->mutex));
880 r = get_aw_pt_bi(chip, &s);
883 s.beacon_interval = interval;
884 return set_aw_pt_bi(chip, &s);
887 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
891 mutex_lock(&chip->mutex);
892 r = set_beacon_interval(chip, interval);
893 mutex_unlock(&chip->mutex);
897 static int hw_init(struct zd_chip *chip)
901 dev_dbg_f(zd_chip_dev(chip), "\n");
902 ZD_ASSERT(mutex_is_locked(&chip->mutex));
903 r = hw_reset_phy(chip);
907 r = hw_init_hmac(chip);
911 return set_beacon_interval(chip, 100);
914 static zd_addr_t fw_reg_addr(struct zd_chip *chip, u16 offset)
916 return (zd_addr_t)((u16)chip->fw_regs_base + offset);
920 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
921 const char *addr_string)
926 r = zd_ioread32_locked(chip, &value, addr);
928 dev_dbg_f(zd_chip_dev(chip),
929 "error reading %s. Error number %d\n", addr_string, r);
933 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
934 addr_string, (unsigned int)value);
938 static int test_init(struct zd_chip *chip)
942 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
945 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
948 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
951 static void dump_fw_registers(struct zd_chip *chip)
953 const zd_addr_t addr[4] = {
954 fw_reg_addr(chip, FW_REG_FIRMWARE_VER),
955 fw_reg_addr(chip, FW_REG_USB_SPEED),
956 fw_reg_addr(chip, FW_REG_FIX_TX_RATE),
957 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
963 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
966 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
971 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
972 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
973 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
974 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
978 static int print_fw_version(struct zd_chip *chip)
983 r = zd_ioread16_locked(chip, &version,
984 fw_reg_addr(chip, FW_REG_FIRMWARE_VER));
988 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
992 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
995 ZD_ASSERT(mutex_is_locked(&chip->mutex));
996 /* This sets the mandatory rates, which only depend from the standard
997 * that the device is supporting. Until further notice we should try
998 * to support 802.11g also for full speed USB.
1002 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1005 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1006 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1011 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1014 int zd_chip_set_rts_cts_rate_locked(struct zd_chip *chip,
1015 u8 rts_rate, int preamble)
1017 int rts_mod = ZD_RX_CCK;
1020 /* Modulation bit */
1021 if (ZD_CS_TYPE(rts_rate) == ZD_CS_OFDM)
1022 rts_mod = ZD_RX_OFDM;
1024 dev_dbg_f(zd_chip_dev(chip), "rts_rate=%x preamble=%x\n",
1025 rts_rate, preamble);
1027 value |= rts_rate << RTSCTS_SH_RTS_RATE;
1028 value |= rts_mod << RTSCTS_SH_RTS_MOD_TYPE;
1029 value |= preamble << RTSCTS_SH_RTS_PMB_TYPE;
1030 value |= preamble << RTSCTS_SH_CTS_PMB_TYPE;
1032 /* We always send 11M self-CTS messages, like the vendor driver. */
1033 value |= ZD_CCK_RATE_11M << RTSCTS_SH_CTS_RATE;
1034 value |= ZD_RX_CCK << RTSCTS_SH_CTS_MOD_TYPE;
1036 return zd_iowrite32_locked(chip, value, CR_RTS_CTS_RATE);
1039 int zd_chip_enable_hwint(struct zd_chip *chip)
1043 mutex_lock(&chip->mutex);
1044 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1045 mutex_unlock(&chip->mutex);
1049 static int disable_hwint(struct zd_chip *chip)
1051 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1054 int zd_chip_disable_hwint(struct zd_chip *chip)
1058 mutex_lock(&chip->mutex);
1059 r = disable_hwint(chip);
1060 mutex_unlock(&chip->mutex);
1064 static int read_fw_regs_offset(struct zd_chip *chip)
1068 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1069 r = zd_ioread16_locked(chip, (u16*)&chip->fw_regs_base,
1073 dev_dbg_f(zd_chip_dev(chip), "fw_regs_base: %#06hx\n",
1074 (u16)chip->fw_regs_base);
1079 /* Read mac address using pre-firmware interface */
1080 int zd_chip_read_mac_addr_fw(struct zd_chip *chip, u8 *addr)
1082 dev_dbg_f(zd_chip_dev(chip), "\n");
1083 return zd_usb_read_fw(&chip->usb, E2P_MAC_ADDR_P1, addr,
1087 int zd_chip_init_hw(struct zd_chip *chip)
1092 dev_dbg_f(zd_chip_dev(chip), "\n");
1094 mutex_lock(&chip->mutex);
1097 r = test_init(chip);
1101 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1105 r = read_fw_regs_offset(chip);
1109 /* GPI is always disabled, also in the other driver.
1111 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1114 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1117 /* Currently we support IEEE 802.11g for full and high speed USB.
1118 * It might be discussed, whether we should suppport pure b mode for
1121 r = set_mandatory_rates(chip, IEEE80211G);
1124 /* Disabling interrupts is certainly a smart thing here.
1126 r = disable_hwint(chip);
1129 r = read_pod(chip, &rf_type);
1135 r = zd_rf_init_hw(&chip->rf, rf_type);
1139 r = print_fw_version(chip);
1144 dump_fw_registers(chip);
1145 r = test_init(chip);
1150 r = read_cal_int_tables(chip);
1156 mutex_unlock(&chip->mutex);
1160 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1162 u8 value = chip->pwr_int_values[channel - 1];
1163 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1165 return zd_iowrite16_locked(chip, value, CR31);
1168 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1170 u8 value = chip->pwr_cal_values[channel-1];
1171 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1173 return zd_iowrite16_locked(chip, value, CR68);
1176 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1178 struct zd_ioreq16 ioreqs[3];
1180 ioreqs[0].addr = CR67;
1181 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1182 ioreqs[1].addr = CR66;
1183 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1184 ioreqs[2].addr = CR65;
1185 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1187 dev_dbg_f(zd_chip_dev(chip),
1188 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1189 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1190 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1193 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1198 if (!zd_rf_should_update_pwr_int(&chip->rf))
1201 r = update_pwr_int(chip, channel);
1204 if (zd_chip_is_zd1211b(chip)) {
1205 static const struct zd_ioreq16 ioreqs[] = {
1211 r = update_ofdm_cal(chip, channel);
1214 r = update_pwr_cal(chip, channel);
1217 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1225 /* The CCK baseband gain can be optionally patched by the EEPROM */
1226 static int patch_cck_gain(struct zd_chip *chip)
1231 if (!chip->patch_cck_gain || !zd_rf_should_patch_cck_gain(&chip->rf))
1234 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1235 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1238 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1239 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1242 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1246 mutex_lock(&chip->mutex);
1247 r = zd_chip_lock_phy_regs(chip);
1250 r = zd_rf_set_channel(&chip->rf, channel);
1253 r = update_channel_integration_and_calibration(chip, channel);
1256 r = patch_cck_gain(chip);
1259 r = patch_6m_band_edge(chip, channel);
1262 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1264 t = zd_chip_unlock_phy_regs(chip);
1268 mutex_unlock(&chip->mutex);
1272 u8 zd_chip_get_channel(struct zd_chip *chip)
1276 mutex_lock(&chip->mutex);
1277 channel = chip->rf.channel;
1278 mutex_unlock(&chip->mutex);
1282 int zd_chip_control_leds(struct zd_chip *chip, enum led_status status)
1284 const zd_addr_t a[] = {
1285 fw_reg_addr(chip, FW_REG_LED_LINK_STATUS),
1290 u16 v[ARRAY_SIZE(a)];
1291 struct zd_ioreq16 ioreqs[ARRAY_SIZE(a)] = {
1292 [0] = { fw_reg_addr(chip, FW_REG_LED_LINK_STATUS) },
1297 mutex_lock(&chip->mutex);
1298 r = zd_ioread16v_locked(chip, v, (const zd_addr_t *)a, ARRAY_SIZE(a));
1302 other_led = chip->link_led == LED1 ? LED2 : LED1;
1306 ioreqs[0].value = FW_LINK_OFF;
1307 ioreqs[1].value = v[1] & ~(LED1|LED2);
1310 ioreqs[0].value = FW_LINK_OFF;
1311 ioreqs[1].value = v[1] & ~other_led;
1312 if (get_seconds() % 3 == 0) {
1313 ioreqs[1].value &= ~chip->link_led;
1315 ioreqs[1].value |= chip->link_led;
1318 case LED_ASSOCIATED:
1319 ioreqs[0].value = FW_LINK_TX;
1320 ioreqs[1].value = v[1] & ~other_led;
1321 ioreqs[1].value |= chip->link_led;
1328 if (v[0] != ioreqs[0].value || v[1] != ioreqs[1].value) {
1329 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1335 mutex_unlock(&chip->mutex);
1339 int zd_chip_set_basic_rates_locked(struct zd_chip *chip, u16 cr_rates)
1341 ZD_ASSERT((cr_rates & ~(CR_RATES_80211B | CR_RATES_80211G)) == 0);
1342 dev_dbg_f(zd_chip_dev(chip), "%x\n", cr_rates);
1344 return zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1347 static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1349 static const u16 constants[] = {
1350 715, 655, 585, 540, 470, 410, 360, 315,
1351 270, 235, 205, 175, 150, 125, 105, 85,
1358 /* It seems that their quality parameter is somehow per signal
1359 * and is now transferred per bit.
1362 case ZD_OFDM_RATE_6M:
1363 case ZD_OFDM_RATE_12M:
1364 case ZD_OFDM_RATE_24M:
1367 case ZD_OFDM_RATE_9M:
1368 case ZD_OFDM_RATE_18M:
1369 case ZD_OFDM_RATE_36M:
1370 case ZD_OFDM_RATE_54M:
1374 case ZD_OFDM_RATE_48M:
1382 x = (10000 * status_quality)/size;
1383 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1384 if (x > constants[i])
1389 case ZD_OFDM_RATE_6M:
1390 case ZD_OFDM_RATE_9M:
1393 case ZD_OFDM_RATE_12M:
1394 case ZD_OFDM_RATE_18M:
1397 case ZD_OFDM_RATE_24M:
1398 case ZD_OFDM_RATE_36M:
1401 case ZD_OFDM_RATE_48M:
1402 case ZD_OFDM_RATE_54M:
1412 static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1416 r = ofdm_qual_db(status_quality, rate, size);
1422 return r <= 100 ? r : 100;
1425 static unsigned int log10times100(unsigned int x)
1427 static const u8 log10[] = {
1429 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1430 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1431 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1432 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1433 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1434 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1435 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1436 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1437 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1438 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1439 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1440 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1441 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1442 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1443 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1444 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1445 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1446 223, 223, 223, 224, 224, 224, 224,
1449 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1453 MAX_CCK_EVM_DB = 45,
1456 static int cck_evm_db(u8 status_quality)
1458 return (20 * log10times100(status_quality)) / 100;
1461 static int cck_snr_db(u8 status_quality)
1463 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1468 static int cck_qual_percent(u8 status_quality)
1472 r = cck_snr_db(status_quality);
1474 return r <= 100 ? r : 100;
1477 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1478 const struct rx_status *status)
1480 return (status->frame_status&ZD_RX_OFDM) ?
1481 ofdm_qual_percent(status->signal_quality_ofdm,
1482 zd_ofdm_plcp_header_rate(rx_frame),
1484 cck_qual_percent(status->signal_quality_cck);
1487 u8 zd_rx_strength_percent(u8 rssi)
1489 int r = (rssi*100) / 41;
1495 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1497 static const u16 ofdm_rates[] = {
1498 [ZD_OFDM_RATE_6M] = 60,
1499 [ZD_OFDM_RATE_9M] = 90,
1500 [ZD_OFDM_RATE_12M] = 120,
1501 [ZD_OFDM_RATE_18M] = 180,
1502 [ZD_OFDM_RATE_24M] = 240,
1503 [ZD_OFDM_RATE_36M] = 360,
1504 [ZD_OFDM_RATE_48M] = 480,
1505 [ZD_OFDM_RATE_54M] = 540,
1508 if (status->frame_status & ZD_RX_OFDM) {
1509 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1510 rate = ofdm_rates[ofdm_rate & 0xf];
1512 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1514 case ZD_CCK_SIGNAL_1M:
1517 case ZD_CCK_SIGNAL_2M:
1520 case ZD_CCK_SIGNAL_5M5:
1523 case ZD_CCK_SIGNAL_11M:
1534 int zd_chip_switch_radio_on(struct zd_chip *chip)
1538 mutex_lock(&chip->mutex);
1539 r = zd_switch_radio_on(&chip->rf);
1540 mutex_unlock(&chip->mutex);
1544 int zd_chip_switch_radio_off(struct zd_chip *chip)
1548 mutex_lock(&chip->mutex);
1549 r = zd_switch_radio_off(&chip->rf);
1550 mutex_unlock(&chip->mutex);
1554 int zd_chip_enable_int(struct zd_chip *chip)
1558 mutex_lock(&chip->mutex);
1559 r = zd_usb_enable_int(&chip->usb);
1560 mutex_unlock(&chip->mutex);
1564 void zd_chip_disable_int(struct zd_chip *chip)
1566 mutex_lock(&chip->mutex);
1567 zd_usb_disable_int(&chip->usb);
1568 mutex_unlock(&chip->mutex);
1571 int zd_chip_enable_rx(struct zd_chip *chip)
1575 mutex_lock(&chip->mutex);
1576 r = zd_usb_enable_rx(&chip->usb);
1577 mutex_unlock(&chip->mutex);
1581 void zd_chip_disable_rx(struct zd_chip *chip)
1583 mutex_lock(&chip->mutex);
1584 zd_usb_disable_rx(&chip->usb);
1585 mutex_unlock(&chip->mutex);
1588 int zd_rfwritev_locked(struct zd_chip *chip,
1589 const u32* values, unsigned int count, u8 bits)
1594 for (i = 0; i < count; i++) {
1595 r = zd_rfwrite_locked(chip, values[i], bits);
1604 * We can optionally program the RF directly through CR regs, if supported by
1605 * the hardware. This is much faster than the older method.
1607 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1609 struct zd_ioreq16 ioreqs[] = {
1610 { CR244, (value >> 16) & 0xff },
1611 { CR243, (value >> 8) & 0xff },
1612 { CR242, value & 0xff },
1614 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1615 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1618 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1619 const u32 *values, unsigned int count)
1624 for (i = 0; i < count; i++) {
1625 r = zd_rfwrite_cr_locked(chip, values[i]);
1633 int zd_chip_set_multicast_hash(struct zd_chip *chip,
1634 struct zd_mc_hash *hash)
1636 struct zd_ioreq32 ioreqs[] = {
1637 { CR_GROUP_HASH_P1, hash->low },
1638 { CR_GROUP_HASH_P2, hash->high },
1641 dev_dbg_f(zd_chip_dev(chip), "hash l 0x%08x h 0x%08x\n",
1642 ioreqs[0].value, ioreqs[1].value);
1643 return zd_iowrite32a(chip, ioreqs, ARRAY_SIZE(ioreqs));