3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License as published by
5 * the Free Software Foundation; either version 2 of the License, or
6 * (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 /* This file implements all the hardware specific functions for the ZD1211
19 * and ZD1211B chips. Support for the ZD1211B was possible after Timothy
20 * Legge sent me a ZD1211B device. Thank you Tim. -- Uli
23 #include <linux/kernel.h>
24 #include <linux/errno.h>
28 #include "zd_ieee80211.h"
33 void zd_chip_init(struct zd_chip *chip,
34 struct net_device *netdev,
35 struct usb_interface *intf)
37 memset(chip, 0, sizeof(*chip));
38 mutex_init(&chip->mutex);
39 zd_usb_init(&chip->usb, netdev, intf);
40 zd_rf_init(&chip->rf);
43 void zd_chip_clear(struct zd_chip *chip)
45 ZD_ASSERT(!mutex_is_locked(&chip->mutex));
46 zd_usb_clear(&chip->usb);
47 zd_rf_clear(&chip->rf);
48 mutex_destroy(&chip->mutex);
49 ZD_MEMCLEAR(chip, sizeof(*chip));
52 static int scnprint_mac_oui(const u8 *addr, char *buffer, size_t size)
54 return scnprintf(buffer, size, "%02x-%02x-%02x",
55 addr[0], addr[1], addr[2]);
58 /* Prints an identifier line, which will support debugging. */
59 static int scnprint_id(struct zd_chip *chip, char *buffer, size_t size)
63 i = scnprintf(buffer, size, "zd1211%s chip ",
64 chip->is_zd1211b ? "b" : "");
65 i += zd_usb_scnprint_id(&chip->usb, buffer+i, size-i);
66 i += scnprintf(buffer+i, size-i, " ");
67 i += scnprint_mac_oui(chip->e2p_mac, buffer+i, size-i);
68 i += scnprintf(buffer+i, size-i, " ");
69 i += zd_rf_scnprint_id(&chip->rf, buffer+i, size-i);
70 i += scnprintf(buffer+i, size-i, " pa%1x %c%c%c%c", chip->pa_type,
71 chip->patch_cck_gain ? 'g' : '-',
72 chip->patch_cr157 ? '7' : '-',
73 chip->patch_6m_band_edge ? '6' : '-',
74 chip->new_phy_layout ? 'N' : '-');
78 static void print_id(struct zd_chip *chip)
82 scnprint_id(chip, buffer, sizeof(buffer));
83 buffer[sizeof(buffer)-1] = 0;
84 dev_info(zd_chip_dev(chip), "%s\n", buffer);
87 /* Read a variable number of 32-bit values. Parameter count is not allowed to
88 * exceed USB_MAX_IOREAD32_COUNT.
90 int zd_ioread32v_locked(struct zd_chip *chip, u32 *values, const zd_addr_t *addr,
95 zd_addr_t *a16 = (zd_addr_t *)NULL;
99 if (count > USB_MAX_IOREAD32_COUNT)
102 /* Allocate a single memory block for values and addresses. */
104 a16 = (zd_addr_t *)kmalloc(count16 * (sizeof(zd_addr_t) + sizeof(u16)),
107 dev_dbg_f(zd_chip_dev(chip),
108 "error ENOMEM in allocation of a16\n");
112 v16 = (u16 *)(a16 + count16);
114 for (i = 0; i < count; i++) {
116 /* We read the high word always first. */
117 a16[j] = zd_inc_word(addr[i]);
121 r = zd_ioread16v_locked(chip, v16, a16, count16);
123 dev_dbg_f(zd_chip_dev(chip),
124 "error: zd_ioread16v_locked. Error number %d\n", r);
128 for (i = 0; i < count; i++) {
130 values[i] = (v16[j] << 16) | v16[j+1];
138 int _zd_iowrite32v_locked(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
142 struct zd_ioreq16 *ioreqs16;
143 unsigned int count16;
145 ZD_ASSERT(mutex_is_locked(&chip->mutex));
149 if (count > USB_MAX_IOWRITE32_COUNT)
152 /* Allocate a single memory block for values and addresses. */
154 ioreqs16 = kmalloc(count16 * sizeof(struct zd_ioreq16), GFP_NOFS);
157 dev_dbg_f(zd_chip_dev(chip),
158 "error %d in ioreqs16 allocation\n", r);
162 for (i = 0; i < count; i++) {
164 /* We write the high word always first. */
165 ioreqs16[j].value = ioreqs[i].value >> 16;
166 ioreqs16[j].addr = zd_inc_word(ioreqs[i].addr);
167 ioreqs16[j+1].value = ioreqs[i].value;
168 ioreqs16[j+1].addr = ioreqs[i].addr;
171 r = zd_usb_iowrite16v(&chip->usb, ioreqs16, count16);
174 dev_dbg_f(zd_chip_dev(chip),
175 "error %d in zd_usb_write16v\n", r);
183 int zd_iowrite16a_locked(struct zd_chip *chip,
184 const struct zd_ioreq16 *ioreqs, unsigned int count)
187 unsigned int i, j, t, max;
189 ZD_ASSERT(mutex_is_locked(&chip->mutex));
190 for (i = 0; i < count; i += j + t) {
193 if (max > USB_MAX_IOWRITE16_COUNT)
194 max = USB_MAX_IOWRITE16_COUNT;
195 for (j = 0; j < max; j++) {
196 if (!ioreqs[i+j].addr) {
202 r = zd_usb_iowrite16v(&chip->usb, &ioreqs[i], j);
204 dev_dbg_f(zd_chip_dev(chip),
205 "error zd_usb_iowrite16v. Error number %d\n",
214 /* Writes a variable number of 32 bit registers. The functions will split
215 * that in several USB requests. A split can be forced by inserting an IO
216 * request with an zero address field.
218 int zd_iowrite32a_locked(struct zd_chip *chip,
219 const struct zd_ioreq32 *ioreqs, unsigned int count)
222 unsigned int i, j, t, max;
224 for (i = 0; i < count; i += j + t) {
227 if (max > USB_MAX_IOWRITE32_COUNT)
228 max = USB_MAX_IOWRITE32_COUNT;
229 for (j = 0; j < max; j++) {
230 if (!ioreqs[i+j].addr) {
236 r = _zd_iowrite32v_locked(chip, &ioreqs[i], j);
238 dev_dbg_f(zd_chip_dev(chip),
239 "error _zd_iowrite32v_locked."
240 " Error number %d\n", r);
248 int zd_ioread16(struct zd_chip *chip, zd_addr_t addr, u16 *value)
252 mutex_lock(&chip->mutex);
253 r = zd_ioread16_locked(chip, value, addr);
254 mutex_unlock(&chip->mutex);
258 int zd_ioread32(struct zd_chip *chip, zd_addr_t addr, u32 *value)
262 mutex_lock(&chip->mutex);
263 r = zd_ioread32_locked(chip, value, addr);
264 mutex_unlock(&chip->mutex);
268 int zd_iowrite16(struct zd_chip *chip, zd_addr_t addr, u16 value)
272 mutex_lock(&chip->mutex);
273 r = zd_iowrite16_locked(chip, value, addr);
274 mutex_unlock(&chip->mutex);
278 int zd_iowrite32(struct zd_chip *chip, zd_addr_t addr, u32 value)
282 mutex_lock(&chip->mutex);
283 r = zd_iowrite32_locked(chip, value, addr);
284 mutex_unlock(&chip->mutex);
288 int zd_ioread32v(struct zd_chip *chip, const zd_addr_t *addresses,
289 u32 *values, unsigned int count)
293 mutex_lock(&chip->mutex);
294 r = zd_ioread32v_locked(chip, values, addresses, count);
295 mutex_unlock(&chip->mutex);
299 int zd_iowrite32a(struct zd_chip *chip, const struct zd_ioreq32 *ioreqs,
304 mutex_lock(&chip->mutex);
305 r = zd_iowrite32a_locked(chip, ioreqs, count);
306 mutex_unlock(&chip->mutex);
310 static int read_pod(struct zd_chip *chip, u8 *rf_type)
315 ZD_ASSERT(mutex_is_locked(&chip->mutex));
316 r = zd_ioread32_locked(chip, &value, E2P_POD);
319 dev_dbg_f(zd_chip_dev(chip), "E2P_POD %#010x\n", value);
321 /* FIXME: AL2230 handling (Bit 7 in POD) */
322 *rf_type = value & 0x0f;
323 chip->pa_type = (value >> 16) & 0x0f;
324 chip->patch_cck_gain = (value >> 8) & 0x1;
325 chip->patch_cr157 = (value >> 13) & 0x1;
326 chip->patch_6m_band_edge = (value >> 21) & 0x1;
327 chip->new_phy_layout = (value >> 31) & 0x1;
329 dev_dbg_f(zd_chip_dev(chip),
330 "RF %s %#01x PA type %#01x patch CCK %d patch CR157 %d "
331 "patch 6M %d new PHY %d\n",
332 zd_rf_name(*rf_type), *rf_type,
333 chip->pa_type, chip->patch_cck_gain,
334 chip->patch_cr157, chip->patch_6m_band_edge, chip->new_phy_layout);
339 chip->patch_cck_gain = 0;
340 chip->patch_cr157 = 0;
341 chip->patch_6m_band_edge = 0;
342 chip->new_phy_layout = 0;
346 static int _read_mac_addr(struct zd_chip *chip, u8 *mac_addr,
347 const zd_addr_t *addr)
352 r = zd_ioread32v_locked(chip, parts, (const zd_addr_t *)addr, 2);
354 dev_dbg_f(zd_chip_dev(chip),
355 "error: couldn't read e2p macs. Error number %d\n", r);
359 mac_addr[0] = parts[0];
360 mac_addr[1] = parts[0] >> 8;
361 mac_addr[2] = parts[0] >> 16;
362 mac_addr[3] = parts[0] >> 24;
363 mac_addr[4] = parts[1];
364 mac_addr[5] = parts[1] >> 8;
369 static int read_e2p_mac_addr(struct zd_chip *chip)
371 static const zd_addr_t addr[2] = { E2P_MAC_ADDR_P1, E2P_MAC_ADDR_P2 };
373 ZD_ASSERT(mutex_is_locked(&chip->mutex));
374 return _read_mac_addr(chip, chip->e2p_mac, (const zd_addr_t *)addr);
377 /* MAC address: if custom mac addresses are to to be used CR_MAC_ADDR_P1 and
378 * CR_MAC_ADDR_P2 must be overwritten
380 void zd_get_e2p_mac_addr(struct zd_chip *chip, u8 *mac_addr)
382 mutex_lock(&chip->mutex);
383 memcpy(mac_addr, chip->e2p_mac, ETH_ALEN);
384 mutex_unlock(&chip->mutex);
387 static int read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
389 static const zd_addr_t addr[2] = { CR_MAC_ADDR_P1, CR_MAC_ADDR_P2 };
390 return _read_mac_addr(chip, mac_addr, (const zd_addr_t *)addr);
393 int zd_read_mac_addr(struct zd_chip *chip, u8 *mac_addr)
397 dev_dbg_f(zd_chip_dev(chip), "\n");
398 mutex_lock(&chip->mutex);
399 r = read_mac_addr(chip, mac_addr);
400 mutex_unlock(&chip->mutex);
404 int zd_write_mac_addr(struct zd_chip *chip, const u8 *mac_addr)
407 struct zd_ioreq32 reqs[2] = {
408 [0] = { .addr = CR_MAC_ADDR_P1 },
409 [1] = { .addr = CR_MAC_ADDR_P2 },
412 reqs[0].value = (mac_addr[3] << 24)
413 | (mac_addr[2] << 16)
416 reqs[1].value = (mac_addr[5] << 8)
419 dev_dbg_f(zd_chip_dev(chip),
420 "mac addr " MAC_FMT "\n", MAC_ARG(mac_addr));
422 mutex_lock(&chip->mutex);
423 r = zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
427 read_mac_addr(chip, tmp);
430 mutex_unlock(&chip->mutex);
434 int zd_read_regdomain(struct zd_chip *chip, u8 *regdomain)
439 mutex_lock(&chip->mutex);
440 r = zd_ioread32_locked(chip, &value, E2P_SUBID);
441 mutex_unlock(&chip->mutex);
445 *regdomain = value >> 16;
446 dev_dbg_f(zd_chip_dev(chip), "regdomain: %#04x\n", *regdomain);
451 static int read_values(struct zd_chip *chip, u8 *values, size_t count,
452 zd_addr_t e2p_addr, u32 guard)
458 ZD_ASSERT(mutex_is_locked(&chip->mutex));
460 r = zd_ioread32_locked(chip, &v, e2p_addr+i/2);
466 values[i++] = v >> 8;
467 values[i++] = v >> 16;
468 values[i++] = v >> 24;
471 for (;i < count; i++)
472 values[i] = v >> (8*(i%3));
477 static int read_pwr_cal_values(struct zd_chip *chip)
479 return read_values(chip, chip->pwr_cal_values,
480 E2P_CHANNEL_COUNT, E2P_PWR_CAL_VALUE1,
484 static int read_pwr_int_values(struct zd_chip *chip)
486 return read_values(chip, chip->pwr_int_values,
487 E2P_CHANNEL_COUNT, E2P_PWR_INT_VALUE1,
491 static int read_ofdm_cal_values(struct zd_chip *chip)
495 static const zd_addr_t addresses[] = {
501 for (i = 0; i < 3; i++) {
502 r = read_values(chip, chip->ofdm_cal_values[i],
503 E2P_CHANNEL_COUNT, addresses[i], 0);
510 static int read_cal_int_tables(struct zd_chip *chip)
514 r = read_pwr_cal_values(chip);
517 r = read_pwr_int_values(chip);
520 r = read_ofdm_cal_values(chip);
526 /* phy means physical registers */
527 int zd_chip_lock_phy_regs(struct zd_chip *chip)
532 ZD_ASSERT(mutex_is_locked(&chip->mutex));
533 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
535 dev_err(zd_chip_dev(chip), "error ioread32(CR_REG1): %d\n", r);
539 dev_dbg_f(zd_chip_dev(chip),
540 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp & ~UNLOCK_PHY_REGS);
541 tmp &= ~UNLOCK_PHY_REGS;
543 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
545 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
549 int zd_chip_unlock_phy_regs(struct zd_chip *chip)
554 ZD_ASSERT(mutex_is_locked(&chip->mutex));
555 r = zd_ioread32_locked(chip, &tmp, CR_REG1);
557 dev_err(zd_chip_dev(chip),
558 "error ioread32(CR_REG1): %d\n", r);
562 dev_dbg_f(zd_chip_dev(chip),
563 "CR_REG1: 0x%02x -> 0x%02x\n", tmp, tmp | UNLOCK_PHY_REGS);
564 tmp |= UNLOCK_PHY_REGS;
566 r = zd_iowrite32_locked(chip, tmp, CR_REG1);
568 dev_err(zd_chip_dev(chip), "error iowrite32(CR_REG1): %d\n", r);
572 /* CR157 can be optionally patched by the EEPROM */
573 static int patch_cr157(struct zd_chip *chip)
578 if (!chip->patch_cr157)
581 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
585 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value >> 8);
586 return zd_iowrite32_locked(chip, value >> 8, CR157);
590 * 6M band edge can be optionally overwritten for certain RF's
591 * Vendor driver says: for FCC regulation, enabled per HWFeature 6M band edge
592 * bit (for AL2230, AL2230S)
594 static int patch_6m_band_edge(struct zd_chip *chip, int channel)
596 struct zd_ioreq16 ioreqs[] = {
597 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
601 if (!chip->patch_6m_band_edge || !chip->rf.patch_6m_band_edge)
604 /* FIXME: Channel 11 is not the edge for all regulatory domains. */
605 if (channel == 1 || channel == 11)
606 ioreqs[0].value = 0x12;
608 dev_dbg_f(zd_chip_dev(chip), "patching for channel %d\n", channel);
609 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
612 static int zd1211_hw_reset_phy(struct zd_chip *chip)
614 static const struct zd_ioreq16 ioreqs[] = {
615 { CR0, 0x0a }, { CR1, 0x06 }, { CR2, 0x26 },
616 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xa0 },
617 { CR10, 0x81 }, { CR11, 0x00 }, { CR12, 0x7f },
618 { CR13, 0x8c }, { CR14, 0x80 }, { CR15, 0x3d },
619 { CR16, 0x20 }, { CR17, 0x1e }, { CR18, 0x0a },
620 { CR19, 0x48 }, { CR20, 0x0c }, { CR21, 0x0c },
621 { CR22, 0x23 }, { CR23, 0x90 }, { CR24, 0x14 },
622 { CR25, 0x40 }, { CR26, 0x10 }, { CR27, 0x19 },
623 { CR28, 0x7f }, { CR29, 0x80 }, { CR30, 0x4b },
624 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
625 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
626 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
627 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
628 { CR43, 0x10 }, { CR44, 0x12 }, { CR46, 0xff },
629 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
630 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
631 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
632 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
633 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
634 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
635 { CR79, 0x68 }, { CR80, 0x64 }, { CR81, 0x64 },
636 { CR82, 0x00 }, { CR83, 0x00 }, { CR84, 0x00 },
637 { CR85, 0x02 }, { CR86, 0x00 }, { CR87, 0x00 },
638 { CR88, 0xff }, { CR89, 0xfc }, { CR90, 0x00 },
639 { CR91, 0x00 }, { CR92, 0x00 }, { CR93, 0x08 },
640 { CR94, 0x00 }, { CR95, 0x00 }, { CR96, 0xff },
641 { CR97, 0xe7 }, { CR98, 0x00 }, { CR99, 0x00 },
642 { CR100, 0x00 }, { CR101, 0xae }, { CR102, 0x02 },
643 { CR103, 0x00 }, { CR104, 0x03 }, { CR105, 0x65 },
644 { CR106, 0x04 }, { CR107, 0x00 }, { CR108, 0x0a },
645 { CR109, 0xaa }, { CR110, 0xaa }, { CR111, 0x25 },
646 { CR112, 0x25 }, { CR113, 0x00 }, { CR119, 0x1e },
647 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
649 { CR5, 0x00 }, { CR6, 0x00 }, { CR7, 0x00 },
650 { CR8, 0x00 }, { CR9, 0x20 }, { CR12, 0xf0 },
651 { CR20, 0x0e }, { CR21, 0x0e }, { CR27, 0x10 },
652 { CR44, 0x33 }, { CR47, 0x1E }, { CR83, 0x24 },
653 { CR84, 0x04 }, { CR85, 0x00 }, { CR86, 0x0C },
654 { CR87, 0x12 }, { CR88, 0x0C }, { CR89, 0x00 },
655 { CR90, 0x10 }, { CR91, 0x08 }, { CR93, 0x00 },
656 { CR94, 0x01 }, { CR95, 0x00 }, { CR96, 0x50 },
657 { CR97, 0x37 }, { CR98, 0x35 }, { CR101, 0x13 },
658 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
659 { CR105, 0x12 }, { CR109, 0x27 }, { CR110, 0x27 },
660 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
661 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
662 { CR117, 0xfc }, { CR118, 0xfa }, { CR120, 0x4f },
663 { CR123, 0x27 }, { CR125, 0xaa }, { CR127, 0x03 },
664 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
665 { CR131, 0x0C }, { CR136, 0xdf }, { CR137, 0x40 },
666 { CR138, 0xa0 }, { CR139, 0xb0 }, { CR140, 0x99 },
667 { CR141, 0x82 }, { CR142, 0x54 }, { CR143, 0x1c },
668 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x4c },
669 { CR149, 0x50 }, { CR150, 0x0e }, { CR151, 0x18 },
670 { CR160, 0xfe }, { CR161, 0xee }, { CR162, 0xaa },
671 { CR163, 0xfa }, { CR164, 0xfa }, { CR165, 0xea },
672 { CR166, 0xbe }, { CR167, 0xbe }, { CR168, 0x6a },
673 { CR169, 0xba }, { CR170, 0xba }, { CR171, 0xba },
674 /* Note: CR204 must lead the CR203 */
682 dev_dbg_f(zd_chip_dev(chip), "\n");
684 r = zd_chip_lock_phy_regs(chip);
688 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
692 r = patch_cr157(chip);
694 t = zd_chip_unlock_phy_regs(chip);
701 static int zd1211b_hw_reset_phy(struct zd_chip *chip)
703 static const struct zd_ioreq16 ioreqs[] = {
704 { CR0, 0x14 }, { CR1, 0x06 }, { CR2, 0x26 },
705 { CR3, 0x38 }, { CR4, 0x80 }, { CR9, 0xe0 },
707 /* power control { { CR11, 1 << 6 }, */
709 { CR12, 0xf0 }, { CR13, 0x8c }, { CR14, 0x80 },
710 { CR15, 0x3d }, { CR16, 0x20 }, { CR17, 0x1e },
711 { CR18, 0x0a }, { CR19, 0x48 },
712 { CR20, 0x10 }, /* Org:0x0E, ComTrend:RalLink AP */
713 { CR21, 0x0e }, { CR22, 0x23 }, { CR23, 0x90 },
714 { CR24, 0x14 }, { CR25, 0x40 }, { CR26, 0x10 },
715 { CR27, 0x10 }, { CR28, 0x7f }, { CR29, 0x80 },
716 { CR30, 0x4b }, /* ASIC/FWT, no jointly decoder */
717 { CR31, 0x60 }, { CR32, 0x43 }, { CR33, 0x08 },
718 { CR34, 0x06 }, { CR35, 0x0a }, { CR36, 0x00 },
719 { CR37, 0x00 }, { CR38, 0x38 }, { CR39, 0x0c },
720 { CR40, 0x84 }, { CR41, 0x2a }, { CR42, 0x80 },
721 { CR43, 0x10 }, { CR44, 0x33 }, { CR46, 0xff },
722 { CR47, 0x1E }, { CR48, 0x26 }, { CR49, 0x5b },
723 { CR64, 0xd0 }, { CR65, 0x04 }, { CR66, 0x58 },
724 { CR67, 0xc9 }, { CR68, 0x88 }, { CR69, 0x41 },
725 { CR70, 0x23 }, { CR71, 0x10 }, { CR72, 0xff },
726 { CR73, 0x32 }, { CR74, 0x30 }, { CR75, 0x65 },
727 { CR76, 0x41 }, { CR77, 0x1b }, { CR78, 0x30 },
728 { CR79, 0xf0 }, { CR80, 0x64 }, { CR81, 0x64 },
729 { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
730 { CR85, 0x00 }, { CR86, 0x0c }, { CR87, 0x12 },
731 { CR88, 0x0c }, { CR89, 0x00 }, { CR90, 0x58 },
732 { CR91, 0x04 }, { CR92, 0x00 }, { CR93, 0x00 },
734 { CR95, 0x20 }, /* ZD1211B */
735 { CR96, 0x50 }, { CR97, 0x37 }, { CR98, 0x35 },
736 { CR99, 0x00 }, { CR100, 0x01 }, { CR101, 0x13 },
737 { CR102, 0x27 }, { CR103, 0x27 }, { CR104, 0x18 },
738 { CR105, 0x12 }, { CR106, 0x04 }, { CR107, 0x00 },
739 { CR108, 0x0a }, { CR109, 0x27 }, { CR110, 0x27 },
740 { CR111, 0x27 }, { CR112, 0x27 }, { CR113, 0x27 },
741 { CR114, 0x27 }, { CR115, 0x26 }, { CR116, 0x24 },
742 { CR117, 0xfc }, { CR118, 0xfa }, { CR119, 0x1e },
743 { CR125, 0x90 }, { CR126, 0x00 }, { CR127, 0x00 },
744 { CR128, 0x14 }, { CR129, 0x12 }, { CR130, 0x10 },
745 { CR131, 0x0c }, { CR136, 0xdf }, { CR137, 0xa0 },
746 { CR138, 0xa8 }, { CR139, 0xb4 }, { CR140, 0x98 },
747 { CR141, 0x82 }, { CR142, 0x53 }, { CR143, 0x1c },
748 { CR144, 0x6c }, { CR147, 0x07 }, { CR148, 0x40 },
749 { CR149, 0x40 }, /* Org:0x50 ComTrend:RalLink AP */
750 { CR150, 0x14 }, /* Org:0x0E ComTrend:RalLink AP */
751 { CR151, 0x18 }, { CR159, 0x70 }, { CR160, 0xfe },
752 { CR161, 0xee }, { CR162, 0xaa }, { CR163, 0xfa },
753 { CR164, 0xfa }, { CR165, 0xea }, { CR166, 0xbe },
754 { CR167, 0xbe }, { CR168, 0x6a }, { CR169, 0xba },
755 { CR170, 0xba }, { CR171, 0xba },
756 /* Note: CR204 must lead the CR203 */
764 dev_dbg_f(zd_chip_dev(chip), "\n");
766 r = zd_chip_lock_phy_regs(chip);
770 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
774 r = patch_cr157(chip);
776 t = zd_chip_unlock_phy_regs(chip);
783 static int hw_reset_phy(struct zd_chip *chip)
785 return chip->is_zd1211b ? zd1211b_hw_reset_phy(chip) :
786 zd1211_hw_reset_phy(chip);
789 static int zd1211_hw_init_hmac(struct zd_chip *chip)
791 static const struct zd_ioreq32 ioreqs[] = {
792 { CR_ACK_TIMEOUT_EXT, 0x20 },
793 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
794 { CR_ZD1211_RETRY_MAX, 0x2 },
795 { CR_SNIFFER_ON, 0 },
796 { CR_RX_FILTER, STA_RX_FILTER },
797 { CR_GROUP_HASH_P1, 0x00 },
798 { CR_GROUP_HASH_P2, 0x80000000 },
800 { CR_ADDA_PWR_DWN, 0x7f },
801 { CR_BCN_PLCP_CFG, 0x00f00401 },
802 { CR_PHY_DELAY, 0x00 },
803 { CR_ACK_TIMEOUT_EXT, 0x80 },
804 { CR_ADDA_PWR_DWN, 0x00 },
805 { CR_ACK_TIME_80211, 0x100 },
806 { CR_RX_PE_DELAY, 0x70 },
807 { CR_PS_CTRL, 0x10000000 },
808 { CR_RTS_CTS_RATE, 0x02030203 },
809 { CR_RX_THRESHOLD, 0x000c0640 },
810 { CR_AFTER_PNP, 0x1 },
811 { CR_WEP_PROTECT, 0x114 },
816 dev_dbg_f(zd_chip_dev(chip), "\n");
817 ZD_ASSERT(mutex_is_locked(&chip->mutex));
818 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
821 dev_err(zd_chip_dev(chip),
822 "error in zd_iowrite32a_locked. Error number %d\n", r);
828 static int zd1211b_hw_init_hmac(struct zd_chip *chip)
830 static const struct zd_ioreq32 ioreqs[] = {
831 { CR_ACK_TIMEOUT_EXT, 0x20 },
832 { CR_ADDA_MBIAS_WARMTIME, 0x30000808 },
833 { CR_ZD1211B_RETRY_MAX, 0x02020202 },
834 { CR_ZD1211B_TX_PWR_CTL4, 0x007f003f },
835 { CR_ZD1211B_TX_PWR_CTL3, 0x007f003f },
836 { CR_ZD1211B_TX_PWR_CTL2, 0x003f001f },
837 { CR_ZD1211B_TX_PWR_CTL1, 0x001f000f },
838 { CR_ZD1211B_AIFS_CTL1, 0x00280028 },
839 { CR_ZD1211B_AIFS_CTL2, 0x008C003C },
840 { CR_ZD1211B_TXOP, 0x01800824 },
841 { CR_SNIFFER_ON, 0 },
842 { CR_RX_FILTER, STA_RX_FILTER },
843 { CR_GROUP_HASH_P1, 0x00 },
844 { CR_GROUP_HASH_P2, 0x80000000 },
846 { CR_ADDA_PWR_DWN, 0x7f },
847 { CR_BCN_PLCP_CFG, 0x00f00401 },
848 { CR_PHY_DELAY, 0x00 },
849 { CR_ACK_TIMEOUT_EXT, 0x80 },
850 { CR_ADDA_PWR_DWN, 0x00 },
851 { CR_ACK_TIME_80211, 0x100 },
852 { CR_RX_PE_DELAY, 0x70 },
853 { CR_PS_CTRL, 0x10000000 },
854 { CR_RTS_CTS_RATE, 0x02030203 },
855 { CR_RX_THRESHOLD, 0x000c0eff, },
856 { CR_AFTER_PNP, 0x1 },
857 { CR_WEP_PROTECT, 0x114 },
862 dev_dbg_f(zd_chip_dev(chip), "\n");
863 ZD_ASSERT(mutex_is_locked(&chip->mutex));
864 r = zd_iowrite32a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
866 dev_dbg_f(zd_chip_dev(chip),
867 "error in zd_iowrite32a_locked. Error number %d\n", r);
872 static int hw_init_hmac(struct zd_chip *chip)
874 return chip->is_zd1211b ?
875 zd1211b_hw_init_hmac(chip) : zd1211_hw_init_hmac(chip);
884 static int get_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
887 static const zd_addr_t aw_pt_bi_addr[] =
888 { CR_ATIM_WND_PERIOD, CR_PRE_TBTT, CR_BCN_INTERVAL };
891 r = zd_ioread32v_locked(chip, values, (const zd_addr_t *)aw_pt_bi_addr,
892 ARRAY_SIZE(aw_pt_bi_addr));
894 memset(s, 0, sizeof(*s));
898 s->atim_wnd_period = values[0];
899 s->pre_tbtt = values[1];
900 s->beacon_interval = values[2];
901 dev_dbg_f(zd_chip_dev(chip), "aw %u pt %u bi %u\n",
902 s->atim_wnd_period, s->pre_tbtt, s->beacon_interval);
906 static int set_aw_pt_bi(struct zd_chip *chip, struct aw_pt_bi *s)
908 struct zd_ioreq32 reqs[3];
910 if (s->beacon_interval <= 5)
911 s->beacon_interval = 5;
912 if (s->pre_tbtt < 4 || s->pre_tbtt >= s->beacon_interval)
913 s->pre_tbtt = s->beacon_interval - 1;
914 if (s->atim_wnd_period >= s->pre_tbtt)
915 s->atim_wnd_period = s->pre_tbtt - 1;
917 reqs[0].addr = CR_ATIM_WND_PERIOD;
918 reqs[0].value = s->atim_wnd_period;
919 reqs[1].addr = CR_PRE_TBTT;
920 reqs[1].value = s->pre_tbtt;
921 reqs[2].addr = CR_BCN_INTERVAL;
922 reqs[2].value = s->beacon_interval;
924 dev_dbg_f(zd_chip_dev(chip),
925 "aw %u pt %u bi %u\n", s->atim_wnd_period, s->pre_tbtt,
927 return zd_iowrite32a_locked(chip, reqs, ARRAY_SIZE(reqs));
931 static int set_beacon_interval(struct zd_chip *chip, u32 interval)
936 ZD_ASSERT(mutex_is_locked(&chip->mutex));
937 r = get_aw_pt_bi(chip, &s);
940 s.beacon_interval = interval;
941 return set_aw_pt_bi(chip, &s);
944 int zd_set_beacon_interval(struct zd_chip *chip, u32 interval)
948 mutex_lock(&chip->mutex);
949 r = set_beacon_interval(chip, interval);
950 mutex_unlock(&chip->mutex);
954 static int hw_init(struct zd_chip *chip)
958 dev_dbg_f(zd_chip_dev(chip), "\n");
959 ZD_ASSERT(mutex_is_locked(&chip->mutex));
960 r = hw_reset_phy(chip);
964 r = hw_init_hmac(chip);
968 /* Although the vendor driver defaults to a different value during
969 * init, it overwrites the IFS value with the following every time
970 * the channel changes. We should aim to be more intelligent... */
971 r = zd_iowrite32_locked(chip, IFS_VALUE_DEFAULT, CR_IFS_VALUE);
975 return set_beacon_interval(chip, 100);
979 static int dump_cr(struct zd_chip *chip, const zd_addr_t addr,
980 const char *addr_string)
985 r = zd_ioread32_locked(chip, &value, addr);
987 dev_dbg_f(zd_chip_dev(chip),
988 "error reading %s. Error number %d\n", addr_string, r);
992 dev_dbg_f(zd_chip_dev(chip), "%s %#010x\n",
993 addr_string, (unsigned int)value);
997 static int test_init(struct zd_chip *chip)
1001 r = dump_cr(chip, CR_AFTER_PNP, "CR_AFTER_PNP");
1004 r = dump_cr(chip, CR_GPI_EN, "CR_GPI_EN");
1007 return dump_cr(chip, CR_INTERRUPT, "CR_INTERRUPT");
1010 static void dump_fw_registers(struct zd_chip *chip)
1012 static const zd_addr_t addr[4] = {
1013 FW_FIRMWARE_VER, FW_USB_SPEED, FW_FIX_TX_RATE,
1020 r = zd_ioread16v_locked(chip, values, (const zd_addr_t*)addr,
1023 dev_dbg_f(zd_chip_dev(chip), "error %d zd_ioread16v_locked\n",
1028 dev_dbg_f(zd_chip_dev(chip), "FW_FIRMWARE_VER %#06hx\n", values[0]);
1029 dev_dbg_f(zd_chip_dev(chip), "FW_USB_SPEED %#06hx\n", values[1]);
1030 dev_dbg_f(zd_chip_dev(chip), "FW_FIX_TX_RATE %#06hx\n", values[2]);
1031 dev_dbg_f(zd_chip_dev(chip), "FW_LINK_STATUS %#06hx\n", values[3]);
1035 static int print_fw_version(struct zd_chip *chip)
1040 r = zd_ioread16_locked(chip, &version, FW_FIRMWARE_VER);
1044 dev_info(zd_chip_dev(chip),"firmware version %04hx\n", version);
1048 static int set_mandatory_rates(struct zd_chip *chip, enum ieee80211_std std)
1051 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1052 /* This sets the mandatory rates, which only depend from the standard
1053 * that the device is supporting. Until further notice we should try
1054 * to support 802.11g also for full speed USB.
1058 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M;
1061 rates = CR_RATE_1M|CR_RATE_2M|CR_RATE_5_5M|CR_RATE_11M|
1062 CR_RATE_6M|CR_RATE_12M|CR_RATE_24M;
1067 return zd_iowrite32_locked(chip, rates, CR_MANDATORY_RATE_TBL);
1070 int zd_chip_enable_hwint(struct zd_chip *chip)
1074 mutex_lock(&chip->mutex);
1075 r = zd_iowrite32_locked(chip, HWINT_ENABLED, CR_INTERRUPT);
1076 mutex_unlock(&chip->mutex);
1080 static int disable_hwint(struct zd_chip *chip)
1082 return zd_iowrite32_locked(chip, HWINT_DISABLED, CR_INTERRUPT);
1085 int zd_chip_disable_hwint(struct zd_chip *chip)
1089 mutex_lock(&chip->mutex);
1090 r = disable_hwint(chip);
1091 mutex_unlock(&chip->mutex);
1095 int zd_chip_init_hw(struct zd_chip *chip, u8 device_type)
1100 dev_dbg_f(zd_chip_dev(chip), "\n");
1102 mutex_lock(&chip->mutex);
1103 chip->is_zd1211b = (device_type == DEVICE_ZD1211B) != 0;
1106 r = test_init(chip);
1110 r = zd_iowrite32_locked(chip, 1, CR_AFTER_PNP);
1114 r = zd_usb_init_hw(&chip->usb);
1118 /* GPI is always disabled, also in the other driver.
1120 r = zd_iowrite32_locked(chip, 0, CR_GPI_EN);
1123 r = zd_iowrite32_locked(chip, CWIN_SIZE, CR_CWMIN_CWMAX);
1126 /* Currently we support IEEE 802.11g for full and high speed USB.
1127 * It might be discussed, whether we should suppport pure b mode for
1130 r = set_mandatory_rates(chip, IEEE80211G);
1133 /* Disabling interrupts is certainly a smart thing here.
1135 r = disable_hwint(chip);
1138 r = read_pod(chip, &rf_type);
1144 r = zd_rf_init_hw(&chip->rf, rf_type);
1148 r = print_fw_version(chip);
1153 dump_fw_registers(chip);
1154 r = test_init(chip);
1159 r = read_e2p_mac_addr(chip);
1163 r = read_cal_int_tables(chip);
1169 mutex_unlock(&chip->mutex);
1173 static int update_pwr_int(struct zd_chip *chip, u8 channel)
1175 u8 value = chip->pwr_int_values[channel - 1];
1176 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_int %#04x\n",
1178 return zd_iowrite16_locked(chip, value, CR31);
1181 static int update_pwr_cal(struct zd_chip *chip, u8 channel)
1183 u8 value = chip->pwr_cal_values[channel-1];
1184 dev_dbg_f(zd_chip_dev(chip), "channel %d pwr_cal %#04x\n",
1186 return zd_iowrite16_locked(chip, value, CR68);
1189 static int update_ofdm_cal(struct zd_chip *chip, u8 channel)
1191 struct zd_ioreq16 ioreqs[3];
1193 ioreqs[0].addr = CR67;
1194 ioreqs[0].value = chip->ofdm_cal_values[OFDM_36M_INDEX][channel-1];
1195 ioreqs[1].addr = CR66;
1196 ioreqs[1].value = chip->ofdm_cal_values[OFDM_48M_INDEX][channel-1];
1197 ioreqs[2].addr = CR65;
1198 ioreqs[2].value = chip->ofdm_cal_values[OFDM_54M_INDEX][channel-1];
1200 dev_dbg_f(zd_chip_dev(chip),
1201 "channel %d ofdm_cal 36M %#04x 48M %#04x 54M %#04x\n",
1202 channel, ioreqs[0].value, ioreqs[1].value, ioreqs[2].value);
1203 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1206 static int update_channel_integration_and_calibration(struct zd_chip *chip,
1211 r = update_pwr_int(chip, channel);
1214 if (chip->is_zd1211b) {
1215 static const struct zd_ioreq16 ioreqs[] = {
1221 r = update_ofdm_cal(chip, channel);
1224 r = update_pwr_cal(chip, channel);
1227 r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1235 /* The CCK baseband gain can be optionally patched by the EEPROM */
1236 static int patch_cck_gain(struct zd_chip *chip)
1241 if (!chip->patch_cck_gain)
1244 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1245 r = zd_ioread32_locked(chip, &value, E2P_PHY_REG);
1248 dev_dbg_f(zd_chip_dev(chip), "patching value %x\n", value & 0xff);
1249 return zd_iowrite16_locked(chip, value & 0xff, CR47);
1252 int zd_chip_set_channel(struct zd_chip *chip, u8 channel)
1256 mutex_lock(&chip->mutex);
1257 r = zd_chip_lock_phy_regs(chip);
1260 r = zd_rf_set_channel(&chip->rf, channel);
1263 r = update_channel_integration_and_calibration(chip, channel);
1266 r = patch_cck_gain(chip);
1269 r = patch_6m_band_edge(chip, channel);
1272 r = zd_iowrite32_locked(chip, 0, CR_CONFIG_PHILIPS);
1274 t = zd_chip_unlock_phy_regs(chip);
1278 mutex_unlock(&chip->mutex);
1282 u8 zd_chip_get_channel(struct zd_chip *chip)
1286 mutex_lock(&chip->mutex);
1287 channel = chip->rf.channel;
1288 mutex_unlock(&chip->mutex);
1292 static u16 led_mask(int led)
1304 static int read_led_reg(struct zd_chip *chip, u16 *status)
1306 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1307 return zd_ioread16_locked(chip, status, CR_LED);
1310 static int write_led_reg(struct zd_chip *chip, u16 status)
1312 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1313 return zd_iowrite16_locked(chip, status, CR_LED);
1316 int zd_chip_led_status(struct zd_chip *chip, int led, enum led_status status)
1319 u16 mask = led_mask(led);
1324 mutex_lock(&chip->mutex);
1325 r = read_led_reg(chip, ®);
1330 return (reg & mask) ? LED_ON : LED_OFF;
1337 ret = (reg&mask) ? LED_ON : LED_OFF;
1346 r = write_led_reg(chip, reg);
1352 mutex_unlock(&chip->mutex);
1356 int zd_chip_led_flip(struct zd_chip *chip, int led,
1357 const unsigned int *phases_msecs, unsigned int count)
1360 enum led_status status;
1362 r = zd_chip_led_status(chip, led, LED_STATUS);
1366 for (i = 0; i < count; i++) {
1367 r = zd_chip_led_status(chip, led, LED_FLIP);
1370 msleep(phases_msecs[i]);
1374 zd_chip_led_status(chip, led, status);
1378 int zd_chip_set_basic_rates(struct zd_chip *chip, u16 cr_rates)
1382 if (cr_rates & ~(CR_RATES_80211B|CR_RATES_80211G))
1385 mutex_lock(&chip->mutex);
1386 r = zd_iowrite32_locked(chip, cr_rates, CR_BASIC_RATE_TBL);
1387 mutex_unlock(&chip->mutex);
1391 static int ofdm_qual_db(u8 status_quality, u8 rate, unsigned int size)
1393 static const u16 constants[] = {
1394 715, 655, 585, 540, 470, 410, 360, 315,
1395 270, 235, 205, 175, 150, 125, 105, 85,
1402 /* It seems that their quality parameter is somehow per signal
1403 * and is now transferred per bit.
1406 case ZD_OFDM_RATE_6M:
1407 case ZD_OFDM_RATE_12M:
1408 case ZD_OFDM_RATE_24M:
1411 case ZD_OFDM_RATE_9M:
1412 case ZD_OFDM_RATE_18M:
1413 case ZD_OFDM_RATE_36M:
1414 case ZD_OFDM_RATE_54M:
1418 case ZD_OFDM_RATE_48M:
1426 x = (10000 * status_quality)/size;
1427 for (i = 0; i < ARRAY_SIZE(constants); i++) {
1428 if (x > constants[i])
1433 case ZD_OFDM_RATE_6M:
1434 case ZD_OFDM_RATE_9M:
1437 case ZD_OFDM_RATE_12M:
1438 case ZD_OFDM_RATE_18M:
1441 case ZD_OFDM_RATE_24M:
1442 case ZD_OFDM_RATE_36M:
1445 case ZD_OFDM_RATE_48M:
1446 case ZD_OFDM_RATE_54M:
1456 static int ofdm_qual_percent(u8 status_quality, u8 rate, unsigned int size)
1460 r = ofdm_qual_db(status_quality, rate, size);
1466 return r <= 100 ? r : 100;
1469 static unsigned int log10times100(unsigned int x)
1471 static const u8 log10[] = {
1473 0, 30, 47, 60, 69, 77, 84, 90, 95, 100,
1474 104, 107, 111, 114, 117, 120, 123, 125, 127, 130,
1475 132, 134, 136, 138, 139, 141, 143, 144, 146, 147,
1476 149, 150, 151, 153, 154, 155, 156, 157, 159, 160,
1477 161, 162, 163, 164, 165, 166, 167, 168, 169, 169,
1478 170, 171, 172, 173, 174, 174, 175, 176, 177, 177,
1479 178, 179, 179, 180, 181, 181, 182, 183, 183, 184,
1480 185, 185, 186, 186, 187, 188, 188, 189, 189, 190,
1481 190, 191, 191, 192, 192, 193, 193, 194, 194, 195,
1482 195, 196, 196, 197, 197, 198, 198, 199, 199, 200,
1483 200, 200, 201, 201, 202, 202, 202, 203, 203, 204,
1484 204, 204, 205, 205, 206, 206, 206, 207, 207, 207,
1485 208, 208, 208, 209, 209, 210, 210, 210, 211, 211,
1486 211, 212, 212, 212, 213, 213, 213, 213, 214, 214,
1487 214, 215, 215, 215, 216, 216, 216, 217, 217, 217,
1488 217, 218, 218, 218, 219, 219, 219, 219, 220, 220,
1489 220, 220, 221, 221, 221, 222, 222, 222, 222, 223,
1490 223, 223, 223, 224, 224, 224, 224,
1493 return x < ARRAY_SIZE(log10) ? log10[x] : 225;
1497 MAX_CCK_EVM_DB = 45,
1500 static int cck_evm_db(u8 status_quality)
1502 return (20 * log10times100(status_quality)) / 100;
1505 static int cck_snr_db(u8 status_quality)
1507 int r = MAX_CCK_EVM_DB - cck_evm_db(status_quality);
1512 static int cck_qual_percent(u8 status_quality)
1516 r = cck_snr_db(status_quality);
1518 return r <= 100 ? r : 100;
1521 u8 zd_rx_qual_percent(const void *rx_frame, unsigned int size,
1522 const struct rx_status *status)
1524 return (status->frame_status&ZD_RX_OFDM) ?
1525 ofdm_qual_percent(status->signal_quality_ofdm,
1526 zd_ofdm_plcp_header_rate(rx_frame),
1528 cck_qual_percent(status->signal_quality_cck);
1531 u8 zd_rx_strength_percent(u8 rssi)
1533 int r = (rssi*100) / 41;
1539 u16 zd_rx_rate(const void *rx_frame, const struct rx_status *status)
1541 static const u16 ofdm_rates[] = {
1542 [ZD_OFDM_RATE_6M] = 60,
1543 [ZD_OFDM_RATE_9M] = 90,
1544 [ZD_OFDM_RATE_12M] = 120,
1545 [ZD_OFDM_RATE_18M] = 180,
1546 [ZD_OFDM_RATE_24M] = 240,
1547 [ZD_OFDM_RATE_36M] = 360,
1548 [ZD_OFDM_RATE_48M] = 480,
1549 [ZD_OFDM_RATE_54M] = 540,
1552 if (status->frame_status & ZD_RX_OFDM) {
1553 u8 ofdm_rate = zd_ofdm_plcp_header_rate(rx_frame);
1554 rate = ofdm_rates[ofdm_rate & 0xf];
1556 u8 cck_rate = zd_cck_plcp_header_rate(rx_frame);
1558 case ZD_CCK_SIGNAL_1M:
1561 case ZD_CCK_SIGNAL_2M:
1564 case ZD_CCK_SIGNAL_5M5:
1567 case ZD_CCK_SIGNAL_11M:
1578 int zd_chip_switch_radio_on(struct zd_chip *chip)
1582 mutex_lock(&chip->mutex);
1583 r = zd_switch_radio_on(&chip->rf);
1584 mutex_unlock(&chip->mutex);
1588 int zd_chip_switch_radio_off(struct zd_chip *chip)
1592 mutex_lock(&chip->mutex);
1593 r = zd_switch_radio_off(&chip->rf);
1594 mutex_unlock(&chip->mutex);
1598 int zd_chip_enable_int(struct zd_chip *chip)
1602 mutex_lock(&chip->mutex);
1603 r = zd_usb_enable_int(&chip->usb);
1604 mutex_unlock(&chip->mutex);
1608 void zd_chip_disable_int(struct zd_chip *chip)
1610 mutex_lock(&chip->mutex);
1611 zd_usb_disable_int(&chip->usb);
1612 mutex_unlock(&chip->mutex);
1615 int zd_chip_enable_rx(struct zd_chip *chip)
1619 mutex_lock(&chip->mutex);
1620 r = zd_usb_enable_rx(&chip->usb);
1621 mutex_unlock(&chip->mutex);
1625 void zd_chip_disable_rx(struct zd_chip *chip)
1627 mutex_lock(&chip->mutex);
1628 zd_usb_disable_rx(&chip->usb);
1629 mutex_unlock(&chip->mutex);
1632 int zd_rfwritev_locked(struct zd_chip *chip,
1633 const u32* values, unsigned int count, u8 bits)
1638 for (i = 0; i < count; i++) {
1639 r = zd_rfwrite_locked(chip, values[i], bits);
1648 * We can optionally program the RF directly through CR regs, if supported by
1649 * the hardware. This is much faster than the older method.
1651 int zd_rfwrite_cr_locked(struct zd_chip *chip, u32 value)
1653 struct zd_ioreq16 ioreqs[] = {
1654 { CR244, (value >> 16) & 0xff },
1655 { CR243, (value >> 8) & 0xff },
1656 { CR242, value & 0xff },
1658 ZD_ASSERT(mutex_is_locked(&chip->mutex));
1659 return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
1662 int zd_rfwritev_cr_locked(struct zd_chip *chip,
1663 const u32 *values, unsigned int count)
1668 for (i = 0; i < count; i++) {
1669 r = zd_rfwrite_cr_locked(chip, values[i]);