2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt73usb device specific routines.
24 Supported chipsets: rt2571W & rt2671.
27 #include <linux/crc-itu-t.h>
28 #include <linux/delay.h>
29 #include <linux/etherdevice.h>
30 #include <linux/init.h>
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/usb.h>
36 #include "rt2x00usb.h"
41 * All access to the CSR registers will go through the methods
42 * rt73usb_register_read and rt73usb_register_write.
43 * BBP and RF register require indirect register access,
44 * and use the CSR registers BBPCSR and RFCSR to achieve this.
45 * These indirect registers work with busy bits,
46 * and we will try maximal REGISTER_BUSY_COUNT times to access
47 * the register while taking a REGISTER_BUSY_DELAY us delay
48 * between each attampt. When the busy bit is still set at that time,
49 * the access attempt is considered to have failed,
50 * and we will print an error.
51 * The _lock versions must be used if you already hold the usb_cache_mutex
53 static inline void rt73usb_register_read(struct rt2x00_dev *rt2x00dev,
54 const unsigned int offset, u32 *value)
57 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
58 USB_VENDOR_REQUEST_IN, offset,
59 ®, sizeof(u32), REGISTER_TIMEOUT);
60 *value = le32_to_cpu(reg);
63 static inline void rt73usb_register_read_lock(struct rt2x00_dev *rt2x00dev,
64 const unsigned int offset, u32 *value)
67 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_READ,
68 USB_VENDOR_REQUEST_IN, offset,
69 ®, sizeof(u32), REGISTER_TIMEOUT);
70 *value = le32_to_cpu(reg);
73 static inline void rt73usb_register_multiread(struct rt2x00_dev *rt2x00dev,
74 const unsigned int offset,
75 void *value, const u32 length)
77 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_READ,
78 USB_VENDOR_REQUEST_IN, offset,
80 REGISTER_TIMEOUT32(length));
83 static inline void rt73usb_register_write(struct rt2x00_dev *rt2x00dev,
84 const unsigned int offset, u32 value)
86 __le32 reg = cpu_to_le32(value);
87 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
88 USB_VENDOR_REQUEST_OUT, offset,
89 ®, sizeof(u32), REGISTER_TIMEOUT);
92 static inline void rt73usb_register_write_lock(struct rt2x00_dev *rt2x00dev,
93 const unsigned int offset, u32 value)
95 __le32 reg = cpu_to_le32(value);
96 rt2x00usb_vendor_req_buff_lock(rt2x00dev, USB_MULTI_WRITE,
97 USB_VENDOR_REQUEST_OUT, offset,
98 ®, sizeof(u32), REGISTER_TIMEOUT);
101 static inline void rt73usb_register_multiwrite(struct rt2x00_dev *rt2x00dev,
102 const unsigned int offset,
103 void *value, const u32 length)
105 rt2x00usb_vendor_request_buff(rt2x00dev, USB_MULTI_WRITE,
106 USB_VENDOR_REQUEST_OUT, offset,
108 REGISTER_TIMEOUT32(length));
111 static u32 rt73usb_bbp_check(struct rt2x00_dev *rt2x00dev)
116 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
117 rt73usb_register_read_lock(rt2x00dev, PHY_CSR3, ®);
118 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
120 udelay(REGISTER_BUSY_DELAY);
126 static void rt73usb_bbp_write(struct rt2x00_dev *rt2x00dev,
127 const unsigned int word, const u8 value)
131 mutex_lock(&rt2x00dev->usb_cache_mutex);
134 * Wait until the BBP becomes ready.
136 reg = rt73usb_bbp_check(rt2x00dev);
137 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
138 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
139 mutex_unlock(&rt2x00dev->usb_cache_mutex);
144 * Write the data into the BBP.
147 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
148 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
149 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
150 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
152 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
153 mutex_unlock(&rt2x00dev->usb_cache_mutex);
156 static void rt73usb_bbp_read(struct rt2x00_dev *rt2x00dev,
157 const unsigned int word, u8 *value)
161 mutex_lock(&rt2x00dev->usb_cache_mutex);
164 * Wait until the BBP becomes ready.
166 reg = rt73usb_bbp_check(rt2x00dev);
167 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
168 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
169 mutex_unlock(&rt2x00dev->usb_cache_mutex);
174 * Write the request into the BBP.
177 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
178 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
179 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
181 rt73usb_register_write_lock(rt2x00dev, PHY_CSR3, reg);
184 * Wait until the BBP becomes ready.
186 reg = rt73usb_bbp_check(rt2x00dev);
187 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
188 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
193 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
194 mutex_unlock(&rt2x00dev->usb_cache_mutex);
197 static void rt73usb_rf_write(struct rt2x00_dev *rt2x00dev,
198 const unsigned int word, const u32 value)
206 mutex_lock(&rt2x00dev->usb_cache_mutex);
208 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
209 rt73usb_register_read_lock(rt2x00dev, PHY_CSR4, ®);
210 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
212 udelay(REGISTER_BUSY_DELAY);
215 mutex_unlock(&rt2x00dev->usb_cache_mutex);
216 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
221 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
224 * RF5225 and RF2527 contain 21 bits per RF register value,
225 * all others contain 20 bits.
227 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS,
228 20 + (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
229 rt2x00_rf(&rt2x00dev->chip, RF2527)));
230 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
231 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
233 rt73usb_register_write_lock(rt2x00dev, PHY_CSR4, reg);
234 rt2x00_rf_write(rt2x00dev, word, value);
235 mutex_unlock(&rt2x00dev->usb_cache_mutex);
238 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
239 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
241 static void rt73usb_read_csr(struct rt2x00_dev *rt2x00dev,
242 const unsigned int word, u32 *data)
244 rt73usb_register_read(rt2x00dev, CSR_OFFSET(word), data);
247 static void rt73usb_write_csr(struct rt2x00_dev *rt2x00dev,
248 const unsigned int word, u32 data)
250 rt73usb_register_write(rt2x00dev, CSR_OFFSET(word), data);
253 static const struct rt2x00debug rt73usb_rt2x00debug = {
254 .owner = THIS_MODULE,
256 .read = rt73usb_read_csr,
257 .write = rt73usb_write_csr,
258 .word_size = sizeof(u32),
259 .word_count = CSR_REG_SIZE / sizeof(u32),
262 .read = rt2x00_eeprom_read,
263 .write = rt2x00_eeprom_write,
264 .word_size = sizeof(u16),
265 .word_count = EEPROM_SIZE / sizeof(u16),
268 .read = rt73usb_bbp_read,
269 .write = rt73usb_bbp_write,
270 .word_size = sizeof(u8),
271 .word_count = BBP_SIZE / sizeof(u8),
274 .read = rt2x00_rf_read,
275 .write = rt73usb_rf_write,
276 .word_size = sizeof(u32),
277 .word_count = RF_SIZE / sizeof(u32),
280 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
282 #ifdef CONFIG_RT73USB_LEDS
283 static void rt73usb_brightness_set(struct led_classdev *led_cdev,
284 enum led_brightness brightness)
286 struct rt2x00_led *led =
287 container_of(led_cdev, struct rt2x00_led, led_dev);
288 unsigned int enabled = brightness != LED_OFF;
289 unsigned int a_mode =
290 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
291 unsigned int bg_mode =
292 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
294 if (led->type == LED_TYPE_RADIO) {
295 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
296 MCU_LEDCS_RADIO_STATUS, enabled);
298 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
299 0, led->rt2x00dev->led_mcu_reg,
301 } else if (led->type == LED_TYPE_ASSOC) {
302 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
303 MCU_LEDCS_LINK_BG_STATUS, bg_mode);
304 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
305 MCU_LEDCS_LINK_A_STATUS, a_mode);
307 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
308 0, led->rt2x00dev->led_mcu_reg,
310 } else if (led->type == LED_TYPE_QUALITY) {
312 * The brightness is divided into 6 levels (0 - 5),
313 * this means we need to convert the brightness
314 * argument into the matching level within that range.
316 rt2x00usb_vendor_request_sw(led->rt2x00dev, USB_LED_CONTROL,
317 brightness / (LED_FULL / 6),
318 led->rt2x00dev->led_mcu_reg,
323 static int rt73usb_blink_set(struct led_classdev *led_cdev,
324 unsigned long *delay_on,
325 unsigned long *delay_off)
327 struct rt2x00_led *led =
328 container_of(led_cdev, struct rt2x00_led, led_dev);
331 rt73usb_register_read(led->rt2x00dev, MAC_CSR14, ®);
332 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
333 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
334 rt73usb_register_write(led->rt2x00dev, MAC_CSR14, reg);
339 static void rt73usb_init_led(struct rt2x00_dev *rt2x00dev,
340 struct rt2x00_led *led,
343 led->rt2x00dev = rt2x00dev;
345 led->led_dev.brightness_set = rt73usb_brightness_set;
346 led->led_dev.blink_set = rt73usb_blink_set;
347 led->flags = LED_INITIALIZED;
349 #endif /* CONFIG_RT73USB_LEDS */
352 * Configuration handlers.
354 static void rt73usb_config_filter(struct rt2x00_dev *rt2x00dev,
355 const unsigned int filter_flags)
360 * Start configuration steps.
361 * Note that the version error will always be dropped
362 * and broadcast frames will always be accepted since
363 * there is no filter for it at this time.
365 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
366 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
367 !(filter_flags & FIF_FCSFAIL));
368 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
369 !(filter_flags & FIF_PLCPFAIL));
370 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
371 !(filter_flags & FIF_CONTROL));
372 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
373 !(filter_flags & FIF_PROMISC_IN_BSS));
374 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
375 !(filter_flags & FIF_PROMISC_IN_BSS) &&
376 !rt2x00dev->intf_ap_count);
377 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
378 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
379 !(filter_flags & FIF_ALLMULTI));
380 rt2x00_set_field32(®, TXRX_CSR0_DROP_BROADCAST, 0);
381 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS,
382 !(filter_flags & FIF_CONTROL));
383 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
386 static void rt73usb_config_intf(struct rt2x00_dev *rt2x00dev,
387 struct rt2x00_intf *intf,
388 struct rt2x00intf_conf *conf,
389 const unsigned int flags)
391 unsigned int beacon_base;
394 if (flags & CONFIG_UPDATE_TYPE) {
396 * Clear current synchronisation setup.
397 * For the Beacon base registers we only need to clear
398 * the first byte since that byte contains the VALID and OWNER
399 * bits which (when set to 0) will invalidate the entire beacon.
401 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
402 rt73usb_register_write(rt2x00dev, beacon_base, 0);
405 * Enable synchronisation.
407 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
408 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
409 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, conf->sync);
410 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
411 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
414 if (flags & CONFIG_UPDATE_MAC) {
415 reg = le32_to_cpu(conf->mac[1]);
416 rt2x00_set_field32(®, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
417 conf->mac[1] = cpu_to_le32(reg);
419 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR2,
420 conf->mac, sizeof(conf->mac));
423 if (flags & CONFIG_UPDATE_BSSID) {
424 reg = le32_to_cpu(conf->bssid[1]);
425 rt2x00_set_field32(®, MAC_CSR5_BSS_ID_MASK, 3);
426 conf->bssid[1] = cpu_to_le32(reg);
428 rt73usb_register_multiwrite(rt2x00dev, MAC_CSR4,
429 conf->bssid, sizeof(conf->bssid));
433 static void rt73usb_config_erp(struct rt2x00_dev *rt2x00dev,
434 struct rt2x00lib_erp *erp)
438 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
439 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
440 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
442 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
443 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
444 !!erp->short_preamble);
445 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
448 static void rt73usb_config_phymode(struct rt2x00_dev *rt2x00dev,
449 const int basic_rate_mask)
451 rt73usb_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
454 static void rt73usb_config_channel(struct rt2x00_dev *rt2x00dev,
455 struct rf_channel *rf, const int txpower)
461 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
462 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
464 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
465 rt2x00_rf(&rt2x00dev->chip, RF2527));
467 rt73usb_bbp_read(rt2x00dev, 3, &r3);
468 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
469 rt73usb_bbp_write(rt2x00dev, 3, r3);
472 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
473 r94 += txpower - MAX_TXPOWER;
474 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
476 rt73usb_bbp_write(rt2x00dev, 94, r94);
478 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
479 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
480 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
481 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
483 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
484 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
485 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
486 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
488 rt73usb_rf_write(rt2x00dev, 1, rf->rf1);
489 rt73usb_rf_write(rt2x00dev, 2, rf->rf2);
490 rt73usb_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
491 rt73usb_rf_write(rt2x00dev, 4, rf->rf4);
496 static void rt73usb_config_txpower(struct rt2x00_dev *rt2x00dev,
499 struct rf_channel rf;
501 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
502 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
503 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
504 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
506 rt73usb_config_channel(rt2x00dev, &rf, txpower);
509 static void rt73usb_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
510 struct antenna_setup *ant)
517 rt73usb_bbp_read(rt2x00dev, 3, &r3);
518 rt73usb_bbp_read(rt2x00dev, 4, &r4);
519 rt73usb_bbp_read(rt2x00dev, 77, &r77);
521 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
524 * Configure the RX antenna.
527 case ANTENNA_HW_DIVERSITY:
528 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
529 temp = !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags)
530 && (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ);
531 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, temp);
534 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
535 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
536 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
537 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
539 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
543 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
544 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
545 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
546 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
548 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
552 rt73usb_bbp_write(rt2x00dev, 77, r77);
553 rt73usb_bbp_write(rt2x00dev, 3, r3);
554 rt73usb_bbp_write(rt2x00dev, 4, r4);
557 static void rt73usb_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
558 struct antenna_setup *ant)
564 rt73usb_bbp_read(rt2x00dev, 3, &r3);
565 rt73usb_bbp_read(rt2x00dev, 4, &r4);
566 rt73usb_bbp_read(rt2x00dev, 77, &r77);
568 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
569 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
570 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
573 * Configure the RX antenna.
576 case ANTENNA_HW_DIVERSITY:
577 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
580 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
581 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
585 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
586 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
590 rt73usb_bbp_write(rt2x00dev, 77, r77);
591 rt73usb_bbp_write(rt2x00dev, 3, r3);
592 rt73usb_bbp_write(rt2x00dev, 4, r4);
598 * value[0] -> non-LNA
604 static const struct antenna_sel antenna_sel_a[] = {
605 { 96, { 0x58, 0x78 } },
606 { 104, { 0x38, 0x48 } },
607 { 75, { 0xfe, 0x80 } },
608 { 86, { 0xfe, 0x80 } },
609 { 88, { 0xfe, 0x80 } },
610 { 35, { 0x60, 0x60 } },
611 { 97, { 0x58, 0x58 } },
612 { 98, { 0x58, 0x58 } },
615 static const struct antenna_sel antenna_sel_bg[] = {
616 { 96, { 0x48, 0x68 } },
617 { 104, { 0x2c, 0x3c } },
618 { 75, { 0xfe, 0x80 } },
619 { 86, { 0xfe, 0x80 } },
620 { 88, { 0xfe, 0x80 } },
621 { 35, { 0x50, 0x50 } },
622 { 97, { 0x48, 0x48 } },
623 { 98, { 0x48, 0x48 } },
626 static void rt73usb_config_antenna(struct rt2x00_dev *rt2x00dev,
627 struct antenna_setup *ant)
629 const struct antenna_sel *sel;
635 * We should never come here because rt2x00lib is supposed
636 * to catch this and send us the correct antenna explicitely.
638 BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
639 ant->tx == ANTENNA_SW_DIVERSITY);
641 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
643 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
645 sel = antenna_sel_bg;
646 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
649 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
650 rt73usb_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
652 rt73usb_register_read(rt2x00dev, PHY_CSR0, ®);
654 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
655 (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ));
656 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
657 (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ));
659 rt73usb_register_write(rt2x00dev, PHY_CSR0, reg);
661 if (rt2x00_rf(&rt2x00dev->chip, RF5226) ||
662 rt2x00_rf(&rt2x00dev->chip, RF5225))
663 rt73usb_config_antenna_5x(rt2x00dev, ant);
664 else if (rt2x00_rf(&rt2x00dev->chip, RF2528) ||
665 rt2x00_rf(&rt2x00dev->chip, RF2527))
666 rt73usb_config_antenna_2x(rt2x00dev, ant);
669 static void rt73usb_config_duration(struct rt2x00_dev *rt2x00dev,
670 struct rt2x00lib_conf *libconf)
674 rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
675 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
676 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
678 rt73usb_register_read(rt2x00dev, MAC_CSR8, ®);
679 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
680 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
681 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
682 rt73usb_register_write(rt2x00dev, MAC_CSR8, reg);
684 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
685 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
686 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
688 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
689 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
690 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
692 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
693 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
694 libconf->conf->beacon_int * 16);
695 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
698 static void rt73usb_config(struct rt2x00_dev *rt2x00dev,
699 struct rt2x00lib_conf *libconf,
700 const unsigned int flags)
702 if (flags & CONFIG_UPDATE_PHYMODE)
703 rt73usb_config_phymode(rt2x00dev, libconf->basic_rates);
704 if (flags & CONFIG_UPDATE_CHANNEL)
705 rt73usb_config_channel(rt2x00dev, &libconf->rf,
706 libconf->conf->power_level);
707 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
708 rt73usb_config_txpower(rt2x00dev, libconf->conf->power_level);
709 if (flags & CONFIG_UPDATE_ANTENNA)
710 rt73usb_config_antenna(rt2x00dev, &libconf->ant);
711 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
712 rt73usb_config_duration(rt2x00dev, libconf);
718 static void rt73usb_link_stats(struct rt2x00_dev *rt2x00dev,
719 struct link_qual *qual)
724 * Update FCS error count from register.
726 rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
727 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
730 * Update False CCA count from register.
732 rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
733 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
736 static void rt73usb_reset_tuner(struct rt2x00_dev *rt2x00dev)
738 rt73usb_bbp_write(rt2x00dev, 17, 0x20);
739 rt2x00dev->link.vgc_level = 0x20;
742 static void rt73usb_link_tuner(struct rt2x00_dev *rt2x00dev)
744 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
749 rt73usb_bbp_read(rt2x00dev, 17, &r17);
752 * Determine r17 bounds.
754 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
758 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
766 } else if (rssi > -84) {
774 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
781 * If we are not associated, we should go straight to the
782 * dynamic CCA tuning.
784 if (!rt2x00dev->intf_associated)
785 goto dynamic_cca_tune;
788 * Special big-R17 for very short distance
792 rt73usb_bbp_write(rt2x00dev, 17, 0x60);
797 * Special big-R17 for short distance
801 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
806 * Special big-R17 for middle-short distance
810 if (r17 != low_bound)
811 rt73usb_bbp_write(rt2x00dev, 17, low_bound);
816 * Special mid-R17 for middle distance
819 if (r17 != (low_bound + 0x10))
820 rt73usb_bbp_write(rt2x00dev, 17, low_bound + 0x08);
825 * Special case: Change up_bound based on the rssi.
826 * Lower up_bound when rssi is weaker then -74 dBm.
828 up_bound -= 2 * (-74 - rssi);
829 if (low_bound > up_bound)
830 up_bound = low_bound;
832 if (r17 > up_bound) {
833 rt73usb_bbp_write(rt2x00dev, 17, up_bound);
840 * r17 does not yet exceed upper limit, continue and base
841 * the r17 tuning on the false CCA count.
843 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
847 rt73usb_bbp_write(rt2x00dev, 17, r17);
848 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
852 rt73usb_bbp_write(rt2x00dev, 17, r17);
859 static char *rt73usb_get_firmware_name(struct rt2x00_dev *rt2x00dev)
861 return FIRMWARE_RT2571;
864 static u16 rt73usb_get_firmware_crc(void *data, const size_t len)
869 * Use the crc itu-t algorithm.
870 * The last 2 bytes in the firmware array are the crc checksum itself,
871 * this means that we should never pass those 2 bytes to the crc
874 crc = crc_itu_t(0, data, len - 2);
875 crc = crc_itu_t_byte(crc, 0);
876 crc = crc_itu_t_byte(crc, 0);
881 static int rt73usb_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
892 * Wait for stable hardware.
894 for (i = 0; i < 100; i++) {
895 rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
902 ERROR(rt2x00dev, "Unstable hardware.\n");
907 * Write firmware to device.
908 * We setup a seperate cache for this action,
909 * since we are going to write larger chunks of data
910 * then normally used cache size.
912 cache = kmalloc(CSR_CACHE_SIZE_FIRMWARE, GFP_KERNEL);
914 ERROR(rt2x00dev, "Failed to allocate firmware cache.\n");
918 for (i = 0; i < len; i += CSR_CACHE_SIZE_FIRMWARE) {
919 buflen = min_t(int, len - i, CSR_CACHE_SIZE_FIRMWARE);
921 memcpy(cache, ptr, buflen);
923 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
924 USB_VENDOR_REQUEST_OUT,
925 FIRMWARE_IMAGE_BASE + i, 0,
927 REGISTER_TIMEOUT32(buflen));
935 * Send firmware request to device to load firmware,
936 * we need to specify a long timeout time.
938 status = rt2x00usb_vendor_request_sw(rt2x00dev, USB_DEVICE_MODE,
939 0, USB_MODE_FIRMWARE,
940 REGISTER_TIMEOUT_FIRMWARE);
942 ERROR(rt2x00dev, "Failed to write Firmware to device.\n");
950 * Initialization functions.
952 static int rt73usb_init_registers(struct rt2x00_dev *rt2x00dev)
956 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
957 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
958 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
959 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
960 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
962 rt73usb_register_read(rt2x00dev, TXRX_CSR1, ®);
963 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
964 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
965 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
966 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
967 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
968 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
969 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
970 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
971 rt73usb_register_write(rt2x00dev, TXRX_CSR1, reg);
974 * CCK TXD BBP registers
976 rt73usb_register_read(rt2x00dev, TXRX_CSR2, ®);
977 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
978 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
979 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
980 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
981 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
982 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
983 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
984 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
985 rt73usb_register_write(rt2x00dev, TXRX_CSR2, reg);
988 * OFDM TXD BBP registers
990 rt73usb_register_read(rt2x00dev, TXRX_CSR3, ®);
991 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
992 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
993 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
994 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
995 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
996 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
997 rt73usb_register_write(rt2x00dev, TXRX_CSR3, reg);
999 rt73usb_register_read(rt2x00dev, TXRX_CSR7, ®);
1000 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1001 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1002 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1003 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1004 rt73usb_register_write(rt2x00dev, TXRX_CSR7, reg);
1006 rt73usb_register_read(rt2x00dev, TXRX_CSR8, ®);
1007 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1008 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1009 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1010 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1011 rt73usb_register_write(rt2x00dev, TXRX_CSR8, reg);
1013 rt73usb_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1015 rt73usb_register_read(rt2x00dev, MAC_CSR6, ®);
1016 rt2x00_set_field32(®, MAC_CSR6_MAX_FRAME_UNIT, 0xfff);
1017 rt73usb_register_write(rt2x00dev, MAC_CSR6, reg);
1019 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00000718);
1021 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1024 rt73usb_register_write(rt2x00dev, MAC_CSR13, 0x00007f00);
1027 * Invalidate all Shared Keys (SEC_CSR0),
1028 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1030 rt73usb_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1031 rt73usb_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1032 rt73usb_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1035 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1036 rt2x00_rf(&rt2x00dev->chip, RF2527))
1037 rt2x00_set_field32(®, PHY_CSR1_RF_RPI, 1);
1038 rt73usb_register_write(rt2x00dev, PHY_CSR1, reg);
1040 rt73usb_register_write(rt2x00dev, PHY_CSR5, 0x00040a06);
1041 rt73usb_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1042 rt73usb_register_write(rt2x00dev, PHY_CSR7, 0x00000408);
1044 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
1045 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
1046 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
1047 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1049 rt73usb_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1050 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1051 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1052 rt73usb_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1054 rt73usb_register_read(rt2x00dev, MAC_CSR9, ®);
1055 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1056 rt73usb_register_write(rt2x00dev, MAC_CSR9, reg);
1060 * For the Beacon base registers we only need to clear
1061 * the first byte since that byte contains the VALID and OWNER
1062 * bits which (when set to 0) will invalidate the entire beacon.
1064 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1065 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1066 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1067 rt73usb_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1070 * We must clear the error counters.
1071 * These registers are cleared on read,
1072 * so we may pass a useless variable to store the value.
1074 rt73usb_register_read(rt2x00dev, STA_CSR0, ®);
1075 rt73usb_register_read(rt2x00dev, STA_CSR1, ®);
1076 rt73usb_register_read(rt2x00dev, STA_CSR2, ®);
1079 * Reset MAC and BBP registers.
1081 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1082 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1083 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1084 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1086 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1087 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1088 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1089 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1091 rt73usb_register_read(rt2x00dev, MAC_CSR1, ®);
1092 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1093 rt73usb_register_write(rt2x00dev, MAC_CSR1, reg);
1098 static int rt73usb_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1103 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1104 rt73usb_bbp_read(rt2x00dev, 0, &value);
1105 if ((value != 0xff) && (value != 0x00))
1107 udelay(REGISTER_BUSY_DELAY);
1110 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1114 static int rt73usb_init_bbp(struct rt2x00_dev *rt2x00dev)
1121 if (unlikely(rt73usb_wait_bbp_ready(rt2x00dev)))
1124 rt73usb_bbp_write(rt2x00dev, 3, 0x80);
1125 rt73usb_bbp_write(rt2x00dev, 15, 0x30);
1126 rt73usb_bbp_write(rt2x00dev, 21, 0xc8);
1127 rt73usb_bbp_write(rt2x00dev, 22, 0x38);
1128 rt73usb_bbp_write(rt2x00dev, 23, 0x06);
1129 rt73usb_bbp_write(rt2x00dev, 24, 0xfe);
1130 rt73usb_bbp_write(rt2x00dev, 25, 0x0a);
1131 rt73usb_bbp_write(rt2x00dev, 26, 0x0d);
1132 rt73usb_bbp_write(rt2x00dev, 32, 0x0b);
1133 rt73usb_bbp_write(rt2x00dev, 34, 0x12);
1134 rt73usb_bbp_write(rt2x00dev, 37, 0x07);
1135 rt73usb_bbp_write(rt2x00dev, 39, 0xf8);
1136 rt73usb_bbp_write(rt2x00dev, 41, 0x60);
1137 rt73usb_bbp_write(rt2x00dev, 53, 0x10);
1138 rt73usb_bbp_write(rt2x00dev, 54, 0x18);
1139 rt73usb_bbp_write(rt2x00dev, 60, 0x10);
1140 rt73usb_bbp_write(rt2x00dev, 61, 0x04);
1141 rt73usb_bbp_write(rt2x00dev, 62, 0x04);
1142 rt73usb_bbp_write(rt2x00dev, 75, 0xfe);
1143 rt73usb_bbp_write(rt2x00dev, 86, 0xfe);
1144 rt73usb_bbp_write(rt2x00dev, 88, 0xfe);
1145 rt73usb_bbp_write(rt2x00dev, 90, 0x0f);
1146 rt73usb_bbp_write(rt2x00dev, 99, 0x00);
1147 rt73usb_bbp_write(rt2x00dev, 102, 0x16);
1148 rt73usb_bbp_write(rt2x00dev, 107, 0x04);
1150 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1151 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1153 if (eeprom != 0xffff && eeprom != 0x0000) {
1154 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1155 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1156 rt73usb_bbp_write(rt2x00dev, reg_id, value);
1164 * Device state switch handlers.
1166 static void rt73usb_toggle_rx(struct rt2x00_dev *rt2x00dev,
1167 enum dev_state state)
1171 rt73usb_register_read(rt2x00dev, TXRX_CSR0, ®);
1172 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1173 (state == STATE_RADIO_RX_OFF) ||
1174 (state == STATE_RADIO_RX_OFF_LINK));
1175 rt73usb_register_write(rt2x00dev, TXRX_CSR0, reg);
1178 static int rt73usb_enable_radio(struct rt2x00_dev *rt2x00dev)
1181 * Initialize all registers.
1183 if (unlikely(rt73usb_init_registers(rt2x00dev) ||
1184 rt73usb_init_bbp(rt2x00dev)))
1190 static void rt73usb_disable_radio(struct rt2x00_dev *rt2x00dev)
1192 rt73usb_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1195 * Disable synchronisation.
1197 rt73usb_register_write(rt2x00dev, TXRX_CSR9, 0);
1199 rt2x00usb_disable_radio(rt2x00dev);
1202 static int rt73usb_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1208 put_to_sleep = (state != STATE_AWAKE);
1210 rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
1211 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1212 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1213 rt73usb_register_write(rt2x00dev, MAC_CSR12, reg);
1216 * Device is not guaranteed to be in the requested state yet.
1217 * We must wait until the register indicates that the
1218 * device has entered the correct state.
1220 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1221 rt73usb_register_read(rt2x00dev, MAC_CSR12, ®);
1222 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1223 if (state == !put_to_sleep)
1231 static int rt73usb_set_device_state(struct rt2x00_dev *rt2x00dev,
1232 enum dev_state state)
1237 case STATE_RADIO_ON:
1238 retval = rt73usb_enable_radio(rt2x00dev);
1240 case STATE_RADIO_OFF:
1241 rt73usb_disable_radio(rt2x00dev);
1243 case STATE_RADIO_RX_ON:
1244 case STATE_RADIO_RX_ON_LINK:
1245 case STATE_RADIO_RX_OFF:
1246 case STATE_RADIO_RX_OFF_LINK:
1247 rt73usb_toggle_rx(rt2x00dev, state);
1249 case STATE_RADIO_IRQ_ON:
1250 case STATE_RADIO_IRQ_OFF:
1251 /* No support, but no error either */
1253 case STATE_DEEP_SLEEP:
1257 retval = rt73usb_set_state(rt2x00dev, state);
1264 if (unlikely(retval))
1265 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1272 * TX descriptor initialization
1274 static void rt73usb_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1275 struct sk_buff *skb,
1276 struct txentry_desc *txdesc)
1278 struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1279 __le32 *txd = skbdesc->desc;
1283 * Start writing the descriptor words.
1285 rt2x00_desc_read(txd, 1, &word);
1286 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1287 rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1288 rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1289 rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1290 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1291 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1292 rt2x00_desc_write(txd, 1, word);
1294 rt2x00_desc_read(txd, 2, &word);
1295 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1296 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1297 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1298 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1299 rt2x00_desc_write(txd, 2, word);
1301 rt2x00_desc_read(txd, 5, &word);
1302 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1303 TXPOWER_TO_DEV(rt2x00dev->tx_power));
1304 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1305 rt2x00_desc_write(txd, 5, word);
1307 rt2x00_desc_read(txd, 0, &word);
1308 rt2x00_set_field32(&word, TXD_W0_BURST,
1309 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1310 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1311 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1312 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1313 rt2x00_set_field32(&word, TXD_W0_ACK,
1314 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1315 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1316 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1317 rt2x00_set_field32(&word, TXD_W0_OFDM,
1318 test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1319 rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1320 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1321 test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1322 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1323 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1324 rt2x00_set_field32(&word, TXD_W0_BURST2,
1325 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1326 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1327 rt2x00_desc_write(txd, 0, word);
1330 static int rt73usb_get_tx_data_len(struct rt2x00_dev *rt2x00dev,
1331 struct sk_buff *skb)
1336 * The length _must_ be a multiple of 4,
1337 * but it must _not_ be a multiple of the USB packet size.
1339 length = roundup(skb->len, 4);
1340 length += (4 * !(length % rt2x00dev->usb_maxpacket));
1346 * TX data initialization
1348 static void rt73usb_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1349 const enum data_queue_qid queue)
1353 if (queue != QID_BEACON) {
1354 rt2x00usb_kick_tx_queue(rt2x00dev, queue);
1359 * For Wi-Fi faily generated beacons between participating stations.
1360 * Set TBTT phase adaptive adjustment step to 8us (default 16us)
1362 rt73usb_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1364 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
1365 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1366 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
1367 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
1368 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1369 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
1374 * RX control handlers
1376 static int rt73usb_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1382 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1397 if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1398 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
1399 if (lna == 3 || lna == 2)
1408 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1409 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1411 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1414 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1415 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1418 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1421 static void rt73usb_fill_rxdone(struct queue_entry *entry,
1422 struct rxdone_entry_desc *rxdesc)
1424 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1425 __le32 *rxd = (__le32 *)entry->skb->data;
1430 * Copy descriptor to the skb->cb array, this has 2 benefits:
1431 * 1) Each descriptor word is 4 byte aligned.
1432 * 2) Descriptor is safe from moving of frame data in rt2x00usb.
1435 min_t(u16, entry->queue->desc_size, sizeof(entry->skb->cb));
1436 memcpy(entry->skb->cb, rxd, skbdesc->desc_len);
1437 skbdesc->desc = entry->skb->cb;
1438 rxd = (__le32 *)skbdesc->desc;
1441 * It is now safe to read the descriptor on all architectures.
1443 rt2x00_desc_read(rxd, 0, &word0);
1444 rt2x00_desc_read(rxd, 1, &word1);
1446 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1447 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1450 * Obtain the status about this packet.
1451 * When frame was received with an OFDM bitrate,
1452 * the signal is the PLCP value. If it was received with
1453 * a CCK bitrate the signal is the rate in 100kbit/s.
1455 rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1456 rxdesc->rssi = rt73usb_agc_to_rssi(entry->queue->rt2x00dev, word1);
1457 rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1459 if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1460 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1461 if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1462 rxdesc->dev_flags |= RXDONE_MY_BSS;
1465 * Set skb pointers, and update frame information.
1467 skb_pull(entry->skb, entry->queue->desc_size);
1468 skb_trim(entry->skb, rxdesc->size);
1469 skbdesc->data = entry->skb->data;
1470 skbdesc->data_len = rxdesc->size;
1474 * Device probe functions.
1476 static int rt73usb_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1482 rt2x00usb_eeprom_read(rt2x00dev, rt2x00dev->eeprom, EEPROM_SIZE);
1485 * Start validation of the data that has been read.
1487 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1488 if (!is_valid_ether_addr(mac)) {
1489 DECLARE_MAC_BUF(macbuf);
1491 random_ether_addr(mac);
1492 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1495 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1496 if (word == 0xffff) {
1497 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1498 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1500 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1502 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1503 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1504 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1505 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5226);
1506 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1507 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1510 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1511 if (word == 0xffff) {
1512 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA, 0);
1513 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1514 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1517 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1518 if (word == 0xffff) {
1519 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_G, 0);
1520 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_RDY_A, 0);
1521 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_ACT, 0);
1522 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_0, 0);
1523 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_1, 0);
1524 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_2, 0);
1525 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_3, 0);
1526 rt2x00_set_field16(&word, EEPROM_LED_POLARITY_GPIO_4, 0);
1527 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1529 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1530 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1533 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1534 if (word == 0xffff) {
1535 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1536 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1537 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1538 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1541 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1542 if (word == 0xffff) {
1543 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1544 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1545 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1546 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1548 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1549 if (value < -10 || value > 10)
1550 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1551 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1552 if (value < -10 || value > 10)
1553 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1554 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1557 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1558 if (word == 0xffff) {
1559 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1560 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1561 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1562 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1564 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1565 if (value < -10 || value > 10)
1566 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1567 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1568 if (value < -10 || value > 10)
1569 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1570 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1576 static int rt73usb_init_eeprom(struct rt2x00_dev *rt2x00dev)
1583 * Read EEPROM word for configuration.
1585 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1588 * Identify RF chipset.
1590 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1591 rt73usb_register_read(rt2x00dev, MAC_CSR0, ®);
1592 rt2x00_set_chip(rt2x00dev, RT2571, value, reg);
1594 if (!rt2x00_check_rev(&rt2x00dev->chip, 0x25730)) {
1595 ERROR(rt2x00dev, "Invalid RT chipset detected.\n");
1599 if (!rt2x00_rf(&rt2x00dev->chip, RF5226) &&
1600 !rt2x00_rf(&rt2x00dev->chip, RF2528) &&
1601 !rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1602 !rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1603 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1608 * Identify default antenna configuration.
1610 rt2x00dev->default_ant.tx =
1611 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1612 rt2x00dev->default_ant.rx =
1613 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1616 * Read the Frame type.
1618 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1619 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1622 * Read frequency offset.
1624 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1625 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1628 * Read external LNA informations.
1630 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1632 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA)) {
1633 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1634 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1638 * Store led settings, for correct led behaviour.
1640 #ifdef CONFIG_RT73USB_LEDS
1641 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
1643 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1644 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
1645 if (value == LED_MODE_SIGNAL_STRENGTH)
1646 rt73usb_init_led(rt2x00dev, &rt2x00dev->led_qual,
1649 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
1650 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
1651 rt2x00_get_field16(eeprom,
1652 EEPROM_LED_POLARITY_GPIO_0));
1653 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
1654 rt2x00_get_field16(eeprom,
1655 EEPROM_LED_POLARITY_GPIO_1));
1656 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
1657 rt2x00_get_field16(eeprom,
1658 EEPROM_LED_POLARITY_GPIO_2));
1659 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
1660 rt2x00_get_field16(eeprom,
1661 EEPROM_LED_POLARITY_GPIO_3));
1662 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
1663 rt2x00_get_field16(eeprom,
1664 EEPROM_LED_POLARITY_GPIO_4));
1665 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
1666 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
1667 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
1668 rt2x00_get_field16(eeprom,
1669 EEPROM_LED_POLARITY_RDY_G));
1670 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
1671 rt2x00_get_field16(eeprom,
1672 EEPROM_LED_POLARITY_RDY_A));
1673 #endif /* CONFIG_RT73USB_LEDS */
1679 * RF value list for RF2528
1682 static const struct rf_channel rf_vals_bg_2528[] = {
1683 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1684 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1685 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1686 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1687 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1688 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1689 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1690 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1691 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1692 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1693 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1694 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1695 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1696 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1700 * RF value list for RF5226
1701 * Supports: 2.4 GHz & 5.2 GHz
1703 static const struct rf_channel rf_vals_5226[] = {
1704 { 1, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea0b },
1705 { 2, 0x00002c0c, 0x00000786, 0x00068255, 0x000fea1f },
1706 { 3, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea0b },
1707 { 4, 0x00002c0c, 0x0000078a, 0x00068255, 0x000fea1f },
1708 { 5, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea0b },
1709 { 6, 0x00002c0c, 0x0000078e, 0x00068255, 0x000fea1f },
1710 { 7, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea0b },
1711 { 8, 0x00002c0c, 0x00000792, 0x00068255, 0x000fea1f },
1712 { 9, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea0b },
1713 { 10, 0x00002c0c, 0x00000796, 0x00068255, 0x000fea1f },
1714 { 11, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea0b },
1715 { 12, 0x00002c0c, 0x0000079a, 0x00068255, 0x000fea1f },
1716 { 13, 0x00002c0c, 0x0000079e, 0x00068255, 0x000fea0b },
1717 { 14, 0x00002c0c, 0x000007a2, 0x00068255, 0x000fea13 },
1719 /* 802.11 UNI / HyperLan 2 */
1720 { 36, 0x00002c0c, 0x0000099a, 0x00098255, 0x000fea23 },
1721 { 40, 0x00002c0c, 0x000009a2, 0x00098255, 0x000fea03 },
1722 { 44, 0x00002c0c, 0x000009a6, 0x00098255, 0x000fea0b },
1723 { 48, 0x00002c0c, 0x000009aa, 0x00098255, 0x000fea13 },
1724 { 52, 0x00002c0c, 0x000009ae, 0x00098255, 0x000fea1b },
1725 { 56, 0x00002c0c, 0x000009b2, 0x00098255, 0x000fea23 },
1726 { 60, 0x00002c0c, 0x000009ba, 0x00098255, 0x000fea03 },
1727 { 64, 0x00002c0c, 0x000009be, 0x00098255, 0x000fea0b },
1729 /* 802.11 HyperLan 2 */
1730 { 100, 0x00002c0c, 0x00000a2a, 0x000b8255, 0x000fea03 },
1731 { 104, 0x00002c0c, 0x00000a2e, 0x000b8255, 0x000fea0b },
1732 { 108, 0x00002c0c, 0x00000a32, 0x000b8255, 0x000fea13 },
1733 { 112, 0x00002c0c, 0x00000a36, 0x000b8255, 0x000fea1b },
1734 { 116, 0x00002c0c, 0x00000a3a, 0x000b8255, 0x000fea23 },
1735 { 120, 0x00002c0c, 0x00000a82, 0x000b8255, 0x000fea03 },
1736 { 124, 0x00002c0c, 0x00000a86, 0x000b8255, 0x000fea0b },
1737 { 128, 0x00002c0c, 0x00000a8a, 0x000b8255, 0x000fea13 },
1738 { 132, 0x00002c0c, 0x00000a8e, 0x000b8255, 0x000fea1b },
1739 { 136, 0x00002c0c, 0x00000a92, 0x000b8255, 0x000fea23 },
1742 { 140, 0x00002c0c, 0x00000a9a, 0x000b8255, 0x000fea03 },
1743 { 149, 0x00002c0c, 0x00000aa2, 0x000b8255, 0x000fea1f },
1744 { 153, 0x00002c0c, 0x00000aa6, 0x000b8255, 0x000fea27 },
1745 { 157, 0x00002c0c, 0x00000aae, 0x000b8255, 0x000fea07 },
1746 { 161, 0x00002c0c, 0x00000ab2, 0x000b8255, 0x000fea0f },
1747 { 165, 0x00002c0c, 0x00000ab6, 0x000b8255, 0x000fea17 },
1749 /* MMAC(Japan)J52 ch 34,38,42,46 */
1750 { 34, 0x00002c0c, 0x0008099a, 0x000da255, 0x000d3a0b },
1751 { 38, 0x00002c0c, 0x0008099e, 0x000da255, 0x000d3a13 },
1752 { 42, 0x00002c0c, 0x000809a2, 0x000da255, 0x000d3a1b },
1753 { 46, 0x00002c0c, 0x000809a6, 0x000da255, 0x000d3a23 },
1757 * RF value list for RF5225 & RF2527
1758 * Supports: 2.4 GHz & 5.2 GHz
1760 static const struct rf_channel rf_vals_5225_2527[] = {
1761 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
1762 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
1763 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
1764 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
1765 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
1766 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
1767 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
1768 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
1769 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
1770 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
1771 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
1772 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
1773 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
1774 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
1776 /* 802.11 UNI / HyperLan 2 */
1777 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
1778 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
1779 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
1780 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
1781 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
1782 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
1783 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
1784 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
1786 /* 802.11 HyperLan 2 */
1787 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
1788 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
1789 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
1790 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
1791 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
1792 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
1793 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
1794 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
1795 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
1796 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
1799 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
1800 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
1801 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
1802 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
1803 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
1804 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
1806 /* MMAC(Japan)J52 ch 34,38,42,46 */
1807 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
1808 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
1809 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
1810 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
1814 static void rt73usb_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1816 struct hw_mode_spec *spec = &rt2x00dev->spec;
1821 * Initialize all hw fields.
1823 rt2x00dev->hw->flags =
1824 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
1825 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1826 IEEE80211_HW_SIGNAL_DBM;
1827 rt2x00dev->hw->extra_tx_headroom = TXD_DESC_SIZE;
1829 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_usb(rt2x00dev)->dev);
1830 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1831 rt2x00_eeprom_addr(rt2x00dev,
1832 EEPROM_MAC_ADDR_0));
1835 * Convert tx_power array in eeprom.
1837 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
1838 for (i = 0; i < 14; i++)
1839 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1842 * Initialize hw_mode information.
1844 spec->supported_bands = SUPPORT_BAND_2GHZ;
1845 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1846 spec->tx_power_a = NULL;
1847 spec->tx_power_bg = txpower;
1848 spec->tx_power_default = DEFAULT_TXPOWER;
1850 if (rt2x00_rf(&rt2x00dev->chip, RF2528)) {
1851 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2528);
1852 spec->channels = rf_vals_bg_2528;
1853 } else if (rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1854 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1855 spec->num_channels = ARRAY_SIZE(rf_vals_5226);
1856 spec->channels = rf_vals_5226;
1857 } else if (rt2x00_rf(&rt2x00dev->chip, RF2527)) {
1858 spec->num_channels = 14;
1859 spec->channels = rf_vals_5225_2527;
1860 } else if (rt2x00_rf(&rt2x00dev->chip, RF5225)) {
1861 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1862 spec->num_channels = ARRAY_SIZE(rf_vals_5225_2527);
1863 spec->channels = rf_vals_5225_2527;
1866 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
1867 rt2x00_rf(&rt2x00dev->chip, RF5226)) {
1868 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
1869 for (i = 0; i < 14; i++)
1870 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1872 spec->tx_power_a = txpower;
1876 static int rt73usb_probe_hw(struct rt2x00_dev *rt2x00dev)
1881 * Allocate eeprom data.
1883 retval = rt73usb_validate_eeprom(rt2x00dev);
1887 retval = rt73usb_init_eeprom(rt2x00dev);
1892 * Initialize hw specifications.
1894 rt73usb_probe_hw_mode(rt2x00dev);
1897 * This device requires firmware.
1899 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
1900 __set_bit(DRIVER_REQUIRE_SCHEDULED, &rt2x00dev->flags);
1903 * Set the rssi offset.
1905 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1911 * IEEE80211 stack callback functions.
1913 static int rt73usb_set_retry_limit(struct ieee80211_hw *hw,
1914 u32 short_retry, u32 long_retry)
1916 struct rt2x00_dev *rt2x00dev = hw->priv;
1919 rt73usb_register_read(rt2x00dev, TXRX_CSR4, ®);
1920 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
1921 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
1922 rt73usb_register_write(rt2x00dev, TXRX_CSR4, reg);
1929 * Mac80211 demands get_tsf must be atomic.
1930 * This is not possible for rt73usb since all register access
1931 * functions require sleeping. Untill mac80211 no longer needs
1932 * get_tsf to be atomic, this function should be disabled.
1934 static u64 rt73usb_get_tsf(struct ieee80211_hw *hw)
1936 struct rt2x00_dev *rt2x00dev = hw->priv;
1940 rt73usb_register_read(rt2x00dev, TXRX_CSR13, ®);
1941 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
1942 rt73usb_register_read(rt2x00dev, TXRX_CSR12, ®);
1943 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
1948 #define rt73usb_get_tsf NULL
1951 static int rt73usb_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
1953 struct rt2x00_dev *rt2x00dev = hw->priv;
1954 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1955 struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
1956 struct skb_frame_desc *skbdesc;
1957 struct txentry_desc txdesc;
1958 unsigned int beacon_base;
1961 if (unlikely(!intf->beacon))
1965 * Copy all TX descriptor information into txdesc,
1966 * after that we are free to use the skb->cb array
1967 * for our information.
1969 intf->beacon->skb = skb;
1970 rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
1973 * Add the descriptor in front of the skb.
1975 skb_push(skb, intf->beacon->queue->desc_size);
1976 memset(skb->data, 0, intf->beacon->queue->desc_size);
1979 * Fill in skb descriptor
1981 skbdesc = get_skb_frame_desc(skb);
1982 memset(skbdesc, 0, sizeof(*skbdesc));
1983 skbdesc->data = skb->data + intf->beacon->queue->desc_size;
1984 skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
1985 skbdesc->desc = skb->data;
1986 skbdesc->desc_len = intf->beacon->queue->desc_size;
1987 skbdesc->entry = intf->beacon;
1990 * Disable beaconing while we are reloading the beacon data,
1991 * otherwise we might be sending out invalid data.
1993 rt73usb_register_read(rt2x00dev, TXRX_CSR9, ®);
1994 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 0);
1995 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 0);
1996 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
1997 rt73usb_register_write(rt2x00dev, TXRX_CSR9, reg);
2000 * Write entire beacon with descriptor to register,
2001 * and kick the beacon generator.
2003 rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
2004 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2005 rt2x00usb_vendor_request(rt2x00dev, USB_MULTI_WRITE,
2006 USB_VENDOR_REQUEST_OUT, beacon_base, 0,
2007 skb->data, skb->len,
2008 REGISTER_TIMEOUT32(skb->len));
2009 rt73usb_kick_tx_queue(rt2x00dev, QID_BEACON);
2014 static const struct ieee80211_ops rt73usb_mac80211_ops = {
2016 .start = rt2x00mac_start,
2017 .stop = rt2x00mac_stop,
2018 .add_interface = rt2x00mac_add_interface,
2019 .remove_interface = rt2x00mac_remove_interface,
2020 .config = rt2x00mac_config,
2021 .config_interface = rt2x00mac_config_interface,
2022 .configure_filter = rt2x00mac_configure_filter,
2023 .get_stats = rt2x00mac_get_stats,
2024 .set_retry_limit = rt73usb_set_retry_limit,
2025 .bss_info_changed = rt2x00mac_bss_info_changed,
2026 .conf_tx = rt2x00mac_conf_tx,
2027 .get_tx_stats = rt2x00mac_get_tx_stats,
2028 .get_tsf = rt73usb_get_tsf,
2029 .beacon_update = rt73usb_beacon_update,
2032 static const struct rt2x00lib_ops rt73usb_rt2x00_ops = {
2033 .probe_hw = rt73usb_probe_hw,
2034 .get_firmware_name = rt73usb_get_firmware_name,
2035 .get_firmware_crc = rt73usb_get_firmware_crc,
2036 .load_firmware = rt73usb_load_firmware,
2037 .initialize = rt2x00usb_initialize,
2038 .uninitialize = rt2x00usb_uninitialize,
2039 .init_rxentry = rt2x00usb_init_rxentry,
2040 .init_txentry = rt2x00usb_init_txentry,
2041 .set_device_state = rt73usb_set_device_state,
2042 .link_stats = rt73usb_link_stats,
2043 .reset_tuner = rt73usb_reset_tuner,
2044 .link_tuner = rt73usb_link_tuner,
2045 .write_tx_desc = rt73usb_write_tx_desc,
2046 .write_tx_data = rt2x00usb_write_tx_data,
2047 .get_tx_data_len = rt73usb_get_tx_data_len,
2048 .kick_tx_queue = rt73usb_kick_tx_queue,
2049 .fill_rxdone = rt73usb_fill_rxdone,
2050 .config_filter = rt73usb_config_filter,
2051 .config_intf = rt73usb_config_intf,
2052 .config_erp = rt73usb_config_erp,
2053 .config = rt73usb_config,
2056 static const struct data_queue_desc rt73usb_queue_rx = {
2057 .entry_num = RX_ENTRIES,
2058 .data_size = DATA_FRAME_SIZE,
2059 .desc_size = RXD_DESC_SIZE,
2060 .priv_size = sizeof(struct queue_entry_priv_usb),
2063 static const struct data_queue_desc rt73usb_queue_tx = {
2064 .entry_num = TX_ENTRIES,
2065 .data_size = DATA_FRAME_SIZE,
2066 .desc_size = TXD_DESC_SIZE,
2067 .priv_size = sizeof(struct queue_entry_priv_usb),
2070 static const struct data_queue_desc rt73usb_queue_bcn = {
2071 .entry_num = 4 * BEACON_ENTRIES,
2072 .data_size = MGMT_FRAME_SIZE,
2073 .desc_size = TXINFO_SIZE,
2074 .priv_size = sizeof(struct queue_entry_priv_usb),
2077 static const struct rt2x00_ops rt73usb_ops = {
2078 .name = KBUILD_MODNAME,
2081 .eeprom_size = EEPROM_SIZE,
2083 .tx_queues = NUM_TX_QUEUES,
2084 .rx = &rt73usb_queue_rx,
2085 .tx = &rt73usb_queue_tx,
2086 .bcn = &rt73usb_queue_bcn,
2087 .lib = &rt73usb_rt2x00_ops,
2088 .hw = &rt73usb_mac80211_ops,
2089 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2090 .debugfs = &rt73usb_rt2x00debug,
2091 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2095 * rt73usb module information.
2097 static struct usb_device_id rt73usb_device_table[] = {
2099 { USB_DEVICE(0x07b8, 0xb21d), USB_DEVICE_DATA(&rt73usb_ops) },
2101 { USB_DEVICE(0x1690, 0x0722), USB_DEVICE_DATA(&rt73usb_ops) },
2103 { USB_DEVICE(0x0b05, 0x1723), USB_DEVICE_DATA(&rt73usb_ops) },
2104 { USB_DEVICE(0x0b05, 0x1724), USB_DEVICE_DATA(&rt73usb_ops) },
2106 { USB_DEVICE(0x050d, 0x7050), USB_DEVICE_DATA(&rt73usb_ops) },
2107 { USB_DEVICE(0x050d, 0x705a), USB_DEVICE_DATA(&rt73usb_ops) },
2108 { USB_DEVICE(0x050d, 0x905b), USB_DEVICE_DATA(&rt73usb_ops) },
2109 { USB_DEVICE(0x050d, 0x905c), USB_DEVICE_DATA(&rt73usb_ops) },
2111 { USB_DEVICE(0x1631, 0xc019), USB_DEVICE_DATA(&rt73usb_ops) },
2113 { USB_DEVICE(0x0411, 0x00f4), USB_DEVICE_DATA(&rt73usb_ops) },
2115 { USB_DEVICE(0x1371, 0x9022), USB_DEVICE_DATA(&rt73usb_ops) },
2116 { USB_DEVICE(0x1371, 0x9032), USB_DEVICE_DATA(&rt73usb_ops) },
2118 { USB_DEVICE(0x14b2, 0x3c22), USB_DEVICE_DATA(&rt73usb_ops) },
2120 { USB_DEVICE(0x07aa, 0x002e), USB_DEVICE_DATA(&rt73usb_ops) },
2122 { USB_DEVICE(0x07d1, 0x3c03), USB_DEVICE_DATA(&rt73usb_ops) },
2123 { USB_DEVICE(0x07d1, 0x3c04), USB_DEVICE_DATA(&rt73usb_ops) },
2124 { USB_DEVICE(0x07d1, 0x3c07), USB_DEVICE_DATA(&rt73usb_ops) },
2126 { USB_DEVICE(0x15a9, 0x0004), USB_DEVICE_DATA(&rt73usb_ops) },
2128 { USB_DEVICE(0x1044, 0x8008), USB_DEVICE_DATA(&rt73usb_ops) },
2129 { USB_DEVICE(0x1044, 0x800a), USB_DEVICE_DATA(&rt73usb_ops) },
2131 { USB_DEVICE(0x1472, 0x0009), USB_DEVICE_DATA(&rt73usb_ops) },
2133 { USB_DEVICE(0x06f8, 0xe010), USB_DEVICE_DATA(&rt73usb_ops) },
2134 { USB_DEVICE(0x06f8, 0xe020), USB_DEVICE_DATA(&rt73usb_ops) },
2136 { USB_DEVICE(0x13b1, 0x0020), USB_DEVICE_DATA(&rt73usb_ops) },
2137 { USB_DEVICE(0x13b1, 0x0023), USB_DEVICE_DATA(&rt73usb_ops) },
2139 { USB_DEVICE(0x0db0, 0x6877), USB_DEVICE_DATA(&rt73usb_ops) },
2140 { USB_DEVICE(0x0db0, 0x6874), USB_DEVICE_DATA(&rt73usb_ops) },
2141 { USB_DEVICE(0x0db0, 0xa861), USB_DEVICE_DATA(&rt73usb_ops) },
2142 { USB_DEVICE(0x0db0, 0xa874), USB_DEVICE_DATA(&rt73usb_ops) },
2144 { USB_DEVICE(0x148f, 0x2573), USB_DEVICE_DATA(&rt73usb_ops) },
2145 { USB_DEVICE(0x148f, 0x2671), USB_DEVICE_DATA(&rt73usb_ops) },
2147 { USB_DEVICE(0x18e8, 0x6196), USB_DEVICE_DATA(&rt73usb_ops) },
2148 { USB_DEVICE(0x18e8, 0x6229), USB_DEVICE_DATA(&rt73usb_ops) },
2149 { USB_DEVICE(0x18e8, 0x6238), USB_DEVICE_DATA(&rt73usb_ops) },
2151 { USB_DEVICE(0x1740, 0x7100), USB_DEVICE_DATA(&rt73usb_ops) },
2153 { USB_DEVICE(0x0df6, 0x9712), USB_DEVICE_DATA(&rt73usb_ops) },
2154 { USB_DEVICE(0x0df6, 0x90ac), USB_DEVICE_DATA(&rt73usb_ops) },
2156 { USB_DEVICE(0x0769, 0x31f3), USB_DEVICE_DATA(&rt73usb_ops) },
2158 { USB_DEVICE(0x2019, 0xab01), USB_DEVICE_DATA(&rt73usb_ops) },
2159 { USB_DEVICE(0x2019, 0xab50), USB_DEVICE_DATA(&rt73usb_ops) },
2163 MODULE_AUTHOR(DRV_PROJECT);
2164 MODULE_VERSION(DRV_VERSION);
2165 MODULE_DESCRIPTION("Ralink RT73 USB Wireless LAN driver.");
2166 MODULE_SUPPORTED_DEVICE("Ralink RT2571W & RT2671 USB chipset based cards");
2167 MODULE_DEVICE_TABLE(usb, rt73usb_device_table);
2168 MODULE_FIRMWARE(FIRMWARE_RT2571);
2169 MODULE_LICENSE("GPL");
2171 static struct usb_driver rt73usb_driver = {
2172 .name = KBUILD_MODNAME,
2173 .id_table = rt73usb_device_table,
2174 .probe = rt2x00usb_probe,
2175 .disconnect = rt2x00usb_disconnect,
2176 .suspend = rt2x00usb_suspend,
2177 .resume = rt2x00usb_resume,
2180 static int __init rt73usb_init(void)
2182 return usb_register(&rt73usb_driver);
2185 static void __exit rt73usb_exit(void)
2187 usb_deregister(&rt73usb_driver);
2190 module_init(rt73usb_init);
2191 module_exit(rt73usb_exit);