2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: Data structures and registers for the rt61pci module.
24 Supported chipsets: RT2561, RT2561s, RT2661.
40 * Defaul offset is required for RSSI <-> dBm conversion.
42 #define MAX_SIGNAL 100
44 #define DEFAULT_RSSI_OFFSET 120
47 * Register layout information.
49 #define CSR_REG_BASE 0x3000
50 #define CSR_REG_SIZE 0x04b0
51 #define EEPROM_BASE 0x0000
52 #define EEPROM_SIZE 0x0100
53 #define BBP_SIZE 0x0080
54 #define RF_SIZE 0x0014
57 * Number of TX queues.
59 #define NUM_TX_QUEUES 4
66 * PCI Configuration Header
68 #define PCI_CONFIG_HEADER_VENDOR 0x0000
69 #define PCI_CONFIG_HEADER_DEVICE 0x0002
72 * HOST_CMD_CSR: For HOST to interrupt embedded processor
74 #define HOST_CMD_CSR 0x0008
75 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x0000007f)
76 #define HOST_CMD_CSR_INTERRUPT_MCU FIELD32(0x00000080)
80 * SELECT_BANK: Select 8051 program bank.
81 * RESET: Enable 8051 reset state.
82 * READY: Ready state for 8051.
84 #define MCU_CNTL_CSR 0x000c
85 #define MCU_CNTL_CSR_SELECT_BANK FIELD32(0x00000001)
86 #define MCU_CNTL_CSR_RESET FIELD32(0x00000002)
87 #define MCU_CNTL_CSR_READY FIELD32(0x00000004)
92 #define SOFT_RESET_CSR 0x0010
95 * MCU_INT_SOURCE_CSR: MCU interrupt source/mask register.
97 #define MCU_INT_SOURCE_CSR 0x0014
98 #define MCU_INT_SOURCE_CSR_0 FIELD32(0x00000001)
99 #define MCU_INT_SOURCE_CSR_1 FIELD32(0x00000002)
100 #define MCU_INT_SOURCE_CSR_2 FIELD32(0x00000004)
101 #define MCU_INT_SOURCE_CSR_3 FIELD32(0x00000008)
102 #define MCU_INT_SOURCE_CSR_4 FIELD32(0x00000010)
103 #define MCU_INT_SOURCE_CSR_5 FIELD32(0x00000020)
104 #define MCU_INT_SOURCE_CSR_6 FIELD32(0x00000040)
105 #define MCU_INT_SOURCE_CSR_7 FIELD32(0x00000080)
106 #define MCU_INT_SOURCE_CSR_TWAKEUP FIELD32(0x00000100)
107 #define MCU_INT_SOURCE_CSR_TBTT_EXPIRE FIELD32(0x00000200)
110 * MCU_INT_MASK_CSR: MCU interrupt source/mask register.
112 #define MCU_INT_MASK_CSR 0x0018
113 #define MCU_INT_MASK_CSR_0 FIELD32(0x00000001)
114 #define MCU_INT_MASK_CSR_1 FIELD32(0x00000002)
115 #define MCU_INT_MASK_CSR_2 FIELD32(0x00000004)
116 #define MCU_INT_MASK_CSR_3 FIELD32(0x00000008)
117 #define MCU_INT_MASK_CSR_4 FIELD32(0x00000010)
118 #define MCU_INT_MASK_CSR_5 FIELD32(0x00000020)
119 #define MCU_INT_MASK_CSR_6 FIELD32(0x00000040)
120 #define MCU_INT_MASK_CSR_7 FIELD32(0x00000080)
121 #define MCU_INT_MASK_CSR_TWAKEUP FIELD32(0x00000100)
122 #define MCU_INT_MASK_CSR_TBTT_EXPIRE FIELD32(0x00000200)
127 #define PCI_USEC_CSR 0x001c
130 * Security key table memory.
131 * 16 entries 32-byte for shared key table
132 * 64 entries 32-byte for pairwise key table
133 * 64 entries 8-byte for pairwise ta key table
135 #define SHARED_KEY_TABLE_BASE 0x1000
136 #define PAIRWISE_KEY_TABLE_BASE 0x1200
137 #define PAIRWISE_TA_TABLE_BASE 0x1a00
139 struct hw_key_entry {
143 } __attribute__ ((packed));
145 struct hw_pairwise_ta_entry {
148 } __attribute__ ((packed));
151 * Other on-chip shared memory space.
153 #define HW_CIS_BASE 0x2000
154 #define HW_NULL_BASE 0x2b00
157 * Since NULL frame won't be that long (256 byte),
158 * We steal 16 tail bytes to save debugging settings.
160 #define HW_DEBUG_SETTING_BASE 0x2bf0
163 * On-chip BEACON frame space.
165 #define HW_BEACON_BASE0 0x2c00
166 #define HW_BEACON_BASE1 0x2d00
167 #define HW_BEACON_BASE2 0x2e00
168 #define HW_BEACON_BASE3 0x2f00
170 #define HW_BEACON_OFFSET(__index) \
171 ( HW_BEACON_BASE0 + (__index * 0x0100) )
174 * HOST-MCU shared memory.
178 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
180 #define H2M_MAILBOX_CSR 0x2100
181 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
182 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
183 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
184 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
187 * MCU_LEDCS: LED control for MCU Mailbox.
189 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
190 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
191 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
192 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
193 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
194 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
195 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
196 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
197 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
198 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
199 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
200 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
205 #define M2H_CMD_DONE_CSR 0x2104
208 * MCU_TXOP_ARRAY_BASE.
210 #define MCU_TXOP_ARRAY_BASE 0x2110
213 * MAC Control/Status Registers(CSR).
214 * Some values are set in TU, whereas 1 TU == 1024 us.
218 * MAC_CSR0: ASIC revision number.
220 #define MAC_CSR0 0x3000
223 * MAC_CSR1: System control register.
224 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
225 * BBP_RESET: Hardware reset BBP.
226 * HOST_READY: Host is ready after initialization, 1: ready.
228 #define MAC_CSR1 0x3004
229 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
230 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
231 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
234 * MAC_CSR2: STA MAC register 0.
236 #define MAC_CSR2 0x3008
237 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
238 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
239 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
240 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
243 * MAC_CSR3: STA MAC register 1.
244 * UNICAST_TO_ME_MASK:
245 * Used to mask off bits from byte 5 of the MAC address
246 * to determine the UNICAST_TO_ME bit for RX frames.
247 * The full mask is complemented by BSS_ID_MASK:
248 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
250 #define MAC_CSR3 0x300c
251 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
252 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
253 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
256 * MAC_CSR4: BSSID register 0.
258 #define MAC_CSR4 0x3010
259 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
260 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
261 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
262 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
265 * MAC_CSR5: BSSID register 1.
267 * This mask is used to mask off bits 0 and 1 of byte 5 of the
268 * BSSID. This will make sure that those bits will be ignored
269 * when determining the MY_BSS of RX frames.
270 * 0: 1-BSSID mode (BSS index = 0)
271 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
272 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
273 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
275 #define MAC_CSR5 0x3014
276 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
277 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
278 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
281 * MAC_CSR6: Maximum frame length register.
283 #define MAC_CSR6 0x3018
284 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
289 #define MAC_CSR7 0x301c
292 * MAC_CSR8: SIFS/EIFS register.
293 * All units are in US.
295 #define MAC_CSR8 0x3020
296 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
297 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
298 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
301 * MAC_CSR9: Back-Off control register.
302 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
303 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
304 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
305 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
307 #define MAC_CSR9 0x3024
308 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
309 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
310 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
311 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
314 * MAC_CSR10: Power state configuration.
316 #define MAC_CSR10 0x3028
319 * MAC_CSR11: Power saving transition time register.
320 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
321 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
322 * WAKEUP_LATENCY: In unit of TU.
324 #define MAC_CSR11 0x302c
325 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
326 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
327 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
328 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
331 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
332 * CURRENT_STATE: 0:sleep, 1:awake.
333 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
334 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
336 #define MAC_CSR12 0x3030
337 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
338 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
339 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
340 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
345 #define MAC_CSR13 0x3034
346 #define MAC_CSR13_BIT0 FIELD32(0x00000001)
347 #define MAC_CSR13_BIT1 FIELD32(0x00000002)
348 #define MAC_CSR13_BIT2 FIELD32(0x00000004)
349 #define MAC_CSR13_BIT3 FIELD32(0x00000008)
350 #define MAC_CSR13_BIT4 FIELD32(0x00000010)
351 #define MAC_CSR13_BIT5 FIELD32(0x00000020)
352 #define MAC_CSR13_BIT6 FIELD32(0x00000040)
353 #define MAC_CSR13_BIT7 FIELD32(0x00000080)
354 #define MAC_CSR13_BIT8 FIELD32(0x00000100)
355 #define MAC_CSR13_BIT9 FIELD32(0x00000200)
356 #define MAC_CSR13_BIT10 FIELD32(0x00000400)
357 #define MAC_CSR13_BIT11 FIELD32(0x00000800)
358 #define MAC_CSR13_BIT12 FIELD32(0x00001000)
361 * MAC_CSR14: LED control register.
362 * ON_PERIOD: On period, default 70ms.
363 * OFF_PERIOD: Off period, default 30ms.
364 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
365 * SW_LED: s/w LED, 1: ON, 0: OFF.
366 * HW_LED_POLARITY: 0: active low, 1: active high.
368 #define MAC_CSR14 0x3038
369 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
370 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
371 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
372 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
373 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
374 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
377 * MAC_CSR15: NAV control.
379 #define MAC_CSR15 0x303c
382 * TXRX control registers.
383 * Some values are set in TU, whereas 1 TU == 1024 us.
387 * TXRX_CSR0: TX/RX configuration register.
388 * TSF_OFFSET: Default is 24.
389 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
390 * DISABLE_RX: Disable Rx engine.
391 * DROP_CRC: Drop CRC error.
392 * DROP_PHYSICAL: Drop physical error.
393 * DROP_CONTROL: Drop control frame.
394 * DROP_NOT_TO_ME: Drop not to me unicast frame.
395 * DROP_TO_DS: Drop fram ToDs bit is true.
396 * DROP_VERSION_ERROR: Drop version error frame.
397 * DROP_MULTICAST: Drop multicast frames.
398 * DROP_BORADCAST: Drop broadcast frames.
399 * ROP_ACK_CTS: Drop received ACK and CTS.
401 #define TXRX_CSR0 0x3040
402 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
403 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
404 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
405 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
406 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
407 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
408 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
409 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
410 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
411 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
412 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
413 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
414 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
415 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
420 #define TXRX_CSR1 0x3044
421 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
422 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
423 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
424 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
425 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
426 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
427 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
428 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
433 #define TXRX_CSR2 0x3048
434 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
435 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
436 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
437 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
438 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
439 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
440 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
441 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
446 #define TXRX_CSR3 0x304c
447 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
448 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
449 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
450 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
451 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
452 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
453 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
454 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
457 * TXRX_CSR4: Auto-Responder/Tx-retry register.
458 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
459 * OFDM_TX_RATE_DOWN: 1:enable.
460 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
461 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
463 #define TXRX_CSR4 0x3050
464 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
465 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
466 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
467 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
468 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
469 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
470 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
471 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
472 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
473 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
478 #define TXRX_CSR5 0x3054
481 * TXRX_CSR6: ACK/CTS payload consumed time
483 #define TXRX_CSR6 0x3058
486 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
488 #define TXRX_CSR7 0x305c
489 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
490 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
491 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
492 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
495 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
497 #define TXRX_CSR8 0x3060
498 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
499 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
500 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
501 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
504 * TXRX_CSR9: Synchronization control register.
505 * BEACON_INTERVAL: In unit of 1/16 TU.
506 * TSF_TICKING: Enable TSF auto counting.
507 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
508 * BEACON_GEN: Enable beacon generator.
510 #define TXRX_CSR9 0x3064
511 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
512 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
513 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
514 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
515 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
516 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
519 * TXRX_CSR10: BEACON alignment.
521 #define TXRX_CSR10 0x3068
524 * TXRX_CSR11: AES mask.
526 #define TXRX_CSR11 0x306c
529 * TXRX_CSR12: TSF low 32.
531 #define TXRX_CSR12 0x3070
532 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
535 * TXRX_CSR13: TSF high 32.
537 #define TXRX_CSR13 0x3074
538 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
541 * TXRX_CSR14: TBTT timer.
543 #define TXRX_CSR14 0x3078
546 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
548 #define TXRX_CSR15 0x307c
551 * PHY control registers.
552 * Some values are set in TU, whereas 1 TU == 1024 us.
556 * PHY_CSR0: RF/PS control.
558 #define PHY_CSR0 0x3080
559 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
560 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
565 #define PHY_CSR1 0x3084
568 * PHY_CSR2: Pre-TX BBP control.
570 #define PHY_CSR2 0x3088
573 * PHY_CSR3: BBP serial control register.
574 * VALUE: Register value to program into BBP.
575 * REG_NUM: Selected BBP register.
576 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
577 * BUSY: 1: ASIC is busy execute BBP programming.
579 #define PHY_CSR3 0x308c
580 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
581 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
582 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
583 #define PHY_CSR3_BUSY FIELD32(0x00010000)
586 * PHY_CSR4: RF serial control register
587 * VALUE: Register value (include register id) serial out to RF/IF chip.
588 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
589 * IF_SELECT: 1: select IF to program, 0: select RF to program.
590 * PLL_LD: RF PLL_LD status.
591 * BUSY: 1: ASIC is busy execute RF programming.
593 #define PHY_CSR4 0x3090
594 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
595 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
596 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
597 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
598 #define PHY_CSR4_BUSY FIELD32(0x80000000)
601 * PHY_CSR5: RX to TX signal switch timing control.
603 #define PHY_CSR5 0x3094
604 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
607 * PHY_CSR6: TX to RX signal timing control.
609 #define PHY_CSR6 0x3098
610 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
613 * PHY_CSR7: TX DAC switching timing control.
615 #define PHY_CSR7 0x309c
618 * Security control register.
622 * SEC_CSR0: Shared key table control.
624 #define SEC_CSR0 0x30a0
625 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
626 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
627 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
628 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
629 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
630 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
631 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
632 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
633 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
634 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
635 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
636 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
637 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
638 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
639 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
640 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
643 * SEC_CSR1: Shared key table security mode register.
645 #define SEC_CSR1 0x30a4
646 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
647 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
648 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
649 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
650 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
651 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
652 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
653 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
656 * Pairwise key table valid bitmap registers.
657 * SEC_CSR2: pairwise key table valid bitmap 0.
658 * SEC_CSR3: pairwise key table valid bitmap 1.
660 #define SEC_CSR2 0x30a8
661 #define SEC_CSR3 0x30ac
664 * SEC_CSR4: Pairwise key table lookup control.
666 #define SEC_CSR4 0x30b0
669 * SEC_CSR5: shared key table security mode register.
671 #define SEC_CSR5 0x30b4
672 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
673 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
674 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
675 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
676 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
677 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
678 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
679 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
682 * STA control registers.
686 * STA_CSR0: RX PLCP error count & RX FCS error count.
688 #define STA_CSR0 0x30c0
689 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
690 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
693 * STA_CSR1: RX False CCA count & RX LONG frame count.
695 #define STA_CSR1 0x30c4
696 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
697 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
700 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
702 #define STA_CSR2 0x30c8
703 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
704 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
707 * STA_CSR3: TX Beacon count.
709 #define STA_CSR3 0x30cc
710 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
713 * STA_CSR4: TX Result status register.
714 * VALID: 1:This register contains a valid TX result.
716 #define STA_CSR4 0x30d0
717 #define STA_CSR4_VALID FIELD32(0x00000001)
718 #define STA_CSR4_TX_RESULT FIELD32(0x0000000e)
719 #define STA_CSR4_RETRY_COUNT FIELD32(0x000000f0)
720 #define STA_CSR4_PID_SUBTYPE FIELD32(0x00001f00)
721 #define STA_CSR4_PID_TYPE FIELD32(0x0000e000)
722 #define STA_CSR4_TXRATE FIELD32(0x000f0000)
725 * QOS control registers.
729 * QOS_CSR0: TXOP holder MAC address register.
731 #define QOS_CSR0 0x30e0
732 #define QOS_CSR0_BYTE0 FIELD32(0x000000ff)
733 #define QOS_CSR0_BYTE1 FIELD32(0x0000ff00)
734 #define QOS_CSR0_BYTE2 FIELD32(0x00ff0000)
735 #define QOS_CSR0_BYTE3 FIELD32(0xff000000)
738 * QOS_CSR1: TXOP holder MAC address register.
740 #define QOS_CSR1 0x30e4
741 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
742 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
745 * QOS_CSR2: TXOP holder timeout register.
747 #define QOS_CSR2 0x30e8
750 * RX QOS-CFPOLL MAC address register.
751 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
752 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
754 #define QOS_CSR3 0x30ec
755 #define QOS_CSR4 0x30f0
758 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
760 #define QOS_CSR5 0x30f4
763 * Host DMA registers.
767 * AC0_BASE_CSR: AC_BK base address.
769 #define AC0_BASE_CSR 0x3400
770 #define AC0_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
773 * AC1_BASE_CSR: AC_BE base address.
775 #define AC1_BASE_CSR 0x3404
776 #define AC1_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
779 * AC2_BASE_CSR: AC_VI base address.
781 #define AC2_BASE_CSR 0x3408
782 #define AC2_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
785 * AC3_BASE_CSR: AC_VO base address.
787 #define AC3_BASE_CSR 0x340c
788 #define AC3_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
791 * MGMT_BASE_CSR: MGMT ring base address.
793 #define MGMT_BASE_CSR 0x3410
794 #define MGMT_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
797 * TX_RING_CSR0: TX Ring size for AC_BK, AC_BE, AC_VI, AC_VO.
799 #define TX_RING_CSR0 0x3418
800 #define TX_RING_CSR0_AC0_RING_SIZE FIELD32(0x000000ff)
801 #define TX_RING_CSR0_AC1_RING_SIZE FIELD32(0x0000ff00)
802 #define TX_RING_CSR0_AC2_RING_SIZE FIELD32(0x00ff0000)
803 #define TX_RING_CSR0_AC3_RING_SIZE FIELD32(0xff000000)
806 * TX_RING_CSR1: TX Ring size for MGMT Ring, HCCA Ring
807 * TXD_SIZE: In unit of 32-bit.
809 #define TX_RING_CSR1 0x341c
810 #define TX_RING_CSR1_MGMT_RING_SIZE FIELD32(0x000000ff)
811 #define TX_RING_CSR1_HCCA_RING_SIZE FIELD32(0x0000ff00)
812 #define TX_RING_CSR1_TXD_SIZE FIELD32(0x003f0000)
815 * AIFSN_CSR: AIFSN for each EDCA AC.
821 #define AIFSN_CSR 0x3420
822 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
823 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
824 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
825 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
828 * CWMIN_CSR: CWmin for each EDCA AC.
834 #define CWMIN_CSR 0x3424
835 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
836 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
837 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
838 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
841 * CWMAX_CSR: CWmax for each EDCA AC.
847 #define CWMAX_CSR 0x3428
848 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
849 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
850 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
851 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
854 * TX_DMA_DST_CSR: TX DMA destination
855 * 0: TX ring0, 1: TX ring1, 2: TX ring2 3: invalid
857 #define TX_DMA_DST_CSR 0x342c
858 #define TX_DMA_DST_CSR_DEST_AC0 FIELD32(0x00000003)
859 #define TX_DMA_DST_CSR_DEST_AC1 FIELD32(0x0000000c)
860 #define TX_DMA_DST_CSR_DEST_AC2 FIELD32(0x00000030)
861 #define TX_DMA_DST_CSR_DEST_AC3 FIELD32(0x000000c0)
862 #define TX_DMA_DST_CSR_DEST_MGMT FIELD32(0x00000300)
865 * TX_CNTL_CSR: KICK/Abort TX.
866 * KICK_TX_AC0: For AC_BK.
867 * KICK_TX_AC1: For AC_BE.
868 * KICK_TX_AC2: For AC_VI.
869 * KICK_TX_AC3: For AC_VO.
870 * ABORT_TX_AC0: For AC_BK.
871 * ABORT_TX_AC1: For AC_BE.
872 * ABORT_TX_AC2: For AC_VI.
873 * ABORT_TX_AC3: For AC_VO.
875 #define TX_CNTL_CSR 0x3430
876 #define TX_CNTL_CSR_KICK_TX_AC0 FIELD32(0x00000001)
877 #define TX_CNTL_CSR_KICK_TX_AC1 FIELD32(0x00000002)
878 #define TX_CNTL_CSR_KICK_TX_AC2 FIELD32(0x00000004)
879 #define TX_CNTL_CSR_KICK_TX_AC3 FIELD32(0x00000008)
880 #define TX_CNTL_CSR_KICK_TX_MGMT FIELD32(0x00000010)
881 #define TX_CNTL_CSR_ABORT_TX_AC0 FIELD32(0x00010000)
882 #define TX_CNTL_CSR_ABORT_TX_AC1 FIELD32(0x00020000)
883 #define TX_CNTL_CSR_ABORT_TX_AC2 FIELD32(0x00040000)
884 #define TX_CNTL_CSR_ABORT_TX_AC3 FIELD32(0x00080000)
885 #define TX_CNTL_CSR_ABORT_TX_MGMT FIELD32(0x00100000)
888 * LOAD_TX_RING_CSR: Load RX desriptor
890 #define LOAD_TX_RING_CSR 0x3434
891 #define LOAD_TX_RING_CSR_LOAD_TXD_AC0 FIELD32(0x00000001)
892 #define LOAD_TX_RING_CSR_LOAD_TXD_AC1 FIELD32(0x00000002)
893 #define LOAD_TX_RING_CSR_LOAD_TXD_AC2 FIELD32(0x00000004)
894 #define LOAD_TX_RING_CSR_LOAD_TXD_AC3 FIELD32(0x00000008)
895 #define LOAD_TX_RING_CSR_LOAD_TXD_MGMT FIELD32(0x00000010)
898 * Several read-only registers, for debugging.
900 #define AC0_TXPTR_CSR 0x3438
901 #define AC1_TXPTR_CSR 0x343c
902 #define AC2_TXPTR_CSR 0x3440
903 #define AC3_TXPTR_CSR 0x3444
904 #define MGMT_TXPTR_CSR 0x3448
909 #define RX_BASE_CSR 0x3450
910 #define RX_BASE_CSR_RING_REGISTER FIELD32(0xffffffff)
914 * RXD_SIZE: In unit of 32-bit.
916 #define RX_RING_CSR 0x3454
917 #define RX_RING_CSR_RING_SIZE FIELD32(0x000000ff)
918 #define RX_RING_CSR_RXD_SIZE FIELD32(0x00003f00)
919 #define RX_RING_CSR_RXD_WRITEBACK_SIZE FIELD32(0x00070000)
924 #define RX_CNTL_CSR 0x3458
925 #define RX_CNTL_CSR_ENABLE_RX_DMA FIELD32(0x00000001)
926 #define RX_CNTL_CSR_LOAD_RXD FIELD32(0x00000002)
929 * RXPTR_CSR: Read-only, for debugging.
931 #define RXPTR_CSR 0x345c
936 #define PCI_CFG_CSR 0x3460
941 #define BUF_FORMAT_CSR 0x3464
944 * INT_SOURCE_CSR: Interrupt source register.
945 * Write one to clear corresponding bit.
947 #define INT_SOURCE_CSR 0x3468
948 #define INT_SOURCE_CSR_TXDONE FIELD32(0x00000001)
949 #define INT_SOURCE_CSR_RXDONE FIELD32(0x00000002)
950 #define INT_SOURCE_CSR_BEACON_DONE FIELD32(0x00000004)
951 #define INT_SOURCE_CSR_TX_ABORT_DONE FIELD32(0x00000010)
952 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00010000)
953 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00020000)
954 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00040000)
955 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00080000)
956 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
957 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
960 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
961 * MITIGATION_PERIOD: Interrupt mitigation in unit of 32 PCI clock.
963 #define INT_MASK_CSR 0x346c
964 #define INT_MASK_CSR_TXDONE FIELD32(0x00000001)
965 #define INT_MASK_CSR_RXDONE FIELD32(0x00000002)
966 #define INT_MASK_CSR_BEACON_DONE FIELD32(0x00000004)
967 #define INT_MASK_CSR_TX_ABORT_DONE FIELD32(0x00000010)
968 #define INT_MASK_CSR_ENABLE_MITIGATION FIELD32(0x00000080)
969 #define INT_MASK_CSR_MITIGATION_PERIOD FIELD32(0x0000ff00)
970 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00010000)
971 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00020000)
972 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00040000)
973 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00080000)
974 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00100000)
975 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00200000)
978 * E2PROM_CSR: EEPROM control register.
979 * RELOAD: Write 1 to reload eeprom content.
980 * TYPE_93C46: 1: 93c46, 0:93c66.
981 * LOAD_STATUS: 1:loading, 0:done.
983 #define E2PROM_CSR 0x3470
984 #define E2PROM_CSR_RELOAD FIELD32(0x00000001)
985 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000002)
986 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000004)
987 #define E2PROM_CSR_DATA_IN FIELD32(0x00000008)
988 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000010)
989 #define E2PROM_CSR_TYPE_93C46 FIELD32(0x00000020)
990 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
993 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
994 * AC0_TX_OP: For AC_BK, in unit of 32us.
995 * AC1_TX_OP: For AC_BE, in unit of 32us.
997 #define AC_TXOP_CSR0 0x3474
998 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
999 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
1002 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
1003 * AC2_TX_OP: For AC_VI, in unit of 32us.
1004 * AC3_TX_OP: For AC_VO, in unit of 32us.
1006 #define AC_TXOP_CSR1 0x3478
1007 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
1008 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
1013 #define DMA_STATUS_CSR 0x3480
1018 #define TEST_MODE_CSR 0x3484
1023 #define UART0_TX_CSR 0x3488
1028 #define UART0_RX_CSR 0x348c
1033 #define UART0_FRAME_CSR 0x3490
1038 #define UART0_BUFFER_CSR 0x3494
1043 #define IO_CNTL_CSR 0x3498
1046 * UART_INT_SOURCE_CSR
1048 #define UART_INT_SOURCE_CSR 0x34a8
1053 #define UART_INT_MASK_CSR 0x34ac
1058 #define PBF_QUEUE_CSR 0x34b0
1061 * Firmware DMA registers.
1062 * Firmware DMA registers are dedicated for MCU usage
1063 * and should not be touched by host driver.
1064 * Therefore we skip the definition of these registers.
1066 #define FW_TX_BASE_CSR 0x34c0
1067 #define FW_TX_START_CSR 0x34c4
1068 #define FW_TX_LAST_CSR 0x34c8
1069 #define FW_MODE_CNTL_CSR 0x34cc
1070 #define FW_TXPTR_CSR 0x34d0
1073 * 8051 firmware image.
1075 #define FIRMWARE_RT2561 "rt2561.bin"
1076 #define FIRMWARE_RT2561s "rt2561s.bin"
1077 #define FIRMWARE_RT2661 "rt2661.bin"
1078 #define FIRMWARE_IMAGE_BASE 0x4000
1082 * The wordsize of the BBP is 8 bits.
1088 #define BBP_R2_BG_MODE FIELD8(0x20)
1093 #define BBP_R3_SMART_MODE FIELD8(0x01)
1096 * R4: RX antenna control
1097 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
1101 * ANTENNA_CONTROL semantics (guessed):
1102 * 0x1: Software controlled antenna switching (fixed or SW diversity)
1103 * 0x2: Hardware diversity.
1105 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
1106 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
1111 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
1120 #define RF3_TXPOWER FIELD32(0x00003e00)
1125 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
1129 * The wordsize of the EEPROM is 16 bits.
1135 #define EEPROM_MAC_ADDR_0 0x0002
1136 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1137 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1138 #define EEPROM_MAC_ADDR1 0x0003
1139 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1140 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1141 #define EEPROM_MAC_ADDR_2 0x0004
1142 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1143 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1147 * ANTENNA_NUM: Number of antenna's.
1148 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1149 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1150 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
1151 * DYN_TXAGC: Dynamic TX AGC control.
1152 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
1153 * RF_TYPE: Rf_type of this adapter.
1155 #define EEPROM_ANTENNA 0x0010
1156 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1157 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1158 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1159 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
1160 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1161 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1162 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1165 * EEPROM NIC config.
1166 * ENABLE_DIVERSITY: 1:enable, 0:disable.
1167 * EXTERNAL_LNA_BG: External LNA enable for 2.4G.
1168 * CARDBUS_ACCEL: 0:enable, 1:disable.
1169 * EXTERNAL_LNA_A: External LNA enable for 5G.
1171 #define EEPROM_NIC 0x0011
1172 #define EEPROM_NIC_ENABLE_DIVERSITY FIELD16(0x0001)
1173 #define EEPROM_NIC_TX_DIVERSITY FIELD16(0x0002)
1174 #define EEPROM_NIC_TX_RX_FIXED FIELD16(0x000c)
1175 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0010)
1176 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0020)
1177 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0040)
1181 * GEO_A: Default geographical setting for 5GHz band
1182 * GEO: Default geographical setting.
1184 #define EEPROM_GEOGRAPHY 0x0012
1185 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
1186 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
1191 #define EEPROM_BBP_START 0x0013
1192 #define EEPROM_BBP_SIZE 16
1193 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1194 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1197 * EEPROM TXPOWER 802.11G
1199 #define EEPROM_TXPOWER_G_START 0x0023
1200 #define EEPROM_TXPOWER_G_SIZE 7
1201 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
1202 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
1207 #define EEPROM_FREQ 0x002f
1208 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1209 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
1210 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
1214 * POLARITY_RDY_G: Polarity RDY_G setting.
1215 * POLARITY_RDY_A: Polarity RDY_A setting.
1216 * POLARITY_ACT: Polarity ACT setting.
1217 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1218 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1219 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1220 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1221 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1222 * LED_MODE: Led mode.
1224 #define EEPROM_LED 0x0030
1225 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
1226 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1227 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1228 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1229 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1230 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1231 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1232 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1233 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1236 * EEPROM TXPOWER 802.11A
1238 #define EEPROM_TXPOWER_A_START 0x0031
1239 #define EEPROM_TXPOWER_A_SIZE 12
1240 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1241 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1244 * EEPROM RSSI offset 802.11BG
1246 #define EEPROM_RSSI_OFFSET_BG 0x004d
1247 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
1248 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
1251 * EEPROM RSSI offset 802.11A
1253 #define EEPROM_RSSI_OFFSET_A 0x004e
1254 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
1255 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
1258 * MCU mailbox commands.
1260 #define MCU_SLEEP 0x30
1261 #define MCU_WAKEUP 0x31
1262 #define MCU_LED 0x50
1263 #define MCU_LED_STRENGTH 0x52
1266 * DMA descriptor defines.
1268 #define TXD_DESC_SIZE ( 16 * sizeof(__le32) )
1269 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
1270 #define RXD_DESC_SIZE ( 16 * sizeof(__le32) )
1273 * TX descriptor format for TX, PRIO and Beacon Ring.
1278 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
1279 * KEY_TABLE: Use per-client pairwise KEY table.
1281 * Key index (0~31) to the pairwise KEY table.
1282 * 0~3 to shared KEY table 0 (BSS0).
1283 * 4~7 to shared KEY table 1 (BSS1).
1284 * 8~11 to shared KEY table 2 (BSS2).
1285 * 12~15 to shared KEY table 3 (BSS3).
1286 * BURST: Next frame belongs to same "burst" event.
1288 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1289 #define TXD_W0_VALID FIELD32(0x00000002)
1290 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
1291 #define TXD_W0_ACK FIELD32(0x00000008)
1292 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
1293 #define TXD_W0_OFDM FIELD32(0x00000020)
1294 #define TXD_W0_IFS FIELD32(0x00000040)
1295 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
1296 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
1297 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
1298 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1299 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1300 #define TXD_W0_BURST FIELD32(0x10000000)
1301 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1305 * HOST_Q_ID: EDCA/HCCA queue ID.
1306 * HW_SEQUENCE: MAC overwrites the frame sequence number.
1307 * BUFFER_COUNT: Number of buffers in this TXD.
1309 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
1310 #define TXD_W1_AIFSN FIELD32(0x000000f0)
1311 #define TXD_W1_CWMIN FIELD32(0x00000f00)
1312 #define TXD_W1_CWMAX FIELD32(0x0000f000)
1313 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
1314 #define TXD_W1_PIGGY_BACK FIELD32(0x01000000)
1315 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
1316 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
1319 * Word2: PLCP information
1321 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
1322 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
1323 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1324 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1329 #define TXD_W3_IV FIELD32(0xffffffff)
1334 #define TXD_W4_EIV FIELD32(0xffffffff)
1338 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
1339 * TXD_W5_PID_SUBTYPE: Driver assigned packet ID index for txdone handler.
1340 * TXD_W5_PID_TYPE: Driver assigned packet ID type for txdone handler.
1341 * WAITING_DMA_DONE_INT: TXD been filled with data
1342 * and waiting for TxDoneISR housekeeping.
1344 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
1345 #define TXD_W5_PID_SUBTYPE FIELD32(0x00001f00)
1346 #define TXD_W5_PID_TYPE FIELD32(0x0000e000)
1347 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
1348 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
1351 * the above 24-byte is called TXINFO and will be DMAed to MAC block
1352 * through TXFIFO. MAC block use this TXINFO to control the transmission
1353 * behavior of this frame.
1354 * The following fields are not used by MAC block.
1355 * They are used by DMA block and HOST driver only.
1356 * Once a frame has been DMA to ASIC, all the following fields are useless
1361 * Word6-10: Buffer physical address
1363 #define TXD_W6_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1364 #define TXD_W7_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1365 #define TXD_W8_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1366 #define TXD_W9_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1367 #define TXD_W10_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1370 * Word11-13: Buffer length
1372 #define TXD_W11_BUFFER_LENGTH0 FIELD32(0x00000fff)
1373 #define TXD_W11_BUFFER_LENGTH1 FIELD32(0x0fff0000)
1374 #define TXD_W12_BUFFER_LENGTH2 FIELD32(0x00000fff)
1375 #define TXD_W12_BUFFER_LENGTH3 FIELD32(0x0fff0000)
1376 #define TXD_W13_BUFFER_LENGTH4 FIELD32(0x00000fff)
1381 #define TXD_W14_SK_BUFFER FIELD32(0xffffffff)
1386 #define TXD_W15_NEXT_SK_BUFFER FIELD32(0xffffffff)
1389 * RX descriptor format for RX Ring.
1394 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
1395 * KEY_INDEX: Decryption key actually used.
1397 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1398 #define RXD_W0_DROP FIELD32(0x00000002)
1399 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
1400 #define RXD_W0_MULTICAST FIELD32(0x00000008)
1401 #define RXD_W0_BROADCAST FIELD32(0x00000010)
1402 #define RXD_W0_MY_BSS FIELD32(0x00000020)
1403 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1404 #define RXD_W0_OFDM FIELD32(0x00000080)
1405 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1406 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1407 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1408 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1412 * SIGNAL: RX raw data rate reported by BBP.
1414 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1415 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1416 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1417 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1421 * IV: Received IV of originally encrypted.
1423 #define RXD_W2_IV FIELD32(0xffffffff)
1427 * EIV: Received EIV of originally encrypted.
1429 #define RXD_W3_EIV FIELD32(0xffffffff)
1434 #define RXD_W4_RESERVED FIELD32(0xffffffff)
1437 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1438 * and passed to the HOST driver.
1439 * The following fields are for DMA block and HOST usage only.
1440 * Can't be touched by ASIC MAC block.
1446 #define RXD_W5_BUFFER_PHYSICAL_ADDRESS FIELD32(0xffffffff)
1449 * Word6-15: Reserved
1451 #define RXD_W6_RESERVED FIELD32(0xffffffff)
1452 #define RXD_W7_RESERVED FIELD32(0xffffffff)
1453 #define RXD_W8_RESERVED FIELD32(0xffffffff)
1454 #define RXD_W9_RESERVED FIELD32(0xffffffff)
1455 #define RXD_W10_RESERVED FIELD32(0xffffffff)
1456 #define RXD_W11_RESERVED FIELD32(0xffffffff)
1457 #define RXD_W12_RESERVED FIELD32(0xffffffff)
1458 #define RXD_W13_RESERVED FIELD32(0xffffffff)
1459 #define RXD_W14_RESERVED FIELD32(0xffffffff)
1460 #define RXD_W15_RESERVED FIELD32(0xffffffff)
1463 * Macro's for converting txpower from EEPROM to mac80211 value
1464 * and from mac80211 value to register value.
1466 #define MIN_TXPOWER 0
1467 #define MAX_TXPOWER 31
1468 #define DEFAULT_TXPOWER 24
1470 #define TXPOWER_FROM_DEV(__txpower) \
1472 ((__txpower) > MAX_TXPOWER) ? \
1473 DEFAULT_TXPOWER : (__txpower); \
1476 #define TXPOWER_TO_DEV(__txpower) \
1478 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
1479 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
1483 #endif /* RT61PCI_H */