err.no Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Register access.
  42  * BBP and RF register require indirect register access,
  43  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  44  * These indirect registers work with busy bits,
  45  * and we will try maximal REGISTER_BUSY_COUNT times to access
  46  * the register while taking a REGISTER_BUSY_DELAY us delay
  47  * between each attampt. When the busy bit is still set at that time,
  48  * the access attempt is considered to have failed,
  49  * and we will print an error.
  50  */
  51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  52 {
  53         u32 reg;
  54         unsigned int i;
  55
  56         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  57                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  58                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  59                         break;
  60                 udelay(REGISTER_BUSY_DELAY);
  61         }
  62
  63         return reg;
  64 }
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         /*
  72          * Wait until the BBP becomes ready.
  73          */
  74         reg = rt61pci_bbp_check(rt2x00dev);
  75         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  76                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  77                 return;
  78         }
  79
  80         /*
  81          * Write the data into the BBP.
  82          */
  83         reg = 0;
  84         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  85         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  86         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  87         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  88
  89         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  90 }
  91
  92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  93                              const unsigned int word, u8 *value)
  94 {
  95         u32 reg;
  96
  97         /*
  98          * Wait until the BBP becomes ready.
  99          */
 100         reg = rt61pci_bbp_check(rt2x00dev);
 101         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 102                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 103                 return;
 104         }
 105
 106         /*
 107          * Write the request into the BBP.
 108          */
 109         reg = 0;
 110         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 111         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 112         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 113
 114         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 115
 116         /*
 117          * Wait until the BBP becomes ready.
 118          */
 119         reg = rt61pci_bbp_check(rt2x00dev);
 120         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 121                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 122                 *value = 0xff;
 123                 return;
 124         }
 125
 126         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 127 }
 128
 129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 130                              const unsigned int word, const u32 value)
 131 {
 132         u32 reg;
 133         unsigned int i;
 134
 135         if (!word)
 136                 return;
 137
 138         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 139                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
 140                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 141                         goto rf_write;
 142                 udelay(REGISTER_BUSY_DELAY);
 143         }
 144
 145         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 146         return;
 147
 148 rf_write:
 149         reg = 0;
 150         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 151         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 152         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 153         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 154
 155         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 156         rt2x00_rf_write(rt2x00dev, word, value);
 157 }
 158
 159 #ifdef CONFIG_RT61PCI_LEDS
 160 /*
 161  * This function is only called from rt61pci_led_brightness()
 162  * make gcc happy by placing this function inside the
 163  * same ifdef statement as the caller.
 164  */
 165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 166                                 const u8 command, const u8 token,
 167                                 const u8 arg0, const u8 arg1)
 168 {
 169         u32 reg;
 170
 171         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
 172
 173         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
 174                 ERROR(rt2x00dev, "mcu request error. "
 175                       "Request 0x%02x failed for token 0x%02x.\n",
 176                       command, token);
 177                 return;
 178         }
 179
 180         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 181         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 182         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 183         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 184         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 185
 186         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 187         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 188         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 189         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 190 }
 191 #endif /* CONFIG_RT61PCI_LEDS */
 192
 193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg;
 197
 198         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 199
 200         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 201         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 202         eeprom->reg_data_clock =
 203             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 204         eeprom->reg_chip_select =
 205             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 206 }
 207
 208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 209 {
 210         struct rt2x00_dev *rt2x00dev = eeprom->data;
 211         u32 reg = 0;
 212
 213         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 214         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 215         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 216                            !!eeprom->reg_data_clock);
 217         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 218                            !!eeprom->reg_chip_select);
 219
 220         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 221 }
 222
 223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 224 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 225
 226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
 227                              const unsigned int word, u32 *data)
 228 {
 229         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 230 }
 231
 232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
 233                               const unsigned int word, u32 data)
 234 {
 235         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 236 }
 237
 238 static const struct rt2x00debug rt61pci_rt2x00debug = {
 239         .owner  = THIS_MODULE,
 240         .csr    = {
 241                 .read           = rt61pci_read_csr,
 242                 .write          = rt61pci_write_csr,
 243                 .word_size      = sizeof(u32),
 244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 245         },
 246         .eeprom = {
 247                 .read           = rt2x00_eeprom_read,
 248                 .write          = rt2x00_eeprom_write,
 249                 .word_size      = sizeof(u16),
 250                 .word_count     = EEPROM_SIZE / sizeof(u16),
 251         },
 252         .bbp    = {
 253                 .read           = rt61pci_bbp_read,
 254                 .write          = rt61pci_bbp_write,
 255                 .word_size      = sizeof(u8),
 256                 .word_count     = BBP_SIZE / sizeof(u8),
 257         },
 258         .rf     = {
 259                 .read           = rt2x00_rf_read,
 260                 .write          = rt61pci_rf_write,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 #ifdef CONFIG_RT61PCI_RFKILL
 268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 269 {
 270         u32 reg;
 271
 272         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 273         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 274 }
 275 #else
 276 #define rt61pci_rfkill_poll     NULL
 277 #endif /* CONFIG_RT61PCI_RFKILL */
 278
 279 #ifdef CONFIG_RT61PCI_LEDS
 280 static void rt61pci_led_brightness(struct led_classdev *led_cdev,
 281                                    enum led_brightness brightness)
 282 {
 283         struct rt2x00_led *led =
 284             container_of(led_cdev, struct rt2x00_led, led_dev);
 285         unsigned int enabled = brightness != LED_OFF;
 286         unsigned int a_mode =
 287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 288         unsigned int bg_mode =
 289             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 290
 291         if (led->type == LED_TYPE_RADIO) {
 292                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 293                                    MCU_LEDCS_RADIO_STATUS, enabled);
 294
 295                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 296                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 297                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 298         } else if (led->type == LED_TYPE_ASSOC) {
 299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 300                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 302                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 303
 304                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 305                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 306                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 307         } else if (led->type == LED_TYPE_QUALITY) {
 308                 /*
 309                  * The brightness is divided into 6 levels (0 - 5),
 310                  * this means we need to convert the brightness
 311                  * argument into the matching level within that range.
 312                  */
 313                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 314                                     brightness / (LED_FULL / 6), 0);
 315         }
 316 }
 317 #else
 318 #define rt61pci_led_brightness  NULL
 319 #endif /* CONFIG_RT61PCI_LEDS */
 320
 321 /*
 322  * Configuration handlers.
 323  */
 324 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 325                                   const unsigned int filter_flags)
 326 {
 327         u32 reg;
 328
 329         /*
 330          * Start configuration steps.
 331          * Note that the version error will always be dropped
 332          * and broadcast frames will always be accepted since
 333          * there is no filter for it at this time.
 334          */
 335         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 336         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 337                            !(filter_flags & FIF_FCSFAIL));
 338         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 339                            !(filter_flags & FIF_PLCPFAIL));
 340         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 341                            !(filter_flags & FIF_CONTROL));
 342         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 343                            !(filter_flags & FIF_PROMISC_IN_BSS));
 344         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 345                            !(filter_flags & FIF_PROMISC_IN_BSS));
 346         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 347         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 348                            !(filter_flags & FIF_ALLMULTI));
 349         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 350         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 351                            !(filter_flags & FIF_CONTROL));
 352         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 353 }
 354
 355 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 356                                 struct rt2x00_intf *intf,
 357                                 struct rt2x00intf_conf *conf,
 358                                 const unsigned int flags)
 359 {
 360         unsigned int beacon_base;
 361         u32 reg;
 362
 363         if (flags & CONFIG_UPDATE_TYPE) {
 364                 /*
 365                  * Clear current synchronisation setup.
 366                  * For the Beacon base registers we only need to clear
 367                  * the first byte since that byte contains the VALID and OWNER
 368                  * bits which (when set to 0) will invalidate the entire beacon.
 369                  */
 370                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 371                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 372
 373                 /*
 374                  * Enable synchronisation.
 375                  */
 376                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 377                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 378                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 379                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 380                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 381         }
 382
 383         if (flags & CONFIG_UPDATE_MAC) {
 384                 reg = le32_to_cpu(conf->mac[1]);
 385                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 386                 conf->mac[1] = cpu_to_le32(reg);
 387
 388                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 389                                               conf->mac, sizeof(conf->mac));
 390         }
 391
 392         if (flags & CONFIG_UPDATE_BSSID) {
 393                 reg = le32_to_cpu(conf->bssid[1]);
 394                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 395                 conf->bssid[1] = cpu_to_le32(reg);
 396
 397                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 398                                               conf->bssid, sizeof(conf->bssid));
 399         }
 400 }
 401
 402 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 403                                struct rt2x00lib_erp *erp)
 404 {
 405         u32 reg;
 406
 407         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 408         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 409         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 410
 411         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 412         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 413                            !!erp->short_preamble);
 414         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 415 }
 416
 417 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 418                                    const int basic_rate_mask)
 419 {
 420         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 421 }
 422
 423 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 424                                    struct rf_channel *rf, const int txpower)
 425 {
 426         u8 r3;
 427         u8 r94;
 428         u8 smart;
 429
 430         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 431         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 432
 433         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 434                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 435
 436         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 437         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 438         rt61pci_bbp_write(rt2x00dev, 3, r3);
 439
 440         r94 = 6;
 441         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 442                 r94 += txpower - MAX_TXPOWER;
 443         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 444                 r94 += txpower;
 445         rt61pci_bbp_write(rt2x00dev, 94, r94);
 446
 447         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 448         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 449         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 450         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 451
 452         udelay(200);
 453
 454         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 455         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 456         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 457         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 458
 459         udelay(200);
 460
 461         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 462         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 463         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 464         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 465
 466         msleep(1);
 467 }
 468
 469 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 470                                    const int txpower)
 471 {
 472         struct rf_channel rf;
 473
 474         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 475         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 476         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 477         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 478
 479         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 480 }
 481
 482 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 483                                       struct antenna_setup *ant)
 484 {
 485         u8 r3;
 486         u8 r4;
 487         u8 r77;
 488
 489         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 490         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 491         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 492
 493         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 494                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 495
 496         /*
 497          * Configure the RX antenna.
 498          */
 499         switch (ant->rx) {
 500         case ANTENNA_HW_DIVERSITY:
 501                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 502                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 503                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 504                 break;
 505         case ANTENNA_A:
 506                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 507                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 508                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 509                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 510                 else
 511                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 512                 break;
 513         case ANTENNA_B:
 514         default:
 515                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 516                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 517                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 518                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 519                 else
 520                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 521                 break;
 522         }
 523
 524         rt61pci_bbp_write(rt2x00dev, 77, r77);
 525         rt61pci_bbp_write(rt2x00dev, 3, r3);
 526         rt61pci_bbp_write(rt2x00dev, 4, r4);
 527 }
 528
 529 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 530                                       struct antenna_setup *ant)
 531 {
 532         u8 r3;
 533         u8 r4;
 534         u8 r77;
 535
 536         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 537         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 538         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 539
 540         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 541                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 542         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 543                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 544
 545         /*
 546          * Configure the RX antenna.
 547          */
 548         switch (ant->rx) {
 549         case ANTENNA_HW_DIVERSITY:
 550                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 551                 break;
 552         case ANTENNA_A:
 553                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 554                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 555                 break;
 556         case ANTENNA_B:
 557         default:
 558                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 559                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 560                 break;
 561         }
 562
 563         rt61pci_bbp_write(rt2x00dev, 77, r77);
 564         rt61pci_bbp_write(rt2x00dev, 3, r3);
 565         rt61pci_bbp_write(rt2x00dev, 4, r4);
 566 }
 567
 568 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 569                                            const int p1, const int p2)
 570 {
 571         u32 reg;
 572
 573         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 574
 575         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 576         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 577
 578         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 579         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 580
 581         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 582 }
 583
 584 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 585                                         struct antenna_setup *ant)
 586 {
 587         u8 r3;
 588         u8 r4;
 589         u8 r77;
 590
 591         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 592         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 593         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 594
 595         /*
 596          * Configure the RX antenna.
 597          */
 598         switch (ant->rx) {
 599         case ANTENNA_A:
 600                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 601                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 602                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 603                 break;
 604         case ANTENNA_HW_DIVERSITY:
 605                 /*
 606                  * FIXME: Antenna selection for the rf 2529 is very confusing
 607                  * in the legacy driver. Just default to antenna B until the
 608                  * legacy code can be properly translated into rt2x00 code.
 609                  */
 610         case ANTENNA_B:
 611         default:
 612                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 613                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 614                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 615                 break;
 616         }
 617
 618         rt61pci_bbp_write(rt2x00dev, 77, r77);
 619         rt61pci_bbp_write(rt2x00dev, 3, r3);
 620         rt61pci_bbp_write(rt2x00dev, 4, r4);
 621 }
 622
 623 struct antenna_sel {
 624         u8 word;
 625         /*
 626          * value[0] -> non-LNA
 627          * value[1] -> LNA
 628          */
 629         u8 value[2];
 630 };
 631
 632 static const struct antenna_sel antenna_sel_a[] = {
 633         { 96,  { 0x58, 0x78 } },
 634         { 104, { 0x38, 0x48 } },
 635         { 75,  { 0xfe, 0x80 } },
 636         { 86,  { 0xfe, 0x80 } },
 637         { 88,  { 0xfe, 0x80 } },
 638         { 35,  { 0x60, 0x60 } },
 639         { 97,  { 0x58, 0x58 } },
 640         { 98,  { 0x58, 0x58 } },
 641 };
 642
 643 static const struct antenna_sel antenna_sel_bg[] = {
 644         { 96,  { 0x48, 0x68 } },
 645         { 104, { 0x2c, 0x3c } },
 646         { 75,  { 0xfe, 0x80 } },
 647         { 86,  { 0xfe, 0x80 } },
 648         { 88,  { 0xfe, 0x80 } },
 649         { 35,  { 0x50, 0x50 } },
 650         { 97,  { 0x48, 0x48 } },
 651         { 98,  { 0x48, 0x48 } },
 652 };
 653
 654 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 655                                    struct antenna_setup *ant)
 656 {
 657         const struct antenna_sel *sel;
 658         unsigned int lna;
 659         unsigned int i;
 660         u32 reg;
 661
 662         /*
 663          * We should never come here because rt2x00lib is supposed
 664          * to catch this and send us the correct antenna explicitely.
 665          */
 666         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 667                ant->tx == ANTENNA_SW_DIVERSITY);
 668
 669         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 670                 sel = antenna_sel_a;
 671                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 672         } else {
 673                 sel = antenna_sel_bg;
 674                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 675         }
 676
 677         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 678                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 679
 680         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 681
 682         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 683                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 684         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 685                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 686
 687         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 688
 689         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 690             rt2x00_rf(&rt2x00dev->chip, RF5325))
 691                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 692         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 693                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 694         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 695                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 696                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 697                 else
 698                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 699         }
 700 }
 701
 702 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 703                                     struct rt2x00lib_conf *libconf)
 704 {
 705         u32 reg;
 706
 707         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 708         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 709         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 710
 711         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 712         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 713         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 714         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 715         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 716
 717         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 718         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 719         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 720
 721         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 722         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 723         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 724
 725         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 726         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 727                            libconf->conf->beacon_int * 16);
 728         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 729 }
 730
 731 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 732                            struct rt2x00lib_conf *libconf,
 733                            const unsigned int flags)
 734 {
 735         if (flags & CONFIG_UPDATE_PHYMODE)
 736                 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
 737         if (flags & CONFIG_UPDATE_CHANNEL)
 738                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 739                                        libconf->conf->power_level);
 740         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 741                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 742         if (flags & CONFIG_UPDATE_ANTENNA)
 743                 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
 744         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 745                 rt61pci_config_duration(rt2x00dev, libconf);
 746 }
 747
 748 /*
 749  * Link tuning
 750  */
 751 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
 752                                struct link_qual *qual)
 753 {
 754         u32 reg;
 755
 756         /*
 757          * Update FCS error count from register.
 758          */
 759         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
 760         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 761
 762         /*
 763          * Update False CCA count from register.
 764          */
 765         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
 766         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 767 }
 768
 769 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 770 {
 771         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
 772         rt2x00dev->link.vgc_level = 0x20;
 773 }
 774
 775 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 776 {
 777         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 778         u8 r17;
 779         u8 up_bound;
 780         u8 low_bound;
 781
 782         rt61pci_bbp_read(rt2x00dev, 17, &r17);
 783
 784         /*
 785          * Determine r17 bounds.
 786          */
 787         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
 788                 low_bound = 0x28;
 789                 up_bound = 0x48;
 790                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
 791                         low_bound += 0x10;
 792                         up_bound += 0x10;
 793                 }
 794         } else {
 795                 low_bound = 0x20;
 796                 up_bound = 0x40;
 797                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 798                         low_bound += 0x10;
 799                         up_bound += 0x10;
 800                 }
 801         }
 802
 803         /*
 804          * If we are not associated, we should go straight to the
 805          * dynamic CCA tuning.
 806          */
 807         if (!rt2x00dev->intf_associated)
 808                 goto dynamic_cca_tune;
 809
 810         /*
 811          * Special big-R17 for very short distance
 812          */
 813         if (rssi >= -35) {
 814                 if (r17 != 0x60)
 815                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
 816                 return;
 817         }
 818
 819         /*
 820          * Special big-R17 for short distance
 821          */
 822         if (rssi >= -58) {
 823                 if (r17 != up_bound)
 824                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
 825                 return;
 826         }
 827
 828         /*
 829          * Special big-R17 for middle-short distance
 830          */
 831         if (rssi >= -66) {
 832                 low_bound += 0x10;
 833                 if (r17 != low_bound)
 834                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
 835                 return;
 836         }
 837
 838         /*
 839          * Special mid-R17 for middle distance
 840          */
 841         if (rssi >= -74) {
 842                 low_bound += 0x08;
 843                 if (r17 != low_bound)
 844                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
 845                 return;
 846         }
 847
 848         /*
 849          * Special case: Change up_bound based on the rssi.
 850          * Lower up_bound when rssi is weaker then -74 dBm.
 851          */
 852         up_bound -= 2 * (-74 - rssi);
 853         if (low_bound > up_bound)
 854                 up_bound = low_bound;
 855
 856         if (r17 > up_bound) {
 857                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
 858                 return;
 859         }
 860
 861 dynamic_cca_tune:
 862
 863         /*
 864          * r17 does not yet exceed upper limit, continue and base
 865          * the r17 tuning on the false CCA count.
 866          */
 867         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
 868                 if (++r17 > up_bound)
 869                         r17 = up_bound;
 870                 rt61pci_bbp_write(rt2x00dev, 17, r17);
 871         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
 872                 if (--r17 < low_bound)
 873                         r17 = low_bound;
 874                 rt61pci_bbp_write(rt2x00dev, 17, r17);
 875         }
 876 }
 877
 878 /*
 879  * Firmware functions
 880  */
 881 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 882 {
 883         char *fw_name;
 884
 885         switch (rt2x00dev->chip.rt) {
 886         case RT2561:
 887                 fw_name = FIRMWARE_RT2561;
 888                 break;
 889         case RT2561s:
 890                 fw_name = FIRMWARE_RT2561s;
 891                 break;
 892         case RT2661:
 893                 fw_name = FIRMWARE_RT2661;
 894                 break;
 895         default:
 896                 fw_name = NULL;
 897                 break;
 898         }
 899
 900         return fw_name;
 901 }
 902
 903 static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
 904 {
 905         u16 crc;
 906
 907         /*
 908          * Use the crc itu-t algorithm.
 909          * The last 2 bytes in the firmware array are the crc checksum itself,
 910          * this means that we should never pass those 2 bytes to the crc
 911          * algorithm.
 912          */
 913         crc = crc_itu_t(0, data, len - 2);
 914         crc = crc_itu_t_byte(crc, 0);
 915         crc = crc_itu_t_byte(crc, 0);
 916
 917         return crc;
 918 }
 919
 920 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
 921                                  const size_t len)
 922 {
 923         int i;
 924         u32 reg;
 925
 926         /*
 927          * Wait for stable hardware.
 928          */
 929         for (i = 0; i < 100; i++) {
 930                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
 931                 if (reg)
 932                         break;
 933                 msleep(1);
 934         }
 935
 936         if (!reg) {
 937                 ERROR(rt2x00dev, "Unstable hardware.\n");
 938                 return -EBUSY;
 939         }
 940
 941         /*
 942          * Prepare MCU and mailbox for firmware loading.
 943          */
 944         reg = 0;
 945         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
 946         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 947         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
 948         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 949         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
 950
 951         /*
 952          * Write firmware to device.
 953          */
 954         reg = 0;
 955         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
 956         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
 957         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 958
 959         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 960                                       data, len);
 961
 962         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
 963         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 964
 965         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
 966         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 967
 968         for (i = 0; i < 100; i++) {
 969                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
 970                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
 971                         break;
 972                 msleep(1);
 973         }
 974
 975         if (i == 100) {
 976                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
 977                 return -EBUSY;
 978         }
 979
 980         /*
 981          * Reset MAC and BBP registers.
 982          */
 983         reg = 0;
 984         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
 985         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
 986         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 987
 988         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
 989         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
 990         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
 991         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 992
 993         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
 994         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
 995         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 996
 997         return 0;
 998 }
 999
1000 /*
1001  * Initialization functions.
1002  */
1003 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1004                                  struct queue_entry *entry)
1005 {
1006         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1007         u32 word;
1008
1009         rt2x00_desc_read(priv_rx->desc, 5, &word);
1010         rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1011                            priv_rx->data_dma);
1012         rt2x00_desc_write(priv_rx->desc, 5, word);
1013
1014         rt2x00_desc_read(priv_rx->desc, 0, &word);
1015         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1016         rt2x00_desc_write(priv_rx->desc, 0, word);
1017 }
1018
1019 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1020                                  struct queue_entry *entry)
1021 {
1022         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
1023         u32 word;
1024
1025         rt2x00_desc_read(priv_tx->desc, 1, &word);
1026         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1027         rt2x00_desc_write(priv_tx->desc, 1, word);
1028
1029         rt2x00_desc_read(priv_tx->desc, 5, &word);
1030         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1031         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1032         rt2x00_desc_write(priv_tx->desc, 5, word);
1033
1034         rt2x00_desc_read(priv_tx->desc, 6, &word);
1035         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1036                            priv_tx->data_dma);
1037         rt2x00_desc_write(priv_tx->desc, 6, word);
1038
1039         rt2x00_desc_read(priv_tx->desc, 0, &word);
1040         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1041         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1042         rt2x00_desc_write(priv_tx->desc, 0, word);
1043 }
1044
1045 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1046 {
1047         struct queue_entry_priv_pci_rx *priv_rx;
1048         struct queue_entry_priv_pci_tx *priv_tx;
1049         u32 reg;
1050
1051         /*
1052          * Initialize registers.
1053          */
1054         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1055         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1056                            rt2x00dev->tx[0].limit);
1057         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1058                            rt2x00dev->tx[1].limit);
1059         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1060                            rt2x00dev->tx[2].limit);
1061         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1062                            rt2x00dev->tx[3].limit);
1063         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1064
1065         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1066         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1067                            rt2x00dev->tx[0].desc_size / 4);
1068         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1069
1070         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1071         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1072         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1073                            priv_tx->desc_dma);
1074         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1075
1076         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1077         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1078         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1079                            priv_tx->desc_dma);
1080         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1081
1082         priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1083         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1084         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1085                            priv_tx->desc_dma);
1086         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1087
1088         priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1089         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1090         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1091                            priv_tx->desc_dma);
1092         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1093
1094         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1095         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1096         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1097                            rt2x00dev->rx->desc_size / 4);
1098         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1099         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1100
1101         priv_rx = rt2x00dev->rx->entries[0].priv_data;
1102         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1103         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1104                            priv_rx->desc_dma);
1105         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1106
1107         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1108         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1109         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1110         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1111         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1112         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1113
1114         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1115         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1116         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1117         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1118         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1119         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1120
1121         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1122         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1123         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1124
1125         return 0;
1126 }
1127
1128 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1129 {
1130         u32 reg;
1131
1132         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1133         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1134         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1135         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1136         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1137
1138         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1139         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1140         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1141         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1142         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1143         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1144         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1145         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1146         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1147         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1148
1149         /*
1150          * CCK TXD BBP registers
1151          */
1152         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1153         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1154         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1155         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1156         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1157         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1158         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1159         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1160         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1161         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1162
1163         /*
1164          * OFDM TXD BBP registers
1165          */
1166         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1167         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1168         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1169         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1170         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1171         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1172         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1173         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1174
1175         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1176         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1177         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1178         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1179         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1180         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1181
1182         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1183         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1184         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1185         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1186         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1187         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1188
1189         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1190
1191         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1192
1193         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1194         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1195         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1196
1197         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1198
1199         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1200                 return -EBUSY;
1201
1202         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1203
1204         rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1205         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1206         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1207         rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1208
1209         /*
1210          * Invalidate all Shared Keys (SEC_CSR0),
1211          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1212          */
1213         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1214         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1215         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1216
1217         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1218         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1219         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1220         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1221
1222         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1223
1224         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1225
1226         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1227
1228         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1229         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1230         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1231         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1232
1233         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1234         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1235         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1236         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1237
1238         /*
1239          * Clear all beacons
1240          * For the Beacon base registers we only need to clear
1241          * the first byte since that byte contains the VALID and OWNER
1242          * bits which (when set to 0) will invalidate the entire beacon.
1243          */
1244         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1245         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1246         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1247         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1248
1249         /*
1250          * We must clear the error counters.
1251          * These registers are cleared on read,
1252          * so we may pass a useless variable to store the value.
1253          */
1254         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1255         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1256         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1257
1258         /*
1259          * Reset MAC and BBP registers.
1260          */
1261         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1262         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1263         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1264         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1265
1266         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1267         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1268         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1269         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1270
1271         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1272         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1273         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1274
1275         return 0;
1276 }
1277
1278 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1279 {
1280         unsigned int i;
1281         u16 eeprom;
1282         u8 reg_id;
1283         u8 value;
1284
1285         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1286                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1287                 if ((value != 0xff) && (value != 0x00))
1288                         goto continue_csr_init;
1289                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1290                 udelay(REGISTER_BUSY_DELAY);
1291         }
1292
1293         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1294         return -EACCES;
1295
1296 continue_csr_init:
1297         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1298         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1299         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1300         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1301         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1302         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1303         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1304         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1305         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1306         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1307         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1308         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1309         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1310         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1311         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1312         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1313         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1314         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1315         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1316         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1317         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1318         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1319         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1320         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1321
1322         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1323                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1324
1325                 if (eeprom != 0xffff && eeprom != 0x0000) {
1326                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1327                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1328                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1329                 }
1330         }
1331
1332         return 0;
1333 }
1334
1335 /*
1336  * Device state switch handlers.
1337  */
1338 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1339                               enum dev_state state)
1340 {
1341         u32 reg;
1342
1343         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1344         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1345                            state == STATE_RADIO_RX_OFF);
1346         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1347 }
1348
1349 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1350                                enum dev_state state)
1351 {
1352         int mask = (state == STATE_RADIO_IRQ_OFF);
1353         u32 reg;
1354
1355         /*
1356          * When interrupts are being enabled, the interrupt registers
1357          * should clear the register to assure a clean state.
1358          */
1359         if (state == STATE_RADIO_IRQ_ON) {
1360                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1361                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1362
1363                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1364                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1365         }
1366
1367         /*
1368          * Only toggle the interrupts bits we are going to use.
1369          * Non-checked interrupt bits are disabled by default.
1370          */
1371         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1372         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1373         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1374         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1375         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1376         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1377
1378         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1379         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1380         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1381         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1382         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1383         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1384         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1385         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1386         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1387         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1388 }
1389
1390 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1391 {
1392         u32 reg;
1393
1394         /*
1395          * Initialize all registers.
1396          */
1397         if (rt61pci_init_queues(rt2x00dev) ||
1398             rt61pci_init_registers(rt2x00dev) ||
1399             rt61pci_init_bbp(rt2x00dev)) {
1400                 ERROR(rt2x00dev, "Register initialization failed.\n");
1401                 return -EIO;
1402         }
1403
1404         /*
1405          * Enable interrupts.
1406          */
1407         rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1408
1409         /*
1410          * Enable RX.
1411          */
1412         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1413         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1414         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1415
1416         return 0;
1417 }
1418
1419 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1420 {
1421         u32 reg;
1422
1423         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1424
1425         /*
1426          * Disable synchronisation.
1427          */
1428         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1429
1430         /*
1431          * Cancel RX and TX.
1432          */
1433         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1434         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1435         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1436         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1437         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1438         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1439
1440         /*
1441          * Disable interrupts.
1442          */
1443         rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1444 }
1445
1446 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1447 {
1448         u32 reg;
1449         unsigned int i;
1450         char put_to_sleep;
1451         char current_state;
1452
1453         put_to_sleep = (state != STATE_AWAKE);
1454
1455         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1456         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1457         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1458         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1459
1460         /*
1461          * Device is not guaranteed to be in the requested state yet.
1462          * We must wait until the register indicates that the
1463          * device has entered the correct state.
1464          */
1465         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1466                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1467                 current_state =
1468                     rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1469                 if (current_state == !put_to_sleep)
1470                         return 0;
1471                 msleep(10);
1472         }
1473
1474         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1475                "current device state %d.\n", !put_to_sleep, current_state);
1476
1477         return -EBUSY;
1478 }
1479
1480 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1481                                     enum dev_state state)
1482 {
1483         int retval = 0;
1484
1485         switch (state) {
1486         case STATE_RADIO_ON:
1487                 retval = rt61pci_enable_radio(rt2x00dev);
1488                 break;
1489         case STATE_RADIO_OFF:
1490                 rt61pci_disable_radio(rt2x00dev);
1491                 break;
1492         case STATE_RADIO_RX_ON:
1493         case STATE_RADIO_RX_ON_LINK:
1494                 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1495                 break;
1496         case STATE_RADIO_RX_OFF:
1497         case STATE_RADIO_RX_OFF_LINK:
1498                 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1499                 break;
1500         case STATE_DEEP_SLEEP:
1501         case STATE_SLEEP:
1502         case STATE_STANDBY:
1503         case STATE_AWAKE:
1504                 retval = rt61pci_set_state(rt2x00dev, state);
1505                 break;
1506         default:
1507                 retval = -ENOTSUPP;
1508                 break;
1509         }
1510
1511         return retval;
1512 }
1513
1514 /*
1515  * TX descriptor initialization
1516  */
1517 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1518                                     struct sk_buff *skb,
1519                                     struct txentry_desc *txdesc,
1520                                     struct ieee80211_tx_control *control)
1521 {
1522         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1523         __le32 *txd = skbdesc->desc;
1524         u32 word;
1525
1526         /*
1527          * Start writing the descriptor words.
1528          */
1529         rt2x00_desc_read(txd, 1, &word);
1530         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1531         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1532         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1533         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1534         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1535         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1536         rt2x00_desc_write(txd, 1, word);
1537
1538         rt2x00_desc_read(txd, 2, &word);
1539         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1540         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1541         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1542         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1543         rt2x00_desc_write(txd, 2, word);
1544
1545         rt2x00_desc_read(txd, 5, &word);
1546         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1547                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1548         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1549         rt2x00_desc_write(txd, 5, word);
1550
1551         if (skbdesc->desc_len > TXINFO_SIZE) {
1552                 rt2x00_desc_read(txd, 11, &word);
1553                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1554                 rt2x00_desc_write(txd, 11, word);
1555         }
1556
1557         rt2x00_desc_read(txd, 0, &word);
1558         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1559         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1560         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1561                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1562         rt2x00_set_field32(&word, TXD_W0_ACK,
1563                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1564         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1565                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1566         rt2x00_set_field32(&word, TXD_W0_OFDM,
1567                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1568         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1569         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1570                            !!(control->flags &
1571                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1572         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1573         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1574         rt2x00_set_field32(&word, TXD_W0_BURST,
1575                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1576         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1577         rt2x00_desc_write(txd, 0, word);
1578 }
1579
1580 /*
1581  * TX data initialization
1582  */
1583 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1584                                   const unsigned int queue)
1585 {
1586         u32 reg;
1587
1588         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1589                 /*
1590                  * For Wi-Fi faily generated beacons between participating
1591                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1592                  */
1593                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1594
1595                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1596                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1597                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1598                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1599                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1600                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1601                 }
1602                 return;
1603         }
1604
1605         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1606         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1607                            (queue == IEEE80211_TX_QUEUE_DATA0));
1608         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1609                            (queue == IEEE80211_TX_QUEUE_DATA1));
1610         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1611                            (queue == IEEE80211_TX_QUEUE_DATA2));
1612         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1613                            (queue == IEEE80211_TX_QUEUE_DATA3));
1614         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1615 }
1616
1617 /*
1618  * RX control handlers
1619  */
1620 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1621 {
1622         u16 eeprom;
1623         u8 offset;
1624         u8 lna;
1625
1626         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1627         switch (lna) {
1628         case 3:
1629                 offset = 90;
1630                 break;
1631         case 2:
1632                 offset = 74;
1633                 break;
1634         case 1:
1635                 offset = 64;
1636                 break;
1637         default:
1638                 return 0;
1639         }
1640
1641         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1642                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1643                         offset += 14;
1644
1645                 if (lna == 3 || lna == 2)
1646                         offset += 10;
1647
1648                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1649                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1650         } else {
1651                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1652                         offset += 14;
1653
1654                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1655                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1656         }
1657
1658         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1659 }
1660
1661 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1662                                 struct rxdone_entry_desc *rxdesc)
1663 {
1664         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1665         u32 word0;
1666         u32 word1;
1667
1668         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1669         rt2x00_desc_read(priv_rx->desc, 1, &word1);
1670
1671         rxdesc->flags = 0;
1672         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1673                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1674
1675         /*
1676          * Obtain the status about this packet.
1677          * When frame was received with an OFDM bitrate,
1678          * the signal is the PLCP value. If it was received with
1679          * a CCK bitrate the signal is the rate in 100kbit/s.
1680          */
1681         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1682         rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1683         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1684
1685         rxdesc->dev_flags = 0;
1686         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1687                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1688         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1689                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1690 }
1691
1692 /*
1693  * Interrupt functions.
1694  */
1695 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1696 {
1697         struct data_queue *queue;
1698         struct queue_entry *entry;
1699         struct queue_entry *entry_done;
1700         struct queue_entry_priv_pci_tx *priv_tx;
1701         struct txdone_entry_desc txdesc;
1702         u32 word;
1703         u32 reg;
1704         u32 old_reg;
1705         int type;
1706         int index;
1707
1708         /*
1709          * During each loop we will compare the freshly read
1710          * STA_CSR4 register value with the value read from
1711          * the previous loop. If the 2 values are equal then
1712          * we should stop processing because the chance it
1713          * quite big that the device has been unplugged and
1714          * we risk going into an endless loop.
1715          */
1716         old_reg = 0;
1717
1718         while (1) {
1719                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1720                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1721                         break;
1722
1723                 if (old_reg == reg)
1724                         break;
1725                 old_reg = reg;
1726
1727                 /*
1728                  * Skip this entry when it contains an invalid
1729                  * queue identication number.
1730                  */
1731                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1732                 queue = rt2x00queue_get_queue(rt2x00dev, type);
1733                 if (unlikely(!queue))
1734                         continue;
1735
1736                 /*
1737                  * Skip this entry when it contains an invalid
1738                  * index number.
1739                  */
1740                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1741                 if (unlikely(index >= queue->limit))
1742                         continue;
1743
1744                 entry = &queue->entries[index];
1745                 priv_tx = entry->priv_data;
1746                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1747
1748                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1749                     !rt2x00_get_field32(word, TXD_W0_VALID))
1750                         return;
1751
1752                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1753                 while (entry != entry_done) {
1754                         /* Catch up.
1755                          * Just report any entries we missed as failed.
1756                          */
1757                         WARNING(rt2x00dev,
1758                                 "TX status report missed for entry %d\n",
1759                                 entry_done->entry_idx);
1760
1761                         txdesc.status = TX_FAIL_OTHER;
1762                         txdesc.retry = 0;
1763
1764                         rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1765                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1766                 }
1767
1768                 /*
1769                  * Obtain the status about this packet.
1770                  */
1771                 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1772                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1773
1774                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1775         }
1776 }
1777
1778 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1779 {
1780         struct rt2x00_dev *rt2x00dev = dev_instance;
1781         u32 reg_mcu;
1782         u32 reg;
1783
1784         /*
1785          * Get the interrupt sources & saved to local variable.
1786          * Write register value back to clear pending interrupts.
1787          */
1788         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1789         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1790
1791         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1792         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1793
1794         if (!reg && !reg_mcu)
1795                 return IRQ_NONE;
1796
1797         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1798                 return IRQ_HANDLED;
1799
1800         /*
1801          * Handle interrupts, walk through all bits
1802          * and run the tasks, the bits are checked in order of
1803          * priority.
1804          */
1805
1806         /*
1807          * 1 - Rx ring done interrupt.
1808          */
1809         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1810                 rt2x00pci_rxdone(rt2x00dev);
1811
1812         /*
1813          * 2 - Tx ring done interrupt.
1814          */
1815         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1816                 rt61pci_txdone(rt2x00dev);
1817
1818         /*
1819          * 3 - Handle MCU command done.
1820          */
1821         if (reg_mcu)
1822                 rt2x00pci_register_write(rt2x00dev,
1823                                          M2H_CMD_DONE_CSR, 0xffffffff);
1824
1825         return IRQ_HANDLED;
1826 }
1827
1828 /*
1829  * Device probe functions.
1830  */
1831 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1832 {
1833         struct eeprom_93cx6 eeprom;
1834         u32 reg;
1835         u16 word;
1836         u8 *mac;
1837         s8 value;
1838
1839         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1840
1841         eeprom.data = rt2x00dev;
1842         eeprom.register_read = rt61pci_eepromregister_read;
1843         eeprom.register_write = rt61pci_eepromregister_write;
1844         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1845             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1846         eeprom.reg_data_in = 0;
1847         eeprom.reg_data_out = 0;
1848         eeprom.reg_data_clock = 0;
1849         eeprom.reg_chip_select = 0;
1850
1851         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1852                                EEPROM_SIZE / sizeof(u16));
1853
1854         /*
1855          * Start validation of the data that has been read.
1856          */
1857         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1858         if (!is_valid_ether_addr(mac)) {
1859                 DECLARE_MAC_BUF(macbuf);
1860
1861                 random_ether_addr(mac);
1862                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1863         }
1864
1865         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1866         if (word == 0xffff) {
1867                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1868                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1869                                    ANTENNA_B);
1870                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1871                                    ANTENNA_B);
1872                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1873                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1874                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1875                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1876                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1877                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1878         }
1879
1880         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1881         if (word == 0xffff) {
1882                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1883                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1884                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1885                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1886                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1887                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1888                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1889                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1890         }
1891
1892         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1893         if (word == 0xffff) {
1894                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1895                                    LED_MODE_DEFAULT);
1896                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1897                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1898         }
1899
1900         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1901         if (word == 0xffff) {
1902                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1903                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1904                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1905                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1906         }
1907
1908         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1909         if (word == 0xffff) {
1910                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1911                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1912                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1913                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1914         } else {
1915                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1916                 if (value < -10 || value > 10)
1917                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1918                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1919                 if (value < -10 || value > 10)
1920                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1921                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1922         }
1923
1924         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1925         if (word == 0xffff) {
1926                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1927                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1928                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1929                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1930         } else {
1931                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1932                 if (value < -10 || value > 10)
1933                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1934                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1935                 if (value < -10 || value > 10)
1936                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1937                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1938         }
1939
1940         return 0;
1941 }
1942
1943 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1944 {
1945         u32 reg;
1946         u16 value;
1947         u16 eeprom;
1948         u16 device;
1949
1950         /*
1951          * Read EEPROM word for configuration.
1952          */
1953         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1954
1955         /*
1956          * Identify RF chipset.
1957          * To determine the RT chip we have to read the
1958          * PCI header of the device.
1959          */
1960         pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1961                              PCI_CONFIG_HEADER_DEVICE, &device);
1962         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1963         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1964         rt2x00_set_chip(rt2x00dev, device, value, reg);
1965
1966         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1967             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1968             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1969             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1970                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1971                 return -ENODEV;
1972         }
1973
1974         /*
1975          * Determine number of antenna's.
1976          */
1977         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1978                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1979
1980         /*
1981          * Identify default antenna configuration.
1982          */
1983         rt2x00dev->default_ant.tx =
1984             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1985         rt2x00dev->default_ant.rx =
1986             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1987
1988         /*
1989          * Read the Frame type.
1990          */
1991         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1992                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1993
1994         /*
1995          * Detect if this device has an hardware controlled radio.
1996          */
1997 #ifdef CONFIG_RT61PCI_RFKILL
1998         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1999                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2000 #endif /* CONFIG_RT61PCI_RFKILL */
2001
2002         /*
2003          * Read frequency offset and RF programming sequence.
2004          */
2005         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2006         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2007                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2008
2009         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2010
2011         /*
2012          * Read external LNA informations.
2013          */
2014         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2015
2016         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2017                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2018         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2019                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2020
2021         /*
2022          * When working with a RF2529 chip without double antenna
2023          * the antenna settings should be gathered from the NIC
2024          * eeprom word.
2025          */
2026         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2027             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2028                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2029                 case 0:
2030                         rt2x00dev->default_ant.tx = ANTENNA_B;
2031                         rt2x00dev->default_ant.rx = ANTENNA_A;
2032                         break;
2033                 case 1:
2034                         rt2x00dev->default_ant.tx = ANTENNA_B;
2035                         rt2x00dev->default_ant.rx = ANTENNA_B;
2036                         break;
2037                 case 2:
2038                         rt2x00dev->default_ant.tx = ANTENNA_A;
2039                         rt2x00dev->default_ant.rx = ANTENNA_A;
2040                         break;
2041                 case 3:
2042                         rt2x00dev->default_ant.tx = ANTENNA_A;
2043                         rt2x00dev->default_ant.rx = ANTENNA_B;
2044                         break;
2045                 }
2046
2047                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2048                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2049                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2050                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2051         }
2052
2053         /*
2054          * Store led settings, for correct led behaviour.
2055          * If the eeprom value is invalid,
2056          * switch to default led mode.
2057          */
2058 #ifdef CONFIG_RT61PCI_LEDS
2059         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2060
2061         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2062
2063         switch (value) {
2064         case LED_MODE_TXRX_ACTIVITY:
2065         case LED_MODE_ASUS:
2066         case LED_MODE_ALPHA:
2067         case LED_MODE_DEFAULT:
2068                 rt2x00dev->led_flags =
2069                     LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2070                 break;
2071         case LED_MODE_SIGNAL_STRENGTH:
2072                 rt2x00dev->led_flags =
2073                     LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2074                     LED_SUPPORT_QUALITY;
2075                 break;
2076         }
2077
2078         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2079         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2080                            rt2x00_get_field16(eeprom,
2081                                               EEPROM_LED_POLARITY_GPIO_0));
2082         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2083                            rt2x00_get_field16(eeprom,
2084                                               EEPROM_LED_POLARITY_GPIO_1));
2085         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2086                            rt2x00_get_field16(eeprom,
2087                                               EEPROM_LED_POLARITY_GPIO_2));
2088         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2089                            rt2x00_get_field16(eeprom,
2090                                               EEPROM_LED_POLARITY_GPIO_3));
2091         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2092                            rt2x00_get_field16(eeprom,
2093                                               EEPROM_LED_POLARITY_GPIO_4));
2094         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2095                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2096         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2097                            rt2x00_get_field16(eeprom,
2098                                               EEPROM_LED_POLARITY_RDY_G));
2099         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2100                            rt2x00_get_field16(eeprom,
2101                                               EEPROM_LED_POLARITY_RDY_A));
2102 #endif /* CONFIG_RT61PCI_LEDS */
2103
2104         return 0;
2105 }
2106
2107 /*
2108  * RF value list for RF5225 & RF5325
2109  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2110  */
2111 static const struct rf_channel rf_vals_noseq[] = {
2112         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2113         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2114         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2115         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2116         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2117         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2118         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2119         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2120         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2121         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2122         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2123         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2124         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2125         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2126
2127         /* 802.11 UNI / HyperLan 2 */
2128         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2129         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2130         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2131         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2132         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2133         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2134         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2135         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2136
2137         /* 802.11 HyperLan 2 */
2138         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2139         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2140         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2141         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2142         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2143         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2144         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2145         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2146         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2147         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2148
2149         /* 802.11 UNII */
2150         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2151         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2152         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2153         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2154         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2155         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2156
2157         /* MMAC(Japan)J52 ch 34,38,42,46 */
2158         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2159         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2160         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2161         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2162 };
2163
2164 /*
2165  * RF value list for RF5225 & RF5325
2166  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2167  */
2168 static const struct rf_channel rf_vals_seq[] = {
2169         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2170         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2171         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2172         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2173         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2174         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2175         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2176         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2177         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2178         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2179         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2180         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2181         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2182         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2183
2184         /* 802.11 UNI / HyperLan 2 */
2185         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2186         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2187         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2188         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2189         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2190         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2191         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2192         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2193
2194         /* 802.11 HyperLan 2 */
2195         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2196         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2197         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2198         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2199         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2200         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2201         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2202         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2203         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2204         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2205
2206         /* 802.11 UNII */
2207         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2208         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2209         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2210         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2211         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2212         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2213
2214         /* MMAC(Japan)J52 ch 34,38,42,46 */
2215         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2216         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2217         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2218         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2219 };
2220
2221 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2222 {
2223         struct hw_mode_spec *spec = &rt2x00dev->spec;
2224         u8 *txpower;
2225         unsigned int i;
2226
2227         /*
2228          * Initialize all hw fields.
2229          */
2230         rt2x00dev->hw->flags =
2231             IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2232             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2233         rt2x00dev->hw->extra_tx_headroom = 0;
2234         rt2x00dev->hw->max_signal = MAX_SIGNAL;
2235         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2236         rt2x00dev->hw->queues = 4;
2237
2238         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2239         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2240                                 rt2x00_eeprom_addr(rt2x00dev,
2241                                                    EEPROM_MAC_ADDR_0));
2242
2243         /*
2244          * Convert tx_power array in eeprom.
2245          */
2246         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2247         for (i = 0; i < 14; i++)
2248                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2249
2250         /*
2251          * Initialize hw_mode information.
2252          */
2253         spec->supported_bands = SUPPORT_BAND_2GHZ;
2254         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2255         spec->tx_power_a = NULL;
2256         spec->tx_power_bg = txpower;
2257         spec->tx_power_default = DEFAULT_TXPOWER;
2258
2259         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2260                 spec->num_channels = 14;
2261                 spec->channels = rf_vals_noseq;
2262         } else {
2263                 spec->num_channels = 14;
2264                 spec->channels = rf_vals_seq;
2265         }
2266
2267         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2268             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2269                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2270                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2271
2272                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2273                 for (i = 0; i < 14; i++)
2274                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2275
2276                 spec->tx_power_a = txpower;
2277         }
2278 }
2279
2280 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2281 {
2282         int retval;
2283
2284         /*
2285          * Allocate eeprom data.
2286          */
2287         retval = rt61pci_validate_eeprom(rt2x00dev);
2288         if (retval)
2289                 return retval;
2290
2291         retval = rt61pci_init_eeprom(rt2x00dev);
2292         if (retval)
2293                 return retval;
2294
2295         /*
2296          * Initialize hw specifications.
2297          */
2298         rt61pci_probe_hw_mode(rt2x00dev);
2299
2300         /*
2301          * This device requires firmware.
2302          */
2303         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2304
2305         /*
2306          * Set the rssi offset.
2307          */
2308         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2309
2310         return 0;
2311 }
2312
2313 /*
2314  * IEEE80211 stack callback functions.
2315  */
2316 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2317                                    u32 short_retry, u32 long_retry)
2318 {
2319         struct rt2x00_dev *rt2x00dev = hw->priv;
2320         u32 reg;
2321
2322         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2323         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2324         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2325         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2326
2327         return 0;
2328 }
2329
2330 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2331 {
2332         struct rt2x00_dev *rt2x00dev = hw->priv;
2333         u64 tsf;
2334         u32 reg;
2335
2336         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2337         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2338         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2339         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2340
2341         return tsf;
2342 }
2343
2344 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2345                           struct ieee80211_tx_control *control)
2346 {
2347         struct rt2x00_dev *rt2x00dev = hw->priv;
2348         struct rt2x00_intf *intf = vif_to_intf(control->vif);
2349         struct skb_frame_desc *skbdesc;
2350         unsigned int beacon_base;
2351         u32 reg;
2352
2353         if (unlikely(!intf->beacon))
2354                 return -ENOBUFS;
2355
2356         /*
2357          * We need to append the descriptor in front of the
2358          * beacon frame.
2359          */
2360         if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2361                 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2362                                      0, GFP_ATOMIC)) {
2363                         dev_kfree_skb(skb);
2364                         return -ENOMEM;
2365                 }
2366         }
2367
2368         /*
2369          * Add the descriptor in front of the skb.
2370          */
2371         skb_push(skb, intf->beacon->queue->desc_size);
2372         memset(skb->data, 0, intf->beacon->queue->desc_size);
2373
2374         /*
2375          * Fill in skb descriptor
2376          */
2377         skbdesc = get_skb_frame_desc(skb);
2378         memset(skbdesc, 0, sizeof(*skbdesc));
2379         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2380         skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2381         skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2382         skbdesc->desc = skb->data;
2383         skbdesc->desc_len = intf->beacon->queue->desc_size;
2384         skbdesc->entry = intf->beacon;
2385
2386         /*
2387          * Disable beaconing while we are reloading the beacon data,
2388          * otherwise we might be sending out invalid data.
2389          */
2390         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2391         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2392         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2393         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2394         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2395
2396         /*
2397          * mac80211 doesn't provide the control->queue variable
2398          * for beacons. Set our own queue identification so
2399          * it can be used during descriptor initialization.
2400          */
2401         control->queue = RT2X00_BCN_QUEUE_BEACON;
2402         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2403
2404         /*
2405          * Write entire beacon with descriptor to register,
2406          * and kick the beacon generator.
2407          */
2408         beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2409         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2410                                       skb->data, skb->len);
2411         rt61pci_kick_tx_queue(rt2x00dev, control->queue);
2412
2413         return 0;
2414 }
2415
2416 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2417         .tx                     = rt2x00mac_tx,
2418         .start                  = rt2x00mac_start,
2419         .stop                   = rt2x00mac_stop,
2420         .add_interface          = rt2x00mac_add_interface,
2421         .remove_interface       = rt2x00mac_remove_interface,
2422         .config                 = rt2x00mac_config,
2423         .config_interface       = rt2x00mac_config_interface,
2424         .configure_filter       = rt2x00mac_configure_filter,
2425         .get_stats              = rt2x00mac_get_stats,
2426         .set_retry_limit        = rt61pci_set_retry_limit,
2427         .bss_info_changed       = rt2x00mac_bss_info_changed,
2428         .conf_tx                = rt2x00mac_conf_tx,
2429         .get_tx_stats           = rt2x00mac_get_tx_stats,
2430         .get_tsf                = rt61pci_get_tsf,
2431         .beacon_update          = rt61pci_beacon_update,
2432 };
2433
2434 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2435         .irq_handler            = rt61pci_interrupt,
2436         .probe_hw               = rt61pci_probe_hw,
2437         .get_firmware_name      = rt61pci_get_firmware_name,
2438         .get_firmware_crc       = rt61pci_get_firmware_crc,
2439         .load_firmware          = rt61pci_load_firmware,
2440         .initialize             = rt2x00pci_initialize,
2441         .uninitialize           = rt2x00pci_uninitialize,
2442         .init_rxentry           = rt61pci_init_rxentry,
2443         .init_txentry           = rt61pci_init_txentry,
2444         .set_device_state       = rt61pci_set_device_state,
2445         .rfkill_poll            = rt61pci_rfkill_poll,
2446         .link_stats             = rt61pci_link_stats,
2447         .reset_tuner            = rt61pci_reset_tuner,
2448         .link_tuner             = rt61pci_link_tuner,
2449         .led_brightness         = rt61pci_led_brightness,
2450         .write_tx_desc          = rt61pci_write_tx_desc,
2451         .write_tx_data          = rt2x00pci_write_tx_data,
2452         .kick_tx_queue          = rt61pci_kick_tx_queue,
2453         .fill_rxdone            = rt61pci_fill_rxdone,
2454         .config_filter          = rt61pci_config_filter,
2455         .config_intf            = rt61pci_config_intf,
2456         .config_erp             = rt61pci_config_erp,
2457         .config                 = rt61pci_config,
2458 };
2459
2460 static const struct data_queue_desc rt61pci_queue_rx = {
2461         .entry_num              = RX_ENTRIES,
2462         .data_size              = DATA_FRAME_SIZE,
2463         .desc_size              = RXD_DESC_SIZE,
2464         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
2465 };
2466
2467 static const struct data_queue_desc rt61pci_queue_tx = {
2468         .entry_num              = TX_ENTRIES,
2469         .data_size              = DATA_FRAME_SIZE,
2470         .desc_size              = TXD_DESC_SIZE,
2471         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
2472 };
2473
2474 static const struct data_queue_desc rt61pci_queue_bcn = {
2475         .entry_num              = 4 * BEACON_ENTRIES,
2476         .data_size              = MGMT_FRAME_SIZE,
2477         .desc_size              = TXINFO_SIZE,
2478         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
2479 };
2480
2481 static const struct rt2x00_ops rt61pci_ops = {
2482         .name           = KBUILD_MODNAME,
2483         .max_sta_intf   = 1,
2484         .max_ap_intf    = 4,
2485         .eeprom_size    = EEPROM_SIZE,
2486         .rf_size        = RF_SIZE,
2487         .rx             = &rt61pci_queue_rx,
2488         .tx             = &rt61pci_queue_tx,
2489         .bcn            = &rt61pci_queue_bcn,
2490         .lib            = &rt61pci_rt2x00_ops,
2491         .hw             = &rt61pci_mac80211_ops,
2492 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2493         .debugfs        = &rt61pci_rt2x00debug,
2494 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2495 };
2496
2497 /*
2498  * RT61pci module information.
2499  */
2500 static struct pci_device_id rt61pci_device_table[] = {
2501         /* RT2561s */
2502         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2503         /* RT2561 v2 */
2504         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2505         /* RT2661 */
2506         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2507         { 0, }
2508 };
2509
2510 MODULE_AUTHOR(DRV_PROJECT);
2511 MODULE_VERSION(DRV_VERSION);
2512 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2513 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2514                         "PCI & PCMCIA chipset based cards");
2515 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2516 MODULE_FIRMWARE(FIRMWARE_RT2561);
2517 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2518 MODULE_FIRMWARE(FIRMWARE_RT2661);
2519 MODULE_LICENSE("GPL");
2520
2521 static struct pci_driver rt61pci_driver = {
2522         .name           = KBUILD_MODNAME,
2523         .id_table       = rt61pci_device_table,
2524         .probe          = rt2x00pci_probe,
2525         .remove         = __devexit_p(rt2x00pci_remove),
2526         .suspend        = rt2x00pci_suspend,
2527         .resume         = rt2x00pci_resume,
2528 };
2529
2530 static int __init rt61pci_init(void)
2531 {
2532         return pci_register_driver(&rt61pci_driver);
2533 }
2534
2535 static void __exit rt61pci_exit(void)
2536 {
2537         pci_unregister_driver(&rt61pci_driver);
2538 }
2539
2540 module_init(rt61pci_init);
2541 module_exit(rt61pci_exit);