err.no Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Register access.
  42  * BBP and RF register require indirect register access,
  43  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  44  * These indirect registers work with busy bits,
  45  * and we will try maximal REGISTER_BUSY_COUNT times to access
  46  * the register while taking a REGISTER_BUSY_DELAY us delay
  47  * between each attampt. When the busy bit is still set at that time,
  48  * the access attempt is considered to have failed,
  49  * and we will print an error.
  50  */
  51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  52 {
  53         u32 reg;
  54         unsigned int i;
  55
  56         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  57                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  58                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  59                         break;
  60                 udelay(REGISTER_BUSY_DELAY);
  61         }
  62
  63         return reg;
  64 }
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         /*
  72          * Wait until the BBP becomes ready.
  73          */
  74         reg = rt61pci_bbp_check(rt2x00dev);
  75         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  76                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  77                 return;
  78         }
  79
  80         /*
  81          * Write the data into the BBP.
  82          */
  83         reg = 0;
  84         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  85         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  86         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  87         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  88
  89         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  90 }
  91
  92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  93                              const unsigned int word, u8 *value)
  94 {
  95         u32 reg;
  96
  97         /*
  98          * Wait until the BBP becomes ready.
  99          */
 100         reg = rt61pci_bbp_check(rt2x00dev);
 101         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 102                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 103                 return;
 104         }
 105
 106         /*
 107          * Write the request into the BBP.
 108          */
 109         reg = 0;
 110         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 111         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 112         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 113
 114         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 115
 116         /*
 117          * Wait until the BBP becomes ready.
 118          */
 119         reg = rt61pci_bbp_check(rt2x00dev);
 120         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 121                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 122                 *value = 0xff;
 123                 return;
 124         }
 125
 126         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 127 }
 128
 129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 130                              const unsigned int word, const u32 value)
 131 {
 132         u32 reg;
 133         unsigned int i;
 134
 135         if (!word)
 136                 return;
 137
 138         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 139                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
 140                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 141                         goto rf_write;
 142                 udelay(REGISTER_BUSY_DELAY);
 143         }
 144
 145         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 146         return;
 147
 148 rf_write:
 149         reg = 0;
 150         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 151         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 152         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 153         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 154
 155         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 156         rt2x00_rf_write(rt2x00dev, word, value);
 157 }
 158
 159 #ifdef CONFIG_RT61PCI_LEDS
 160 /*
 161  * This function is only called from rt61pci_led_brightness()
 162  * make gcc happy by placing this function inside the
 163  * same ifdef statement as the caller.
 164  */
 165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 166                                 const u8 command, const u8 token,
 167                                 const u8 arg0, const u8 arg1)
 168 {
 169         u32 reg;
 170
 171         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
 172
 173         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
 174                 ERROR(rt2x00dev, "mcu request error. "
 175                       "Request 0x%02x failed for token 0x%02x.\n",
 176                       command, token);
 177                 return;
 178         }
 179
 180         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 181         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 182         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 183         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 184         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 185
 186         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 187         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 188         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 189         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 190 }
 191 #endif /* CONFIG_RT61PCI_LEDS */
 192
 193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg;
 197
 198         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 199
 200         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 201         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 202         eeprom->reg_data_clock =
 203             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 204         eeprom->reg_chip_select =
 205             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 206 }
 207
 208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 209 {
 210         struct rt2x00_dev *rt2x00dev = eeprom->data;
 211         u32 reg = 0;
 212
 213         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 214         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 215         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 216                            !!eeprom->reg_data_clock);
 217         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 218                            !!eeprom->reg_chip_select);
 219
 220         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 221 }
 222
 223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 224 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 225
 226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
 227                              const unsigned int word, u32 *data)
 228 {
 229         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 230 }
 231
 232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
 233                               const unsigned int word, u32 data)
 234 {
 235         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 236 }
 237
 238 static const struct rt2x00debug rt61pci_rt2x00debug = {
 239         .owner  = THIS_MODULE,
 240         .csr    = {
 241                 .read           = rt61pci_read_csr,
 242                 .write          = rt61pci_write_csr,
 243                 .word_size      = sizeof(u32),
 244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 245         },
 246         .eeprom = {
 247                 .read           = rt2x00_eeprom_read,
 248                 .write          = rt2x00_eeprom_write,
 249                 .word_size      = sizeof(u16),
 250                 .word_count     = EEPROM_SIZE / sizeof(u16),
 251         },
 252         .bbp    = {
 253                 .read           = rt61pci_bbp_read,
 254                 .write          = rt61pci_bbp_write,
 255                 .word_size      = sizeof(u8),
 256                 .word_count     = BBP_SIZE / sizeof(u8),
 257         },
 258         .rf     = {
 259                 .read           = rt2x00_rf_read,
 260                 .write          = rt61pci_rf_write,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 #ifdef CONFIG_RT61PCI_RFKILL
 268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 269 {
 270         u32 reg;
 271
 272         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 273         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 274 }
 275 #else
 276 #define rt61pci_rfkill_poll     NULL
 277 #endif /* CONFIG_RT61PCI_RFKILL */
 278
 279 #ifdef CONFIG_RT61PCI_LEDS
 280 static void rt61pci_led_brightness(struct led_classdev *led_cdev,
 281                                    enum led_brightness brightness)
 282 {
 283         struct rt2x00_led *led =
 284             container_of(led_cdev, struct rt2x00_led, led_dev);
 285         unsigned int enabled = brightness != LED_OFF;
 286         unsigned int a_mode =
 287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 288         unsigned int bg_mode =
 289             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 290
 291         if (led->type == LED_TYPE_RADIO) {
 292                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 293                                    MCU_LEDCS_RADIO_STATUS, enabled);
 294
 295                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 296                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 297                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 298         } else if (led->type == LED_TYPE_ASSOC) {
 299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 300                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 302                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 303
 304                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 305                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 306                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 307         } else if (led->type == LED_TYPE_QUALITY) {
 308                 /*
 309                  * The brightness is divided into 6 levels (0 - 5),
 310                  * this means we need to convert the brightness
 311                  * argument into the matching level within that range.
 312                  */
 313                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 314                                     brightness / (LED_FULL / 6), 0);
 315         }
 316 }
 317 #else
 318 #define rt61pci_led_brightness  NULL
 319 #endif /* CONFIG_RT61PCI_LEDS */
 320
 321 /*
 322  * Configuration handlers.
 323  */
 324 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 325                                   const unsigned int filter_flags)
 326 {
 327         u32 reg;
 328
 329         /*
 330          * Start configuration steps.
 331          * Note that the version error will always be dropped
 332          * and broadcast frames will always be accepted since
 333          * there is no filter for it at this time.
 334          */
 335         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 336         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 337                            !(filter_flags & FIF_FCSFAIL));
 338         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 339                            !(filter_flags & FIF_PLCPFAIL));
 340         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 341                            !(filter_flags & FIF_CONTROL));
 342         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 343                            !(filter_flags & FIF_PROMISC_IN_BSS));
 344         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 345                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 346                            !rt2x00dev->intf_ap_count);
 347         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 348         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 349                            !(filter_flags & FIF_ALLMULTI));
 350         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 351         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 352                            !(filter_flags & FIF_CONTROL));
 353         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 354 }
 355
 356 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 357                                 struct rt2x00_intf *intf,
 358                                 struct rt2x00intf_conf *conf,
 359                                 const unsigned int flags)
 360 {
 361         unsigned int beacon_base;
 362         u32 reg;
 363
 364         if (flags & CONFIG_UPDATE_TYPE) {
 365                 /*
 366                  * Clear current synchronisation setup.
 367                  * For the Beacon base registers we only need to clear
 368                  * the first byte since that byte contains the VALID and OWNER
 369                  * bits which (when set to 0) will invalidate the entire beacon.
 370                  */
 371                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 372                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 373
 374                 /*
 375                  * Enable synchronisation.
 376                  */
 377                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 378                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 379                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 380                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 381                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 382         }
 383
 384         if (flags & CONFIG_UPDATE_MAC) {
 385                 reg = le32_to_cpu(conf->mac[1]);
 386                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 387                 conf->mac[1] = cpu_to_le32(reg);
 388
 389                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 390                                               conf->mac, sizeof(conf->mac));
 391         }
 392
 393         if (flags & CONFIG_UPDATE_BSSID) {
 394                 reg = le32_to_cpu(conf->bssid[1]);
 395                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 396                 conf->bssid[1] = cpu_to_le32(reg);
 397
 398                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 399                                               conf->bssid, sizeof(conf->bssid));
 400         }
 401 }
 402
 403 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 404                                struct rt2x00lib_erp *erp)
 405 {
 406         u32 reg;
 407
 408         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 409         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 410         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 411
 412         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 413         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 414                            !!erp->short_preamble);
 415         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 416 }
 417
 418 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 419                                    const int basic_rate_mask)
 420 {
 421         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 422 }
 423
 424 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 425                                    struct rf_channel *rf, const int txpower)
 426 {
 427         u8 r3;
 428         u8 r94;
 429         u8 smart;
 430
 431         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 432         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 433
 434         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 435                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 436
 437         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 438         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 439         rt61pci_bbp_write(rt2x00dev, 3, r3);
 440
 441         r94 = 6;
 442         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 443                 r94 += txpower - MAX_TXPOWER;
 444         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 445                 r94 += txpower;
 446         rt61pci_bbp_write(rt2x00dev, 94, r94);
 447
 448         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 449         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 450         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 451         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 452
 453         udelay(200);
 454
 455         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 456         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 457         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 458         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 459
 460         udelay(200);
 461
 462         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 463         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 464         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 465         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 466
 467         msleep(1);
 468 }
 469
 470 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 471                                    const int txpower)
 472 {
 473         struct rf_channel rf;
 474
 475         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 476         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 477         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 478         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 479
 480         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 481 }
 482
 483 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 484                                       struct antenna_setup *ant)
 485 {
 486         u8 r3;
 487         u8 r4;
 488         u8 r77;
 489
 490         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 491         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 492         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 493
 494         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 495                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 496
 497         /*
 498          * Configure the RX antenna.
 499          */
 500         switch (ant->rx) {
 501         case ANTENNA_HW_DIVERSITY:
 502                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 503                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 504                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 505                 break;
 506         case ANTENNA_A:
 507                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 508                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 509                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 510                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 511                 else
 512                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 513                 break;
 514         case ANTENNA_B:
 515         default:
 516                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 517                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 518                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 519                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 520                 else
 521                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 522                 break;
 523         }
 524
 525         rt61pci_bbp_write(rt2x00dev, 77, r77);
 526         rt61pci_bbp_write(rt2x00dev, 3, r3);
 527         rt61pci_bbp_write(rt2x00dev, 4, r4);
 528 }
 529
 530 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 531                                       struct antenna_setup *ant)
 532 {
 533         u8 r3;
 534         u8 r4;
 535         u8 r77;
 536
 537         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 538         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 539         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 540
 541         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 542                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 543         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 544                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 545
 546         /*
 547          * Configure the RX antenna.
 548          */
 549         switch (ant->rx) {
 550         case ANTENNA_HW_DIVERSITY:
 551                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 552                 break;
 553         case ANTENNA_A:
 554                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 555                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 556                 break;
 557         case ANTENNA_B:
 558         default:
 559                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 560                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 561                 break;
 562         }
 563
 564         rt61pci_bbp_write(rt2x00dev, 77, r77);
 565         rt61pci_bbp_write(rt2x00dev, 3, r3);
 566         rt61pci_bbp_write(rt2x00dev, 4, r4);
 567 }
 568
 569 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 570                                            const int p1, const int p2)
 571 {
 572         u32 reg;
 573
 574         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 575
 576         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 577         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 578
 579         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 580         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 581
 582         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 583 }
 584
 585 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 586                                         struct antenna_setup *ant)
 587 {
 588         u8 r3;
 589         u8 r4;
 590         u8 r77;
 591
 592         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 593         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 594         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 595
 596         /*
 597          * Configure the RX antenna.
 598          */
 599         switch (ant->rx) {
 600         case ANTENNA_A:
 601                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 602                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 603                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 604                 break;
 605         case ANTENNA_HW_DIVERSITY:
 606                 /*
 607                  * FIXME: Antenna selection for the rf 2529 is very confusing
 608                  * in the legacy driver. Just default to antenna B until the
 609                  * legacy code can be properly translated into rt2x00 code.
 610                  */
 611         case ANTENNA_B:
 612         default:
 613                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 614                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 615                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 616                 break;
 617         }
 618
 619         rt61pci_bbp_write(rt2x00dev, 77, r77);
 620         rt61pci_bbp_write(rt2x00dev, 3, r3);
 621         rt61pci_bbp_write(rt2x00dev, 4, r4);
 622 }
 623
 624 struct antenna_sel {
 625         u8 word;
 626         /*
 627          * value[0] -> non-LNA
 628          * value[1] -> LNA
 629          */
 630         u8 value[2];
 631 };
 632
 633 static const struct antenna_sel antenna_sel_a[] = {
 634         { 96,  { 0x58, 0x78 } },
 635         { 104, { 0x38, 0x48 } },
 636         { 75,  { 0xfe, 0x80 } },
 637         { 86,  { 0xfe, 0x80 } },
 638         { 88,  { 0xfe, 0x80 } },
 639         { 35,  { 0x60, 0x60 } },
 640         { 97,  { 0x58, 0x58 } },
 641         { 98,  { 0x58, 0x58 } },
 642 };
 643
 644 static const struct antenna_sel antenna_sel_bg[] = {
 645         { 96,  { 0x48, 0x68 } },
 646         { 104, { 0x2c, 0x3c } },
 647         { 75,  { 0xfe, 0x80 } },
 648         { 86,  { 0xfe, 0x80 } },
 649         { 88,  { 0xfe, 0x80 } },
 650         { 35,  { 0x50, 0x50 } },
 651         { 97,  { 0x48, 0x48 } },
 652         { 98,  { 0x48, 0x48 } },
 653 };
 654
 655 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 656                                    struct antenna_setup *ant)
 657 {
 658         const struct antenna_sel *sel;
 659         unsigned int lna;
 660         unsigned int i;
 661         u32 reg;
 662
 663         /*
 664          * We should never come here because rt2x00lib is supposed
 665          * to catch this and send us the correct antenna explicitely.
 666          */
 667         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 668                ant->tx == ANTENNA_SW_DIVERSITY);
 669
 670         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 671                 sel = antenna_sel_a;
 672                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 673         } else {
 674                 sel = antenna_sel_bg;
 675                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 676         }
 677
 678         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 679                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 680
 681         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 682
 683         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 684                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 685         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 686                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 687
 688         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 689
 690         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 691             rt2x00_rf(&rt2x00dev->chip, RF5325))
 692                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 693         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 694                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 695         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 696                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 697                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 698                 else
 699                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 700         }
 701 }
 702
 703 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 704                                     struct rt2x00lib_conf *libconf)
 705 {
 706         u32 reg;
 707
 708         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 709         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 710         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 711
 712         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 713         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 714         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 715         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 716         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 717
 718         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 719         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 720         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 721
 722         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 723         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 724         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 725
 726         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 727         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 728                            libconf->conf->beacon_int * 16);
 729         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 730 }
 731
 732 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 733                            struct rt2x00lib_conf *libconf,
 734                            const unsigned int flags)
 735 {
 736         if (flags & CONFIG_UPDATE_PHYMODE)
 737                 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
 738         if (flags & CONFIG_UPDATE_CHANNEL)
 739                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 740                                        libconf->conf->power_level);
 741         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 742                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 743         if (flags & CONFIG_UPDATE_ANTENNA)
 744                 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
 745         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 746                 rt61pci_config_duration(rt2x00dev, libconf);
 747 }
 748
 749 /*
 750  * Link tuning
 751  */
 752 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
 753                                struct link_qual *qual)
 754 {
 755         u32 reg;
 756
 757         /*
 758          * Update FCS error count from register.
 759          */
 760         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
 761         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 762
 763         /*
 764          * Update False CCA count from register.
 765          */
 766         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
 767         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 768 }
 769
 770 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 771 {
 772         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
 773         rt2x00dev->link.vgc_level = 0x20;
 774 }
 775
 776 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 777 {
 778         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 779         u8 r17;
 780         u8 up_bound;
 781         u8 low_bound;
 782
 783         rt61pci_bbp_read(rt2x00dev, 17, &r17);
 784
 785         /*
 786          * Determine r17 bounds.
 787          */
 788         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
 789                 low_bound = 0x28;
 790                 up_bound = 0x48;
 791                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
 792                         low_bound += 0x10;
 793                         up_bound += 0x10;
 794                 }
 795         } else {
 796                 low_bound = 0x20;
 797                 up_bound = 0x40;
 798                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 799                         low_bound += 0x10;
 800                         up_bound += 0x10;
 801                 }
 802         }
 803
 804         /*
 805          * If we are not associated, we should go straight to the
 806          * dynamic CCA tuning.
 807          */
 808         if (!rt2x00dev->intf_associated)
 809                 goto dynamic_cca_tune;
 810
 811         /*
 812          * Special big-R17 for very short distance
 813          */
 814         if (rssi >= -35) {
 815                 if (r17 != 0x60)
 816                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
 817                 return;
 818         }
 819
 820         /*
 821          * Special big-R17 for short distance
 822          */
 823         if (rssi >= -58) {
 824                 if (r17 != up_bound)
 825                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
 826                 return;
 827         }
 828
 829         /*
 830          * Special big-R17 for middle-short distance
 831          */
 832         if (rssi >= -66) {
 833                 low_bound += 0x10;
 834                 if (r17 != low_bound)
 835                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
 836                 return;
 837         }
 838
 839         /*
 840          * Special mid-R17 for middle distance
 841          */
 842         if (rssi >= -74) {
 843                 low_bound += 0x08;
 844                 if (r17 != low_bound)
 845                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
 846                 return;
 847         }
 848
 849         /*
 850          * Special case: Change up_bound based on the rssi.
 851          * Lower up_bound when rssi is weaker then -74 dBm.
 852          */
 853         up_bound -= 2 * (-74 - rssi);
 854         if (low_bound > up_bound)
 855                 up_bound = low_bound;
 856
 857         if (r17 > up_bound) {
 858                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
 859                 return;
 860         }
 861
 862 dynamic_cca_tune:
 863
 864         /*
 865          * r17 does not yet exceed upper limit, continue and base
 866          * the r17 tuning on the false CCA count.
 867          */
 868         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
 869                 if (++r17 > up_bound)
 870                         r17 = up_bound;
 871                 rt61pci_bbp_write(rt2x00dev, 17, r17);
 872         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
 873                 if (--r17 < low_bound)
 874                         r17 = low_bound;
 875                 rt61pci_bbp_write(rt2x00dev, 17, r17);
 876         }
 877 }
 878
 879 /*
 880  * Firmware functions
 881  */
 882 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 883 {
 884         char *fw_name;
 885
 886         switch (rt2x00dev->chip.rt) {
 887         case RT2561:
 888                 fw_name = FIRMWARE_RT2561;
 889                 break;
 890         case RT2561s:
 891                 fw_name = FIRMWARE_RT2561s;
 892                 break;
 893         case RT2661:
 894                 fw_name = FIRMWARE_RT2661;
 895                 break;
 896         default:
 897                 fw_name = NULL;
 898                 break;
 899         }
 900
 901         return fw_name;
 902 }
 903
 904 static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
 905 {
 906         u16 crc;
 907
 908         /*
 909          * Use the crc itu-t algorithm.
 910          * The last 2 bytes in the firmware array are the crc checksum itself,
 911          * this means that we should never pass those 2 bytes to the crc
 912          * algorithm.
 913          */
 914         crc = crc_itu_t(0, data, len - 2);
 915         crc = crc_itu_t_byte(crc, 0);
 916         crc = crc_itu_t_byte(crc, 0);
 917
 918         return crc;
 919 }
 920
 921 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
 922                                  const size_t len)
 923 {
 924         int i;
 925         u32 reg;
 926
 927         /*
 928          * Wait for stable hardware.
 929          */
 930         for (i = 0; i < 100; i++) {
 931                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
 932                 if (reg)
 933                         break;
 934                 msleep(1);
 935         }
 936
 937         if (!reg) {
 938                 ERROR(rt2x00dev, "Unstable hardware.\n");
 939                 return -EBUSY;
 940         }
 941
 942         /*
 943          * Prepare MCU and mailbox for firmware loading.
 944          */
 945         reg = 0;
 946         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
 947         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 948         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
 949         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 950         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
 951
 952         /*
 953          * Write firmware to device.
 954          */
 955         reg = 0;
 956         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
 957         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
 958         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 959
 960         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 961                                       data, len);
 962
 963         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
 964         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 965
 966         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
 967         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 968
 969         for (i = 0; i < 100; i++) {
 970                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
 971                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
 972                         break;
 973                 msleep(1);
 974         }
 975
 976         if (i == 100) {
 977                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
 978                 return -EBUSY;
 979         }
 980
 981         /*
 982          * Reset MAC and BBP registers.
 983          */
 984         reg = 0;
 985         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
 986         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
 987         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 988
 989         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
 990         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
 991         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
 992         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 993
 994         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
 995         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
 996         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 997
 998         return 0;
 999 }
1000
1001 /*
1002  * Initialization functions.
1003  */
1004 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1005                                  struct queue_entry *entry)
1006 {
1007         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1008         u32 word;
1009
1010         rt2x00_desc_read(priv_rx->desc, 5, &word);
1011         rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1012                            priv_rx->data_dma);
1013         rt2x00_desc_write(priv_rx->desc, 5, word);
1014
1015         rt2x00_desc_read(priv_rx->desc, 0, &word);
1016         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1017         rt2x00_desc_write(priv_rx->desc, 0, word);
1018 }
1019
1020 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1021                                  struct queue_entry *entry)
1022 {
1023         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
1024         u32 word;
1025
1026         rt2x00_desc_read(priv_tx->desc, 1, &word);
1027         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1028         rt2x00_desc_write(priv_tx->desc, 1, word);
1029
1030         rt2x00_desc_read(priv_tx->desc, 5, &word);
1031         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1032         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1033         rt2x00_desc_write(priv_tx->desc, 5, word);
1034
1035         rt2x00_desc_read(priv_tx->desc, 6, &word);
1036         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1037                            priv_tx->data_dma);
1038         rt2x00_desc_write(priv_tx->desc, 6, word);
1039
1040         rt2x00_desc_read(priv_tx->desc, 0, &word);
1041         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1042         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1043         rt2x00_desc_write(priv_tx->desc, 0, word);
1044 }
1045
1046 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1047 {
1048         struct queue_entry_priv_pci_rx *priv_rx;
1049         struct queue_entry_priv_pci_tx *priv_tx;
1050         u32 reg;
1051
1052         /*
1053          * Initialize registers.
1054          */
1055         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1056         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1057                            rt2x00dev->tx[0].limit);
1058         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1059                            rt2x00dev->tx[1].limit);
1060         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1061                            rt2x00dev->tx[2].limit);
1062         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1063                            rt2x00dev->tx[3].limit);
1064         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1065
1066         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1067         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1068                            rt2x00dev->tx[0].desc_size / 4);
1069         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1070
1071         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1072         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1073         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1074                            priv_tx->desc_dma);
1075         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1076
1077         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1078         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1079         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1080                            priv_tx->desc_dma);
1081         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1082
1083         priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1084         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1085         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1086                            priv_tx->desc_dma);
1087         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1088
1089         priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1090         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1091         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1092                            priv_tx->desc_dma);
1093         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1094
1095         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1096         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1097         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1098                            rt2x00dev->rx->desc_size / 4);
1099         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1100         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1101
1102         priv_rx = rt2x00dev->rx->entries[0].priv_data;
1103         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1104         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1105                            priv_rx->desc_dma);
1106         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1107
1108         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1109         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1110         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1111         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1112         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1113         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1114
1115         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1116         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1117         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1118         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1119         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1120         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1121
1122         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1123         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1124         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1125
1126         return 0;
1127 }
1128
1129 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1130 {
1131         u32 reg;
1132
1133         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1134         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1135         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1136         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1137         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1138
1139         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1140         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1141         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1142         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1143         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1144         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1145         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1146         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1147         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1148         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1149
1150         /*
1151          * CCK TXD BBP registers
1152          */
1153         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1154         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1155         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1156         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1157         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1158         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1159         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1160         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1161         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1162         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1163
1164         /*
1165          * OFDM TXD BBP registers
1166          */
1167         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1168         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1169         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1170         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1171         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1172         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1173         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1174         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1175
1176         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1177         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1178         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1179         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1180         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1181         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1182
1183         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1184         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1185         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1186         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1187         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1188         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1189
1190         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1191
1192         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1193
1194         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1195         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1196         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1197
1198         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1199
1200         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1201                 return -EBUSY;
1202
1203         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1204
1205         rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1206         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1207         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1208         rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1209
1210         /*
1211          * Invalidate all Shared Keys (SEC_CSR0),
1212          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1213          */
1214         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1215         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1216         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1217
1218         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1219         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1220         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1221         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1222
1223         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1224
1225         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1226
1227         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1228
1229         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1230         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1231         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1232         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1233
1234         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1235         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1236         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1237         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1238
1239         /*
1240          * Clear all beacons
1241          * For the Beacon base registers we only need to clear
1242          * the first byte since that byte contains the VALID and OWNER
1243          * bits which (when set to 0) will invalidate the entire beacon.
1244          */
1245         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1246         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1247         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1248         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1249
1250         /*
1251          * We must clear the error counters.
1252          * These registers are cleared on read,
1253          * so we may pass a useless variable to store the value.
1254          */
1255         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1256         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1257         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1258
1259         /*
1260          * Reset MAC and BBP registers.
1261          */
1262         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1263         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1264         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1265         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1266
1267         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1268         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1269         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1270         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1271
1272         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1273         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1274         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1275
1276         return 0;
1277 }
1278
1279 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1280 {
1281         unsigned int i;
1282         u16 eeprom;
1283         u8 reg_id;
1284         u8 value;
1285
1286         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1287                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1288                 if ((value != 0xff) && (value != 0x00))
1289                         goto continue_csr_init;
1290                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1291                 udelay(REGISTER_BUSY_DELAY);
1292         }
1293
1294         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1295         return -EACCES;
1296
1297 continue_csr_init:
1298         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1299         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1300         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1301         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1302         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1303         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1304         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1305         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1306         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1307         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1308         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1309         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1310         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1311         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1312         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1313         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1314         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1315         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1316         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1317         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1318         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1319         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1320         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1321         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1322
1323         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1324                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1325
1326                 if (eeprom != 0xffff && eeprom != 0x0000) {
1327                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1328                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1329                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1330                 }
1331         }
1332
1333         return 0;
1334 }
1335
1336 /*
1337  * Device state switch handlers.
1338  */
1339 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1340                               enum dev_state state)
1341 {
1342         u32 reg;
1343
1344         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1345         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1346                            state == STATE_RADIO_RX_OFF);
1347         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1348 }
1349
1350 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1351                                enum dev_state state)
1352 {
1353         int mask = (state == STATE_RADIO_IRQ_OFF);
1354         u32 reg;
1355
1356         /*
1357          * When interrupts are being enabled, the interrupt registers
1358          * should clear the register to assure a clean state.
1359          */
1360         if (state == STATE_RADIO_IRQ_ON) {
1361                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1362                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1363
1364                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1365                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1366         }
1367
1368         /*
1369          * Only toggle the interrupts bits we are going to use.
1370          * Non-checked interrupt bits are disabled by default.
1371          */
1372         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1373         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1374         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1375         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1376         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1377         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1378
1379         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1380         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1381         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1382         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1383         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1384         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1385         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1386         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1387         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1388         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1389 }
1390
1391 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1392 {
1393         u32 reg;
1394
1395         /*
1396          * Initialize all registers.
1397          */
1398         if (rt61pci_init_queues(rt2x00dev) ||
1399             rt61pci_init_registers(rt2x00dev) ||
1400             rt61pci_init_bbp(rt2x00dev)) {
1401                 ERROR(rt2x00dev, "Register initialization failed.\n");
1402                 return -EIO;
1403         }
1404
1405         /*
1406          * Enable interrupts.
1407          */
1408         rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1409
1410         /*
1411          * Enable RX.
1412          */
1413         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1414         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1415         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1416
1417         return 0;
1418 }
1419
1420 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1421 {
1422         u32 reg;
1423
1424         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1425
1426         /*
1427          * Disable synchronisation.
1428          */
1429         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1430
1431         /*
1432          * Cancel RX and TX.
1433          */
1434         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1435         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1436         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1437         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1438         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1439         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1440
1441         /*
1442          * Disable interrupts.
1443          */
1444         rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1445 }
1446
1447 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1448 {
1449         u32 reg;
1450         unsigned int i;
1451         char put_to_sleep;
1452         char current_state;
1453
1454         put_to_sleep = (state != STATE_AWAKE);
1455
1456         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1457         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1458         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1459         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1460
1461         /*
1462          * Device is not guaranteed to be in the requested state yet.
1463          * We must wait until the register indicates that the
1464          * device has entered the correct state.
1465          */
1466         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1467                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1468                 current_state =
1469                     rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1470                 if (current_state == !put_to_sleep)
1471                         return 0;
1472                 msleep(10);
1473         }
1474
1475         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1476                "current device state %d.\n", !put_to_sleep, current_state);
1477
1478         return -EBUSY;
1479 }
1480
1481 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1482                                     enum dev_state state)
1483 {
1484         int retval = 0;
1485
1486         switch (state) {
1487         case STATE_RADIO_ON:
1488                 retval = rt61pci_enable_radio(rt2x00dev);
1489                 break;
1490         case STATE_RADIO_OFF:
1491                 rt61pci_disable_radio(rt2x00dev);
1492                 break;
1493         case STATE_RADIO_RX_ON:
1494         case STATE_RADIO_RX_ON_LINK:
1495                 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1496                 break;
1497         case STATE_RADIO_RX_OFF:
1498         case STATE_RADIO_RX_OFF_LINK:
1499                 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1500                 break;
1501         case STATE_DEEP_SLEEP:
1502         case STATE_SLEEP:
1503         case STATE_STANDBY:
1504         case STATE_AWAKE:
1505                 retval = rt61pci_set_state(rt2x00dev, state);
1506                 break;
1507         default:
1508                 retval = -ENOTSUPP;
1509                 break;
1510         }
1511
1512         return retval;
1513 }
1514
1515 /*
1516  * TX descriptor initialization
1517  */
1518 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1519                                     struct sk_buff *skb,
1520                                     struct txentry_desc *txdesc,
1521                                     struct ieee80211_tx_control *control)
1522 {
1523         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1524         __le32 *txd = skbdesc->desc;
1525         u32 word;
1526
1527         /*
1528          * Start writing the descriptor words.
1529          */
1530         rt2x00_desc_read(txd, 1, &word);
1531         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1532         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1533         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1534         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1535         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1536         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1537         rt2x00_desc_write(txd, 1, word);
1538
1539         rt2x00_desc_read(txd, 2, &word);
1540         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1541         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1542         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1543         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1544         rt2x00_desc_write(txd, 2, word);
1545
1546         rt2x00_desc_read(txd, 5, &word);
1547         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1548                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1549         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1550         rt2x00_desc_write(txd, 5, word);
1551
1552         if (skbdesc->desc_len > TXINFO_SIZE) {
1553                 rt2x00_desc_read(txd, 11, &word);
1554                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1555                 rt2x00_desc_write(txd, 11, word);
1556         }
1557
1558         rt2x00_desc_read(txd, 0, &word);
1559         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1560         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1561         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1562                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1563         rt2x00_set_field32(&word, TXD_W0_ACK,
1564                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1565         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1566                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1567         rt2x00_set_field32(&word, TXD_W0_OFDM,
1568                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1569         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1570         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1571                            !!(control->flags &
1572                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1573         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1574         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1575         rt2x00_set_field32(&word, TXD_W0_BURST,
1576                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1577         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1578         rt2x00_desc_write(txd, 0, word);
1579 }
1580
1581 /*
1582  * TX data initialization
1583  */
1584 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1585                                   const unsigned int queue)
1586 {
1587         u32 reg;
1588
1589         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1590                 /*
1591                  * For Wi-Fi faily generated beacons between participating
1592                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1593                  */
1594                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1595
1596                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1597                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1598                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1599                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1600                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1601                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1602                 }
1603                 return;
1604         }
1605
1606         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1607         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1608                            (queue == IEEE80211_TX_QUEUE_DATA0));
1609         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1610                            (queue == IEEE80211_TX_QUEUE_DATA1));
1611         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1612                            (queue == IEEE80211_TX_QUEUE_DATA2));
1613         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1614                            (queue == IEEE80211_TX_QUEUE_DATA3));
1615         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1616 }
1617
1618 /*
1619  * RX control handlers
1620  */
1621 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1622 {
1623         u16 eeprom;
1624         u8 offset;
1625         u8 lna;
1626
1627         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1628         switch (lna) {
1629         case 3:
1630                 offset = 90;
1631                 break;
1632         case 2:
1633                 offset = 74;
1634                 break;
1635         case 1:
1636                 offset = 64;
1637                 break;
1638         default:
1639                 return 0;
1640         }
1641
1642         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1643                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1644                         offset += 14;
1645
1646                 if (lna == 3 || lna == 2)
1647                         offset += 10;
1648
1649                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1650                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1651         } else {
1652                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1653                         offset += 14;
1654
1655                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1656                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1657         }
1658
1659         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1660 }
1661
1662 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1663                                 struct rxdone_entry_desc *rxdesc)
1664 {
1665         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1666         u32 word0;
1667         u32 word1;
1668
1669         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1670         rt2x00_desc_read(priv_rx->desc, 1, &word1);
1671
1672         rxdesc->flags = 0;
1673         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1674                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1675
1676         /*
1677          * Obtain the status about this packet.
1678          * When frame was received with an OFDM bitrate,
1679          * the signal is the PLCP value. If it was received with
1680          * a CCK bitrate the signal is the rate in 100kbit/s.
1681          */
1682         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1683         rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1684         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1685
1686         rxdesc->dev_flags = 0;
1687         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1688                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1689         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1690                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1691 }
1692
1693 /*
1694  * Interrupt functions.
1695  */
1696 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1697 {
1698         struct data_queue *queue;
1699         struct queue_entry *entry;
1700         struct queue_entry *entry_done;
1701         struct queue_entry_priv_pci_tx *priv_tx;
1702         struct txdone_entry_desc txdesc;
1703         u32 word;
1704         u32 reg;
1705         u32 old_reg;
1706         int type;
1707         int index;
1708
1709         /*
1710          * During each loop we will compare the freshly read
1711          * STA_CSR4 register value with the value read from
1712          * the previous loop. If the 2 values are equal then
1713          * we should stop processing because the chance it
1714          * quite big that the device has been unplugged and
1715          * we risk going into an endless loop.
1716          */
1717         old_reg = 0;
1718
1719         while (1) {
1720                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1721                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1722                         break;
1723
1724                 if (old_reg == reg)
1725                         break;
1726                 old_reg = reg;
1727
1728                 /*
1729                  * Skip this entry when it contains an invalid
1730                  * queue identication number.
1731                  */
1732                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1733                 queue = rt2x00queue_get_queue(rt2x00dev, type);
1734                 if (unlikely(!queue))
1735                         continue;
1736
1737                 /*
1738                  * Skip this entry when it contains an invalid
1739                  * index number.
1740                  */
1741                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1742                 if (unlikely(index >= queue->limit))
1743                         continue;
1744
1745                 entry = &queue->entries[index];
1746                 priv_tx = entry->priv_data;
1747                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1748
1749                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1750                     !rt2x00_get_field32(word, TXD_W0_VALID))
1751                         return;
1752
1753                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1754                 while (entry != entry_done) {
1755                         /* Catch up.
1756                          * Just report any entries we missed as failed.
1757                          */
1758                         WARNING(rt2x00dev,
1759                                 "TX status report missed for entry %d\n",
1760                                 entry_done->entry_idx);
1761
1762                         txdesc.status = TX_FAIL_OTHER;
1763                         txdesc.retry = 0;
1764
1765                         rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1766                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1767                 }
1768
1769                 /*
1770                  * Obtain the status about this packet.
1771                  */
1772                 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1773                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1774
1775                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1776         }
1777 }
1778
1779 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1780 {
1781         struct rt2x00_dev *rt2x00dev = dev_instance;
1782         u32 reg_mcu;
1783         u32 reg;
1784
1785         /*
1786          * Get the interrupt sources & saved to local variable.
1787          * Write register value back to clear pending interrupts.
1788          */
1789         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1790         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1791
1792         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1793         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1794
1795         if (!reg && !reg_mcu)
1796                 return IRQ_NONE;
1797
1798         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1799                 return IRQ_HANDLED;
1800
1801         /*
1802          * Handle interrupts, walk through all bits
1803          * and run the tasks, the bits are checked in order of
1804          * priority.
1805          */
1806
1807         /*
1808          * 1 - Rx ring done interrupt.
1809          */
1810         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1811                 rt2x00pci_rxdone(rt2x00dev);
1812
1813         /*
1814          * 2 - Tx ring done interrupt.
1815          */
1816         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1817                 rt61pci_txdone(rt2x00dev);
1818
1819         /*
1820          * 3 - Handle MCU command done.
1821          */
1822         if (reg_mcu)
1823                 rt2x00pci_register_write(rt2x00dev,
1824                                          M2H_CMD_DONE_CSR, 0xffffffff);
1825
1826         return IRQ_HANDLED;
1827 }
1828
1829 /*
1830  * Device probe functions.
1831  */
1832 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1833 {
1834         struct eeprom_93cx6 eeprom;
1835         u32 reg;
1836         u16 word;
1837         u8 *mac;
1838         s8 value;
1839
1840         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1841
1842         eeprom.data = rt2x00dev;
1843         eeprom.register_read = rt61pci_eepromregister_read;
1844         eeprom.register_write = rt61pci_eepromregister_write;
1845         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1846             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1847         eeprom.reg_data_in = 0;
1848         eeprom.reg_data_out = 0;
1849         eeprom.reg_data_clock = 0;
1850         eeprom.reg_chip_select = 0;
1851
1852         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1853                                EEPROM_SIZE / sizeof(u16));
1854
1855         /*
1856          * Start validation of the data that has been read.
1857          */
1858         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1859         if (!is_valid_ether_addr(mac)) {
1860                 DECLARE_MAC_BUF(macbuf);
1861
1862                 random_ether_addr(mac);
1863                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1864         }
1865
1866         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1867         if (word == 0xffff) {
1868                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1869                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1870                                    ANTENNA_B);
1871                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1872                                    ANTENNA_B);
1873                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1874                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1875                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1876                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1877                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1878                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1879         }
1880
1881         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1882         if (word == 0xffff) {
1883                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1884                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1885                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1886                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1887                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1888                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1889                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1890                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1891         }
1892
1893         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1894         if (word == 0xffff) {
1895                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1896                                    LED_MODE_DEFAULT);
1897                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1898                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1899         }
1900
1901         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1902         if (word == 0xffff) {
1903                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1904                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1905                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1906                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1907         }
1908
1909         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1910         if (word == 0xffff) {
1911                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1912                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1913                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1914                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1915         } else {
1916                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1917                 if (value < -10 || value > 10)
1918                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1919                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1920                 if (value < -10 || value > 10)
1921                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1922                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1923         }
1924
1925         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1926         if (word == 0xffff) {
1927                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1928                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1929                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1930                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1931         } else {
1932                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1933                 if (value < -10 || value > 10)
1934                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1935                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1936                 if (value < -10 || value > 10)
1937                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1938                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1939         }
1940
1941         return 0;
1942 }
1943
1944 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1945 {
1946         u32 reg;
1947         u16 value;
1948         u16 eeprom;
1949         u16 device;
1950
1951         /*
1952          * Read EEPROM word for configuration.
1953          */
1954         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1955
1956         /*
1957          * Identify RF chipset.
1958          * To determine the RT chip we have to read the
1959          * PCI header of the device.
1960          */
1961         pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1962                              PCI_CONFIG_HEADER_DEVICE, &device);
1963         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1964         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1965         rt2x00_set_chip(rt2x00dev, device, value, reg);
1966
1967         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1968             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1969             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1970             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1971                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1972                 return -ENODEV;
1973         }
1974
1975         /*
1976          * Determine number of antenna's.
1977          */
1978         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1979                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1980
1981         /*
1982          * Identify default antenna configuration.
1983          */
1984         rt2x00dev->default_ant.tx =
1985             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1986         rt2x00dev->default_ant.rx =
1987             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1988
1989         /*
1990          * Read the Frame type.
1991          */
1992         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1993                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1994
1995         /*
1996          * Detect if this device has an hardware controlled radio.
1997          */
1998 #ifdef CONFIG_RT61PCI_RFKILL
1999         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2000                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2001 #endif /* CONFIG_RT61PCI_RFKILL */
2002
2003         /*
2004          * Read frequency offset and RF programming sequence.
2005          */
2006         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2007         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2008                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2009
2010         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2011
2012         /*
2013          * Read external LNA informations.
2014          */
2015         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2016
2017         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2018                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2019         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2020                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2021
2022         /*
2023          * When working with a RF2529 chip without double antenna
2024          * the antenna settings should be gathered from the NIC
2025          * eeprom word.
2026          */
2027         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2028             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2029                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2030                 case 0:
2031                         rt2x00dev->default_ant.tx = ANTENNA_B;
2032                         rt2x00dev->default_ant.rx = ANTENNA_A;
2033                         break;
2034                 case 1:
2035                         rt2x00dev->default_ant.tx = ANTENNA_B;
2036                         rt2x00dev->default_ant.rx = ANTENNA_B;
2037                         break;
2038                 case 2:
2039                         rt2x00dev->default_ant.tx = ANTENNA_A;
2040                         rt2x00dev->default_ant.rx = ANTENNA_A;
2041                         break;
2042                 case 3:
2043                         rt2x00dev->default_ant.tx = ANTENNA_A;
2044                         rt2x00dev->default_ant.rx = ANTENNA_B;
2045                         break;
2046                 }
2047
2048                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2049                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2050                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2051                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2052         }
2053
2054         /*
2055          * Store led settings, for correct led behaviour.
2056          * If the eeprom value is invalid,
2057          * switch to default led mode.
2058          */
2059 #ifdef CONFIG_RT61PCI_LEDS
2060         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2061
2062         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2063
2064         switch (value) {
2065         case LED_MODE_TXRX_ACTIVITY:
2066         case LED_MODE_ASUS:
2067         case LED_MODE_ALPHA:
2068         case LED_MODE_DEFAULT:
2069                 rt2x00dev->led_flags =
2070                     LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2071                 break;
2072         case LED_MODE_SIGNAL_STRENGTH:
2073                 rt2x00dev->led_flags =
2074                     LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2075                     LED_SUPPORT_QUALITY;
2076                 break;
2077         }
2078
2079         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2080         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2081                            rt2x00_get_field16(eeprom,
2082                                               EEPROM_LED_POLARITY_GPIO_0));
2083         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2084                            rt2x00_get_field16(eeprom,
2085                                               EEPROM_LED_POLARITY_GPIO_1));
2086         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2087                            rt2x00_get_field16(eeprom,
2088                                               EEPROM_LED_POLARITY_GPIO_2));
2089         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2090                            rt2x00_get_field16(eeprom,
2091                                               EEPROM_LED_POLARITY_GPIO_3));
2092         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2093                            rt2x00_get_field16(eeprom,
2094                                               EEPROM_LED_POLARITY_GPIO_4));
2095         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2096                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2097         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2098                            rt2x00_get_field16(eeprom,
2099                                               EEPROM_LED_POLARITY_RDY_G));
2100         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2101                            rt2x00_get_field16(eeprom,
2102                                               EEPROM_LED_POLARITY_RDY_A));
2103 #endif /* CONFIG_RT61PCI_LEDS */
2104
2105         return 0;
2106 }
2107
2108 /*
2109  * RF value list for RF5225 & RF5325
2110  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2111  */
2112 static const struct rf_channel rf_vals_noseq[] = {
2113         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2114         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2115         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2116         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2117         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2118         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2119         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2120         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2121         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2122         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2123         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2124         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2125         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2126         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2127
2128         /* 802.11 UNI / HyperLan 2 */
2129         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2130         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2131         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2132         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2133         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2134         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2135         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2136         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2137
2138         /* 802.11 HyperLan 2 */
2139         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2140         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2141         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2142         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2143         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2144         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2145         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2146         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2147         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2148         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2149
2150         /* 802.11 UNII */
2151         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2152         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2153         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2154         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2155         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2156         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2157
2158         /* MMAC(Japan)J52 ch 34,38,42,46 */
2159         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2160         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2161         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2162         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2163 };
2164
2165 /*
2166  * RF value list for RF5225 & RF5325
2167  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2168  */
2169 static const struct rf_channel rf_vals_seq[] = {
2170         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2171         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2172         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2173         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2174         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2175         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2176         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2177         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2178         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2179         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2180         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2181         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2182         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2183         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2184
2185         /* 802.11 UNI / HyperLan 2 */
2186         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2187         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2188         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2189         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2190         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2191         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2192         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2193         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2194
2195         /* 802.11 HyperLan 2 */
2196         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2197         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2198         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2199         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2200         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2201         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2202         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2203         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2204         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2205         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2206
2207         /* 802.11 UNII */
2208         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2209         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2210         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2211         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2212         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2213         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2214
2215         /* MMAC(Japan)J52 ch 34,38,42,46 */
2216         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2217         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2218         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2219         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2220 };
2221
2222 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2223 {
2224         struct hw_mode_spec *spec = &rt2x00dev->spec;
2225         u8 *txpower;
2226         unsigned int i;
2227
2228         /*
2229          * Initialize all hw fields.
2230          */
2231         rt2x00dev->hw->flags =
2232             IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2233             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2234         rt2x00dev->hw->extra_tx_headroom = 0;
2235         rt2x00dev->hw->max_signal = MAX_SIGNAL;
2236         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2237         rt2x00dev->hw->queues = 4;
2238
2239         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2240         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2241                                 rt2x00_eeprom_addr(rt2x00dev,
2242                                                    EEPROM_MAC_ADDR_0));
2243
2244         /*
2245          * Convert tx_power array in eeprom.
2246          */
2247         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2248         for (i = 0; i < 14; i++)
2249                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2250
2251         /*
2252          * Initialize hw_mode information.
2253          */
2254         spec->supported_bands = SUPPORT_BAND_2GHZ;
2255         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2256         spec->tx_power_a = NULL;
2257         spec->tx_power_bg = txpower;
2258         spec->tx_power_default = DEFAULT_TXPOWER;
2259
2260         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2261                 spec->num_channels = 14;
2262                 spec->channels = rf_vals_noseq;
2263         } else {
2264                 spec->num_channels = 14;
2265                 spec->channels = rf_vals_seq;
2266         }
2267
2268         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2269             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2270                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2271                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2272
2273                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2274                 for (i = 0; i < 14; i++)
2275                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2276
2277                 spec->tx_power_a = txpower;
2278         }
2279 }
2280
2281 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2282 {
2283         int retval;
2284
2285         /*
2286          * Allocate eeprom data.
2287          */
2288         retval = rt61pci_validate_eeprom(rt2x00dev);
2289         if (retval)
2290                 return retval;
2291
2292         retval = rt61pci_init_eeprom(rt2x00dev);
2293         if (retval)
2294                 return retval;
2295
2296         /*
2297          * Initialize hw specifications.
2298          */
2299         rt61pci_probe_hw_mode(rt2x00dev);
2300
2301         /*
2302          * This device requires firmware.
2303          */
2304         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2305
2306         /*
2307          * Set the rssi offset.
2308          */
2309         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2310
2311         return 0;
2312 }
2313
2314 /*
2315  * IEEE80211 stack callback functions.
2316  */
2317 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2318                                    u32 short_retry, u32 long_retry)
2319 {
2320         struct rt2x00_dev *rt2x00dev = hw->priv;
2321         u32 reg;
2322
2323         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2324         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2325         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2326         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2327
2328         return 0;
2329 }
2330
2331 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2332 {
2333         struct rt2x00_dev *rt2x00dev = hw->priv;
2334         u64 tsf;
2335         u32 reg;
2336
2337         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2338         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2339         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2340         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2341
2342         return tsf;
2343 }
2344
2345 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2346                           struct ieee80211_tx_control *control)
2347 {
2348         struct rt2x00_dev *rt2x00dev = hw->priv;
2349         struct rt2x00_intf *intf = vif_to_intf(control->vif);
2350         struct skb_frame_desc *skbdesc;
2351         unsigned int beacon_base;
2352         u32 reg;
2353
2354         if (unlikely(!intf->beacon))
2355                 return -ENOBUFS;
2356
2357         /*
2358          * We need to append the descriptor in front of the
2359          * beacon frame.
2360          */
2361         if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2362                 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2363                                      0, GFP_ATOMIC)) {
2364                         dev_kfree_skb(skb);
2365                         return -ENOMEM;
2366                 }
2367         }
2368
2369         /*
2370          * Add the descriptor in front of the skb.
2371          */
2372         skb_push(skb, intf->beacon->queue->desc_size);
2373         memset(skb->data, 0, intf->beacon->queue->desc_size);
2374
2375         /*
2376          * Fill in skb descriptor
2377          */
2378         skbdesc = get_skb_frame_desc(skb);
2379         memset(skbdesc, 0, sizeof(*skbdesc));
2380         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2381         skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2382         skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2383         skbdesc->desc = skb->data;
2384         skbdesc->desc_len = intf->beacon->queue->desc_size;
2385         skbdesc->entry = intf->beacon;
2386
2387         /*
2388          * Disable beaconing while we are reloading the beacon data,
2389          * otherwise we might be sending out invalid data.
2390          */
2391         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2392         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2393         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2394         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2395         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2396
2397         /*
2398          * mac80211 doesn't provide the control->queue variable
2399          * for beacons. Set our own queue identification so
2400          * it can be used during descriptor initialization.
2401          */
2402         control->queue = RT2X00_BCN_QUEUE_BEACON;
2403         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2404
2405         /*
2406          * Write entire beacon with descriptor to register,
2407          * and kick the beacon generator.
2408          */
2409         beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2410         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2411                                       skb->data, skb->len);
2412         rt61pci_kick_tx_queue(rt2x00dev, control->queue);
2413
2414         return 0;
2415 }
2416
2417 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2418         .tx                     = rt2x00mac_tx,
2419         .start                  = rt2x00mac_start,
2420         .stop                   = rt2x00mac_stop,
2421         .add_interface          = rt2x00mac_add_interface,
2422         .remove_interface       = rt2x00mac_remove_interface,
2423         .config                 = rt2x00mac_config,
2424         .config_interface       = rt2x00mac_config_interface,
2425         .configure_filter       = rt2x00mac_configure_filter,
2426         .get_stats              = rt2x00mac_get_stats,
2427         .set_retry_limit        = rt61pci_set_retry_limit,
2428         .bss_info_changed       = rt2x00mac_bss_info_changed,
2429         .conf_tx                = rt2x00mac_conf_tx,
2430         .get_tx_stats           = rt2x00mac_get_tx_stats,
2431         .get_tsf                = rt61pci_get_tsf,
2432         .beacon_update          = rt61pci_beacon_update,
2433 };
2434
2435 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2436         .irq_handler            = rt61pci_interrupt,
2437         .probe_hw               = rt61pci_probe_hw,
2438         .get_firmware_name      = rt61pci_get_firmware_name,
2439         .get_firmware_crc       = rt61pci_get_firmware_crc,
2440         .load_firmware          = rt61pci_load_firmware,
2441         .initialize             = rt2x00pci_initialize,
2442         .uninitialize           = rt2x00pci_uninitialize,
2443         .init_rxentry           = rt61pci_init_rxentry,
2444         .init_txentry           = rt61pci_init_txentry,
2445         .set_device_state       = rt61pci_set_device_state,
2446         .rfkill_poll            = rt61pci_rfkill_poll,
2447         .link_stats             = rt61pci_link_stats,
2448         .reset_tuner            = rt61pci_reset_tuner,
2449         .link_tuner             = rt61pci_link_tuner,
2450         .led_brightness         = rt61pci_led_brightness,
2451         .write_tx_desc          = rt61pci_write_tx_desc,
2452         .write_tx_data          = rt2x00pci_write_tx_data,
2453         .kick_tx_queue          = rt61pci_kick_tx_queue,
2454         .fill_rxdone            = rt61pci_fill_rxdone,
2455         .config_filter          = rt61pci_config_filter,
2456         .config_intf            = rt61pci_config_intf,
2457         .config_erp             = rt61pci_config_erp,
2458         .config                 = rt61pci_config,
2459 };
2460
2461 static const struct data_queue_desc rt61pci_queue_rx = {
2462         .entry_num              = RX_ENTRIES,
2463         .data_size              = DATA_FRAME_SIZE,
2464         .desc_size              = RXD_DESC_SIZE,
2465         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
2466 };
2467
2468 static const struct data_queue_desc rt61pci_queue_tx = {
2469         .entry_num              = TX_ENTRIES,
2470         .data_size              = DATA_FRAME_SIZE,
2471         .desc_size              = TXD_DESC_SIZE,
2472         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
2473 };
2474
2475 static const struct data_queue_desc rt61pci_queue_bcn = {
2476         .entry_num              = 4 * BEACON_ENTRIES,
2477         .data_size              = MGMT_FRAME_SIZE,
2478         .desc_size              = TXINFO_SIZE,
2479         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
2480 };
2481
2482 static const struct rt2x00_ops rt61pci_ops = {
2483         .name           = KBUILD_MODNAME,
2484         .max_sta_intf   = 1,
2485         .max_ap_intf    = 4,
2486         .eeprom_size    = EEPROM_SIZE,
2487         .rf_size        = RF_SIZE,
2488         .rx             = &rt61pci_queue_rx,
2489         .tx             = &rt61pci_queue_tx,
2490         .bcn            = &rt61pci_queue_bcn,
2491         .lib            = &rt61pci_rt2x00_ops,
2492         .hw             = &rt61pci_mac80211_ops,
2493 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2494         .debugfs        = &rt61pci_rt2x00debug,
2495 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2496 };
2497
2498 /*
2499  * RT61pci module information.
2500  */
2501 static struct pci_device_id rt61pci_device_table[] = {
2502         /* RT2561s */
2503         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2504         /* RT2561 v2 */
2505         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2506         /* RT2661 */
2507         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2508         { 0, }
2509 };
2510
2511 MODULE_AUTHOR(DRV_PROJECT);
2512 MODULE_VERSION(DRV_VERSION);
2513 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2514 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2515                         "PCI & PCMCIA chipset based cards");
2516 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2517 MODULE_FIRMWARE(FIRMWARE_RT2561);
2518 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2519 MODULE_FIRMWARE(FIRMWARE_RT2661);
2520 MODULE_LICENSE("GPL");
2521
2522 static struct pci_driver rt61pci_driver = {
2523         .name           = KBUILD_MODNAME,
2524         .id_table       = rt61pci_device_table,
2525         .probe          = rt2x00pci_probe,
2526         .remove         = __devexit_p(rt2x00pci_remove),
2527         .suspend        = rt2x00pci_suspend,
2528         .resume         = rt2x00pci_resume,
2529 };
2530
2531 static int __init rt61pci_init(void)
2532 {
2533         return pci_register_driver(&rt61pci_driver);
2534 }
2535
2536 static void __exit rt61pci_exit(void)
2537 {
2538         pci_unregister_driver(&rt61pci_driver);
2539 }
2540
2541 module_init(rt61pci_init);
2542 module_exit(rt61pci_exit);