2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
28 * Set enviroment defines for rt2x00.h
30 #define DRV_NAME "rt61pci"
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
41 #include "rt2x00pci.h"
46 * BBP and RF register require indirect register access,
47 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
48 * These indirect registers work with busy bits,
49 * and we will try maximal REGISTER_BUSY_COUNT times to access
50 * the register while taking a REGISTER_BUSY_DELAY us delay
51 * between each attampt. When the busy bit is still set at that time,
52 * the access attempt is considered to have failed,
53 * and we will print an error.
55 static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
60 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
61 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
62 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
64 udelay(REGISTER_BUSY_DELAY);
70 static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
76 * Wait until the BBP becomes ready.
78 reg = rt61pci_bbp_check(rt2x00dev);
79 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
80 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
85 * Write the data into the BBP.
88 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
89 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
90 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
91 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
93 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
96 static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
97 const unsigned int word, u8 *value)
102 * Wait until the BBP becomes ready.
104 reg = rt61pci_bbp_check(rt2x00dev);
105 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
106 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
111 * Write the request into the BBP.
114 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
115 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
116 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
118 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
121 * Wait until the BBP becomes ready.
123 reg = rt61pci_bbp_check(rt2x00dev);
124 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
125 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
130 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
133 static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u32 value)
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
143 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
144 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
146 udelay(REGISTER_BUSY_DELAY);
149 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
154 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
155 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
156 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
157 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
159 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
160 rt2x00_rf_write(rt2x00dev, word, value);
163 static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token,
165 const u8 arg0, const u8 arg1)
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
178 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
185 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
199 eeprom->reg_data_clock =
200 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
201 eeprom->reg_chip_select =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
205 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
207 struct rt2x00_dev *rt2x00dev = eeprom->data;
210 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
211 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
212 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
213 !!eeprom->reg_data_clock);
214 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
215 !!eeprom->reg_chip_select);
217 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
220 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
221 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
223 static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
224 const unsigned int word, u32 *data)
226 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
229 static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
230 const unsigned int word, u32 data)
232 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
235 static const struct rt2x00debug rt61pci_rt2x00debug = {
236 .owner = THIS_MODULE,
238 .read = rt61pci_read_csr,
239 .write = rt61pci_write_csr,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_size = sizeof(u16),
247 .word_count = EEPROM_SIZE / sizeof(u16),
250 .read = rt61pci_bbp_read,
251 .write = rt61pci_bbp_write,
252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
258 .word_size = sizeof(u32),
259 .word_count = RF_SIZE / sizeof(u32),
262 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
264 #ifdef CONFIG_RT61PCI_RFKILL
265 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
270 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
273 #define rt61pci_rfkill_poll NULL
274 #endif /* CONFIG_RT61PCI_RFKILL */
277 * Configuration handlers.
279 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
283 tmp = le32_to_cpu(mac[1]);
284 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
285 mac[1] = cpu_to_le32(tmp);
287 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
288 (2 * sizeof(__le32)));
291 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
295 tmp = le32_to_cpu(bssid[1]);
296 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
297 bssid[1] = cpu_to_le32(tmp);
299 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
300 (2 * sizeof(__le32)));
303 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
309 * Clear current synchronisation setup.
310 * For the Beacon base registers we only need to clear
311 * the first byte since that byte contains the VALID and OWNER
312 * bits which (when set to 0) will invalidate the entire beacon.
314 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
315 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
316 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
317 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
318 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
321 * Enable synchronisation.
323 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
324 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
325 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
326 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
327 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, tsf_sync);
328 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
331 static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
332 const int short_preamble,
333 const int ack_timeout,
334 const int ack_consume_time)
338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
339 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
340 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
342 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
343 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
345 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
348 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
349 const int basic_rate_mask)
351 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
354 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
355 struct rf_channel *rf, const int txpower)
361 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
362 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
364 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
365 rt2x00_rf(&rt2x00dev->chip, RF2527));
367 rt61pci_bbp_read(rt2x00dev, 3, &r3);
368 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
369 rt61pci_bbp_write(rt2x00dev, 3, r3);
372 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
373 r94 += txpower - MAX_TXPOWER;
374 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
376 rt61pci_bbp_write(rt2x00dev, 94, r94);
378 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
379 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
380 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
381 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
385 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
386 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
387 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
388 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
392 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
393 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
394 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
395 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
400 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
403 struct rf_channel rf;
405 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
406 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
407 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
408 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
410 rt61pci_config_channel(rt2x00dev, &rf, txpower);
413 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
414 struct antenna_setup *ant)
420 rt61pci_bbp_read(rt2x00dev, 3, &r3);
421 rt61pci_bbp_read(rt2x00dev, 4, &r4);
422 rt61pci_bbp_read(rt2x00dev, 77, &r77);
424 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
425 !rt2x00_rf(&rt2x00dev->chip, RF5225));
428 case ANTENNA_SW_DIVERSITY:
429 case ANTENNA_HW_DIVERSITY:
430 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
431 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
432 !!(rt2x00dev->curr_hwmode != HWMODE_A));
435 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
436 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
438 if (rt2x00dev->curr_hwmode == HWMODE_A)
439 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
441 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
444 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
445 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
447 if (rt2x00dev->curr_hwmode == HWMODE_A)
448 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
450 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
454 rt61pci_bbp_write(rt2x00dev, 77, r77);
455 rt61pci_bbp_write(rt2x00dev, 3, r3);
456 rt61pci_bbp_write(rt2x00dev, 4, r4);
459 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
460 struct antenna_setup *ant)
466 rt61pci_bbp_read(rt2x00dev, 3, &r3);
467 rt61pci_bbp_read(rt2x00dev, 4, &r4);
468 rt61pci_bbp_read(rt2x00dev, 77, &r77);
470 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
471 !rt2x00_rf(&rt2x00dev->chip, RF2527));
472 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
473 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
476 case ANTENNA_SW_DIVERSITY:
477 case ANTENNA_HW_DIVERSITY:
478 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
481 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
482 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
485 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
486 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
490 rt61pci_bbp_write(rt2x00dev, 77, r77);
491 rt61pci_bbp_write(rt2x00dev, 3, r3);
492 rt61pci_bbp_write(rt2x00dev, 4, r4);
495 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
496 const int p1, const int p2)
500 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
503 rt2x00_set_field32(®, MAC_CSR13_BIT4, !!p1);
504 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
505 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
508 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
509 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
510 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
514 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
515 struct antenna_setup *ant)
522 rt61pci_bbp_read(rt2x00dev, 3, &r3);
523 rt61pci_bbp_read(rt2x00dev, 4, &r4);
524 rt61pci_bbp_read(rt2x00dev, 77, &r77);
525 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
527 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
529 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
530 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
531 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
532 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
533 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
534 } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
535 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
536 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
537 rt61pci_bbp_write(rt2x00dev, 77, r77);
539 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
540 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
541 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
542 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
543 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
544 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
546 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
548 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
551 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
554 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
557 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
560 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
561 !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
562 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
563 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
565 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
567 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
568 rt61pci_bbp_write(rt2x00dev, 77, r77);
569 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
572 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
573 rt61pci_bbp_write(rt2x00dev, 77, r77);
574 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
577 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
578 rt61pci_bbp_write(rt2x00dev, 77, r77);
579 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
582 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
583 rt61pci_bbp_write(rt2x00dev, 77, r77);
584 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
589 rt61pci_bbp_write(rt2x00dev, 3, r3);
590 rt61pci_bbp_write(rt2x00dev, 4, r4);
596 * value[0] -> non-LNA
602 static const struct antenna_sel antenna_sel_a[] = {
603 { 96, { 0x58, 0x78 } },
604 { 104, { 0x38, 0x48 } },
605 { 75, { 0xfe, 0x80 } },
606 { 86, { 0xfe, 0x80 } },
607 { 88, { 0xfe, 0x80 } },
608 { 35, { 0x60, 0x60 } },
609 { 97, { 0x58, 0x58 } },
610 { 98, { 0x58, 0x58 } },
613 static const struct antenna_sel antenna_sel_bg[] = {
614 { 96, { 0x48, 0x68 } },
615 { 104, { 0x2c, 0x3c } },
616 { 75, { 0xfe, 0x80 } },
617 { 86, { 0xfe, 0x80 } },
618 { 88, { 0xfe, 0x80 } },
619 { 35, { 0x50, 0x50 } },
620 { 97, { 0x48, 0x48 } },
621 { 98, { 0x48, 0x48 } },
624 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
625 struct antenna_setup *ant)
627 const struct antenna_sel *sel;
632 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
634 if (rt2x00dev->curr_hwmode == HWMODE_A) {
636 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
638 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 0);
639 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 1);
641 sel = antenna_sel_bg;
642 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
644 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 1);
645 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 0);
648 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
649 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
651 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
653 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
654 rt2x00_rf(&rt2x00dev->chip, RF5325))
655 rt61pci_config_antenna_5x(rt2x00dev, ant);
656 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
657 rt61pci_config_antenna_2x(rt2x00dev, ant);
658 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
659 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
660 rt61pci_config_antenna_2x(rt2x00dev, ant);
662 rt61pci_config_antenna_2529(rt2x00dev, ant);
666 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
667 struct rt2x00lib_conf *libconf)
671 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
672 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
673 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
675 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
676 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
677 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
678 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
679 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
681 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
682 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
683 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
685 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
686 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
687 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
689 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
690 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
691 libconf->conf->beacon_int * 16);
692 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
695 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
696 const unsigned int flags,
697 struct rt2x00lib_conf *libconf)
699 if (flags & CONFIG_UPDATE_PHYMODE)
700 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
701 if (flags & CONFIG_UPDATE_CHANNEL)
702 rt61pci_config_channel(rt2x00dev, &libconf->rf,
703 libconf->conf->power_level);
704 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
705 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
706 if (flags & CONFIG_UPDATE_ANTENNA)
707 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
708 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
709 rt61pci_config_duration(rt2x00dev, libconf);
715 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
722 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, ®);
723 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
724 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
725 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
727 led_reg = rt2x00dev->led_reg;
728 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
729 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
730 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
732 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
734 arg0 = led_reg & 0xff;
735 arg1 = (led_reg >> 8) & 0xff;
737 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
740 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
746 led_reg = rt2x00dev->led_reg;
747 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
748 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
749 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
751 arg0 = led_reg & 0xff;
752 arg1 = (led_reg >> 8) & 0xff;
754 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
757 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
761 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
765 * Led handling requires a positive value for the rssi,
766 * to do that correctly we need to add the correction.
768 rssi += rt2x00dev->rssi_offset;
783 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
789 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
790 struct link_qual *qual)
795 * Update FCS error count from register.
797 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
798 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
801 * Update False CCA count from register.
803 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
804 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
807 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
809 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
810 rt2x00dev->link.vgc_level = 0x20;
813 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
815 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
821 * Update Led strength
823 rt61pci_activity_led(rt2x00dev, rssi);
825 rt61pci_bbp_read(rt2x00dev, 17, &r17);
828 * Determine r17 bounds.
830 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
833 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
840 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
847 * Special big-R17 for very short distance
851 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
856 * Special big-R17 for short distance
860 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
865 * Special big-R17 for middle-short distance
869 if (r17 != low_bound)
870 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
875 * Special mid-R17 for middle distance
879 if (r17 != low_bound)
880 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
885 * Special case: Change up_bound based on the rssi.
886 * Lower up_bound when rssi is weaker then -74 dBm.
888 up_bound -= 2 * (-74 - rssi);
889 if (low_bound > up_bound)
890 up_bound = low_bound;
892 if (r17 > up_bound) {
893 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
898 * r17 does not yet exceed upper limit, continue and base
899 * the r17 tuning on the false CCA count.
901 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
902 if (++r17 > up_bound)
904 rt61pci_bbp_write(rt2x00dev, 17, r17);
905 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
906 if (--r17 < low_bound)
908 rt61pci_bbp_write(rt2x00dev, 17, r17);
913 * Firmware name function.
915 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
919 switch (rt2x00dev->chip.rt) {
921 fw_name = FIRMWARE_RT2561;
924 fw_name = FIRMWARE_RT2561s;
927 fw_name = FIRMWARE_RT2661;
938 * Initialization functions.
940 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
947 * Wait for stable hardware.
949 for (i = 0; i < 100; i++) {
950 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
957 ERROR(rt2x00dev, "Unstable hardware.\n");
962 * Prepare MCU and mailbox for firmware loading.
965 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
966 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
967 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
968 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
969 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
972 * Write firmware to device.
975 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
976 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
977 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
979 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
982 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
983 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
985 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
986 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
988 for (i = 0; i < 100; i++) {
989 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
990 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
996 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1001 * Reset MAC and BBP registers.
1004 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1005 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1006 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1008 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1009 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1010 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1011 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1013 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1014 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1015 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1020 static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1022 struct data_ring *ring = rt2x00dev->rx;
1023 struct data_desc *rxd;
1027 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1029 for (i = 0; i < ring->stats.limit; i++) {
1030 rxd = ring->entry[i].priv;
1032 rt2x00_desc_read(rxd, 5, &word);
1033 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1034 ring->entry[i].data_dma);
1035 rt2x00_desc_write(rxd, 5, word);
1037 rt2x00_desc_read(rxd, 0, &word);
1038 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1039 rt2x00_desc_write(rxd, 0, word);
1042 rt2x00_ring_index_clear(rt2x00dev->rx);
1045 static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1047 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1048 struct data_desc *txd;
1052 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1054 for (i = 0; i < ring->stats.limit; i++) {
1055 txd = ring->entry[i].priv;
1057 rt2x00_desc_read(txd, 1, &word);
1058 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1059 rt2x00_desc_write(txd, 1, word);
1061 rt2x00_desc_read(txd, 5, &word);
1062 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1063 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1064 rt2x00_desc_write(txd, 5, word);
1066 rt2x00_desc_read(txd, 6, &word);
1067 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1068 ring->entry[i].data_dma);
1069 rt2x00_desc_write(txd, 6, word);
1071 rt2x00_desc_read(txd, 0, &word);
1072 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1073 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1074 rt2x00_desc_write(txd, 0, word);
1077 rt2x00_ring_index_clear(ring);
1080 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1087 rt61pci_init_rxring(rt2x00dev);
1088 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1089 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1090 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1091 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1092 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1095 * Initialize registers.
1097 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1098 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1099 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1100 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1101 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1102 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1103 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1104 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1105 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1106 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1108 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1109 rt2x00_set_field32(®, TX_RING_CSR1_MGMT_RING_SIZE,
1110 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1111 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1112 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1114 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1116 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1117 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1118 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1119 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1121 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1122 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1123 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1124 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1126 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1127 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1128 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1129 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1131 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1132 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1133 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1134 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1136 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, ®);
1137 rt2x00_set_field32(®, MGMT_BASE_CSR_RING_REGISTER,
1138 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1139 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1141 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1142 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE,
1143 rt2x00dev->rx->stats.limit);
1144 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1145 rt2x00dev->rx->desc_size / 4);
1146 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1147 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1149 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1150 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1151 rt2x00dev->rx->data_dma);
1152 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1154 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1155 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1156 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1157 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1158 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1159 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_MGMT, 0);
1160 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1162 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1163 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1164 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1165 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1166 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1167 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1168 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1170 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1171 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1172 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1177 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1181 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1182 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1183 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1184 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1185 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1187 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1188 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1189 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1190 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1191 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1192 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1193 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1194 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1195 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1196 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1199 * CCK TXD BBP registers
1201 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1202 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1203 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1204 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1205 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1206 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1207 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1208 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1209 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1210 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1213 * OFDM TXD BBP registers
1215 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1216 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1217 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1218 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1219 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1220 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1221 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1222 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1224 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1225 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1226 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1227 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1228 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1229 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1231 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1232 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1233 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1234 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1235 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1236 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1238 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1240 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1242 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1243 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1244 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1246 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1248 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1251 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1254 * Invalidate all Shared Keys (SEC_CSR0),
1255 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1257 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1258 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1259 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1261 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1262 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1263 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1264 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1266 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1268 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1270 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1272 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
1273 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
1274 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
1275 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1277 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1278 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1279 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1280 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1283 * We must clear the error counters.
1284 * These registers are cleared on read,
1285 * so we may pass a useless variable to store the value.
1287 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1288 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1289 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1292 * Reset MAC and BBP registers.
1294 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1295 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1296 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1297 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1299 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1300 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1301 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1302 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1304 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1305 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1306 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1311 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1318 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1319 rt61pci_bbp_read(rt2x00dev, 0, &value);
1320 if ((value != 0xff) && (value != 0x00))
1321 goto continue_csr_init;
1322 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1323 udelay(REGISTER_BUSY_DELAY);
1326 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1330 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1331 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1332 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1333 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1334 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1335 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1336 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1337 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1338 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1339 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1340 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1341 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1342 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1343 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1344 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1345 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1346 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1347 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1348 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1349 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1350 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1351 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1352 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1353 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1355 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1356 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1357 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1359 if (eeprom != 0xffff && eeprom != 0x0000) {
1360 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1361 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1362 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1364 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1367 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1373 * Device state switch handlers.
1375 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1376 enum dev_state state)
1380 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1381 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1382 state == STATE_RADIO_RX_OFF);
1383 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1386 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1387 enum dev_state state)
1389 int mask = (state == STATE_RADIO_IRQ_OFF);
1393 * When interrupts are being enabled, the interrupt registers
1394 * should clear the register to assure a clean state.
1396 if (state == STATE_RADIO_IRQ_ON) {
1397 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1398 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1400 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1401 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1405 * Only toggle the interrupts bits we are going to use.
1406 * Non-checked interrupt bits are disabled by default.
1408 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1409 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1410 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1411 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1412 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1413 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1415 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1416 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1417 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1418 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1419 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1420 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1421 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1422 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1423 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1424 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1427 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1432 * Initialize all registers.
1434 if (rt61pci_init_rings(rt2x00dev) ||
1435 rt61pci_init_registers(rt2x00dev) ||
1436 rt61pci_init_bbp(rt2x00dev)) {
1437 ERROR(rt2x00dev, "Register initialization failed.\n");
1442 * Enable interrupts.
1444 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1449 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1450 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1451 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1456 rt61pci_enable_led(rt2x00dev);
1461 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1468 rt61pci_disable_led(rt2x00dev);
1470 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1473 * Disable synchronisation.
1475 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1480 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1481 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1482 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1483 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1484 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1485 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1486 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1489 * Disable interrupts.
1491 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1494 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1501 put_to_sleep = (state != STATE_AWAKE);
1503 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1504 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1505 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1506 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1509 * Device is not guaranteed to be in the requested state yet.
1510 * We must wait until the register indicates that the
1511 * device has entered the correct state.
1513 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1514 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1516 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1517 if (current_state == !put_to_sleep)
1522 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1523 "current device state %d.\n", !put_to_sleep, current_state);
1528 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1529 enum dev_state state)
1534 case STATE_RADIO_ON:
1535 retval = rt61pci_enable_radio(rt2x00dev);
1537 case STATE_RADIO_OFF:
1538 rt61pci_disable_radio(rt2x00dev);
1540 case STATE_RADIO_RX_ON:
1541 case STATE_RADIO_RX_OFF:
1542 rt61pci_toggle_rx(rt2x00dev, state);
1544 case STATE_DEEP_SLEEP:
1548 retval = rt61pci_set_state(rt2x00dev, state);
1559 * TX descriptor initialization
1561 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1562 struct data_desc *txd,
1563 struct txdata_entry_desc *desc,
1564 struct ieee80211_hdr *ieee80211hdr,
1565 unsigned int length,
1566 struct ieee80211_tx_control *control)
1571 * Start writing the descriptor words.
1573 rt2x00_desc_read(txd, 1, &word);
1574 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1575 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1576 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1577 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1578 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1579 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1580 rt2x00_desc_write(txd, 1, word);
1582 rt2x00_desc_read(txd, 2, &word);
1583 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1584 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1585 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1586 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1587 rt2x00_desc_write(txd, 2, word);
1589 rt2x00_desc_read(txd, 5, &word);
1590 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1591 TXPOWER_TO_DEV(control->power_level));
1592 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1593 rt2x00_desc_write(txd, 5, word);
1595 rt2x00_desc_read(txd, 11, &word);
1596 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1597 rt2x00_desc_write(txd, 11, word);
1599 rt2x00_desc_read(txd, 0, &word);
1600 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1601 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1602 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1603 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1604 rt2x00_set_field32(&word, TXD_W0_ACK,
1605 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1606 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1607 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1608 rt2x00_set_field32(&word, TXD_W0_OFDM,
1609 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1610 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1611 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1613 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1614 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1615 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1616 rt2x00_set_field32(&word, TXD_W0_BURST,
1617 test_bit(ENTRY_TXD_BURST, &desc->flags));
1618 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1619 rt2x00_desc_write(txd, 0, word);
1623 * TX data initialization
1625 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1630 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1632 * For Wi-Fi faily generated beacons between participating
1633 * stations. Set TBTT phase adaptive adjustment step to 8us.
1635 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1637 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1638 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1639 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1640 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1645 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1646 if (queue == IEEE80211_TX_QUEUE_DATA0)
1647 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1);
1648 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1649 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1);
1650 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1651 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1);
1652 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1653 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1);
1654 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1655 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1656 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1660 * RX control handlers
1662 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1668 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1683 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1684 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1687 if (lna == 3 || lna == 2)
1690 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1691 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1693 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1696 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1697 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1700 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1703 static void rt61pci_fill_rxdone(struct data_entry *entry,
1704 struct rxdata_entry_desc *desc)
1706 struct data_desc *rxd = entry->priv;
1710 rt2x00_desc_read(rxd, 0, &word0);
1711 rt2x00_desc_read(rxd, 1, &word1);
1714 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1715 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1718 * Obtain the status about this packet.
1720 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1721 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1722 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1723 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1729 * Interrupt functions.
1731 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1733 struct data_ring *ring;
1734 struct data_entry *entry;
1735 struct data_entry *entry_done;
1736 struct data_desc *txd;
1746 * During each loop we will compare the freshly read
1747 * STA_CSR4 register value with the value read from
1748 * the previous loop. If the 2 values are equal then
1749 * we should stop processing because the chance it
1750 * quite big that the device has been unplugged and
1751 * we risk going into an endless loop.
1756 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
1757 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1765 * Skip this entry when it contains an invalid
1766 * ring identication number.
1768 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1769 ring = rt2x00lib_get_ring(rt2x00dev, type);
1770 if (unlikely(!ring))
1774 * Skip this entry when it contains an invalid
1777 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1778 if (unlikely(index >= ring->stats.limit))
1781 entry = &ring->entry[index];
1783 rt2x00_desc_read(txd, 0, &word);
1785 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1786 !rt2x00_get_field32(word, TXD_W0_VALID))
1789 entry_done = rt2x00_get_data_entry_done(ring);
1790 while (entry != entry_done) {
1791 /* Catch up. Just report any entries we missed as
1794 "TX status report missed for entry %p\n",
1796 rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
1797 entry_done = rt2x00_get_data_entry_done(ring);
1801 * Obtain the status about this packet.
1803 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1804 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1806 rt2x00lib_txdone(entry, tx_status, retry);
1809 * Make this entry available for reuse.
1812 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1813 rt2x00_desc_write(txd, 0, word);
1814 rt2x00_ring_index_done_inc(entry->ring);
1817 * If the data ring was full before the txdone handler
1818 * we must make sure the packet queue in the mac80211 stack
1819 * is reenabled when the txdone handler has finished.
1821 if (!rt2x00_ring_full(ring))
1822 ieee80211_wake_queue(rt2x00dev->hw,
1823 entry->tx_status.control.queue);
1827 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1829 struct rt2x00_dev *rt2x00dev = dev_instance;
1834 * Get the interrupt sources & saved to local variable.
1835 * Write register value back to clear pending interrupts.
1837 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
1838 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1840 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1841 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1843 if (!reg && !reg_mcu)
1846 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1850 * Handle interrupts, walk through all bits
1851 * and run the tasks, the bits are checked in order of
1856 * 1 - Rx ring done interrupt.
1858 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1859 rt2x00pci_rxdone(rt2x00dev);
1862 * 2 - Tx ring done interrupt.
1864 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1865 rt61pci_txdone(rt2x00dev);
1868 * 3 - Handle MCU command done.
1871 rt2x00pci_register_write(rt2x00dev,
1872 M2H_CMD_DONE_CSR, 0xffffffff);
1878 * Device probe functions.
1880 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1882 struct eeprom_93cx6 eeprom;
1888 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
1890 eeprom.data = rt2x00dev;
1891 eeprom.register_read = rt61pci_eepromregister_read;
1892 eeprom.register_write = rt61pci_eepromregister_write;
1893 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1894 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1895 eeprom.reg_data_in = 0;
1896 eeprom.reg_data_out = 0;
1897 eeprom.reg_data_clock = 0;
1898 eeprom.reg_chip_select = 0;
1900 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1901 EEPROM_SIZE / sizeof(u16));
1904 * Start validation of the data that has been read.
1906 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1907 if (!is_valid_ether_addr(mac)) {
1908 DECLARE_MAC_BUF(macbuf);
1910 random_ether_addr(mac);
1911 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1914 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1915 if (word == 0xffff) {
1916 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1917 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1919 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1921 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1922 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1923 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1924 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1925 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1926 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1929 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1930 if (word == 0xffff) {
1931 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1932 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1933 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1934 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1935 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1936 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1937 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1938 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1941 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1942 if (word == 0xffff) {
1943 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1945 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1946 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1949 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1950 if (word == 0xffff) {
1951 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1952 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1953 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1954 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1957 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1958 if (word == 0xffff) {
1959 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1960 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1961 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1962 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1964 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1965 if (value < -10 || value > 10)
1966 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1967 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1968 if (value < -10 || value > 10)
1969 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1970 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1973 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1974 if (word == 0xffff) {
1975 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1976 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1977 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1978 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1980 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1981 if (value < -10 || value > 10)
1982 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1983 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1984 if (value < -10 || value > 10)
1985 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1986 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1992 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2000 * Read EEPROM word for configuration.
2002 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2005 * Identify RF chipset.
2006 * To determine the RT chip we have to read the
2007 * PCI header of the device.
2009 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2010 PCI_CONFIG_HEADER_DEVICE, &device);
2011 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2012 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
2013 rt2x00_set_chip(rt2x00dev, device, value, reg);
2015 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2016 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2017 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2018 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2019 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2024 * Identify default antenna configuration.
2026 rt2x00dev->default_ant.tx =
2027 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2028 rt2x00dev->default_ant.rx =
2029 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2032 * Read the Frame type.
2034 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2035 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2038 * Determine number of antenna's.
2040 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2041 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2044 * Detect if this device has an hardware controlled radio.
2046 #ifdef CONFIG_RT61PCI_RFKILL
2047 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2048 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2049 #endif /* CONFIG_RT61PCI_RFKILL */
2052 * Read frequency offset and RF programming sequence.
2054 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2055 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2056 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2058 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2061 * Read external LNA informations.
2063 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2065 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2066 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2067 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2068 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2071 * Store led settings, for correct led behaviour.
2072 * If the eeprom value is invalid,
2073 * switch to default led mode.
2075 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2077 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2079 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2080 rt2x00dev->led_mode);
2081 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2082 rt2x00_get_field16(eeprom,
2083 EEPROM_LED_POLARITY_GPIO_0));
2084 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2085 rt2x00_get_field16(eeprom,
2086 EEPROM_LED_POLARITY_GPIO_1));
2087 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2088 rt2x00_get_field16(eeprom,
2089 EEPROM_LED_POLARITY_GPIO_2));
2090 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2091 rt2x00_get_field16(eeprom,
2092 EEPROM_LED_POLARITY_GPIO_3));
2093 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2094 rt2x00_get_field16(eeprom,
2095 EEPROM_LED_POLARITY_GPIO_4));
2096 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2097 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2098 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2099 rt2x00_get_field16(eeprom,
2100 EEPROM_LED_POLARITY_RDY_G));
2101 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2102 rt2x00_get_field16(eeprom,
2103 EEPROM_LED_POLARITY_RDY_A));
2109 * RF value list for RF5225 & RF5325
2110 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2112 static const struct rf_channel rf_vals_noseq[] = {
2113 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2114 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2115 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2116 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2117 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2118 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2119 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2120 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2121 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2122 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2123 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2124 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2125 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2126 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2128 /* 802.11 UNI / HyperLan 2 */
2129 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2130 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2131 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2132 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2133 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2134 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2135 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2136 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2138 /* 802.11 HyperLan 2 */
2139 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2140 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2141 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2142 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2143 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2144 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2145 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2146 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2147 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2148 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2151 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2152 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2153 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2154 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2155 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2156 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2158 /* MMAC(Japan)J52 ch 34,38,42,46 */
2159 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2160 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2161 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2162 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2166 * RF value list for RF5225 & RF5325
2167 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2169 static const struct rf_channel rf_vals_seq[] = {
2170 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2171 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2172 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2173 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2174 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2175 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2176 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2177 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2178 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2179 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2180 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2181 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2182 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2183 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2185 /* 802.11 UNI / HyperLan 2 */
2186 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2187 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2188 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2189 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2190 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2191 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2192 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2193 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2195 /* 802.11 HyperLan 2 */
2196 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2197 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2198 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2199 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2200 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2201 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2202 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2203 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2204 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2205 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2208 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2209 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2210 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2211 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2212 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2213 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2215 /* MMAC(Japan)J52 ch 34,38,42,46 */
2216 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2217 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2218 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2219 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2222 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2224 struct hw_mode_spec *spec = &rt2x00dev->spec;
2229 * Initialize all hw fields.
2231 rt2x00dev->hw->flags =
2232 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2233 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2234 rt2x00dev->hw->extra_tx_headroom = 0;
2235 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2236 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2237 rt2x00dev->hw->queues = 5;
2239 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2240 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2241 rt2x00_eeprom_addr(rt2x00dev,
2242 EEPROM_MAC_ADDR_0));
2245 * Convert tx_power array in eeprom.
2247 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2248 for (i = 0; i < 14; i++)
2249 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2252 * Initialize hw_mode information.
2254 spec->num_modes = 2;
2255 spec->num_rates = 12;
2256 spec->tx_power_a = NULL;
2257 spec->tx_power_bg = txpower;
2258 spec->tx_power_default = DEFAULT_TXPOWER;
2260 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2261 spec->num_channels = 14;
2262 spec->channels = rf_vals_noseq;
2264 spec->num_channels = 14;
2265 spec->channels = rf_vals_seq;
2268 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2269 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2270 spec->num_modes = 3;
2271 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2273 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2274 for (i = 0; i < 14; i++)
2275 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2277 spec->tx_power_a = txpower;
2281 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2286 * Allocate eeprom data.
2288 retval = rt61pci_validate_eeprom(rt2x00dev);
2292 retval = rt61pci_init_eeprom(rt2x00dev);
2297 * Initialize hw specifications.
2299 rt61pci_probe_hw_mode(rt2x00dev);
2302 * This device requires firmware
2304 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2307 * Set the rssi offset.
2309 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2315 * IEEE80211 stack callback functions.
2317 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2318 unsigned int changed_flags,
2319 unsigned int *total_flags,
2321 struct dev_addr_list *mc_list)
2323 struct rt2x00_dev *rt2x00dev = hw->priv;
2324 struct interface *intf = &rt2x00dev->interface;
2328 * Mask off any flags we are going to ignore from
2329 * the total_flags field.
2340 * Apply some rules to the filters:
2341 * - Some filters imply different filters to be set.
2342 * - Some things we can't filter out at all.
2343 * - Some filters are set based on interface type.
2346 *total_flags |= FIF_ALLMULTI;
2347 if (*total_flags & FIF_OTHER_BSS ||
2348 *total_flags & FIF_PROMISC_IN_BSS)
2349 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2350 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2351 *total_flags |= FIF_PROMISC_IN_BSS;
2354 * Check if there is any work left for us.
2356 if (intf->filter == *total_flags)
2358 intf->filter = *total_flags;
2361 * Start configuration steps.
2362 * Note that the version error will always be dropped
2363 * and broadcast frames will always be accepted since
2364 * there is no filter for it at this time.
2366 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
2367 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
2368 !(*total_flags & FIF_FCSFAIL));
2369 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
2370 !(*total_flags & FIF_PLCPFAIL));
2371 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
2372 !(*total_flags & FIF_CONTROL));
2373 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
2374 !(*total_flags & FIF_PROMISC_IN_BSS));
2375 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
2376 !(*total_flags & FIF_PROMISC_IN_BSS));
2377 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2378 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
2379 !(*total_flags & FIF_ALLMULTI));
2380 rt2x00_set_field32(®, TXRX_CSR0_DROP_BORADCAST, 0);
2381 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
2382 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2385 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2386 u32 short_retry, u32 long_retry)
2388 struct rt2x00_dev *rt2x00dev = hw->priv;
2391 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
2392 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2393 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2394 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2399 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2401 struct rt2x00_dev *rt2x00dev = hw->priv;
2405 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2406 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2407 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2408 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2413 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2415 struct rt2x00_dev *rt2x00dev = hw->priv;
2417 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2418 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2421 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2422 struct ieee80211_tx_control *control)
2424 struct rt2x00_dev *rt2x00dev = hw->priv;
2427 * Just in case the ieee80211 doesn't set this,
2428 * but we need this queue set for the descriptor
2431 control->queue = IEEE80211_TX_QUEUE_BEACON;
2434 * We need to append the descriptor in front of the
2437 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2438 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2445 * First we create the beacon.
2447 skb_push(skb, TXD_DESC_SIZE);
2448 memset(skb->data, 0, TXD_DESC_SIZE);
2450 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
2451 (struct ieee80211_hdr *)(skb->data +
2453 skb->len - TXD_DESC_SIZE, control);
2456 * Write entire beacon with descriptor to register,
2457 * and kick the beacon generator.
2459 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2460 skb->data, skb->len);
2461 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2466 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2468 .start = rt2x00mac_start,
2469 .stop = rt2x00mac_stop,
2470 .add_interface = rt2x00mac_add_interface,
2471 .remove_interface = rt2x00mac_remove_interface,
2472 .config = rt2x00mac_config,
2473 .config_interface = rt2x00mac_config_interface,
2474 .configure_filter = rt61pci_configure_filter,
2475 .get_stats = rt2x00mac_get_stats,
2476 .set_retry_limit = rt61pci_set_retry_limit,
2477 .erp_ie_changed = rt2x00mac_erp_ie_changed,
2478 .conf_tx = rt2x00mac_conf_tx,
2479 .get_tx_stats = rt2x00mac_get_tx_stats,
2480 .get_tsf = rt61pci_get_tsf,
2481 .reset_tsf = rt61pci_reset_tsf,
2482 .beacon_update = rt61pci_beacon_update,
2485 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2486 .irq_handler = rt61pci_interrupt,
2487 .probe_hw = rt61pci_probe_hw,
2488 .get_firmware_name = rt61pci_get_firmware_name,
2489 .load_firmware = rt61pci_load_firmware,
2490 .initialize = rt2x00pci_initialize,
2491 .uninitialize = rt2x00pci_uninitialize,
2492 .set_device_state = rt61pci_set_device_state,
2493 .rfkill_poll = rt61pci_rfkill_poll,
2494 .link_stats = rt61pci_link_stats,
2495 .reset_tuner = rt61pci_reset_tuner,
2496 .link_tuner = rt61pci_link_tuner,
2497 .write_tx_desc = rt61pci_write_tx_desc,
2498 .write_tx_data = rt2x00pci_write_tx_data,
2499 .kick_tx_queue = rt61pci_kick_tx_queue,
2500 .fill_rxdone = rt61pci_fill_rxdone,
2501 .config_mac_addr = rt61pci_config_mac_addr,
2502 .config_bssid = rt61pci_config_bssid,
2503 .config_type = rt61pci_config_type,
2504 .config_preamble = rt61pci_config_preamble,
2505 .config = rt61pci_config,
2508 static const struct rt2x00_ops rt61pci_ops = {
2510 .rxd_size = RXD_DESC_SIZE,
2511 .txd_size = TXD_DESC_SIZE,
2512 .eeprom_size = EEPROM_SIZE,
2514 .lib = &rt61pci_rt2x00_ops,
2515 .hw = &rt61pci_mac80211_ops,
2516 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2517 .debugfs = &rt61pci_rt2x00debug,
2518 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2522 * RT61pci module information.
2524 static struct pci_device_id rt61pci_device_table[] = {
2526 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2528 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2530 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2534 MODULE_AUTHOR(DRV_PROJECT);
2535 MODULE_VERSION(DRV_VERSION);
2536 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2537 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2538 "PCI & PCMCIA chipset based cards");
2539 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2540 MODULE_FIRMWARE(FIRMWARE_RT2561);
2541 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2542 MODULE_FIRMWARE(FIRMWARE_RT2661);
2543 MODULE_LICENSE("GPL");
2545 static struct pci_driver rt61pci_driver = {
2547 .id_table = rt61pci_device_table,
2548 .probe = rt2x00pci_probe,
2549 .remove = __devexit_p(rt2x00pci_remove),
2550 .suspend = rt2x00pci_suspend,
2551 .resume = rt2x00pci_resume,
2554 static int __init rt61pci_init(void)
2556 return pci_register_driver(&rt61pci_driver);
2559 static void __exit rt61pci_exit(void)
2561 pci_unregister_driver(&rt61pci_driver);
2564 module_init(rt61pci_init);
2565 module_exit(rt61pci_exit);