2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
27 #include <linux/delay.h>
28 #include <linux/etherdevice.h>
29 #include <linux/init.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/pci.h>
33 #include <linux/eeprom_93cx6.h>
36 #include "rt2x00pci.h"
41 * BBP and RF register require indirect register access,
42 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
43 * These indirect registers work with busy bits,
44 * and we will try maximal REGISTER_BUSY_COUNT times to access
45 * the register while taking a REGISTER_BUSY_DELAY us delay
46 * between each attampt. When the busy bit is still set at that time,
47 * the access attempt is considered to have failed,
48 * and we will print an error.
50 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
55 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
56 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
57 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
59 udelay(REGISTER_BUSY_DELAY);
65 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
66 const unsigned int word, const u8 value)
71 * Wait until the BBP becomes ready.
73 reg = rt61pci_bbp_check(rt2x00dev);
74 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
75 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
80 * Write the data into the BBP.
83 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
84 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
85 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
86 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
88 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
91 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
92 const unsigned int word, u8 *value)
97 * Wait until the BBP becomes ready.
99 reg = rt61pci_bbp_check(rt2x00dev);
100 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
101 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
106 * Write the request into the BBP.
109 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
110 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
111 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
113 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
116 * Wait until the BBP becomes ready.
118 reg = rt61pci_bbp_check(rt2x00dev);
119 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
120 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
125 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
128 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
129 const unsigned int word, const u32 value)
137 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
138 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
139 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
141 udelay(REGISTER_BUSY_DELAY);
144 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
149 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
150 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
151 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
152 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
154 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
155 rt2x00_rf_write(rt2x00dev, word, value);
158 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
159 const u8 command, const u8 token,
160 const u8 arg0, const u8 arg1)
164 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
166 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
167 ERROR(rt2x00dev, "mcu request error. "
168 "Request 0x%02x failed for token 0x%02x.\n",
173 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
174 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
175 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
176 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
177 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
179 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
180 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
181 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
182 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
185 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
187 struct rt2x00_dev *rt2x00dev = eeprom->data;
190 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
192 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
193 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
194 eeprom->reg_data_clock =
195 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
196 eeprom->reg_chip_select =
197 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
200 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
202 struct rt2x00_dev *rt2x00dev = eeprom->data;
205 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
206 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
207 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
208 !!eeprom->reg_data_clock);
209 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
210 !!eeprom->reg_chip_select);
212 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
215 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
216 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
218 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
219 const unsigned int word, u32 *data)
221 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
224 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
225 const unsigned int word, u32 data)
227 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
230 static const struct rt2x00debug rt61pci_rt2x00debug = {
231 .owner = THIS_MODULE,
233 .read = rt61pci_read_csr,
234 .write = rt61pci_write_csr,
235 .word_size = sizeof(u32),
236 .word_count = CSR_REG_SIZE / sizeof(u32),
239 .read = rt2x00_eeprom_read,
240 .write = rt2x00_eeprom_write,
241 .word_size = sizeof(u16),
242 .word_count = EEPROM_SIZE / sizeof(u16),
245 .read = rt61pci_bbp_read,
246 .write = rt61pci_bbp_write,
247 .word_size = sizeof(u8),
248 .word_count = BBP_SIZE / sizeof(u8),
251 .read = rt2x00_rf_read,
252 .write = rt61pci_rf_write,
253 .word_size = sizeof(u32),
254 .word_count = RF_SIZE / sizeof(u32),
257 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
259 #ifdef CONFIG_RT61PCI_RFKILL
260 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
264 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
265 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
268 #define rt61pci_rfkill_poll NULL
269 #endif /* CONFIG_RT61PCI_RFKILL */
272 * Configuration handlers.
274 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
278 tmp = le32_to_cpu(mac[1]);
279 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
280 mac[1] = cpu_to_le32(tmp);
282 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
283 (2 * sizeof(__le32)));
286 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
290 tmp = le32_to_cpu(bssid[1]);
291 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
292 bssid[1] = cpu_to_le32(tmp);
294 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
295 (2 * sizeof(__le32)));
298 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
304 * Clear current synchronisation setup.
305 * For the Beacon base registers we only need to clear
306 * the first byte since that byte contains the VALID and OWNER
307 * bits which (when set to 0) will invalidate the entire beacon.
309 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
310 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
311 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
312 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
313 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
316 * Enable synchronisation.
318 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
319 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
320 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE,
321 (tsf_sync == TSF_SYNC_BEACON));
322 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
323 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, tsf_sync);
324 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
327 static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
328 const int short_preamble,
329 const int ack_timeout,
330 const int ack_consume_time)
334 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
335 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
336 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
339 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
341 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
344 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
345 const int basic_rate_mask)
347 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
350 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
351 struct rf_channel *rf, const int txpower)
357 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
358 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
360 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
361 rt2x00_rf(&rt2x00dev->chip, RF2527));
363 rt61pci_bbp_read(rt2x00dev, 3, &r3);
364 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
365 rt61pci_bbp_write(rt2x00dev, 3, r3);
368 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
369 r94 += txpower - MAX_TXPOWER;
370 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
372 rt61pci_bbp_write(rt2x00dev, 94, r94);
374 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
375 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
376 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
377 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
381 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
382 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
383 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
384 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
388 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
389 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
390 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
391 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
396 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
399 struct rf_channel rf;
401 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
402 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
403 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
404 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
406 rt61pci_config_channel(rt2x00dev, &rf, txpower);
409 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
410 struct antenna_setup *ant)
416 rt61pci_bbp_read(rt2x00dev, 3, &r3);
417 rt61pci_bbp_read(rt2x00dev, 4, &r4);
418 rt61pci_bbp_read(rt2x00dev, 77, &r77);
420 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
421 rt2x00_rf(&rt2x00dev->chip, RF5325));
424 * Configure the RX antenna.
427 case ANTENNA_HW_DIVERSITY:
428 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
429 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
430 (rt2x00dev->curr_hwmode != HWMODE_A));
433 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
434 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
435 if (rt2x00dev->curr_hwmode == HWMODE_A)
436 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
438 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
440 case ANTENNA_SW_DIVERSITY:
442 * NOTE: We should never come here because rt2x00lib is
443 * supposed to catch this and send us the correct antenna
444 * explicitely. However we are nog going to bug about this.
445 * Instead, just default to antenna B.
448 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
449 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
450 if (rt2x00dev->curr_hwmode == HWMODE_A)
451 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
453 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
457 rt61pci_bbp_write(rt2x00dev, 77, r77);
458 rt61pci_bbp_write(rt2x00dev, 3, r3);
459 rt61pci_bbp_write(rt2x00dev, 4, r4);
462 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
463 struct antenna_setup *ant)
469 rt61pci_bbp_read(rt2x00dev, 3, &r3);
470 rt61pci_bbp_read(rt2x00dev, 4, &r4);
471 rt61pci_bbp_read(rt2x00dev, 77, &r77);
473 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
474 rt2x00_rf(&rt2x00dev->chip, RF2529));
475 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
476 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
479 * Configure the RX antenna.
482 case ANTENNA_HW_DIVERSITY:
483 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
486 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
487 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
489 case ANTENNA_SW_DIVERSITY:
491 * NOTE: We should never come here because rt2x00lib is
492 * supposed to catch this and send us the correct antenna
493 * explicitely. However we are nog going to bug about this.
494 * Instead, just default to antenna B.
497 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
498 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
502 rt61pci_bbp_write(rt2x00dev, 77, r77);
503 rt61pci_bbp_write(rt2x00dev, 3, r3);
504 rt61pci_bbp_write(rt2x00dev, 4, r4);
507 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
508 const int p1, const int p2)
512 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
514 rt2x00_set_field32(®, MAC_CSR13_BIT4, p1);
515 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
517 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
518 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
520 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
523 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
524 struct antenna_setup *ant)
530 rt61pci_bbp_read(rt2x00dev, 3, &r3);
531 rt61pci_bbp_read(rt2x00dev, 4, &r4);
532 rt61pci_bbp_read(rt2x00dev, 77, &r77);
534 /* FIXME: Antenna selection for the rf 2529 is very confusing in the
535 * legacy driver. The code below should be ok for non-diversity setups.
539 * Configure the RX antenna.
543 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
544 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
545 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
547 case ANTENNA_SW_DIVERSITY:
548 case ANTENNA_HW_DIVERSITY:
550 * NOTE: We should never come here because rt2x00lib is
551 * supposed to catch this and send us the correct antenna
552 * explicitely. However we are nog going to bug about this.
553 * Instead, just default to antenna B.
556 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
557 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
558 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
562 rt61pci_bbp_write(rt2x00dev, 77, r77);
563 rt61pci_bbp_write(rt2x00dev, 3, r3);
564 rt61pci_bbp_write(rt2x00dev, 4, r4);
570 * value[0] -> non-LNA
576 static const struct antenna_sel antenna_sel_a[] = {
577 { 96, { 0x58, 0x78 } },
578 { 104, { 0x38, 0x48 } },
579 { 75, { 0xfe, 0x80 } },
580 { 86, { 0xfe, 0x80 } },
581 { 88, { 0xfe, 0x80 } },
582 { 35, { 0x60, 0x60 } },
583 { 97, { 0x58, 0x58 } },
584 { 98, { 0x58, 0x58 } },
587 static const struct antenna_sel antenna_sel_bg[] = {
588 { 96, { 0x48, 0x68 } },
589 { 104, { 0x2c, 0x3c } },
590 { 75, { 0xfe, 0x80 } },
591 { 86, { 0xfe, 0x80 } },
592 { 88, { 0xfe, 0x80 } },
593 { 35, { 0x50, 0x50 } },
594 { 97, { 0x48, 0x48 } },
595 { 98, { 0x48, 0x48 } },
598 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
599 struct antenna_setup *ant)
601 const struct antenna_sel *sel;
606 if (rt2x00dev->curr_hwmode == HWMODE_A) {
608 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
610 sel = antenna_sel_bg;
611 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
614 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
615 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
617 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
619 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
620 (rt2x00dev->curr_hwmode == HWMODE_B ||
621 rt2x00dev->curr_hwmode == HWMODE_G));
622 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
623 (rt2x00dev->curr_hwmode == HWMODE_A));
625 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
627 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
628 rt2x00_rf(&rt2x00dev->chip, RF5325))
629 rt61pci_config_antenna_5x(rt2x00dev, ant);
630 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
631 rt61pci_config_antenna_2x(rt2x00dev, ant);
632 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
633 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
634 rt61pci_config_antenna_2x(rt2x00dev, ant);
636 rt61pci_config_antenna_2529(rt2x00dev, ant);
640 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
641 struct rt2x00lib_conf *libconf)
645 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
646 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
647 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
649 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
650 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
651 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
652 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
653 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
655 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
656 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
657 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
659 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
660 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
661 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
663 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
664 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
665 libconf->conf->beacon_int * 16);
666 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
669 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
670 const unsigned int flags,
671 struct rt2x00lib_conf *libconf)
673 if (flags & CONFIG_UPDATE_PHYMODE)
674 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
675 if (flags & CONFIG_UPDATE_CHANNEL)
676 rt61pci_config_channel(rt2x00dev, &libconf->rf,
677 libconf->conf->power_level);
678 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
679 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
680 if (flags & CONFIG_UPDATE_ANTENNA)
681 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
682 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
683 rt61pci_config_duration(rt2x00dev, libconf);
689 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
695 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, ®);
696 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
697 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
698 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
700 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
701 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
702 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
703 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
704 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
706 arg0 = rt2x00dev->led_reg & 0xff;
707 arg1 = (rt2x00dev->led_reg >> 8) & 0xff;
709 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
712 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
718 led_reg = rt2x00dev->led_reg;
719 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
720 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
721 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
723 arg0 = led_reg & 0xff;
724 arg1 = (led_reg >> 8) & 0xff;
726 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
729 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
733 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
737 * Led handling requires a positive value for the rssi,
738 * to do that correctly we need to add the correction.
740 rssi += rt2x00dev->rssi_offset;
755 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
761 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
762 struct link_qual *qual)
767 * Update FCS error count from register.
769 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
770 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
773 * Update False CCA count from register.
775 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
776 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
779 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
781 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
782 rt2x00dev->link.vgc_level = 0x20;
785 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
787 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
793 * Update Led strength
795 rt61pci_activity_led(rt2x00dev, rssi);
797 rt61pci_bbp_read(rt2x00dev, 17, &r17);
800 * Determine r17 bounds.
802 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
805 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
812 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
819 * Special big-R17 for very short distance
823 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
828 * Special big-R17 for short distance
832 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
837 * Special big-R17 for middle-short distance
841 if (r17 != low_bound)
842 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
847 * Special mid-R17 for middle distance
851 if (r17 != low_bound)
852 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
857 * Special case: Change up_bound based on the rssi.
858 * Lower up_bound when rssi is weaker then -74 dBm.
860 up_bound -= 2 * (-74 - rssi);
861 if (low_bound > up_bound)
862 up_bound = low_bound;
864 if (r17 > up_bound) {
865 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
870 * r17 does not yet exceed upper limit, continue and base
871 * the r17 tuning on the false CCA count.
873 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
874 if (++r17 > up_bound)
876 rt61pci_bbp_write(rt2x00dev, 17, r17);
877 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
878 if (--r17 < low_bound)
880 rt61pci_bbp_write(rt2x00dev, 17, r17);
885 * Firmware name function.
887 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
891 switch (rt2x00dev->chip.rt) {
893 fw_name = FIRMWARE_RT2561;
896 fw_name = FIRMWARE_RT2561s;
899 fw_name = FIRMWARE_RT2661;
910 * Initialization functions.
912 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
919 * Wait for stable hardware.
921 for (i = 0; i < 100; i++) {
922 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
929 ERROR(rt2x00dev, "Unstable hardware.\n");
934 * Prepare MCU and mailbox for firmware loading.
937 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
938 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
939 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
940 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
941 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
944 * Write firmware to device.
947 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
948 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
949 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
951 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
954 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
955 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
957 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
958 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
960 for (i = 0; i < 100; i++) {
961 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
962 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
968 ERROR(rt2x00dev, "MCU Control register not ready.\n");
973 * Reset MAC and BBP registers.
976 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
977 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
978 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
980 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
981 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
982 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
983 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
985 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
986 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
987 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
992 static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
994 struct data_ring *ring = rt2x00dev->rx;
999 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1001 for (i = 0; i < ring->stats.limit; i++) {
1002 rxd = ring->entry[i].priv;
1004 rt2x00_desc_read(rxd, 5, &word);
1005 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1006 ring->entry[i].data_dma);
1007 rt2x00_desc_write(rxd, 5, word);
1009 rt2x00_desc_read(rxd, 0, &word);
1010 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1011 rt2x00_desc_write(rxd, 0, word);
1014 rt2x00_ring_index_clear(rt2x00dev->rx);
1017 static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1019 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1024 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1026 for (i = 0; i < ring->stats.limit; i++) {
1027 txd = ring->entry[i].priv;
1029 rt2x00_desc_read(txd, 1, &word);
1030 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1031 rt2x00_desc_write(txd, 1, word);
1033 rt2x00_desc_read(txd, 5, &word);
1034 rt2x00_set_field32(&word, TXD_W5_PID_TYPE,
1036 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1037 ring->entry[i].entry_idx);
1038 rt2x00_desc_write(txd, 5, word);
1040 rt2x00_desc_read(txd, 6, &word);
1041 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1042 ring->entry[i].data_dma);
1043 rt2x00_desc_write(txd, 6, word);
1045 rt2x00_desc_read(txd, 0, &word);
1046 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1047 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1048 rt2x00_desc_write(txd, 0, word);
1051 rt2x00_ring_index_clear(ring);
1054 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1061 rt61pci_init_rxring(rt2x00dev);
1062 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1063 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1064 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1065 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1066 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1069 * Initialize registers.
1071 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1072 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1073 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1074 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1075 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1076 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1077 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1078 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1079 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1080 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1082 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1083 rt2x00_set_field32(®, TX_RING_CSR1_MGMT_RING_SIZE,
1084 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1085 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1086 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1088 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1090 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1091 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1092 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1093 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1095 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1096 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1097 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1098 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1100 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1101 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1102 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1103 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1105 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1106 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1107 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1108 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1110 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, ®);
1111 rt2x00_set_field32(®, MGMT_BASE_CSR_RING_REGISTER,
1112 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1113 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1115 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1116 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE,
1117 rt2x00dev->rx->stats.limit);
1118 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1119 rt2x00dev->rx->desc_size / 4);
1120 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1121 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1123 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1124 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1125 rt2x00dev->rx->data_dma);
1126 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1128 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1129 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1130 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1131 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1132 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1133 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_MGMT, 0);
1134 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1136 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1137 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1138 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1139 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1140 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1141 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1142 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1144 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1145 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1146 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1151 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1155 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1156 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1157 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1158 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1159 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1161 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1162 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1163 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1164 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1165 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1166 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1167 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1168 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1169 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1170 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1173 * CCK TXD BBP registers
1175 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1176 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1177 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1178 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1179 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1180 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1181 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1182 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1183 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1184 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1187 * OFDM TXD BBP registers
1189 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1190 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1191 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1192 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1193 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1194 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1195 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1196 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1198 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1199 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1200 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1201 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1202 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1203 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1205 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1206 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1207 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1208 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1209 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1210 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1212 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1214 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1216 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1217 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1218 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1220 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1222 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1225 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1228 * Invalidate all Shared Keys (SEC_CSR0),
1229 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1231 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1232 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1233 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1235 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1236 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1237 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1238 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1240 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1242 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1244 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1246 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
1247 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
1248 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
1249 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1251 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1252 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1253 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1254 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1257 * We must clear the error counters.
1258 * These registers are cleared on read,
1259 * so we may pass a useless variable to store the value.
1261 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1262 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1263 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1266 * Reset MAC and BBP registers.
1268 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1269 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1270 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1271 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1273 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1274 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1275 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1276 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1278 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1279 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1280 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1285 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1292 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1293 rt61pci_bbp_read(rt2x00dev, 0, &value);
1294 if ((value != 0xff) && (value != 0x00))
1295 goto continue_csr_init;
1296 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1297 udelay(REGISTER_BUSY_DELAY);
1300 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1304 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1305 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1306 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1307 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1308 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1309 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1310 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1311 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1312 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1313 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1314 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1315 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1316 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1317 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1318 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1319 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1320 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1321 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1322 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1323 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1324 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1325 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1326 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1327 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1329 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1330 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1331 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1333 if (eeprom != 0xffff && eeprom != 0x0000) {
1334 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1335 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1336 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1338 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1341 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1347 * Device state switch handlers.
1349 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1350 enum dev_state state)
1354 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1355 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1356 state == STATE_RADIO_RX_OFF);
1357 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1360 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1361 enum dev_state state)
1363 int mask = (state == STATE_RADIO_IRQ_OFF);
1367 * When interrupts are being enabled, the interrupt registers
1368 * should clear the register to assure a clean state.
1370 if (state == STATE_RADIO_IRQ_ON) {
1371 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1372 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1374 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1375 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1379 * Only toggle the interrupts bits we are going to use.
1380 * Non-checked interrupt bits are disabled by default.
1382 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1383 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1384 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1385 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1386 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1387 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1389 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1390 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1391 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1392 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1393 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1394 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1395 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1396 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1397 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1398 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1401 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1406 * Initialize all registers.
1408 if (rt61pci_init_rings(rt2x00dev) ||
1409 rt61pci_init_registers(rt2x00dev) ||
1410 rt61pci_init_bbp(rt2x00dev)) {
1411 ERROR(rt2x00dev, "Register initialization failed.\n");
1416 * Enable interrupts.
1418 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1423 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1424 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1425 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1430 rt61pci_enable_led(rt2x00dev);
1435 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1442 rt61pci_disable_led(rt2x00dev);
1444 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1447 * Disable synchronisation.
1449 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1454 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1455 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1456 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1457 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1458 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1459 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1460 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1463 * Disable interrupts.
1465 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1468 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1475 put_to_sleep = (state != STATE_AWAKE);
1477 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1478 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1479 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1480 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1483 * Device is not guaranteed to be in the requested state yet.
1484 * We must wait until the register indicates that the
1485 * device has entered the correct state.
1487 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1488 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1490 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1491 if (current_state == !put_to_sleep)
1496 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1497 "current device state %d.\n", !put_to_sleep, current_state);
1502 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1503 enum dev_state state)
1508 case STATE_RADIO_ON:
1509 retval = rt61pci_enable_radio(rt2x00dev);
1511 case STATE_RADIO_OFF:
1512 rt61pci_disable_radio(rt2x00dev);
1514 case STATE_RADIO_RX_ON:
1515 case STATE_RADIO_RX_OFF:
1516 rt61pci_toggle_rx(rt2x00dev, state);
1518 case STATE_DEEP_SLEEP:
1522 retval = rt61pci_set_state(rt2x00dev, state);
1533 * TX descriptor initialization
1535 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1536 struct sk_buff *skb,
1537 struct txdata_entry_desc *desc,
1538 struct ieee80211_tx_control *control)
1540 struct skb_desc *skbdesc = get_skb_desc(skb);
1541 __le32 *txd = skbdesc->desc;
1545 * Start writing the descriptor words.
1547 rt2x00_desc_read(txd, 1, &word);
1548 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1549 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1550 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1551 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1552 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1553 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1554 rt2x00_desc_write(txd, 1, word);
1556 rt2x00_desc_read(txd, 2, &word);
1557 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1558 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1559 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1560 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1561 rt2x00_desc_write(txd, 2, word);
1563 rt2x00_desc_read(txd, 5, &word);
1564 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1565 TXPOWER_TO_DEV(control->power_level));
1566 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1567 rt2x00_desc_write(txd, 5, word);
1569 rt2x00_desc_read(txd, 11, &word);
1570 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1571 rt2x00_desc_write(txd, 11, word);
1573 rt2x00_desc_read(txd, 0, &word);
1574 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1575 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1576 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1577 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1578 rt2x00_set_field32(&word, TXD_W0_ACK,
1579 test_bit(ENTRY_TXD_ACK, &desc->flags));
1580 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1581 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1582 rt2x00_set_field32(&word, TXD_W0_OFDM,
1583 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1584 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1585 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1587 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1588 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1589 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1590 rt2x00_set_field32(&word, TXD_W0_BURST,
1591 test_bit(ENTRY_TXD_BURST, &desc->flags));
1592 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1593 rt2x00_desc_write(txd, 0, word);
1597 * TX data initialization
1599 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1604 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1606 * For Wi-Fi faily generated beacons between participating
1607 * stations. Set TBTT phase adaptive adjustment step to 8us.
1609 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1611 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1612 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1613 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1614 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1619 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1620 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0,
1621 (queue == IEEE80211_TX_QUEUE_DATA0));
1622 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1,
1623 (queue == IEEE80211_TX_QUEUE_DATA1));
1624 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2,
1625 (queue == IEEE80211_TX_QUEUE_DATA2));
1626 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3,
1627 (queue == IEEE80211_TX_QUEUE_DATA3));
1628 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_MGMT,
1629 (queue == IEEE80211_TX_QUEUE_DATA4));
1630 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1634 * RX control handlers
1636 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1642 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1657 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1658 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1661 if (lna == 3 || lna == 2)
1664 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1665 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1667 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1670 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1671 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1674 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1677 static void rt61pci_fill_rxdone(struct data_entry *entry,
1678 struct rxdata_entry_desc *desc)
1680 __le32 *rxd = entry->priv;
1684 rt2x00_desc_read(rxd, 0, &word0);
1685 rt2x00_desc_read(rxd, 1, &word1);
1688 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1689 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1692 * Obtain the status about this packet.
1694 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1695 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1696 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1697 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1698 desc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1702 * Interrupt functions.
1704 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1706 struct data_ring *ring;
1707 struct data_entry *entry;
1708 struct data_entry *entry_done;
1719 * During each loop we will compare the freshly read
1720 * STA_CSR4 register value with the value read from
1721 * the previous loop. If the 2 values are equal then
1722 * we should stop processing because the chance it
1723 * quite big that the device has been unplugged and
1724 * we risk going into an endless loop.
1729 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
1730 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1738 * Skip this entry when it contains an invalid
1739 * ring identication number.
1741 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1742 ring = rt2x00lib_get_ring(rt2x00dev, type);
1743 if (unlikely(!ring))
1747 * Skip this entry when it contains an invalid
1750 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1751 if (unlikely(index >= ring->stats.limit))
1754 entry = &ring->entry[index];
1756 rt2x00_desc_read(txd, 0, &word);
1758 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1759 !rt2x00_get_field32(word, TXD_W0_VALID))
1762 entry_done = rt2x00_get_data_entry_done(ring);
1763 while (entry != entry_done) {
1764 /* Catch up. Just report any entries we missed as
1767 "TX status report missed for entry %p\n",
1769 rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
1770 entry_done = rt2x00_get_data_entry_done(ring);
1774 * Obtain the status about this packet.
1776 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1777 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1779 rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
1783 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1785 struct rt2x00_dev *rt2x00dev = dev_instance;
1790 * Get the interrupt sources & saved to local variable.
1791 * Write register value back to clear pending interrupts.
1793 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
1794 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1796 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1797 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1799 if (!reg && !reg_mcu)
1802 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1806 * Handle interrupts, walk through all bits
1807 * and run the tasks, the bits are checked in order of
1812 * 1 - Rx ring done interrupt.
1814 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1815 rt2x00pci_rxdone(rt2x00dev);
1818 * 2 - Tx ring done interrupt.
1820 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1821 rt61pci_txdone(rt2x00dev);
1824 * 3 - Handle MCU command done.
1827 rt2x00pci_register_write(rt2x00dev,
1828 M2H_CMD_DONE_CSR, 0xffffffff);
1834 * Device probe functions.
1836 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1838 struct eeprom_93cx6 eeprom;
1844 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
1846 eeprom.data = rt2x00dev;
1847 eeprom.register_read = rt61pci_eepromregister_read;
1848 eeprom.register_write = rt61pci_eepromregister_write;
1849 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1850 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1851 eeprom.reg_data_in = 0;
1852 eeprom.reg_data_out = 0;
1853 eeprom.reg_data_clock = 0;
1854 eeprom.reg_chip_select = 0;
1856 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1857 EEPROM_SIZE / sizeof(u16));
1860 * Start validation of the data that has been read.
1862 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1863 if (!is_valid_ether_addr(mac)) {
1864 DECLARE_MAC_BUF(macbuf);
1866 random_ether_addr(mac);
1867 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1870 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1871 if (word == 0xffff) {
1872 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1873 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1875 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1877 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1878 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1879 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1880 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1881 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1882 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1885 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1886 if (word == 0xffff) {
1887 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1888 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1889 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1890 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1891 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1892 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1893 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1894 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1897 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1898 if (word == 0xffff) {
1899 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1901 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1902 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1905 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1906 if (word == 0xffff) {
1907 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1908 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1909 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1910 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1913 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1914 if (word == 0xffff) {
1915 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1916 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1917 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1918 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1920 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1921 if (value < -10 || value > 10)
1922 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1923 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1924 if (value < -10 || value > 10)
1925 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1926 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1929 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1930 if (word == 0xffff) {
1931 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1932 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1933 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1934 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1936 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1937 if (value < -10 || value > 10)
1938 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1939 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1940 if (value < -10 || value > 10)
1941 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1942 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1948 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1956 * Read EEPROM word for configuration.
1958 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1961 * Identify RF chipset.
1962 * To determine the RT chip we have to read the
1963 * PCI header of the device.
1965 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1966 PCI_CONFIG_HEADER_DEVICE, &device);
1967 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1968 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1969 rt2x00_set_chip(rt2x00dev, device, value, reg);
1971 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1972 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1973 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1974 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1975 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1980 * Determine number of antenna's.
1982 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1983 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1986 * Identify default antenna configuration.
1988 rt2x00dev->default_ant.tx =
1989 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1990 rt2x00dev->default_ant.rx =
1991 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1994 * Read the Frame type.
1996 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1997 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2000 * Detect if this device has an hardware controlled radio.
2002 #ifdef CONFIG_RT61PCI_RFKILL
2003 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2004 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2005 #endif /* CONFIG_RT61PCI_RFKILL */
2008 * Read frequency offset and RF programming sequence.
2010 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2011 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2012 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2014 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2017 * Read external LNA informations.
2019 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2021 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2022 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2023 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2024 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2027 * When working with a RF2529 chip without double antenna
2028 * the antenna settings should be gathered from the NIC
2031 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2032 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2033 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2035 rt2x00dev->default_ant.tx = ANTENNA_B;
2036 rt2x00dev->default_ant.rx = ANTENNA_A;
2039 rt2x00dev->default_ant.tx = ANTENNA_B;
2040 rt2x00dev->default_ant.rx = ANTENNA_B;
2043 rt2x00dev->default_ant.tx = ANTENNA_A;
2044 rt2x00dev->default_ant.rx = ANTENNA_A;
2047 rt2x00dev->default_ant.tx = ANTENNA_A;
2048 rt2x00dev->default_ant.rx = ANTENNA_B;
2052 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2053 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2054 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2055 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2059 * Store led settings, for correct led behaviour.
2060 * If the eeprom value is invalid,
2061 * switch to default led mode.
2063 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2065 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2067 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2068 rt2x00dev->led_mode);
2069 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2070 rt2x00_get_field16(eeprom,
2071 EEPROM_LED_POLARITY_GPIO_0));
2072 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2073 rt2x00_get_field16(eeprom,
2074 EEPROM_LED_POLARITY_GPIO_1));
2075 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2076 rt2x00_get_field16(eeprom,
2077 EEPROM_LED_POLARITY_GPIO_2));
2078 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2079 rt2x00_get_field16(eeprom,
2080 EEPROM_LED_POLARITY_GPIO_3));
2081 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2082 rt2x00_get_field16(eeprom,
2083 EEPROM_LED_POLARITY_GPIO_4));
2084 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2085 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2086 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2087 rt2x00_get_field16(eeprom,
2088 EEPROM_LED_POLARITY_RDY_G));
2089 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2090 rt2x00_get_field16(eeprom,
2091 EEPROM_LED_POLARITY_RDY_A));
2097 * RF value list for RF5225 & RF5325
2098 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2100 static const struct rf_channel rf_vals_noseq[] = {
2101 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2102 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2103 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2104 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2105 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2106 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2107 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2108 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2109 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2110 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2111 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2112 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2113 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2114 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2116 /* 802.11 UNI / HyperLan 2 */
2117 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2118 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2119 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2120 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2121 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2122 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2123 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2124 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2126 /* 802.11 HyperLan 2 */
2127 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2128 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2129 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2130 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2131 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2132 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2133 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2134 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2135 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2136 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2139 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2140 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2141 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2142 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2143 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2144 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2146 /* MMAC(Japan)J52 ch 34,38,42,46 */
2147 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2148 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2149 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2150 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2154 * RF value list for RF5225 & RF5325
2155 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2157 static const struct rf_channel rf_vals_seq[] = {
2158 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2159 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2160 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2161 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2162 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2163 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2164 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2165 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2166 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2167 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2168 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2169 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2170 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2171 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2173 /* 802.11 UNI / HyperLan 2 */
2174 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2175 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2176 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2177 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2178 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2179 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2180 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2181 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2183 /* 802.11 HyperLan 2 */
2184 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2185 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2186 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2187 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2188 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2189 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2190 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2191 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2192 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2193 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2196 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2197 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2198 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2199 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2200 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2201 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2203 /* MMAC(Japan)J52 ch 34,38,42,46 */
2204 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2205 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2206 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2207 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2210 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2212 struct hw_mode_spec *spec = &rt2x00dev->spec;
2217 * Initialize all hw fields.
2219 rt2x00dev->hw->flags =
2220 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2221 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2222 rt2x00dev->hw->extra_tx_headroom = 0;
2223 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2224 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2225 rt2x00dev->hw->queues = 5;
2227 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2228 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2229 rt2x00_eeprom_addr(rt2x00dev,
2230 EEPROM_MAC_ADDR_0));
2233 * Convert tx_power array in eeprom.
2235 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2236 for (i = 0; i < 14; i++)
2237 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2240 * Initialize hw_mode information.
2242 spec->num_modes = 2;
2243 spec->num_rates = 12;
2244 spec->tx_power_a = NULL;
2245 spec->tx_power_bg = txpower;
2246 spec->tx_power_default = DEFAULT_TXPOWER;
2248 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2249 spec->num_channels = 14;
2250 spec->channels = rf_vals_noseq;
2252 spec->num_channels = 14;
2253 spec->channels = rf_vals_seq;
2256 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2257 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2258 spec->num_modes = 3;
2259 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2261 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2262 for (i = 0; i < 14; i++)
2263 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2265 spec->tx_power_a = txpower;
2269 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2274 * Allocate eeprom data.
2276 retval = rt61pci_validate_eeprom(rt2x00dev);
2280 retval = rt61pci_init_eeprom(rt2x00dev);
2285 * Initialize hw specifications.
2287 rt61pci_probe_hw_mode(rt2x00dev);
2290 * This device requires firmware
2292 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2295 * Set the rssi offset.
2297 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2303 * IEEE80211 stack callback functions.
2305 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2306 unsigned int changed_flags,
2307 unsigned int *total_flags,
2309 struct dev_addr_list *mc_list)
2311 struct rt2x00_dev *rt2x00dev = hw->priv;
2315 * Mask off any flags we are going to ignore from
2316 * the total_flags field.
2327 * Apply some rules to the filters:
2328 * - Some filters imply different filters to be set.
2329 * - Some things we can't filter out at all.
2332 *total_flags |= FIF_ALLMULTI;
2333 if (*total_flags & FIF_OTHER_BSS ||
2334 *total_flags & FIF_PROMISC_IN_BSS)
2335 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2338 * Check if there is any work left for us.
2340 if (rt2x00dev->packet_filter == *total_flags)
2342 rt2x00dev->packet_filter = *total_flags;
2345 * Start configuration steps.
2346 * Note that the version error will always be dropped
2347 * and broadcast frames will always be accepted since
2348 * there is no filter for it at this time.
2350 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
2351 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
2352 !(*total_flags & FIF_FCSFAIL));
2353 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
2354 !(*total_flags & FIF_PLCPFAIL));
2355 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
2356 !(*total_flags & FIF_CONTROL));
2357 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
2358 !(*total_flags & FIF_PROMISC_IN_BSS));
2359 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
2360 !(*total_flags & FIF_PROMISC_IN_BSS));
2361 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2362 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
2363 !(*total_flags & FIF_ALLMULTI));
2364 rt2x00_set_field32(®, TXRX_CSR0_DROP_BORADCAST, 0);
2365 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
2366 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2369 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2370 u32 short_retry, u32 long_retry)
2372 struct rt2x00_dev *rt2x00dev = hw->priv;
2375 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
2376 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2377 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2378 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2383 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2385 struct rt2x00_dev *rt2x00dev = hw->priv;
2389 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2390 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2391 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2392 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2397 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2399 struct rt2x00_dev *rt2x00dev = hw->priv;
2401 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2402 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2405 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2406 struct ieee80211_tx_control *control)
2408 struct rt2x00_dev *rt2x00dev = hw->priv;
2409 struct skb_desc *desc;
2410 struct data_ring *ring;
2411 struct data_entry *entry;
2414 * Just in case the ieee80211 doesn't set this,
2415 * but we need this queue set for the descriptor
2418 control->queue = IEEE80211_TX_QUEUE_BEACON;
2419 ring = rt2x00lib_get_ring(rt2x00dev, control->queue);
2420 entry = rt2x00_get_data_entry(ring);
2423 * We need to append the descriptor in front of the
2426 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2427 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2434 * Add the descriptor in front of the skb.
2436 skb_push(skb, ring->desc_size);
2437 memset(skb->data, 0, ring->desc_size);
2440 * Fill in skb descriptor
2442 desc = get_skb_desc(skb);
2443 desc->desc_len = ring->desc_size;
2444 desc->data_len = skb->len - ring->desc_size;
2445 desc->desc = skb->data;
2446 desc->data = skb->data + ring->desc_size;
2448 desc->entry = entry;
2450 rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2453 * Write entire beacon with descriptor to register,
2454 * and kick the beacon generator.
2456 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2457 skb->data, skb->len);
2458 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2463 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2465 .start = rt2x00mac_start,
2466 .stop = rt2x00mac_stop,
2467 .add_interface = rt2x00mac_add_interface,
2468 .remove_interface = rt2x00mac_remove_interface,
2469 .config = rt2x00mac_config,
2470 .config_interface = rt2x00mac_config_interface,
2471 .configure_filter = rt61pci_configure_filter,
2472 .get_stats = rt2x00mac_get_stats,
2473 .set_retry_limit = rt61pci_set_retry_limit,
2474 .erp_ie_changed = rt2x00mac_erp_ie_changed,
2475 .conf_tx = rt2x00mac_conf_tx,
2476 .get_tx_stats = rt2x00mac_get_tx_stats,
2477 .get_tsf = rt61pci_get_tsf,
2478 .reset_tsf = rt61pci_reset_tsf,
2479 .beacon_update = rt61pci_beacon_update,
2482 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2483 .irq_handler = rt61pci_interrupt,
2484 .probe_hw = rt61pci_probe_hw,
2485 .get_firmware_name = rt61pci_get_firmware_name,
2486 .load_firmware = rt61pci_load_firmware,
2487 .initialize = rt2x00pci_initialize,
2488 .uninitialize = rt2x00pci_uninitialize,
2489 .set_device_state = rt61pci_set_device_state,
2490 .rfkill_poll = rt61pci_rfkill_poll,
2491 .link_stats = rt61pci_link_stats,
2492 .reset_tuner = rt61pci_reset_tuner,
2493 .link_tuner = rt61pci_link_tuner,
2494 .write_tx_desc = rt61pci_write_tx_desc,
2495 .write_tx_data = rt2x00pci_write_tx_data,
2496 .kick_tx_queue = rt61pci_kick_tx_queue,
2497 .fill_rxdone = rt61pci_fill_rxdone,
2498 .config_mac_addr = rt61pci_config_mac_addr,
2499 .config_bssid = rt61pci_config_bssid,
2500 .config_type = rt61pci_config_type,
2501 .config_preamble = rt61pci_config_preamble,
2502 .config = rt61pci_config,
2505 static const struct rt2x00_ops rt61pci_ops = {
2506 .name = KBUILD_MODNAME,
2507 .rxd_size = RXD_DESC_SIZE,
2508 .txd_size = TXD_DESC_SIZE,
2509 .eeprom_size = EEPROM_SIZE,
2511 .lib = &rt61pci_rt2x00_ops,
2512 .hw = &rt61pci_mac80211_ops,
2513 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2514 .debugfs = &rt61pci_rt2x00debug,
2515 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2519 * RT61pci module information.
2521 static struct pci_device_id rt61pci_device_table[] = {
2523 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2525 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2527 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2531 MODULE_AUTHOR(DRV_PROJECT);
2532 MODULE_VERSION(DRV_VERSION);
2533 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2534 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2535 "PCI & PCMCIA chipset based cards");
2536 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2537 MODULE_FIRMWARE(FIRMWARE_RT2561);
2538 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2539 MODULE_FIRMWARE(FIRMWARE_RT2661);
2540 MODULE_LICENSE("GPL");
2542 static struct pci_driver rt61pci_driver = {
2543 .name = KBUILD_MODNAME,
2544 .id_table = rt61pci_device_table,
2545 .probe = rt2x00pci_probe,
2546 .remove = __devexit_p(rt2x00pci_remove),
2547 .suspend = rt2x00pci_suspend,
2548 .resume = rt2x00pci_resume,
2551 static int __init rt61pci_init(void)
2553 return pci_register_driver(&rt61pci_driver);
2556 static void __exit rt61pci_exit(void)
2558 pci_unregister_driver(&rt61pci_driver);
2561 module_init(rt61pci_init);
2562 module_exit(rt61pci_exit);