err.no Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Register access.
  42  * BBP and RF register require indirect register access,
  43  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  44  * These indirect registers work with busy bits,
  45  * and we will try maximal REGISTER_BUSY_COUNT times to access
  46  * the register while taking a REGISTER_BUSY_DELAY us delay
  47  * between each attampt. When the busy bit is still set at that time,
  48  * the access attempt is considered to have failed,
  49  * and we will print an error.
  50  */
  51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  52 {
  53         u32 reg;
  54         unsigned int i;
  55
  56         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  57                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  58                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  59                         break;
  60                 udelay(REGISTER_BUSY_DELAY);
  61         }
  62
  63         return reg;
  64 }
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         /*
  72          * Wait until the BBP becomes ready.
  73          */
  74         reg = rt61pci_bbp_check(rt2x00dev);
  75         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  76                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  77                 return;
  78         }
  79
  80         /*
  81          * Write the data into the BBP.
  82          */
  83         reg = 0;
  84         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  85         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  86         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  87         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  88
  89         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  90 }
  91
  92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  93                              const unsigned int word, u8 *value)
  94 {
  95         u32 reg;
  96
  97         /*
  98          * Wait until the BBP becomes ready.
  99          */
 100         reg = rt61pci_bbp_check(rt2x00dev);
 101         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 102                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 103                 return;
 104         }
 105
 106         /*
 107          * Write the request into the BBP.
 108          */
 109         reg = 0;
 110         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 111         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 112         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 113
 114         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 115
 116         /*
 117          * Wait until the BBP becomes ready.
 118          */
 119         reg = rt61pci_bbp_check(rt2x00dev);
 120         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 121                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 122                 *value = 0xff;
 123                 return;
 124         }
 125
 126         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 127 }
 128
 129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 130                              const unsigned int word, const u32 value)
 131 {
 132         u32 reg;
 133         unsigned int i;
 134
 135         if (!word)
 136                 return;
 137
 138         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 139                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
 140                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 141                         goto rf_write;
 142                 udelay(REGISTER_BUSY_DELAY);
 143         }
 144
 145         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 146         return;
 147
 148 rf_write:
 149         reg = 0;
 150         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 151         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 152         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 153         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 154
 155         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 156         rt2x00_rf_write(rt2x00dev, word, value);
 157 }
 158
 159 #ifdef CONFIG_RT61PCI_LEDS
 160 /*
 161  * This function is only called from rt61pci_led_brightness()
 162  * make gcc happy by placing this function inside the
 163  * same ifdef statement as the caller.
 164  */
 165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 166                                 const u8 command, const u8 token,
 167                                 const u8 arg0, const u8 arg1)
 168 {
 169         u32 reg;
 170
 171         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
 172
 173         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
 174                 ERROR(rt2x00dev, "mcu request error. "
 175                       "Request 0x%02x failed for token 0x%02x.\n",
 176                       command, token);
 177                 return;
 178         }
 179
 180         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 181         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 182         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 183         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 184         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 185
 186         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 187         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 188         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 189         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 190 }
 191 #endif /* CONFIG_RT61PCI_LEDS */
 192
 193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg;
 197
 198         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 199
 200         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 201         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 202         eeprom->reg_data_clock =
 203             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 204         eeprom->reg_chip_select =
 205             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 206 }
 207
 208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 209 {
 210         struct rt2x00_dev *rt2x00dev = eeprom->data;
 211         u32 reg = 0;
 212
 213         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 214         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 215         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 216                            !!eeprom->reg_data_clock);
 217         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 218                            !!eeprom->reg_chip_select);
 219
 220         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 221 }
 222
 223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 224 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 225
 226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
 227                              const unsigned int word, u32 *data)
 228 {
 229         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 230 }
 231
 232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
 233                               const unsigned int word, u32 data)
 234 {
 235         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 236 }
 237
 238 static const struct rt2x00debug rt61pci_rt2x00debug = {
 239         .owner  = THIS_MODULE,
 240         .csr    = {
 241                 .read           = rt61pci_read_csr,
 242                 .write          = rt61pci_write_csr,
 243                 .word_size      = sizeof(u32),
 244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 245         },
 246         .eeprom = {
 247                 .read           = rt2x00_eeprom_read,
 248                 .write          = rt2x00_eeprom_write,
 249                 .word_size      = sizeof(u16),
 250                 .word_count     = EEPROM_SIZE / sizeof(u16),
 251         },
 252         .bbp    = {
 253                 .read           = rt61pci_bbp_read,
 254                 .write          = rt61pci_bbp_write,
 255                 .word_size      = sizeof(u8),
 256                 .word_count     = BBP_SIZE / sizeof(u8),
 257         },
 258         .rf     = {
 259                 .read           = rt2x00_rf_read,
 260                 .write          = rt61pci_rf_write,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 #ifdef CONFIG_RT61PCI_RFKILL
 268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 269 {
 270         u32 reg;
 271
 272         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 273         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 274 }
 275 #else
 276 #define rt61pci_rfkill_poll     NULL
 277 #endif /* CONFIG_RT61PCI_RFKILL */
 278
 279 #ifdef CONFIG_RT61PCI_LEDS
 280 static void rt61pci_led_brightness(struct led_classdev *led_cdev,
 281                                    enum led_brightness brightness)
 282 {
 283         struct rt2x00_led *led =
 284             container_of(led_cdev, struct rt2x00_led, led_dev);
 285         unsigned int enabled = brightness != LED_OFF;
 286         unsigned int a_mode =
 287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 288         unsigned int bg_mode =
 289             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 290
 291         if (led->type == LED_TYPE_RADIO) {
 292                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 293                                    MCU_LEDCS_RADIO_STATUS, enabled);
 294
 295                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 296                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 297                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 298         } else if (led->type == LED_TYPE_ASSOC) {
 299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 300                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 302                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 303
 304                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 305                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 306                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 307         } else if (led->type == LED_TYPE_QUALITY) {
 308                 /*
 309                  * The brightness is divided into 6 levels (0 - 5),
 310                  * this means we need to convert the brightness
 311                  * argument into the matching level within that range.
 312                  */
 313                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 314                                     brightness / (LED_FULL / 6), 0);
 315         }
 316 }
 317 #else
 318 #define rt61pci_led_brightness  NULL
 319 #endif /* CONFIG_RT61PCI_LEDS */
 320
 321 /*
 322  * Configuration handlers.
 323  */
 324 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 325                                 struct rt2x00_intf *intf,
 326                                 struct rt2x00intf_conf *conf,
 327                                 const unsigned int flags)
 328 {
 329         unsigned int beacon_base;
 330         u32 reg;
 331
 332         if (flags & CONFIG_UPDATE_TYPE) {
 333                 /*
 334                  * Clear current synchronisation setup.
 335                  * For the Beacon base registers we only need to clear
 336                  * the first byte since that byte contains the VALID and OWNER
 337                  * bits which (when set to 0) will invalidate the entire beacon.
 338                  */
 339                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 340                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 341
 342                 /*
 343                  * Enable synchronisation.
 344                  */
 345                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 346                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 347                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 348                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 349                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 350         }
 351
 352         if (flags & CONFIG_UPDATE_MAC) {
 353                 reg = le32_to_cpu(conf->mac[1]);
 354                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 355                 conf->mac[1] = cpu_to_le32(reg);
 356
 357                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 358                                               conf->mac, sizeof(conf->mac));
 359         }
 360
 361         if (flags & CONFIG_UPDATE_BSSID) {
 362                 reg = le32_to_cpu(conf->bssid[1]);
 363                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 364                 conf->bssid[1] = cpu_to_le32(reg);
 365
 366                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 367                                               conf->bssid, sizeof(conf->bssid));
 368         }
 369 }
 370
 371 static int rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 372                               struct rt2x00lib_erp *erp)
 373 {
 374         u32 reg;
 375
 376         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 377         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 378         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 379
 380         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 381         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 382                            !!erp->short_preamble);
 383         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 384
 385         return 0;
 386 }
 387
 388 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 389                                    const int basic_rate_mask)
 390 {
 391         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 392 }
 393
 394 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 395                                    struct rf_channel *rf, const int txpower)
 396 {
 397         u8 r3;
 398         u8 r94;
 399         u8 smart;
 400
 401         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 402         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 403
 404         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 405                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 406
 407         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 408         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 409         rt61pci_bbp_write(rt2x00dev, 3, r3);
 410
 411         r94 = 6;
 412         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 413                 r94 += txpower - MAX_TXPOWER;
 414         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 415                 r94 += txpower;
 416         rt61pci_bbp_write(rt2x00dev, 94, r94);
 417
 418         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 419         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 420         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 421         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 422
 423         udelay(200);
 424
 425         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 426         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 427         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 428         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 429
 430         udelay(200);
 431
 432         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 433         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 434         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 435         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 436
 437         msleep(1);
 438 }
 439
 440 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 441                                    const int txpower)
 442 {
 443         struct rf_channel rf;
 444
 445         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 446         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 447         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 448         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 449
 450         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 451 }
 452
 453 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 454                                       struct antenna_setup *ant)
 455 {
 456         u8 r3;
 457         u8 r4;
 458         u8 r77;
 459
 460         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 461         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 462         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 463
 464         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 465                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 466
 467         /*
 468          * Configure the RX antenna.
 469          */
 470         switch (ant->rx) {
 471         case ANTENNA_HW_DIVERSITY:
 472                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 473                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 474                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 475                 break;
 476         case ANTENNA_A:
 477                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 478                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 479                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 480                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 481                 else
 482                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 483                 break;
 484         case ANTENNA_B:
 485         default:
 486                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 487                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 488                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 489                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 490                 else
 491                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 492                 break;
 493         }
 494
 495         rt61pci_bbp_write(rt2x00dev, 77, r77);
 496         rt61pci_bbp_write(rt2x00dev, 3, r3);
 497         rt61pci_bbp_write(rt2x00dev, 4, r4);
 498 }
 499
 500 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 501                                       struct antenna_setup *ant)
 502 {
 503         u8 r3;
 504         u8 r4;
 505         u8 r77;
 506
 507         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 508         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 509         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 510
 511         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 512                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 513         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 514                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 515
 516         /*
 517          * Configure the RX antenna.
 518          */
 519         switch (ant->rx) {
 520         case ANTENNA_HW_DIVERSITY:
 521                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 522                 break;
 523         case ANTENNA_A:
 524                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 525                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 526                 break;
 527         case ANTENNA_B:
 528         default:
 529                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 530                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 531                 break;
 532         }
 533
 534         rt61pci_bbp_write(rt2x00dev, 77, r77);
 535         rt61pci_bbp_write(rt2x00dev, 3, r3);
 536         rt61pci_bbp_write(rt2x00dev, 4, r4);
 537 }
 538
 539 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 540                                            const int p1, const int p2)
 541 {
 542         u32 reg;
 543
 544         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 545
 546         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 547         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 548
 549         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 550         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 551
 552         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 553 }
 554
 555 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 556                                         struct antenna_setup *ant)
 557 {
 558         u8 r3;
 559         u8 r4;
 560         u8 r77;
 561
 562         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 563         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 564         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 565
 566         /*
 567          * Configure the RX antenna.
 568          */
 569         switch (ant->rx) {
 570         case ANTENNA_A:
 571                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 572                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 573                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 574                 break;
 575         case ANTENNA_HW_DIVERSITY:
 576                 /*
 577                  * FIXME: Antenna selection for the rf 2529 is very confusing
 578                  * in the legacy driver. Just default to antenna B until the
 579                  * legacy code can be properly translated into rt2x00 code.
 580                  */
 581         case ANTENNA_B:
 582         default:
 583                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 584                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 585                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 586                 break;
 587         }
 588
 589         rt61pci_bbp_write(rt2x00dev, 77, r77);
 590         rt61pci_bbp_write(rt2x00dev, 3, r3);
 591         rt61pci_bbp_write(rt2x00dev, 4, r4);
 592 }
 593
 594 struct antenna_sel {
 595         u8 word;
 596         /*
 597          * value[0] -> non-LNA
 598          * value[1] -> LNA
 599          */
 600         u8 value[2];
 601 };
 602
 603 static const struct antenna_sel antenna_sel_a[] = {
 604         { 96,  { 0x58, 0x78 } },
 605         { 104, { 0x38, 0x48 } },
 606         { 75,  { 0xfe, 0x80 } },
 607         { 86,  { 0xfe, 0x80 } },
 608         { 88,  { 0xfe, 0x80 } },
 609         { 35,  { 0x60, 0x60 } },
 610         { 97,  { 0x58, 0x58 } },
 611         { 98,  { 0x58, 0x58 } },
 612 };
 613
 614 static const struct antenna_sel antenna_sel_bg[] = {
 615         { 96,  { 0x48, 0x68 } },
 616         { 104, { 0x2c, 0x3c } },
 617         { 75,  { 0xfe, 0x80 } },
 618         { 86,  { 0xfe, 0x80 } },
 619         { 88,  { 0xfe, 0x80 } },
 620         { 35,  { 0x50, 0x50 } },
 621         { 97,  { 0x48, 0x48 } },
 622         { 98,  { 0x48, 0x48 } },
 623 };
 624
 625 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 626                                    struct antenna_setup *ant)
 627 {
 628         const struct antenna_sel *sel;
 629         unsigned int lna;
 630         unsigned int i;
 631         u32 reg;
 632
 633         /*
 634          * We should never come here because rt2x00lib is supposed
 635          * to catch this and send us the correct antenna explicitely.
 636          */
 637         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 638                ant->tx == ANTENNA_SW_DIVERSITY);
 639
 640         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 641                 sel = antenna_sel_a;
 642                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 643         } else {
 644                 sel = antenna_sel_bg;
 645                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 646         }
 647
 648         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 649                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 650
 651         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 652
 653         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 654                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 655         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 656                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 657
 658         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 659
 660         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 661             rt2x00_rf(&rt2x00dev->chip, RF5325))
 662                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 663         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 664                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 665         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 666                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 667                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 668                 else
 669                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 670         }
 671 }
 672
 673 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 674                                     struct rt2x00lib_conf *libconf)
 675 {
 676         u32 reg;
 677
 678         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 679         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 680         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 681
 682         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 683         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 684         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 685         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 686         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 687
 688         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 689         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 690         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 691
 692         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 693         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 694         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 695
 696         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 697         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 698                            libconf->conf->beacon_int * 16);
 699         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 700 }
 701
 702 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 703                            struct rt2x00lib_conf *libconf,
 704                            const unsigned int flags)
 705 {
 706         if (flags & CONFIG_UPDATE_PHYMODE)
 707                 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
 708         if (flags & CONFIG_UPDATE_CHANNEL)
 709                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 710                                        libconf->conf->power_level);
 711         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 712                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 713         if (flags & CONFIG_UPDATE_ANTENNA)
 714                 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
 715         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 716                 rt61pci_config_duration(rt2x00dev, libconf);
 717 }
 718
 719 /*
 720  * Link tuning
 721  */
 722 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
 723                                struct link_qual *qual)
 724 {
 725         u32 reg;
 726
 727         /*
 728          * Update FCS error count from register.
 729          */
 730         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
 731         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 732
 733         /*
 734          * Update False CCA count from register.
 735          */
 736         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
 737         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 738 }
 739
 740 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 741 {
 742         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
 743         rt2x00dev->link.vgc_level = 0x20;
 744 }
 745
 746 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 747 {
 748         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 749         u8 r17;
 750         u8 up_bound;
 751         u8 low_bound;
 752
 753         rt61pci_bbp_read(rt2x00dev, 17, &r17);
 754
 755         /*
 756          * Determine r17 bounds.
 757          */
 758         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
 759                 low_bound = 0x28;
 760                 up_bound = 0x48;
 761                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
 762                         low_bound += 0x10;
 763                         up_bound += 0x10;
 764                 }
 765         } else {
 766                 low_bound = 0x20;
 767                 up_bound = 0x40;
 768                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 769                         low_bound += 0x10;
 770                         up_bound += 0x10;
 771                 }
 772         }
 773
 774         /*
 775          * If we are not associated, we should go straight to the
 776          * dynamic CCA tuning.
 777          */
 778         if (!rt2x00dev->intf_associated)
 779                 goto dynamic_cca_tune;
 780
 781         /*
 782          * Special big-R17 for very short distance
 783          */
 784         if (rssi >= -35) {
 785                 if (r17 != 0x60)
 786                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
 787                 return;
 788         }
 789
 790         /*
 791          * Special big-R17 for short distance
 792          */
 793         if (rssi >= -58) {
 794                 if (r17 != up_bound)
 795                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
 796                 return;
 797         }
 798
 799         /*
 800          * Special big-R17 for middle-short distance
 801          */
 802         if (rssi >= -66) {
 803                 low_bound += 0x10;
 804                 if (r17 != low_bound)
 805                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
 806                 return;
 807         }
 808
 809         /*
 810          * Special mid-R17 for middle distance
 811          */
 812         if (rssi >= -74) {
 813                 low_bound += 0x08;
 814                 if (r17 != low_bound)
 815                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
 816                 return;
 817         }
 818
 819         /*
 820          * Special case: Change up_bound based on the rssi.
 821          * Lower up_bound when rssi is weaker then -74 dBm.
 822          */
 823         up_bound -= 2 * (-74 - rssi);
 824         if (low_bound > up_bound)
 825                 up_bound = low_bound;
 826
 827         if (r17 > up_bound) {
 828                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
 829                 return;
 830         }
 831
 832 dynamic_cca_tune:
 833
 834         /*
 835          * r17 does not yet exceed upper limit, continue and base
 836          * the r17 tuning on the false CCA count.
 837          */
 838         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
 839                 if (++r17 > up_bound)
 840                         r17 = up_bound;
 841                 rt61pci_bbp_write(rt2x00dev, 17, r17);
 842         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
 843                 if (--r17 < low_bound)
 844                         r17 = low_bound;
 845                 rt61pci_bbp_write(rt2x00dev, 17, r17);
 846         }
 847 }
 848
 849 /*
 850  * Firmware functions
 851  */
 852 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 853 {
 854         char *fw_name;
 855
 856         switch (rt2x00dev->chip.rt) {
 857         case RT2561:
 858                 fw_name = FIRMWARE_RT2561;
 859                 break;
 860         case RT2561s:
 861                 fw_name = FIRMWARE_RT2561s;
 862                 break;
 863         case RT2661:
 864                 fw_name = FIRMWARE_RT2661;
 865                 break;
 866         default:
 867                 fw_name = NULL;
 868                 break;
 869         }
 870
 871         return fw_name;
 872 }
 873
 874 static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
 875 {
 876         u16 crc;
 877
 878         /*
 879          * Use the crc itu-t algorithm.
 880          * The last 2 bytes in the firmware array are the crc checksum itself,
 881          * this means that we should never pass those 2 bytes to the crc
 882          * algorithm.
 883          */
 884         crc = crc_itu_t(0, data, len - 2);
 885         crc = crc_itu_t_byte(crc, 0);
 886         crc = crc_itu_t_byte(crc, 0);
 887
 888         return crc;
 889 }
 890
 891 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
 892                                  const size_t len)
 893 {
 894         int i;
 895         u32 reg;
 896
 897         /*
 898          * Wait for stable hardware.
 899          */
 900         for (i = 0; i < 100; i++) {
 901                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
 902                 if (reg)
 903                         break;
 904                 msleep(1);
 905         }
 906
 907         if (!reg) {
 908                 ERROR(rt2x00dev, "Unstable hardware.\n");
 909                 return -EBUSY;
 910         }
 911
 912         /*
 913          * Prepare MCU and mailbox for firmware loading.
 914          */
 915         reg = 0;
 916         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
 917         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 918         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
 919         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 920         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
 921
 922         /*
 923          * Write firmware to device.
 924          */
 925         reg = 0;
 926         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
 927         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
 928         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 929
 930         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 931                                       data, len);
 932
 933         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
 934         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 935
 936         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
 937         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 938
 939         for (i = 0; i < 100; i++) {
 940                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
 941                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
 942                         break;
 943                 msleep(1);
 944         }
 945
 946         if (i == 100) {
 947                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
 948                 return -EBUSY;
 949         }
 950
 951         /*
 952          * Reset MAC and BBP registers.
 953          */
 954         reg = 0;
 955         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
 956         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
 957         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 958
 959         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
 960         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
 961         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
 962         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 963
 964         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
 965         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
 966         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
 967
 968         return 0;
 969 }
 970
 971 /*
 972  * Initialization functions.
 973  */
 974 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 975                                  struct queue_entry *entry)
 976 {
 977         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 978         u32 word;
 979
 980         rt2x00_desc_read(priv_rx->desc, 5, &word);
 981         rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
 982                            priv_rx->data_dma);
 983         rt2x00_desc_write(priv_rx->desc, 5, word);
 984
 985         rt2x00_desc_read(priv_rx->desc, 0, &word);
 986         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 987         rt2x00_desc_write(priv_rx->desc, 0, word);
 988 }
 989
 990 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 991                                  struct queue_entry *entry)
 992 {
 993         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 994         u32 word;
 995
 996         rt2x00_desc_read(priv_tx->desc, 1, &word);
 997         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
 998         rt2x00_desc_write(priv_tx->desc, 1, word);
 999
1000         rt2x00_desc_read(priv_tx->desc, 5, &word);
1001         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
1002         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
1003         rt2x00_desc_write(priv_tx->desc, 5, word);
1004
1005         rt2x00_desc_read(priv_tx->desc, 6, &word);
1006         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1007                            priv_tx->data_dma);
1008         rt2x00_desc_write(priv_tx->desc, 6, word);
1009
1010         rt2x00_desc_read(priv_tx->desc, 0, &word);
1011         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1012         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1013         rt2x00_desc_write(priv_tx->desc, 0, word);
1014 }
1015
1016 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1017 {
1018         struct queue_entry_priv_pci_rx *priv_rx;
1019         struct queue_entry_priv_pci_tx *priv_tx;
1020         u32 reg;
1021
1022         /*
1023          * Initialize registers.
1024          */
1025         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1026         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1027                            rt2x00dev->tx[0].limit);
1028         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1029                            rt2x00dev->tx[1].limit);
1030         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1031                            rt2x00dev->tx[2].limit);
1032         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1033                            rt2x00dev->tx[3].limit);
1034         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1035
1036         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1037         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1038                            rt2x00dev->tx[0].desc_size / 4);
1039         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1040
1041         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
1042         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1043         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1044                            priv_tx->desc_dma);
1045         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1046
1047         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
1048         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1049         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1050                            priv_tx->desc_dma);
1051         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1052
1053         priv_tx = rt2x00dev->tx[2].entries[0].priv_data;
1054         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1055         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1056                            priv_tx->desc_dma);
1057         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1058
1059         priv_tx = rt2x00dev->tx[3].entries[0].priv_data;
1060         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1061         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1062                            priv_tx->desc_dma);
1063         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1064
1065         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1066         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1067         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1068                            rt2x00dev->rx->desc_size / 4);
1069         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1070         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1071
1072         priv_rx = rt2x00dev->rx->entries[0].priv_data;
1073         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1074         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1075                            priv_rx->desc_dma);
1076         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1077
1078         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1079         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1080         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1081         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1082         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1083         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1084
1085         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1086         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1087         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1088         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1089         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1090         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1091
1092         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1093         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1094         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1095
1096         return 0;
1097 }
1098
1099 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1100 {
1101         u32 reg;
1102
1103         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1104         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1105         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1106         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1107         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1108
1109         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1110         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1111         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1112         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1113         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1114         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1115         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1116         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1117         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1118         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1119
1120         /*
1121          * CCK TXD BBP registers
1122          */
1123         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1124         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1125         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1126         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1127         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1128         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1129         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1130         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1131         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1132         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1133
1134         /*
1135          * OFDM TXD BBP registers
1136          */
1137         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1138         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1139         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1140         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1141         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1142         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1143         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1144         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1145
1146         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1147         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1148         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1149         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1150         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1151         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1152
1153         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1154         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1155         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1156         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1157         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1158         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1159
1160         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1161
1162         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1163
1164         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1165         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1166         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1167
1168         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1169
1170         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1171                 return -EBUSY;
1172
1173         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1174
1175         rt2x00pci_register_read(rt2x00dev, MAC_CSR14, &reg);
1176         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, 70);
1177         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, 30);
1178         rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
1179
1180         /*
1181          * Invalidate all Shared Keys (SEC_CSR0),
1182          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1183          */
1184         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1185         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1186         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1187
1188         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1189         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1190         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1191         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1192
1193         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1194
1195         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1196
1197         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1198
1199         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1200         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1201         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1202         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1203
1204         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1205         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1206         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1207         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1208
1209         /*
1210          * Clear all beacons
1211          * For the Beacon base registers we only need to clear
1212          * the first byte since that byte contains the VALID and OWNER
1213          * bits which (when set to 0) will invalidate the entire beacon.
1214          */
1215         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1216         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1217         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1218         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1219
1220         /*
1221          * We must clear the error counters.
1222          * These registers are cleared on read,
1223          * so we may pass a useless variable to store the value.
1224          */
1225         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1226         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1227         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1228
1229         /*
1230          * Reset MAC and BBP registers.
1231          */
1232         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1233         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1234         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1235         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1236
1237         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1238         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1239         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1240         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1241
1242         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1243         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1244         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1245
1246         return 0;
1247 }
1248
1249 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1250 {
1251         unsigned int i;
1252         u16 eeprom;
1253         u8 reg_id;
1254         u8 value;
1255
1256         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1257                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1258                 if ((value != 0xff) && (value != 0x00))
1259                         goto continue_csr_init;
1260                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1261                 udelay(REGISTER_BUSY_DELAY);
1262         }
1263
1264         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1265         return -EACCES;
1266
1267 continue_csr_init:
1268         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1269         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1270         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1271         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1272         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1273         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1274         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1275         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1276         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1277         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1278         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1279         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1280         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1281         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1282         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1283         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1284         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1285         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1286         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1287         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1288         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1289         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1290         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1291         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1292
1293         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1294                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1295
1296                 if (eeprom != 0xffff && eeprom != 0x0000) {
1297                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1298                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1299                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1300                 }
1301         }
1302
1303         return 0;
1304 }
1305
1306 /*
1307  * Device state switch handlers.
1308  */
1309 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1310                               enum dev_state state)
1311 {
1312         u32 reg;
1313
1314         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1315         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1316                            state == STATE_RADIO_RX_OFF);
1317         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1318 }
1319
1320 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1321                                enum dev_state state)
1322 {
1323         int mask = (state == STATE_RADIO_IRQ_OFF);
1324         u32 reg;
1325
1326         /*
1327          * When interrupts are being enabled, the interrupt registers
1328          * should clear the register to assure a clean state.
1329          */
1330         if (state == STATE_RADIO_IRQ_ON) {
1331                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1332                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1333
1334                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1335                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1336         }
1337
1338         /*
1339          * Only toggle the interrupts bits we are going to use.
1340          * Non-checked interrupt bits are disabled by default.
1341          */
1342         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1343         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1344         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1345         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1346         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1347         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1348
1349         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1350         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1351         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1352         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1353         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1354         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1355         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1356         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1357         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1358         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1359 }
1360
1361 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1362 {
1363         u32 reg;
1364
1365         /*
1366          * Initialize all registers.
1367          */
1368         if (rt61pci_init_queues(rt2x00dev) ||
1369             rt61pci_init_registers(rt2x00dev) ||
1370             rt61pci_init_bbp(rt2x00dev)) {
1371                 ERROR(rt2x00dev, "Register initialization failed.\n");
1372                 return -EIO;
1373         }
1374
1375         /*
1376          * Enable interrupts.
1377          */
1378         rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1379
1380         /*
1381          * Enable RX.
1382          */
1383         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1384         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1385         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1386
1387         return 0;
1388 }
1389
1390 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1391 {
1392         u32 reg;
1393
1394         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1395
1396         /*
1397          * Disable synchronisation.
1398          */
1399         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1400
1401         /*
1402          * Cancel RX and TX.
1403          */
1404         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1405         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1406         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1407         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1408         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1409         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1410
1411         /*
1412          * Disable interrupts.
1413          */
1414         rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1415 }
1416
1417 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1418 {
1419         u32 reg;
1420         unsigned int i;
1421         char put_to_sleep;
1422         char current_state;
1423
1424         put_to_sleep = (state != STATE_AWAKE);
1425
1426         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1427         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1428         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1429         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1430
1431         /*
1432          * Device is not guaranteed to be in the requested state yet.
1433          * We must wait until the register indicates that the
1434          * device has entered the correct state.
1435          */
1436         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1437                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1438                 current_state =
1439                     rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1440                 if (current_state == !put_to_sleep)
1441                         return 0;
1442                 msleep(10);
1443         }
1444
1445         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1446                "current device state %d.\n", !put_to_sleep, current_state);
1447
1448         return -EBUSY;
1449 }
1450
1451 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1452                                     enum dev_state state)
1453 {
1454         int retval = 0;
1455
1456         switch (state) {
1457         case STATE_RADIO_ON:
1458                 retval = rt61pci_enable_radio(rt2x00dev);
1459                 break;
1460         case STATE_RADIO_OFF:
1461                 rt61pci_disable_radio(rt2x00dev);
1462                 break;
1463         case STATE_RADIO_RX_ON:
1464         case STATE_RADIO_RX_ON_LINK:
1465                 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1466                 break;
1467         case STATE_RADIO_RX_OFF:
1468         case STATE_RADIO_RX_OFF_LINK:
1469                 rt61pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1470                 break;
1471         case STATE_DEEP_SLEEP:
1472         case STATE_SLEEP:
1473         case STATE_STANDBY:
1474         case STATE_AWAKE:
1475                 retval = rt61pci_set_state(rt2x00dev, state);
1476                 break;
1477         default:
1478                 retval = -ENOTSUPP;
1479                 break;
1480         }
1481
1482         return retval;
1483 }
1484
1485 /*
1486  * TX descriptor initialization
1487  */
1488 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1489                                     struct sk_buff *skb,
1490                                     struct txentry_desc *txdesc,
1491                                     struct ieee80211_tx_control *control)
1492 {
1493         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1494         __le32 *txd = skbdesc->desc;
1495         u32 word;
1496
1497         /*
1498          * Start writing the descriptor words.
1499          */
1500         rt2x00_desc_read(txd, 1, &word);
1501         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1502         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1503         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1504         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1505         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1506         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1507         rt2x00_desc_write(txd, 1, word);
1508
1509         rt2x00_desc_read(txd, 2, &word);
1510         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1511         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1512         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1513         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1514         rt2x00_desc_write(txd, 2, word);
1515
1516         rt2x00_desc_read(txd, 5, &word);
1517         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1518                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1519         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1520         rt2x00_desc_write(txd, 5, word);
1521
1522         if (skbdesc->desc_len > TXINFO_SIZE) {
1523                 rt2x00_desc_read(txd, 11, &word);
1524                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1525                 rt2x00_desc_write(txd, 11, word);
1526         }
1527
1528         rt2x00_desc_read(txd, 0, &word);
1529         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1530         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1531         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1532                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1533         rt2x00_set_field32(&word, TXD_W0_ACK,
1534                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1535         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1536                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1537         rt2x00_set_field32(&word, TXD_W0_OFDM,
1538                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1539         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1540         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1541                            !!(control->flags &
1542                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1543         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1544         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1545         rt2x00_set_field32(&word, TXD_W0_BURST,
1546                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1547         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1548         rt2x00_desc_write(txd, 0, word);
1549 }
1550
1551 /*
1552  * TX data initialization
1553  */
1554 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1555                                   const unsigned int queue)
1556 {
1557         u32 reg;
1558
1559         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1560                 /*
1561                  * For Wi-Fi faily generated beacons between participating
1562                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1563                  */
1564                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1565
1566                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1567                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1568                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1569                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1570                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1571                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1572                 }
1573                 return;
1574         }
1575
1576         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1577         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0,
1578                            (queue == IEEE80211_TX_QUEUE_DATA0));
1579         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1,
1580                            (queue == IEEE80211_TX_QUEUE_DATA1));
1581         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2,
1582                            (queue == IEEE80211_TX_QUEUE_DATA2));
1583         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3,
1584                            (queue == IEEE80211_TX_QUEUE_DATA3));
1585         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1586 }
1587
1588 /*
1589  * RX control handlers
1590  */
1591 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1592 {
1593         u16 eeprom;
1594         u8 offset;
1595         u8 lna;
1596
1597         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1598         switch (lna) {
1599         case 3:
1600                 offset = 90;
1601                 break;
1602         case 2:
1603                 offset = 74;
1604                 break;
1605         case 1:
1606                 offset = 64;
1607                 break;
1608         default:
1609                 return 0;
1610         }
1611
1612         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1613                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1614                         offset += 14;
1615
1616                 if (lna == 3 || lna == 2)
1617                         offset += 10;
1618
1619                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1620                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1621         } else {
1622                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1623                         offset += 14;
1624
1625                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1626                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1627         }
1628
1629         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1630 }
1631
1632 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1633                                 struct rxdone_entry_desc *rxdesc)
1634 {
1635         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1636         u32 word0;
1637         u32 word1;
1638
1639         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1640         rt2x00_desc_read(priv_rx->desc, 1, &word1);
1641
1642         rxdesc->flags = 0;
1643         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1644                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1645
1646         /*
1647          * Obtain the status about this packet.
1648          * When frame was received with an OFDM bitrate,
1649          * the signal is the PLCP value. If it was received with
1650          * a CCK bitrate the signal is the rate in 100kbit/s.
1651          */
1652         rxdesc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1653         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1654         rxdesc->signal_plcp = rxdesc->ofdm;
1655         rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1656         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1657         rxdesc->my_bss = !!rt2x00_get_field32(word0, RXD_W0_MY_BSS);
1658 }
1659
1660 /*
1661  * Interrupt functions.
1662  */
1663 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1664 {
1665         struct data_queue *queue;
1666         struct queue_entry *entry;
1667         struct queue_entry *entry_done;
1668         struct queue_entry_priv_pci_tx *priv_tx;
1669         struct txdone_entry_desc txdesc;
1670         u32 word;
1671         u32 reg;
1672         u32 old_reg;
1673         int type;
1674         int index;
1675
1676         /*
1677          * During each loop we will compare the freshly read
1678          * STA_CSR4 register value with the value read from
1679          * the previous loop. If the 2 values are equal then
1680          * we should stop processing because the chance it
1681          * quite big that the device has been unplugged and
1682          * we risk going into an endless loop.
1683          */
1684         old_reg = 0;
1685
1686         while (1) {
1687                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1688                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1689                         break;
1690
1691                 if (old_reg == reg)
1692                         break;
1693                 old_reg = reg;
1694
1695                 /*
1696                  * Skip this entry when it contains an invalid
1697                  * queue identication number.
1698                  */
1699                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1700                 queue = rt2x00queue_get_queue(rt2x00dev, type);
1701                 if (unlikely(!queue))
1702                         continue;
1703
1704                 /*
1705                  * Skip this entry when it contains an invalid
1706                  * index number.
1707                  */
1708                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1709                 if (unlikely(index >= queue->limit))
1710                         continue;
1711
1712                 entry = &queue->entries[index];
1713                 priv_tx = entry->priv_data;
1714                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1715
1716                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1717                     !rt2x00_get_field32(word, TXD_W0_VALID))
1718                         return;
1719
1720                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1721                 while (entry != entry_done) {
1722                         /* Catch up.
1723                          * Just report any entries we missed as failed.
1724                          */
1725                         WARNING(rt2x00dev,
1726                                 "TX status report missed for entry %d\n",
1727                                 entry_done->entry_idx);
1728
1729                         txdesc.status = TX_FAIL_OTHER;
1730                         txdesc.retry = 0;
1731
1732                         rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1733                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1734                 }
1735
1736                 /*
1737                  * Obtain the status about this packet.
1738                  */
1739                 txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1740                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1741
1742                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1743         }
1744 }
1745
1746 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1747 {
1748         struct rt2x00_dev *rt2x00dev = dev_instance;
1749         u32 reg_mcu;
1750         u32 reg;
1751
1752         /*
1753          * Get the interrupt sources & saved to local variable.
1754          * Write register value back to clear pending interrupts.
1755          */
1756         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1757         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1758
1759         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1760         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1761
1762         if (!reg && !reg_mcu)
1763                 return IRQ_NONE;
1764
1765         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1766                 return IRQ_HANDLED;
1767
1768         /*
1769          * Handle interrupts, walk through all bits
1770          * and run the tasks, the bits are checked in order of
1771          * priority.
1772          */
1773
1774         /*
1775          * 1 - Rx ring done interrupt.
1776          */
1777         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1778                 rt2x00pci_rxdone(rt2x00dev);
1779
1780         /*
1781          * 2 - Tx ring done interrupt.
1782          */
1783         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1784                 rt61pci_txdone(rt2x00dev);
1785
1786         /*
1787          * 3 - Handle MCU command done.
1788          */
1789         if (reg_mcu)
1790                 rt2x00pci_register_write(rt2x00dev,
1791                                          M2H_CMD_DONE_CSR, 0xffffffff);
1792
1793         return IRQ_HANDLED;
1794 }
1795
1796 /*
1797  * Device probe functions.
1798  */
1799 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1800 {
1801         struct eeprom_93cx6 eeprom;
1802         u32 reg;
1803         u16 word;
1804         u8 *mac;
1805         s8 value;
1806
1807         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1808
1809         eeprom.data = rt2x00dev;
1810         eeprom.register_read = rt61pci_eepromregister_read;
1811         eeprom.register_write = rt61pci_eepromregister_write;
1812         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1813             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1814         eeprom.reg_data_in = 0;
1815         eeprom.reg_data_out = 0;
1816         eeprom.reg_data_clock = 0;
1817         eeprom.reg_chip_select = 0;
1818
1819         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1820                                EEPROM_SIZE / sizeof(u16));
1821
1822         /*
1823          * Start validation of the data that has been read.
1824          */
1825         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1826         if (!is_valid_ether_addr(mac)) {
1827                 DECLARE_MAC_BUF(macbuf);
1828
1829                 random_ether_addr(mac);
1830                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1831         }
1832
1833         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1834         if (word == 0xffff) {
1835                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1836                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1837                                    ANTENNA_B);
1838                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1839                                    ANTENNA_B);
1840                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1841                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1842                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1843                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1844                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1845                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1846         }
1847
1848         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1849         if (word == 0xffff) {
1850                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1851                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1852                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1853                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1854                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1855                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1856                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1857                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1858         }
1859
1860         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1861         if (word == 0xffff) {
1862                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1863                                    LED_MODE_DEFAULT);
1864                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1865                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1866         }
1867
1868         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1869         if (word == 0xffff) {
1870                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1871                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1872                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1873                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1874         }
1875
1876         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1877         if (word == 0xffff) {
1878                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1879                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1880                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1881                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1882         } else {
1883                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1884                 if (value < -10 || value > 10)
1885                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1886                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1887                 if (value < -10 || value > 10)
1888                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1889                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1890         }
1891
1892         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1893         if (word == 0xffff) {
1894                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1895                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1896                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1897                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1898         } else {
1899                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1900                 if (value < -10 || value > 10)
1901                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1902                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1903                 if (value < -10 || value > 10)
1904                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1905                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1906         }
1907
1908         return 0;
1909 }
1910
1911 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1912 {
1913         u32 reg;
1914         u16 value;
1915         u16 eeprom;
1916         u16 device;
1917
1918         /*
1919          * Read EEPROM word for configuration.
1920          */
1921         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1922
1923         /*
1924          * Identify RF chipset.
1925          * To determine the RT chip we have to read the
1926          * PCI header of the device.
1927          */
1928         pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1929                              PCI_CONFIG_HEADER_DEVICE, &device);
1930         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1931         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1932         rt2x00_set_chip(rt2x00dev, device, value, reg);
1933
1934         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1935             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1936             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1937             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1938                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1939                 return -ENODEV;
1940         }
1941
1942         /*
1943          * Determine number of antenna's.
1944          */
1945         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1946                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1947
1948         /*
1949          * Identify default antenna configuration.
1950          */
1951         rt2x00dev->default_ant.tx =
1952             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1953         rt2x00dev->default_ant.rx =
1954             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1955
1956         /*
1957          * Read the Frame type.
1958          */
1959         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1960                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1961
1962         /*
1963          * Detect if this device has an hardware controlled radio.
1964          */
1965 #ifdef CONFIG_RT61PCI_RFKILL
1966         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1967                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1968 #endif /* CONFIG_RT61PCI_RFKILL */
1969
1970         /*
1971          * Read frequency offset and RF programming sequence.
1972          */
1973         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1974         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
1975                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
1976
1977         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
1978
1979         /*
1980          * Read external LNA informations.
1981          */
1982         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1983
1984         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
1985                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
1986         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
1987                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
1988
1989         /*
1990          * When working with a RF2529 chip without double antenna
1991          * the antenna settings should be gathered from the NIC
1992          * eeprom word.
1993          */
1994         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
1995             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
1996                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
1997                 case 0:
1998                         rt2x00dev->default_ant.tx = ANTENNA_B;
1999                         rt2x00dev->default_ant.rx = ANTENNA_A;
2000                         break;
2001                 case 1:
2002                         rt2x00dev->default_ant.tx = ANTENNA_B;
2003                         rt2x00dev->default_ant.rx = ANTENNA_B;
2004                         break;
2005                 case 2:
2006                         rt2x00dev->default_ant.tx = ANTENNA_A;
2007                         rt2x00dev->default_ant.rx = ANTENNA_A;
2008                         break;
2009                 case 3:
2010                         rt2x00dev->default_ant.tx = ANTENNA_A;
2011                         rt2x00dev->default_ant.rx = ANTENNA_B;
2012                         break;
2013                 }
2014
2015                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2016                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2017                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2018                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2019         }
2020
2021         /*
2022          * Store led settings, for correct led behaviour.
2023          * If the eeprom value is invalid,
2024          * switch to default led mode.
2025          */
2026 #ifdef CONFIG_RT61PCI_LEDS
2027         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2028
2029         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2030
2031         switch (value) {
2032         case LED_MODE_TXRX_ACTIVITY:
2033         case LED_MODE_ASUS:
2034         case LED_MODE_ALPHA:
2035         case LED_MODE_DEFAULT:
2036                 rt2x00dev->led_flags =
2037                     LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
2038                 break;
2039         case LED_MODE_SIGNAL_STRENGTH:
2040                 rt2x00dev->led_flags =
2041                     LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
2042                     LED_SUPPORT_QUALITY;
2043                 break;
2044         }
2045
2046         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2047         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2048                            rt2x00_get_field16(eeprom,
2049                                               EEPROM_LED_POLARITY_GPIO_0));
2050         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2051                            rt2x00_get_field16(eeprom,
2052                                               EEPROM_LED_POLARITY_GPIO_1));
2053         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2054                            rt2x00_get_field16(eeprom,
2055                                               EEPROM_LED_POLARITY_GPIO_2));
2056         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2057                            rt2x00_get_field16(eeprom,
2058                                               EEPROM_LED_POLARITY_GPIO_3));
2059         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2060                            rt2x00_get_field16(eeprom,
2061                                               EEPROM_LED_POLARITY_GPIO_4));
2062         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2063                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2064         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2065                            rt2x00_get_field16(eeprom,
2066                                               EEPROM_LED_POLARITY_RDY_G));
2067         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2068                            rt2x00_get_field16(eeprom,
2069                                               EEPROM_LED_POLARITY_RDY_A));
2070 #endif /* CONFIG_RT61PCI_LEDS */
2071
2072         return 0;
2073 }
2074
2075 /*
2076  * RF value list for RF5225 & RF5325
2077  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2078  */
2079 static const struct rf_channel rf_vals_noseq[] = {
2080         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2081         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2082         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2083         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2084         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2085         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2086         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2087         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2088         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2089         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2090         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2091         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2092         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2093         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2094
2095         /* 802.11 UNI / HyperLan 2 */
2096         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2097         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2098         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2099         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2100         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2101         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2102         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2103         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2104
2105         /* 802.11 HyperLan 2 */
2106         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2107         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2108         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2109         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2110         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2111         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2112         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2113         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2114         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2115         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2116
2117         /* 802.11 UNII */
2118         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2119         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2120         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2121         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2122         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2123         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2124
2125         /* MMAC(Japan)J52 ch 34,38,42,46 */
2126         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2127         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2128         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2129         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2130 };
2131
2132 /*
2133  * RF value list for RF5225 & RF5325
2134  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2135  */
2136 static const struct rf_channel rf_vals_seq[] = {
2137         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2138         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2139         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2140         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2141         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2142         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2143         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2144         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2145         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2146         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2147         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2148         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2149         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2150         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2151
2152         /* 802.11 UNI / HyperLan 2 */
2153         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2154         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2155         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2156         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2157         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2158         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2159         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2160         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2161
2162         /* 802.11 HyperLan 2 */
2163         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2164         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2165         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2166         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2167         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2168         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2169         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2170         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2171         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2172         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2173
2174         /* 802.11 UNII */
2175         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2176         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2177         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2178         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2179         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2180         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2181
2182         /* MMAC(Japan)J52 ch 34,38,42,46 */
2183         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2184         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2185         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2186         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2187 };
2188
2189 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2190 {
2191         struct hw_mode_spec *spec = &rt2x00dev->spec;
2192         u8 *txpower;
2193         unsigned int i;
2194
2195         /*
2196          * Initialize all hw fields.
2197          */
2198         rt2x00dev->hw->flags =
2199             IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2200             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2201         rt2x00dev->hw->extra_tx_headroom = 0;
2202         rt2x00dev->hw->max_signal = MAX_SIGNAL;
2203         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2204         rt2x00dev->hw->queues = 4;
2205
2206         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2207         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2208                                 rt2x00_eeprom_addr(rt2x00dev,
2209                                                    EEPROM_MAC_ADDR_0));
2210
2211         /*
2212          * Convert tx_power array in eeprom.
2213          */
2214         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2215         for (i = 0; i < 14; i++)
2216                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2217
2218         /*
2219          * Initialize hw_mode information.
2220          */
2221         spec->supported_bands = SUPPORT_BAND_2GHZ;
2222         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2223         spec->tx_power_a = NULL;
2224         spec->tx_power_bg = txpower;
2225         spec->tx_power_default = DEFAULT_TXPOWER;
2226
2227         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2228                 spec->num_channels = 14;
2229                 spec->channels = rf_vals_noseq;
2230         } else {
2231                 spec->num_channels = 14;
2232                 spec->channels = rf_vals_seq;
2233         }
2234
2235         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2236             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2237                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2238                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2239
2240                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2241                 for (i = 0; i < 14; i++)
2242                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2243
2244                 spec->tx_power_a = txpower;
2245         }
2246 }
2247
2248 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2249 {
2250         int retval;
2251
2252         /*
2253          * Allocate eeprom data.
2254          */
2255         retval = rt61pci_validate_eeprom(rt2x00dev);
2256         if (retval)
2257                 return retval;
2258
2259         retval = rt61pci_init_eeprom(rt2x00dev);
2260         if (retval)
2261                 return retval;
2262
2263         /*
2264          * Initialize hw specifications.
2265          */
2266         rt61pci_probe_hw_mode(rt2x00dev);
2267
2268         /*
2269          * This device requires firmware.
2270          */
2271         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2272
2273         /*
2274          * Set the rssi offset.
2275          */
2276         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2277
2278         return 0;
2279 }
2280
2281 /*
2282  * IEEE80211 stack callback functions.
2283  */
2284 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2285                                      unsigned int changed_flags,
2286                                      unsigned int *total_flags,
2287                                      int mc_count,
2288                                      struct dev_addr_list *mc_list)
2289 {
2290         struct rt2x00_dev *rt2x00dev = hw->priv;
2291         u32 reg;
2292
2293         /*
2294          * Mask off any flags we are going to ignore from
2295          * the total_flags field.
2296          */
2297         *total_flags &=
2298             FIF_ALLMULTI |
2299             FIF_FCSFAIL |
2300             FIF_PLCPFAIL |
2301             FIF_CONTROL |
2302             FIF_OTHER_BSS |
2303             FIF_PROMISC_IN_BSS;
2304
2305         /*
2306          * Apply some rules to the filters:
2307          * - Some filters imply different filters to be set.
2308          * - Some things we can't filter out at all.
2309          * - Multicast filter seems to kill broadcast traffic so never use it.
2310          */
2311         *total_flags |= FIF_ALLMULTI;
2312         if (*total_flags & FIF_OTHER_BSS ||
2313             *total_flags & FIF_PROMISC_IN_BSS)
2314                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2315
2316         /*
2317          * Check if there is any work left for us.
2318          */
2319         if (rt2x00dev->packet_filter == *total_flags)
2320                 return;
2321         rt2x00dev->packet_filter = *total_flags;
2322
2323         /*
2324          * Start configuration steps.
2325          * Note that the version error will always be dropped
2326          * and broadcast frames will always be accepted since
2327          * there is no filter for it at this time.
2328          */
2329         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
2330         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
2331                            !(*total_flags & FIF_FCSFAIL));
2332         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
2333                            !(*total_flags & FIF_PLCPFAIL));
2334         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
2335                            !(*total_flags & FIF_CONTROL));
2336         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
2337                            !(*total_flags & FIF_PROMISC_IN_BSS));
2338         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
2339                            !(*total_flags & FIF_PROMISC_IN_BSS));
2340         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2341         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
2342                            !(*total_flags & FIF_ALLMULTI));
2343         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
2344         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
2345                            !(*total_flags & FIF_CONTROL));
2346         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2347 }
2348
2349 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2350                                    u32 short_retry, u32 long_retry)
2351 {
2352         struct rt2x00_dev *rt2x00dev = hw->priv;
2353         u32 reg;
2354
2355         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2356         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2357         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2358         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2359
2360         return 0;
2361 }
2362
2363 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2364 {
2365         struct rt2x00_dev *rt2x00dev = hw->priv;
2366         u64 tsf;
2367         u32 reg;
2368
2369         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2370         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2371         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2372         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2373
2374         return tsf;
2375 }
2376
2377 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2378                           struct ieee80211_tx_control *control)
2379 {
2380         struct rt2x00_dev *rt2x00dev = hw->priv;
2381         struct rt2x00_intf *intf = vif_to_intf(control->vif);
2382         struct skb_frame_desc *skbdesc;
2383         unsigned int beacon_base;
2384         u32 reg;
2385
2386         if (unlikely(!intf->beacon))
2387                 return -ENOBUFS;
2388
2389         /*
2390          * We need to append the descriptor in front of the
2391          * beacon frame.
2392          */
2393         if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
2394                 if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
2395                                      0, GFP_ATOMIC)) {
2396                         dev_kfree_skb(skb);
2397                         return -ENOMEM;
2398                 }
2399         }
2400
2401         /*
2402          * Add the descriptor in front of the skb.
2403          */
2404         skb_push(skb, intf->beacon->queue->desc_size);
2405         memset(skb->data, 0, intf->beacon->queue->desc_size);
2406
2407         /*
2408          * Fill in skb descriptor
2409          */
2410         skbdesc = get_skb_frame_desc(skb);
2411         memset(skbdesc, 0, sizeof(*skbdesc));
2412         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2413         skbdesc->data = skb->data + intf->beacon->queue->desc_size;
2414         skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
2415         skbdesc->desc = skb->data;
2416         skbdesc->desc_len = intf->beacon->queue->desc_size;
2417         skbdesc->entry = intf->beacon;
2418
2419         /*
2420          * Disable beaconing while we are reloading the beacon data,
2421          * otherwise we might be sending out invalid data.
2422          */
2423         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2424         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2425         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2426         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2427         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2428
2429         /*
2430          * mac80211 doesn't provide the control->queue variable
2431          * for beacons. Set our own queue identification so
2432          * it can be used during descriptor initialization.
2433          */
2434         control->queue = RT2X00_BCN_QUEUE_BEACON;
2435         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
2436
2437         /*
2438          * Write entire beacon with descriptor to register,
2439          * and kick the beacon generator.
2440          */
2441         beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2442         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2443                                       skb->data, skb->len);
2444         rt61pci_kick_tx_queue(rt2x00dev, control->queue);
2445
2446         return 0;
2447 }
2448
2449 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2450         .tx                     = rt2x00mac_tx,
2451         .start                  = rt2x00mac_start,
2452         .stop                   = rt2x00mac_stop,
2453         .add_interface          = rt2x00mac_add_interface,
2454         .remove_interface       = rt2x00mac_remove_interface,
2455         .config                 = rt2x00mac_config,
2456         .config_interface       = rt2x00mac_config_interface,
2457         .configure_filter       = rt61pci_configure_filter,
2458         .get_stats              = rt2x00mac_get_stats,
2459         .set_retry_limit        = rt61pci_set_retry_limit,
2460         .bss_info_changed       = rt2x00mac_bss_info_changed,
2461         .conf_tx                = rt2x00mac_conf_tx,
2462         .get_tx_stats           = rt2x00mac_get_tx_stats,
2463         .get_tsf                = rt61pci_get_tsf,
2464         .beacon_update          = rt61pci_beacon_update,
2465 };
2466
2467 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2468         .irq_handler            = rt61pci_interrupt,
2469         .probe_hw               = rt61pci_probe_hw,
2470         .get_firmware_name      = rt61pci_get_firmware_name,
2471         .get_firmware_crc       = rt61pci_get_firmware_crc,
2472         .load_firmware          = rt61pci_load_firmware,
2473         .initialize             = rt2x00pci_initialize,
2474         .uninitialize           = rt2x00pci_uninitialize,
2475         .init_rxentry           = rt61pci_init_rxentry,
2476         .init_txentry           = rt61pci_init_txentry,
2477         .set_device_state       = rt61pci_set_device_state,
2478         .rfkill_poll            = rt61pci_rfkill_poll,
2479         .link_stats             = rt61pci_link_stats,
2480         .reset_tuner            = rt61pci_reset_tuner,
2481         .link_tuner             = rt61pci_link_tuner,
2482         .led_brightness         = rt61pci_led_brightness,
2483         .write_tx_desc          = rt61pci_write_tx_desc,
2484         .write_tx_data          = rt2x00pci_write_tx_data,
2485         .kick_tx_queue          = rt61pci_kick_tx_queue,
2486         .fill_rxdone            = rt61pci_fill_rxdone,
2487         .config_intf            = rt61pci_config_intf,
2488         .config_erp             = rt61pci_config_erp,
2489         .config                 = rt61pci_config,
2490 };
2491
2492 static const struct data_queue_desc rt61pci_queue_rx = {
2493         .entry_num              = RX_ENTRIES,
2494         .data_size              = DATA_FRAME_SIZE,
2495         .desc_size              = RXD_DESC_SIZE,
2496         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
2497 };
2498
2499 static const struct data_queue_desc rt61pci_queue_tx = {
2500         .entry_num              = TX_ENTRIES,
2501         .data_size              = DATA_FRAME_SIZE,
2502         .desc_size              = TXD_DESC_SIZE,
2503         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
2504 };
2505
2506 static const struct data_queue_desc rt61pci_queue_bcn = {
2507         .entry_num              = 4 * BEACON_ENTRIES,
2508         .data_size              = MGMT_FRAME_SIZE,
2509         .desc_size              = TXINFO_SIZE,
2510         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
2511 };
2512
2513 static const struct rt2x00_ops rt61pci_ops = {
2514         .name           = KBUILD_MODNAME,
2515         .max_sta_intf   = 1,
2516         .max_ap_intf    = 4,
2517         .eeprom_size    = EEPROM_SIZE,
2518         .rf_size        = RF_SIZE,
2519         .rx             = &rt61pci_queue_rx,
2520         .tx             = &rt61pci_queue_tx,
2521         .bcn            = &rt61pci_queue_bcn,
2522         .lib            = &rt61pci_rt2x00_ops,
2523         .hw             = &rt61pci_mac80211_ops,
2524 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2525         .debugfs        = &rt61pci_rt2x00debug,
2526 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2527 };
2528
2529 /*
2530  * RT61pci module information.
2531  */
2532 static struct pci_device_id rt61pci_device_table[] = {
2533         /* RT2561s */
2534         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2535         /* RT2561 v2 */
2536         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2537         /* RT2661 */
2538         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2539         { 0, }
2540 };
2541
2542 MODULE_AUTHOR(DRV_PROJECT);
2543 MODULE_VERSION(DRV_VERSION);
2544 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2545 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2546                         "PCI & PCMCIA chipset based cards");
2547 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2548 MODULE_FIRMWARE(FIRMWARE_RT2561);
2549 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2550 MODULE_FIRMWARE(FIRMWARE_RT2661);
2551 MODULE_LICENSE("GPL");
2552
2553 static struct pci_driver rt61pci_driver = {
2554         .name           = KBUILD_MODNAME,
2555         .id_table       = rt61pci_device_table,
2556         .probe          = rt2x00pci_probe,
2557         .remove         = __devexit_p(rt2x00pci_remove),
2558         .suspend        = rt2x00pci_suspend,
2559         .resume         = rt2x00pci_resume,
2560 };
2561
2562 static int __init rt61pci_init(void)
2563 {
2564         return pci_register_driver(&rt61pci_driver);
2565 }
2566
2567 static void __exit rt61pci_exit(void)
2568 {
2569         pci_unregister_driver(&rt61pci_driver);
2570 }
2571
2572 module_init(rt61pci_init);
2573 module_exit(rt61pci_exit);