2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
28 * Set enviroment defines for rt2x00.h
30 #define DRV_NAME "rt61pci"
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
41 #include "rt2x00pci.h"
46 * BBP and RF register require indirect register access,
47 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
48 * These indirect registers work with busy bits,
49 * and we will try maximal REGISTER_BUSY_COUNT times to access
50 * the register while taking a REGISTER_BUSY_DELAY us delay
51 * between each attampt. When the busy bit is still set at that time,
52 * the access attempt is considered to have failed,
53 * and we will print an error.
55 static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
60 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
61 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
62 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
64 udelay(REGISTER_BUSY_DELAY);
70 static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
76 * Wait until the BBP becomes ready.
78 reg = rt61pci_bbp_check(rt2x00dev);
79 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
80 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
85 * Write the data into the BBP.
88 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
89 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
90 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
91 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
93 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
96 static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
97 const unsigned int word, u8 *value)
102 * Wait until the BBP becomes ready.
104 reg = rt61pci_bbp_check(rt2x00dev);
105 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
106 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
111 * Write the request into the BBP.
114 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
115 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
116 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
118 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
121 * Wait until the BBP becomes ready.
123 reg = rt61pci_bbp_check(rt2x00dev);
124 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
125 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
130 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
133 static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u32 value)
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
143 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
144 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
146 udelay(REGISTER_BUSY_DELAY);
149 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
154 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
155 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
156 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
157 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
159 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
160 rt2x00_rf_write(rt2x00dev, word, value);
163 static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token,
165 const u8 arg0, const u8 arg1)
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
178 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
185 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
199 eeprom->reg_data_clock =
200 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
201 eeprom->reg_chip_select =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
205 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
207 struct rt2x00_dev *rt2x00dev = eeprom->data;
210 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
211 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
212 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
213 !!eeprom->reg_data_clock);
214 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
215 !!eeprom->reg_chip_select);
217 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
220 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
221 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
223 static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
224 const unsigned int word, u32 *data)
226 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
229 static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
230 const unsigned int word, u32 data)
232 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
235 static const struct rt2x00debug rt61pci_rt2x00debug = {
236 .owner = THIS_MODULE,
238 .read = rt61pci_read_csr,
239 .write = rt61pci_write_csr,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_size = sizeof(u16),
247 .word_count = EEPROM_SIZE / sizeof(u16),
250 .read = rt61pci_bbp_read,
251 .write = rt61pci_bbp_write,
252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
258 .word_size = sizeof(u32),
259 .word_count = RF_SIZE / sizeof(u32),
262 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
264 #ifdef CONFIG_RT61PCI_RFKILL
265 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
270 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
273 #define rt61pci_rfkill_poll NULL
274 #endif /* CONFIG_RT61PCI_RFKILL */
277 * Configuration handlers.
279 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, __le32 *mac)
283 tmp = le32_to_cpu(mac[1]);
284 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
285 mac[1] = cpu_to_le32(tmp);
287 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, mac,
288 (2 * sizeof(__le32)));
291 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, __le32 *bssid)
295 tmp = le32_to_cpu(bssid[1]);
296 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
297 bssid[1] = cpu_to_le32(tmp);
299 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, bssid,
300 (2 * sizeof(__le32)));
303 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
309 * Clear current synchronisation setup.
310 * For the Beacon base registers we only need to clear
311 * the first byte since that byte contains the VALID and OWNER
312 * bits which (when set to 0) will invalidate the entire beacon.
314 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
315 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
316 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
317 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
318 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
321 * Enable synchronisation.
323 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
324 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
325 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
326 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
327 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, tsf_sync);
328 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
331 static void rt61pci_config_preamble(struct rt2x00_dev *rt2x00dev,
332 const int short_preamble,
333 const int ack_timeout,
334 const int ack_consume_time)
338 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
339 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, ack_timeout);
340 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
342 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
343 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE,
345 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
348 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
349 const int basic_rate_mask)
351 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
354 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
355 struct rf_channel *rf, const int txpower)
361 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
362 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
364 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
365 rt2x00_rf(&rt2x00dev->chip, RF2527));
367 rt61pci_bbp_read(rt2x00dev, 3, &r3);
368 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
369 rt61pci_bbp_write(rt2x00dev, 3, r3);
372 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
373 r94 += txpower - MAX_TXPOWER;
374 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
376 rt61pci_bbp_write(rt2x00dev, 94, r94);
378 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
379 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
380 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
381 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
385 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
386 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
387 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
388 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
392 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
393 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
394 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
395 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
400 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
403 struct rf_channel rf;
405 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
406 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
407 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
408 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
410 rt61pci_config_channel(rt2x00dev, &rf, txpower);
413 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
414 struct antenna_setup *ant)
420 rt61pci_bbp_read(rt2x00dev, 3, &r3);
421 rt61pci_bbp_read(rt2x00dev, 4, &r4);
422 rt61pci_bbp_read(rt2x00dev, 77, &r77);
424 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
425 !rt2x00_rf(&rt2x00dev->chip, RF5225));
428 * Configure the TX antenna.
432 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 0);
434 case ANTENNA_SW_DIVERSITY:
435 case ANTENNA_HW_DIVERSITY:
437 * NOTE: We should never come here because rt2x00lib is
438 * supposed to catch this and send us the correct antenna
439 * explicitely. However we are nog going to bug about this.
440 * Instead, just default to antenna B.
443 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 3);
448 * Configure the RX antenna.
451 case ANTENNA_HW_DIVERSITY:
452 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
453 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
454 (rt2x00dev->curr_hwmode != HWMODE_A));
457 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
458 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
460 case ANTENNA_SW_DIVERSITY:
462 * NOTE: We should never come here because rt2x00lib is
463 * supposed to catch this and send us the correct antenna
464 * explicitely. However we are nog going to bug about this.
465 * Instead, just default to antenna B.
468 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
469 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
473 rt61pci_bbp_write(rt2x00dev, 77, r77);
474 rt61pci_bbp_write(rt2x00dev, 3, r3);
475 rt61pci_bbp_write(rt2x00dev, 4, r4);
478 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
479 struct antenna_setup *ant)
485 rt61pci_bbp_read(rt2x00dev, 3, &r3);
486 rt61pci_bbp_read(rt2x00dev, 4, &r4);
487 rt61pci_bbp_read(rt2x00dev, 77, &r77);
489 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
490 !rt2x00_rf(&rt2x00dev->chip, RF2527));
491 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
492 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
495 * Configure the TX antenna.
499 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 0);
501 case ANTENNA_SW_DIVERSITY:
502 case ANTENNA_HW_DIVERSITY:
504 * NOTE: We should never come here because rt2x00lib is
505 * supposed to catch this and send us the correct antenna
506 * explicitely. However we are nog going to bug about this.
507 * Instead, just default to antenna B.
510 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 3);
515 * Configure the RX antenna.
518 case ANTENNA_HW_DIVERSITY:
519 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
522 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
524 case ANTENNA_SW_DIVERSITY:
526 * NOTE: We should never come here because rt2x00lib is
527 * supposed to catch this and send us the correct antenna
528 * explicitely. However we are nog going to bug about this.
529 * Instead, just default to antenna B.
532 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
536 rt61pci_bbp_write(rt2x00dev, 77, r77);
537 rt61pci_bbp_write(rt2x00dev, 3, r3);
538 rt61pci_bbp_write(rt2x00dev, 4, r4);
541 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
542 const int p1, const int p2)
546 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
549 rt2x00_set_field32(®, MAC_CSR13_BIT4, !!p1);
550 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
551 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
554 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
555 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
556 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
560 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
561 struct antenna_setup *ant)
569 rt61pci_bbp_read(rt2x00dev, 3, &r3);
570 rt61pci_bbp_read(rt2x00dev, 4, &r4);
571 rt61pci_bbp_read(rt2x00dev, 77, &r77);
573 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
574 rx_ant = !!(rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) & 2);
576 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
579 * Configure the TX antenna.
583 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 0);
585 case ANTENNA_SW_DIVERSITY:
586 case ANTENNA_HW_DIVERSITY:
588 * NOTE: We should never come here because rt2x00lib is
589 * supposed to catch this and send us the correct antenna
590 * explicitely. However we are nog going to bug about this.
591 * Instead, just default to antenna B.
594 rt2x00_set_field8(&r77, BBP_R77_TX_ANTENNA, 3);
599 * Configure the RX antenna.
603 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, rx_ant);
605 case ANTENNA_SW_DIVERSITY:
606 case ANTENNA_HW_DIVERSITY:
608 * NOTE: We should never come here because rt2x00lib is
609 * supposed to catch this and send us the correct antenna
610 * explicitely. However we are nog going to bug about this.
611 * Instead, just default to antenna B.
614 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, rx_ant);
619 * FIXME: We are using the default antenna setup to
620 * determine the remaining settings. This because we
621 * need to know what the EEPROM indicated.
622 * It is however unclear if this is required, and overall
623 * using the default antenna settings here is incorrect
624 * since mac80211 might have told us to use fixed settings.
626 if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
627 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
629 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
631 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
632 (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY) &&
633 (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY));
635 rt61pci_bbp_write(rt2x00dev, 77, r77);
636 rt61pci_bbp_write(rt2x00dev, 3, r3);
637 rt61pci_bbp_write(rt2x00dev, 4, r4);
643 * value[0] -> non-LNA
649 static const struct antenna_sel antenna_sel_a[] = {
650 { 96, { 0x58, 0x78 } },
651 { 104, { 0x38, 0x48 } },
652 { 75, { 0xfe, 0x80 } },
653 { 86, { 0xfe, 0x80 } },
654 { 88, { 0xfe, 0x80 } },
655 { 35, { 0x60, 0x60 } },
656 { 97, { 0x58, 0x58 } },
657 { 98, { 0x58, 0x58 } },
660 static const struct antenna_sel antenna_sel_bg[] = {
661 { 96, { 0x48, 0x68 } },
662 { 104, { 0x2c, 0x3c } },
663 { 75, { 0xfe, 0x80 } },
664 { 86, { 0xfe, 0x80 } },
665 { 88, { 0xfe, 0x80 } },
666 { 35, { 0x50, 0x50 } },
667 { 97, { 0x48, 0x48 } },
668 { 98, { 0x48, 0x48 } },
671 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
672 struct antenna_setup *ant)
674 const struct antenna_sel *sel;
679 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
681 if (rt2x00dev->curr_hwmode == HWMODE_A) {
683 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
685 sel = antenna_sel_bg;
686 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
689 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG,
690 (rt2x00dev->curr_hwmode == HWMODE_B ||
691 rt2x00dev->curr_hwmode == HWMODE_G));
692 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A,
693 (rt2x00dev->curr_hwmode == HWMODE_A));
695 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
696 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
698 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
700 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
701 rt2x00_rf(&rt2x00dev->chip, RF5325))
702 rt61pci_config_antenna_5x(rt2x00dev, ant);
703 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
704 rt61pci_config_antenna_2x(rt2x00dev, ant);
705 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
706 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
707 rt61pci_config_antenna_2x(rt2x00dev, ant);
709 rt61pci_config_antenna_2529(rt2x00dev, ant);
713 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
714 struct rt2x00lib_conf *libconf)
718 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
719 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME, libconf->slot_time);
720 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
722 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
723 rt2x00_set_field32(®, MAC_CSR8_SIFS, libconf->sifs);
724 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
725 rt2x00_set_field32(®, MAC_CSR8_EIFS, libconf->eifs);
726 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
728 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
729 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
730 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
732 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
733 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
734 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
736 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
737 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL,
738 libconf->conf->beacon_int * 16);
739 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
742 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
743 const unsigned int flags,
744 struct rt2x00lib_conf *libconf)
746 if (flags & CONFIG_UPDATE_PHYMODE)
747 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
748 if (flags & CONFIG_UPDATE_CHANNEL)
749 rt61pci_config_channel(rt2x00dev, &libconf->rf,
750 libconf->conf->power_level);
751 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
752 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
753 if (flags & CONFIG_UPDATE_ANTENNA)
754 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
755 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
756 rt61pci_config_duration(rt2x00dev, libconf);
762 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
768 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, ®);
769 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
770 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
771 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
773 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_RADIO_STATUS, 1);
774 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_A_STATUS,
775 (rt2x00dev->rx_status.phymode == MODE_IEEE80211A));
776 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LINK_BG_STATUS,
777 (rt2x00dev->rx_status.phymode != MODE_IEEE80211A));
779 arg0 = rt2x00dev->led_reg & 0xff;
780 arg1 = (rt2x00dev->led_reg >> 8) & 0xff;
782 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
785 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
791 led_reg = rt2x00dev->led_reg;
792 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
793 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
794 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
796 arg0 = led_reg & 0xff;
797 arg1 = (led_reg >> 8) & 0xff;
799 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
802 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
806 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
810 * Led handling requires a positive value for the rssi,
811 * to do that correctly we need to add the correction.
813 rssi += rt2x00dev->rssi_offset;
828 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
834 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
835 struct link_qual *qual)
840 * Update FCS error count from register.
842 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
843 qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
846 * Update False CCA count from register.
848 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
849 qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
852 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
854 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
855 rt2x00dev->link.vgc_level = 0x20;
858 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
860 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
866 * Update Led strength
868 rt61pci_activity_led(rt2x00dev, rssi);
870 rt61pci_bbp_read(rt2x00dev, 17, &r17);
873 * Determine r17 bounds.
875 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
878 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
885 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
892 * Special big-R17 for very short distance
896 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
901 * Special big-R17 for short distance
905 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
910 * Special big-R17 for middle-short distance
914 if (r17 != low_bound)
915 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
920 * Special mid-R17 for middle distance
924 if (r17 != low_bound)
925 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
930 * Special case: Change up_bound based on the rssi.
931 * Lower up_bound when rssi is weaker then -74 dBm.
933 up_bound -= 2 * (-74 - rssi);
934 if (low_bound > up_bound)
935 up_bound = low_bound;
937 if (r17 > up_bound) {
938 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
943 * r17 does not yet exceed upper limit, continue and base
944 * the r17 tuning on the false CCA count.
946 if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
947 if (++r17 > up_bound)
949 rt61pci_bbp_write(rt2x00dev, 17, r17);
950 } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
951 if (--r17 < low_bound)
953 rt61pci_bbp_write(rt2x00dev, 17, r17);
958 * Firmware name function.
960 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
964 switch (rt2x00dev->chip.rt) {
966 fw_name = FIRMWARE_RT2561;
969 fw_name = FIRMWARE_RT2561s;
972 fw_name = FIRMWARE_RT2661;
983 * Initialization functions.
985 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
992 * Wait for stable hardware.
994 for (i = 0; i < 100; i++) {
995 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1002 ERROR(rt2x00dev, "Unstable hardware.\n");
1007 * Prepare MCU and mailbox for firmware loading.
1010 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1011 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1012 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1013 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1014 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1017 * Write firmware to device.
1020 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1021 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
1022 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1024 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1027 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
1028 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1030 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
1031 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1033 for (i = 0; i < 100; i++) {
1034 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
1035 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1041 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1046 * Reset MAC and BBP registers.
1049 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1050 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1051 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1053 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1054 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1055 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1056 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1058 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1059 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1060 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1065 static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1067 struct data_ring *ring = rt2x00dev->rx;
1068 struct data_desc *rxd;
1072 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1074 for (i = 0; i < ring->stats.limit; i++) {
1075 rxd = ring->entry[i].priv;
1077 rt2x00_desc_read(rxd, 5, &word);
1078 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1079 ring->entry[i].data_dma);
1080 rt2x00_desc_write(rxd, 5, word);
1082 rt2x00_desc_read(rxd, 0, &word);
1083 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1084 rt2x00_desc_write(rxd, 0, word);
1087 rt2x00_ring_index_clear(rt2x00dev->rx);
1090 static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1092 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1093 struct data_desc *txd;
1097 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1099 for (i = 0; i < ring->stats.limit; i++) {
1100 txd = ring->entry[i].priv;
1102 rt2x00_desc_read(txd, 1, &word);
1103 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1104 rt2x00_desc_write(txd, 1, word);
1106 rt2x00_desc_read(txd, 5, &word);
1107 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1108 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1109 rt2x00_desc_write(txd, 5, word);
1111 rt2x00_desc_read(txd, 6, &word);
1112 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1113 ring->entry[i].data_dma);
1114 rt2x00_desc_write(txd, 6, word);
1116 rt2x00_desc_read(txd, 0, &word);
1117 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1118 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1119 rt2x00_desc_write(txd, 0, word);
1122 rt2x00_ring_index_clear(ring);
1125 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1132 rt61pci_init_rxring(rt2x00dev);
1133 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1134 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1135 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1136 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1137 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1140 * Initialize registers.
1142 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1143 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1144 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1145 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1146 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1147 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1148 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1149 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1150 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1151 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1153 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1154 rt2x00_set_field32(®, TX_RING_CSR1_MGMT_RING_SIZE,
1155 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1156 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1157 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1159 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1161 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1162 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1163 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1164 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1166 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1167 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1168 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1169 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1171 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1172 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1173 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1174 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1176 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1177 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1178 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1179 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1181 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, ®);
1182 rt2x00_set_field32(®, MGMT_BASE_CSR_RING_REGISTER,
1183 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1184 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1186 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1187 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE,
1188 rt2x00dev->rx->stats.limit);
1189 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1190 rt2x00dev->rx->desc_size / 4);
1191 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1192 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1194 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1195 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1196 rt2x00dev->rx->data_dma);
1197 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1199 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1200 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1201 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1202 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1203 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1204 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_MGMT, 0);
1205 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1207 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1208 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1209 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1210 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1211 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1212 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1213 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1215 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1216 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1217 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1222 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1226 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1227 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1228 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1229 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1230 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1232 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1233 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1234 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1235 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1236 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1237 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1238 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1239 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1240 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1241 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1244 * CCK TXD BBP registers
1246 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1247 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1248 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1249 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1250 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1251 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1252 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1253 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1254 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1255 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1258 * OFDM TXD BBP registers
1260 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1261 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1262 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1263 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1264 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1265 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1266 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1267 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1269 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1270 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1271 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1272 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1273 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1274 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1276 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1277 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1278 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1279 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1280 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1281 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1283 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1285 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1287 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1288 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1289 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1291 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1293 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1296 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1299 * Invalidate all Shared Keys (SEC_CSR0),
1300 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1302 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1303 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1304 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1306 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1307 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1308 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1309 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1311 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1313 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1315 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1317 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
1318 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
1319 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
1320 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1322 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1323 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1324 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1325 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1328 * We must clear the error counters.
1329 * These registers are cleared on read,
1330 * so we may pass a useless variable to store the value.
1332 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1333 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1334 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1337 * Reset MAC and BBP registers.
1339 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1340 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1341 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1342 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1344 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1345 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1346 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1347 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1349 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1350 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1351 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1356 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1363 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1364 rt61pci_bbp_read(rt2x00dev, 0, &value);
1365 if ((value != 0xff) && (value != 0x00))
1366 goto continue_csr_init;
1367 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1368 udelay(REGISTER_BUSY_DELAY);
1371 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1375 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1376 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1377 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1378 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1379 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1380 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1381 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1382 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1383 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1384 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1385 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1386 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1387 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1388 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1389 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1390 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1391 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1392 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1393 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1394 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1395 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1396 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1397 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1398 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1400 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1401 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1402 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1404 if (eeprom != 0xffff && eeprom != 0x0000) {
1405 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1406 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1407 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1409 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1412 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1418 * Device state switch handlers.
1420 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1421 enum dev_state state)
1425 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1426 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1427 state == STATE_RADIO_RX_OFF);
1428 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1431 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1432 enum dev_state state)
1434 int mask = (state == STATE_RADIO_IRQ_OFF);
1438 * When interrupts are being enabled, the interrupt registers
1439 * should clear the register to assure a clean state.
1441 if (state == STATE_RADIO_IRQ_ON) {
1442 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1443 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1445 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1446 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1450 * Only toggle the interrupts bits we are going to use.
1451 * Non-checked interrupt bits are disabled by default.
1453 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1454 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1455 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1456 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1457 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1458 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1460 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1461 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1462 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1463 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1464 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1465 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1466 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1467 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1468 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1469 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1472 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1477 * Initialize all registers.
1479 if (rt61pci_init_rings(rt2x00dev) ||
1480 rt61pci_init_registers(rt2x00dev) ||
1481 rt61pci_init_bbp(rt2x00dev)) {
1482 ERROR(rt2x00dev, "Register initialization failed.\n");
1487 * Enable interrupts.
1489 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1494 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1495 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1496 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1501 rt61pci_enable_led(rt2x00dev);
1506 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1513 rt61pci_disable_led(rt2x00dev);
1515 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1518 * Disable synchronisation.
1520 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1525 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1526 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1527 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1528 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1529 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1530 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1531 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1534 * Disable interrupts.
1536 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1539 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1546 put_to_sleep = (state != STATE_AWAKE);
1548 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1549 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1550 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1551 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1554 * Device is not guaranteed to be in the requested state yet.
1555 * We must wait until the register indicates that the
1556 * device has entered the correct state.
1558 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1559 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1561 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1562 if (current_state == !put_to_sleep)
1567 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1568 "current device state %d.\n", !put_to_sleep, current_state);
1573 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1574 enum dev_state state)
1579 case STATE_RADIO_ON:
1580 retval = rt61pci_enable_radio(rt2x00dev);
1582 case STATE_RADIO_OFF:
1583 rt61pci_disable_radio(rt2x00dev);
1585 case STATE_RADIO_RX_ON:
1586 case STATE_RADIO_RX_OFF:
1587 rt61pci_toggle_rx(rt2x00dev, state);
1589 case STATE_DEEP_SLEEP:
1593 retval = rt61pci_set_state(rt2x00dev, state);
1604 * TX descriptor initialization
1606 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1607 struct data_desc *txd,
1608 struct txdata_entry_desc *desc,
1609 struct ieee80211_hdr *ieee80211hdr,
1610 unsigned int length,
1611 struct ieee80211_tx_control *control)
1616 * Start writing the descriptor words.
1618 rt2x00_desc_read(txd, 1, &word);
1619 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1620 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1621 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1622 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1623 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1624 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1625 rt2x00_desc_write(txd, 1, word);
1627 rt2x00_desc_read(txd, 2, &word);
1628 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1629 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1630 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1631 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1632 rt2x00_desc_write(txd, 2, word);
1634 rt2x00_desc_read(txd, 5, &word);
1635 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1636 TXPOWER_TO_DEV(control->power_level));
1637 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1638 rt2x00_desc_write(txd, 5, word);
1640 rt2x00_desc_read(txd, 11, &word);
1641 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1642 rt2x00_desc_write(txd, 11, word);
1644 rt2x00_desc_read(txd, 0, &word);
1645 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1646 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1647 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1648 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1649 rt2x00_set_field32(&word, TXD_W0_ACK,
1650 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1651 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1652 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1653 rt2x00_set_field32(&word, TXD_W0_OFDM,
1654 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1655 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1656 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1658 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1659 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1660 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1661 rt2x00_set_field32(&word, TXD_W0_BURST,
1662 test_bit(ENTRY_TXD_BURST, &desc->flags));
1663 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1664 rt2x00_desc_write(txd, 0, word);
1668 * TX data initialization
1670 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1675 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1677 * For Wi-Fi faily generated beacons between participating
1678 * stations. Set TBTT phase adaptive adjustment step to 8us.
1680 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1682 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1683 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1684 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1685 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1690 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1691 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0,
1692 (queue == IEEE80211_TX_QUEUE_DATA0));
1693 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1,
1694 (queue == IEEE80211_TX_QUEUE_DATA1));
1695 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2,
1696 (queue == IEEE80211_TX_QUEUE_DATA2));
1697 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3,
1698 (queue == IEEE80211_TX_QUEUE_DATA3));
1699 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_MGMT,
1700 (queue == IEEE80211_TX_QUEUE_DATA4));
1701 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1705 * RX control handlers
1707 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1713 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1728 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1729 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1732 if (lna == 3 || lna == 2)
1735 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1736 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1738 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1741 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1742 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1745 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1748 static void rt61pci_fill_rxdone(struct data_entry *entry,
1749 struct rxdata_entry_desc *desc)
1751 struct data_desc *rxd = entry->priv;
1755 rt2x00_desc_read(rxd, 0, &word0);
1756 rt2x00_desc_read(rxd, 1, &word1);
1759 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1760 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1763 * Obtain the status about this packet.
1765 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1766 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1767 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1768 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1774 * Interrupt functions.
1776 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1778 struct data_ring *ring;
1779 struct data_entry *entry;
1780 struct data_entry *entry_done;
1781 struct data_desc *txd;
1791 * During each loop we will compare the freshly read
1792 * STA_CSR4 register value with the value read from
1793 * the previous loop. If the 2 values are equal then
1794 * we should stop processing because the chance it
1795 * quite big that the device has been unplugged and
1796 * we risk going into an endless loop.
1801 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
1802 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1810 * Skip this entry when it contains an invalid
1811 * ring identication number.
1813 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1814 ring = rt2x00lib_get_ring(rt2x00dev, type);
1815 if (unlikely(!ring))
1819 * Skip this entry when it contains an invalid
1822 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1823 if (unlikely(index >= ring->stats.limit))
1826 entry = &ring->entry[index];
1828 rt2x00_desc_read(txd, 0, &word);
1830 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1831 !rt2x00_get_field32(word, TXD_W0_VALID))
1834 entry_done = rt2x00_get_data_entry_done(ring);
1835 while (entry != entry_done) {
1836 /* Catch up. Just report any entries we missed as
1839 "TX status report missed for entry %p\n",
1841 rt2x00lib_txdone(entry_done, TX_FAIL_OTHER, 0);
1842 entry_done = rt2x00_get_data_entry_done(ring);
1846 * Obtain the status about this packet.
1848 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1849 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1851 rt2x00lib_txdone(entry, tx_status, retry);
1854 * Make this entry available for reuse.
1857 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1858 rt2x00_desc_write(txd, 0, word);
1859 rt2x00_ring_index_done_inc(entry->ring);
1862 * If the data ring was full before the txdone handler
1863 * we must make sure the packet queue in the mac80211 stack
1864 * is reenabled when the txdone handler has finished.
1866 if (!rt2x00_ring_full(ring))
1867 ieee80211_wake_queue(rt2x00dev->hw,
1868 entry->tx_status.control.queue);
1872 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1874 struct rt2x00_dev *rt2x00dev = dev_instance;
1879 * Get the interrupt sources & saved to local variable.
1880 * Write register value back to clear pending interrupts.
1882 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
1883 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1885 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1886 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1888 if (!reg && !reg_mcu)
1891 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1895 * Handle interrupts, walk through all bits
1896 * and run the tasks, the bits are checked in order of
1901 * 1 - Rx ring done interrupt.
1903 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1904 rt2x00pci_rxdone(rt2x00dev);
1907 * 2 - Tx ring done interrupt.
1909 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1910 rt61pci_txdone(rt2x00dev);
1913 * 3 - Handle MCU command done.
1916 rt2x00pci_register_write(rt2x00dev,
1917 M2H_CMD_DONE_CSR, 0xffffffff);
1923 * Device probe functions.
1925 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1927 struct eeprom_93cx6 eeprom;
1933 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
1935 eeprom.data = rt2x00dev;
1936 eeprom.register_read = rt61pci_eepromregister_read;
1937 eeprom.register_write = rt61pci_eepromregister_write;
1938 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1939 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1940 eeprom.reg_data_in = 0;
1941 eeprom.reg_data_out = 0;
1942 eeprom.reg_data_clock = 0;
1943 eeprom.reg_chip_select = 0;
1945 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1946 EEPROM_SIZE / sizeof(u16));
1949 * Start validation of the data that has been read.
1951 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1952 if (!is_valid_ether_addr(mac)) {
1953 DECLARE_MAC_BUF(macbuf);
1955 random_ether_addr(mac);
1956 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1959 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1960 if (word == 0xffff) {
1961 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1962 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1964 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1966 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1967 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1968 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1969 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1970 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1971 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1974 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1975 if (word == 0xffff) {
1976 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1977 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1978 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1979 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1980 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1981 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1982 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1983 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1986 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1987 if (word == 0xffff) {
1988 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1990 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1991 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1994 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1995 if (word == 0xffff) {
1996 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1997 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1998 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1999 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2002 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2003 if (word == 0xffff) {
2004 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2005 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2006 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2007 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2009 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2010 if (value < -10 || value > 10)
2011 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2012 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2013 if (value < -10 || value > 10)
2014 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2015 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2018 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2019 if (word == 0xffff) {
2020 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2021 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2022 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2023 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2025 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2026 if (value < -10 || value > 10)
2027 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2028 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2029 if (value < -10 || value > 10)
2030 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2031 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2037 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2045 * Read EEPROM word for configuration.
2047 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2050 * Identify RF chipset.
2051 * To determine the RT chip we have to read the
2052 * PCI header of the device.
2054 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2055 PCI_CONFIG_HEADER_DEVICE, &device);
2056 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2057 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
2058 rt2x00_set_chip(rt2x00dev, device, value, reg);
2060 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2061 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2062 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2063 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2064 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2069 * Determine number of antenna's.
2071 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2072 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2075 * Identify default antenna configuration.
2077 rt2x00dev->default_ant.tx =
2078 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2079 rt2x00dev->default_ant.rx =
2080 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2083 * Read the Frame type.
2085 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2086 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2089 * Detect if this device has an hardware controlled radio.
2091 #ifdef CONFIG_RT61PCI_RFKILL
2092 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2093 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2094 #endif /* CONFIG_RT61PCI_RFKILL */
2097 * Read frequency offset and RF programming sequence.
2099 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2100 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2101 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2103 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2106 * Read external LNA informations.
2108 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2110 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2111 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2112 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2113 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2116 * When working with a RF2529 chip without double antenna
2117 * the antenna settings should be gathered from the NIC
2120 if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2121 !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2122 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2124 rt2x00dev->default_ant.tx = ANTENNA_B;
2125 rt2x00dev->default_ant.rx = ANTENNA_A;
2128 rt2x00dev->default_ant.tx = ANTENNA_B;
2129 rt2x00dev->default_ant.rx = ANTENNA_B;
2132 rt2x00dev->default_ant.tx = ANTENNA_A;
2133 rt2x00dev->default_ant.rx = ANTENNA_A;
2136 rt2x00dev->default_ant.tx = ANTENNA_A;
2137 rt2x00dev->default_ant.rx = ANTENNA_B;
2141 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2142 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2143 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2144 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2148 * Store led settings, for correct led behaviour.
2149 * If the eeprom value is invalid,
2150 * switch to default led mode.
2152 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2154 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2156 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2157 rt2x00dev->led_mode);
2158 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2159 rt2x00_get_field16(eeprom,
2160 EEPROM_LED_POLARITY_GPIO_0));
2161 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2162 rt2x00_get_field16(eeprom,
2163 EEPROM_LED_POLARITY_GPIO_1));
2164 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2165 rt2x00_get_field16(eeprom,
2166 EEPROM_LED_POLARITY_GPIO_2));
2167 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2168 rt2x00_get_field16(eeprom,
2169 EEPROM_LED_POLARITY_GPIO_3));
2170 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2171 rt2x00_get_field16(eeprom,
2172 EEPROM_LED_POLARITY_GPIO_4));
2173 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2174 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2175 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2176 rt2x00_get_field16(eeprom,
2177 EEPROM_LED_POLARITY_RDY_G));
2178 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2179 rt2x00_get_field16(eeprom,
2180 EEPROM_LED_POLARITY_RDY_A));
2186 * RF value list for RF5225 & RF5325
2187 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2189 static const struct rf_channel rf_vals_noseq[] = {
2190 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2191 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2192 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2193 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2194 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2195 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2196 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2197 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2198 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2199 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2200 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2201 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2202 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2203 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2205 /* 802.11 UNI / HyperLan 2 */
2206 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2207 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2208 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2209 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2210 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2211 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2212 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2213 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2215 /* 802.11 HyperLan 2 */
2216 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2217 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2218 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2219 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2220 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2221 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2222 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2223 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2224 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2225 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2228 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2229 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2230 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2231 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2232 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2233 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2235 /* MMAC(Japan)J52 ch 34,38,42,46 */
2236 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2237 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2238 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2239 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2243 * RF value list for RF5225 & RF5325
2244 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2246 static const struct rf_channel rf_vals_seq[] = {
2247 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2248 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2249 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2250 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2251 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2252 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2253 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2254 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2255 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2256 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2257 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2258 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2259 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2260 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2262 /* 802.11 UNI / HyperLan 2 */
2263 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2264 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2265 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2266 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2267 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2268 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2269 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2270 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2272 /* 802.11 HyperLan 2 */
2273 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2274 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2275 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2276 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2277 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2278 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2279 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2280 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2281 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2282 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2285 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2286 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2287 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2288 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2289 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2290 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2292 /* MMAC(Japan)J52 ch 34,38,42,46 */
2293 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2294 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2295 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2296 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2299 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2301 struct hw_mode_spec *spec = &rt2x00dev->spec;
2306 * Initialize all hw fields.
2308 rt2x00dev->hw->flags =
2309 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2310 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2311 rt2x00dev->hw->extra_tx_headroom = 0;
2312 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2313 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2314 rt2x00dev->hw->queues = 5;
2316 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2317 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2318 rt2x00_eeprom_addr(rt2x00dev,
2319 EEPROM_MAC_ADDR_0));
2322 * Convert tx_power array in eeprom.
2324 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2325 for (i = 0; i < 14; i++)
2326 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2329 * Initialize hw_mode information.
2331 spec->num_modes = 2;
2332 spec->num_rates = 12;
2333 spec->tx_power_a = NULL;
2334 spec->tx_power_bg = txpower;
2335 spec->tx_power_default = DEFAULT_TXPOWER;
2337 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2338 spec->num_channels = 14;
2339 spec->channels = rf_vals_noseq;
2341 spec->num_channels = 14;
2342 spec->channels = rf_vals_seq;
2345 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2346 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2347 spec->num_modes = 3;
2348 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2350 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2351 for (i = 0; i < 14; i++)
2352 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2354 spec->tx_power_a = txpower;
2358 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2363 * Allocate eeprom data.
2365 retval = rt61pci_validate_eeprom(rt2x00dev);
2369 retval = rt61pci_init_eeprom(rt2x00dev);
2374 * Initialize hw specifications.
2376 rt61pci_probe_hw_mode(rt2x00dev);
2379 * This device requires firmware
2381 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2384 * Set the rssi offset.
2386 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2392 * IEEE80211 stack callback functions.
2394 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2395 unsigned int changed_flags,
2396 unsigned int *total_flags,
2398 struct dev_addr_list *mc_list)
2400 struct rt2x00_dev *rt2x00dev = hw->priv;
2401 struct interface *intf = &rt2x00dev->interface;
2405 * Mask off any flags we are going to ignore from
2406 * the total_flags field.
2417 * Apply some rules to the filters:
2418 * - Some filters imply different filters to be set.
2419 * - Some things we can't filter out at all.
2420 * - Some filters are set based on interface type.
2423 *total_flags |= FIF_ALLMULTI;
2424 if (*total_flags & FIF_OTHER_BSS ||
2425 *total_flags & FIF_PROMISC_IN_BSS)
2426 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2427 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2428 *total_flags |= FIF_PROMISC_IN_BSS;
2431 * Check if there is any work left for us.
2433 if (intf->filter == *total_flags)
2435 intf->filter = *total_flags;
2438 * Start configuration steps.
2439 * Note that the version error will always be dropped
2440 * and broadcast frames will always be accepted since
2441 * there is no filter for it at this time.
2443 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
2444 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
2445 !(*total_flags & FIF_FCSFAIL));
2446 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
2447 !(*total_flags & FIF_PLCPFAIL));
2448 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
2449 !(*total_flags & FIF_CONTROL));
2450 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
2451 !(*total_flags & FIF_PROMISC_IN_BSS));
2452 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
2453 !(*total_flags & FIF_PROMISC_IN_BSS));
2454 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2455 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
2456 !(*total_flags & FIF_ALLMULTI));
2457 rt2x00_set_field32(®, TXRX_CSR0_DROP_BORADCAST, 0);
2458 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
2459 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2462 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2463 u32 short_retry, u32 long_retry)
2465 struct rt2x00_dev *rt2x00dev = hw->priv;
2468 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
2469 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2470 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2471 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2476 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2478 struct rt2x00_dev *rt2x00dev = hw->priv;
2482 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2483 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2484 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2485 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2490 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2492 struct rt2x00_dev *rt2x00dev = hw->priv;
2494 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2495 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2498 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2499 struct ieee80211_tx_control *control)
2501 struct rt2x00_dev *rt2x00dev = hw->priv;
2504 * Just in case the ieee80211 doesn't set this,
2505 * but we need this queue set for the descriptor
2508 control->queue = IEEE80211_TX_QUEUE_BEACON;
2511 * We need to append the descriptor in front of the
2514 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2515 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2522 * First we create the beacon.
2524 skb_push(skb, TXD_DESC_SIZE);
2525 memset(skb->data, 0, TXD_DESC_SIZE);
2527 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
2528 (struct ieee80211_hdr *)(skb->data +
2530 skb->len - TXD_DESC_SIZE, control);
2533 * Write entire beacon with descriptor to register,
2534 * and kick the beacon generator.
2536 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0,
2537 skb->data, skb->len);
2538 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2543 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2545 .start = rt2x00mac_start,
2546 .stop = rt2x00mac_stop,
2547 .add_interface = rt2x00mac_add_interface,
2548 .remove_interface = rt2x00mac_remove_interface,
2549 .config = rt2x00mac_config,
2550 .config_interface = rt2x00mac_config_interface,
2551 .configure_filter = rt61pci_configure_filter,
2552 .get_stats = rt2x00mac_get_stats,
2553 .set_retry_limit = rt61pci_set_retry_limit,
2554 .erp_ie_changed = rt2x00mac_erp_ie_changed,
2555 .conf_tx = rt2x00mac_conf_tx,
2556 .get_tx_stats = rt2x00mac_get_tx_stats,
2557 .get_tsf = rt61pci_get_tsf,
2558 .reset_tsf = rt61pci_reset_tsf,
2559 .beacon_update = rt61pci_beacon_update,
2562 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2563 .irq_handler = rt61pci_interrupt,
2564 .probe_hw = rt61pci_probe_hw,
2565 .get_firmware_name = rt61pci_get_firmware_name,
2566 .load_firmware = rt61pci_load_firmware,
2567 .initialize = rt2x00pci_initialize,
2568 .uninitialize = rt2x00pci_uninitialize,
2569 .set_device_state = rt61pci_set_device_state,
2570 .rfkill_poll = rt61pci_rfkill_poll,
2571 .link_stats = rt61pci_link_stats,
2572 .reset_tuner = rt61pci_reset_tuner,
2573 .link_tuner = rt61pci_link_tuner,
2574 .write_tx_desc = rt61pci_write_tx_desc,
2575 .write_tx_data = rt2x00pci_write_tx_data,
2576 .kick_tx_queue = rt61pci_kick_tx_queue,
2577 .fill_rxdone = rt61pci_fill_rxdone,
2578 .config_mac_addr = rt61pci_config_mac_addr,
2579 .config_bssid = rt61pci_config_bssid,
2580 .config_type = rt61pci_config_type,
2581 .config_preamble = rt61pci_config_preamble,
2582 .config = rt61pci_config,
2585 static const struct rt2x00_ops rt61pci_ops = {
2587 .rxd_size = RXD_DESC_SIZE,
2588 .txd_size = TXD_DESC_SIZE,
2589 .eeprom_size = EEPROM_SIZE,
2591 .lib = &rt61pci_rt2x00_ops,
2592 .hw = &rt61pci_mac80211_ops,
2593 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2594 .debugfs = &rt61pci_rt2x00debug,
2595 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2599 * RT61pci module information.
2601 static struct pci_device_id rt61pci_device_table[] = {
2603 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2605 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2607 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2611 MODULE_AUTHOR(DRV_PROJECT);
2612 MODULE_VERSION(DRV_VERSION);
2613 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2614 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2615 "PCI & PCMCIA chipset based cards");
2616 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2617 MODULE_FIRMWARE(FIRMWARE_RT2561);
2618 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2619 MODULE_FIRMWARE(FIRMWARE_RT2661);
2620 MODULE_LICENSE("GPL");
2622 static struct pci_driver rt61pci_driver = {
2624 .id_table = rt61pci_device_table,
2625 .probe = rt2x00pci_probe,
2626 .remove = __devexit_p(rt2x00pci_remove),
2627 .suspend = rt2x00pci_suspend,
2628 .resume = rt2x00pci_resume,
2631 static int __init rt61pci_init(void)
2633 return pci_register_driver(&rt61pci_driver);
2636 static void __exit rt61pci_exit(void)
2638 pci_unregister_driver(&rt61pci_driver);
2641 module_init(rt61pci_init);
2642 module_exit(rt61pci_exit);