err.no Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt61pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt61pci
  23         Abstract: rt61pci device specific routines.
  24         Supported chipsets: RT2561, RT2561s, RT2661.
  25  */
  26
  27 #include <linux/crc-itu-t.h>
  28 #include <linux/delay.h>
  29 #include <linux/etherdevice.h>
  30 #include <linux/init.h>
  31 #include <linux/kernel.h>
  32 #include <linux/module.h>
  33 #include <linux/pci.h>
  34 #include <linux/eeprom_93cx6.h>
  35
  36 #include "rt2x00.h"
  37 #include "rt2x00pci.h"
  38 #include "rt61pci.h"
  39
  40 /*
  41  * Register access.
  42  * BBP and RF register require indirect register access,
  43  * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
  44  * These indirect registers work with busy bits,
  45  * and we will try maximal REGISTER_BUSY_COUNT times to access
  46  * the register while taking a REGISTER_BUSY_DELAY us delay
  47  * between each attampt. When the busy bit is still set at that time,
  48  * the access attempt is considered to have failed,
  49  * and we will print an error.
  50  */
  51 static u32 rt61pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  52 {
  53         u32 reg;
  54         unsigned int i;
  55
  56         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  57                 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, &reg);
  58                 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
  59                         break;
  60                 udelay(REGISTER_BUSY_DELAY);
  61         }
  62
  63         return reg;
  64 }
  65
  66 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  67                               const unsigned int word, const u8 value)
  68 {
  69         u32 reg;
  70
  71         /*
  72          * Wait until the BBP becomes ready.
  73          */
  74         reg = rt61pci_bbp_check(rt2x00dev);
  75         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
  76                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
  77                 return;
  78         }
  79
  80         /*
  81          * Write the data into the BBP.
  82          */
  83         reg = 0;
  84         rt2x00_set_field32(&reg, PHY_CSR3_VALUE, value);
  85         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
  86         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
  87         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 0);
  88
  89         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
  90 }
  91
  92 static void rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  93                              const unsigned int word, u8 *value)
  94 {
  95         u32 reg;
  96
  97         /*
  98          * Wait until the BBP becomes ready.
  99          */
 100         reg = rt61pci_bbp_check(rt2x00dev);
 101         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 102                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 103                 return;
 104         }
 105
 106         /*
 107          * Write the request into the BBP.
 108          */
 109         reg = 0;
 110         rt2x00_set_field32(&reg, PHY_CSR3_REGNUM, word);
 111         rt2x00_set_field32(&reg, PHY_CSR3_BUSY, 1);
 112         rt2x00_set_field32(&reg, PHY_CSR3_READ_CONTROL, 1);
 113
 114         rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
 115
 116         /*
 117          * Wait until the BBP becomes ready.
 118          */
 119         reg = rt61pci_bbp_check(rt2x00dev);
 120         if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
 121                 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
 122                 *value = 0xff;
 123                 return;
 124         }
 125
 126         *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
 127 }
 128
 129 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev,
 130                              const unsigned int word, const u32 value)
 131 {
 132         u32 reg;
 133         unsigned int i;
 134
 135         if (!word)
 136                 return;
 137
 138         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 139                 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, &reg);
 140                 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
 141                         goto rf_write;
 142                 udelay(REGISTER_BUSY_DELAY);
 143         }
 144
 145         ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
 146         return;
 147
 148 rf_write:
 149         reg = 0;
 150         rt2x00_set_field32(&reg, PHY_CSR4_VALUE, value);
 151         rt2x00_set_field32(&reg, PHY_CSR4_NUMBER_OF_BITS, 21);
 152         rt2x00_set_field32(&reg, PHY_CSR4_IF_SELECT, 0);
 153         rt2x00_set_field32(&reg, PHY_CSR4_BUSY, 1);
 154
 155         rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
 156         rt2x00_rf_write(rt2x00dev, word, value);
 157 }
 158
 159 #ifdef CONFIG_RT61PCI_LEDS
 160 /*
 161  * This function is only called from rt61pci_led_brightness()
 162  * make gcc happy by placing this function inside the
 163  * same ifdef statement as the caller.
 164  */
 165 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev,
 166                                 const u8 command, const u8 token,
 167                                 const u8 arg0, const u8 arg1)
 168 {
 169         u32 reg;
 170
 171         rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, &reg);
 172
 173         if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
 174                 ERROR(rt2x00dev, "mcu request error. "
 175                       "Request 0x%02x failed for token 0x%02x.\n",
 176                       command, token);
 177                 return;
 178         }
 179
 180         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 181         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 182         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 183         rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 184         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
 185
 186         rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, &reg);
 187         rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 188         rt2x00_set_field32(&reg, HOST_CMD_CSR_INTERRUPT_MCU, 1);
 189         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
 190 }
 191 #endif /* CONFIG_RT61PCI_LEDS */
 192
 193 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 194 {
 195         struct rt2x00_dev *rt2x00dev = eeprom->data;
 196         u32 reg;
 197
 198         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
 199
 200         eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
 201         eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
 202         eeprom->reg_data_clock =
 203             !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
 204         eeprom->reg_chip_select =
 205             !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
 206 }
 207
 208 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 209 {
 210         struct rt2x00_dev *rt2x00dev = eeprom->data;
 211         u32 reg = 0;
 212
 213         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
 214         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
 215         rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK,
 216                            !!eeprom->reg_data_clock);
 217         rt2x00_set_field32(&reg, E2PROM_CSR_CHIP_SELECT,
 218                            !!eeprom->reg_chip_select);
 219
 220         rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
 221 }
 222
 223 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 224 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 225
 226 static void rt61pci_read_csr(struct rt2x00_dev *rt2x00dev,
 227                              const unsigned int word, u32 *data)
 228 {
 229         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 230 }
 231
 232 static void rt61pci_write_csr(struct rt2x00_dev *rt2x00dev,
 233                               const unsigned int word, u32 data)
 234 {
 235         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 236 }
 237
 238 static const struct rt2x00debug rt61pci_rt2x00debug = {
 239         .owner  = THIS_MODULE,
 240         .csr    = {
 241                 .read           = rt61pci_read_csr,
 242                 .write          = rt61pci_write_csr,
 243                 .word_size      = sizeof(u32),
 244                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 245         },
 246         .eeprom = {
 247                 .read           = rt2x00_eeprom_read,
 248                 .write          = rt2x00_eeprom_write,
 249                 .word_size      = sizeof(u16),
 250                 .word_count     = EEPROM_SIZE / sizeof(u16),
 251         },
 252         .bbp    = {
 253                 .read           = rt61pci_bbp_read,
 254                 .write          = rt61pci_bbp_write,
 255                 .word_size      = sizeof(u8),
 256                 .word_count     = BBP_SIZE / sizeof(u8),
 257         },
 258         .rf     = {
 259                 .read           = rt2x00_rf_read,
 260                 .write          = rt61pci_rf_write,
 261                 .word_size      = sizeof(u32),
 262                 .word_count     = RF_SIZE / sizeof(u32),
 263         },
 264 };
 265 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 266
 267 #ifdef CONFIG_RT61PCI_RFKILL
 268 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 269 {
 270         u32 reg;
 271
 272         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 273         return rt2x00_get_field32(reg, MAC_CSR13_BIT5);
 274 }
 275 #else
 276 #define rt61pci_rfkill_poll     NULL
 277 #endif /* CONFIG_RT61PCI_RFKILL */
 278
 279 #ifdef CONFIG_RT61PCI_LEDS
 280 static void rt61pci_brightness_set(struct led_classdev *led_cdev,
 281                                    enum led_brightness brightness)
 282 {
 283         struct rt2x00_led *led =
 284             container_of(led_cdev, struct rt2x00_led, led_dev);
 285         unsigned int enabled = brightness != LED_OFF;
 286         unsigned int a_mode =
 287             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 288         unsigned int bg_mode =
 289             (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 290
 291         if (led->type == LED_TYPE_RADIO) {
 292                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 293                                    MCU_LEDCS_RADIO_STATUS, enabled);
 294
 295                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 296                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 297                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 298         } else if (led->type == LED_TYPE_ASSOC) {
 299                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 300                                    MCU_LEDCS_LINK_BG_STATUS, bg_mode);
 301                 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg,
 302                                    MCU_LEDCS_LINK_A_STATUS, a_mode);
 303
 304                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff,
 305                                     (led->rt2x00dev->led_mcu_reg & 0xff),
 306                                     ((led->rt2x00dev->led_mcu_reg >> 8)));
 307         } else if (led->type == LED_TYPE_QUALITY) {
 308                 /*
 309                  * The brightness is divided into 6 levels (0 - 5),
 310                  * this means we need to convert the brightness
 311                  * argument into the matching level within that range.
 312                  */
 313                 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
 314                                     brightness / (LED_FULL / 6), 0);
 315         }
 316 }
 317
 318 static int rt61pci_blink_set(struct led_classdev *led_cdev,
 319                              unsigned long *delay_on,
 320                              unsigned long *delay_off)
 321 {
 322         struct rt2x00_led *led =
 323             container_of(led_cdev, struct rt2x00_led, led_dev);
 324         u32 reg;
 325
 326         rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, &reg);
 327         rt2x00_set_field32(&reg, MAC_CSR14_ON_PERIOD, *delay_on);
 328         rt2x00_set_field32(&reg, MAC_CSR14_OFF_PERIOD, *delay_off);
 329         rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
 330
 331         return 0;
 332 }
 333 #endif /* CONFIG_RT61PCI_LEDS */
 334
 335 /*
 336  * Configuration handlers.
 337  */
 338 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev,
 339                                   const unsigned int filter_flags)
 340 {
 341         u32 reg;
 342
 343         /*
 344          * Start configuration steps.
 345          * Note that the version error will always be dropped
 346          * and broadcast frames will always be accepted since
 347          * there is no filter for it at this time.
 348          */
 349         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 350         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CRC,
 351                            !(filter_flags & FIF_FCSFAIL));
 352         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_PHYSICAL,
 353                            !(filter_flags & FIF_PLCPFAIL));
 354         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_CONTROL,
 355                            !(filter_flags & FIF_CONTROL));
 356         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_NOT_TO_ME,
 357                            !(filter_flags & FIF_PROMISC_IN_BSS));
 358         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_TO_DS,
 359                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 360                            !rt2x00dev->intf_ap_count);
 361         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_VERSION_ERROR, 1);
 362         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_MULTICAST,
 363                            !(filter_flags & FIF_ALLMULTI));
 364         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_BROADCAST, 0);
 365         rt2x00_set_field32(&reg, TXRX_CSR0_DROP_ACK_CTS,
 366                            !(filter_flags & FIF_CONTROL));
 367         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 368 }
 369
 370 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev,
 371                                 struct rt2x00_intf *intf,
 372                                 struct rt2x00intf_conf *conf,
 373                                 const unsigned int flags)
 374 {
 375         unsigned int beacon_base;
 376         u32 reg;
 377
 378         if (flags & CONFIG_UPDATE_TYPE) {
 379                 /*
 380                  * Clear current synchronisation setup.
 381                  * For the Beacon base registers we only need to clear
 382                  * the first byte since that byte contains the VALID and OWNER
 383                  * bits which (when set to 0) will invalidate the entire beacon.
 384                  */
 385                 beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
 386                 rt2x00pci_register_write(rt2x00dev, beacon_base, 0);
 387
 388                 /*
 389                  * Enable synchronisation.
 390                  */
 391                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 392                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
 393                 rt2x00_set_field32(&reg, TXRX_CSR9_TSF_SYNC, conf->sync);
 394                 rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
 395                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 396         }
 397
 398         if (flags & CONFIG_UPDATE_MAC) {
 399                 reg = le32_to_cpu(conf->mac[1]);
 400                 rt2x00_set_field32(&reg, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
 401                 conf->mac[1] = cpu_to_le32(reg);
 402
 403                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2,
 404                                               conf->mac, sizeof(conf->mac));
 405         }
 406
 407         if (flags & CONFIG_UPDATE_BSSID) {
 408                 reg = le32_to_cpu(conf->bssid[1]);
 409                 rt2x00_set_field32(&reg, MAC_CSR5_BSS_ID_MASK, 3);
 410                 conf->bssid[1] = cpu_to_le32(reg);
 411
 412                 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4,
 413                                               conf->bssid, sizeof(conf->bssid));
 414         }
 415 }
 416
 417 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev,
 418                                struct rt2x00lib_erp *erp)
 419 {
 420         u32 reg;
 421
 422         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 423         rt2x00_set_field32(&reg, TXRX_CSR0_RX_ACK_TIMEOUT, erp->ack_timeout);
 424         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 425
 426         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 427         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_PREAMBLE,
 428                            !!erp->short_preamble);
 429         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 430 }
 431
 432 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 433                                    const int basic_rate_mask)
 434 {
 435         rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, basic_rate_mask);
 436 }
 437
 438 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
 439                                    struct rf_channel *rf, const int txpower)
 440 {
 441         u8 r3;
 442         u8 r94;
 443         u8 smart;
 444
 445         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 446         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
 447
 448         smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 449                   rt2x00_rf(&rt2x00dev->chip, RF2527));
 450
 451         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 452         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
 453         rt61pci_bbp_write(rt2x00dev, 3, r3);
 454
 455         r94 = 6;
 456         if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
 457                 r94 += txpower - MAX_TXPOWER;
 458         else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
 459                 r94 += txpower;
 460         rt61pci_bbp_write(rt2x00dev, 94, r94);
 461
 462         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 463         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 464         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 465         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 466
 467         udelay(200);
 468
 469         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 470         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 471         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
 472         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 473
 474         udelay(200);
 475
 476         rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
 477         rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
 478         rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
 479         rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
 480
 481         msleep(1);
 482 }
 483
 484 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 485                                    const int txpower)
 486 {
 487         struct rf_channel rf;
 488
 489         rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
 490         rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
 491         rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
 492         rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
 493
 494         rt61pci_config_channel(rt2x00dev, &rf, txpower);
 495 }
 496
 497 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
 498                                       struct antenna_setup *ant)
 499 {
 500         u8 r3;
 501         u8 r4;
 502         u8 r77;
 503
 504         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 505         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 506         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 507
 508         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 509                           rt2x00_rf(&rt2x00dev->chip, RF5325));
 510
 511         /*
 512          * Configure the RX antenna.
 513          */
 514         switch (ant->rx) {
 515         case ANTENNA_HW_DIVERSITY:
 516                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 517                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 518                                   (rt2x00dev->curr_band != IEEE80211_BAND_5GHZ));
 519                 break;
 520         case ANTENNA_A:
 521                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 522                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 523                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 524                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 525                 else
 526                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 527                 break;
 528         case ANTENNA_B:
 529         default:
 530                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 531                 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
 532                 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ)
 533                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 534                 else
 535                         rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 536                 break;
 537         }
 538
 539         rt61pci_bbp_write(rt2x00dev, 77, r77);
 540         rt61pci_bbp_write(rt2x00dev, 3, r3);
 541         rt61pci_bbp_write(rt2x00dev, 4, r4);
 542 }
 543
 544 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
 545                                       struct antenna_setup *ant)
 546 {
 547         u8 r3;
 548         u8 r4;
 549         u8 r77;
 550
 551         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 552         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 553         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 554
 555         rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
 556                           rt2x00_rf(&rt2x00dev->chip, RF2529));
 557         rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
 558                           !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
 559
 560         /*
 561          * Configure the RX antenna.
 562          */
 563         switch (ant->rx) {
 564         case ANTENNA_HW_DIVERSITY:
 565                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 2);
 566                 break;
 567         case ANTENNA_A:
 568                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 569                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 570                 break;
 571         case ANTENNA_B:
 572         default:
 573                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 574                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 575                 break;
 576         }
 577
 578         rt61pci_bbp_write(rt2x00dev, 77, r77);
 579         rt61pci_bbp_write(rt2x00dev, 3, r3);
 580         rt61pci_bbp_write(rt2x00dev, 4, r4);
 581 }
 582
 583 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
 584                                            const int p1, const int p2)
 585 {
 586         u32 reg;
 587
 588         rt2x00pci_register_read(rt2x00dev, MAC_CSR13, &reg);
 589
 590         rt2x00_set_field32(&reg, MAC_CSR13_BIT4, p1);
 591         rt2x00_set_field32(&reg, MAC_CSR13_BIT12, 0);
 592
 593         rt2x00_set_field32(&reg, MAC_CSR13_BIT3, !p2);
 594         rt2x00_set_field32(&reg, MAC_CSR13_BIT11, 0);
 595
 596         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
 597 }
 598
 599 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
 600                                         struct antenna_setup *ant)
 601 {
 602         u8 r3;
 603         u8 r4;
 604         u8 r77;
 605
 606         rt61pci_bbp_read(rt2x00dev, 3, &r3);
 607         rt61pci_bbp_read(rt2x00dev, 4, &r4);
 608         rt61pci_bbp_read(rt2x00dev, 77, &r77);
 609
 610         /*
 611          * Configure the RX antenna.
 612          */
 613         switch (ant->rx) {
 614         case ANTENNA_A:
 615                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 616                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 0);
 617                 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
 618                 break;
 619         case ANTENNA_HW_DIVERSITY:
 620                 /*
 621                  * FIXME: Antenna selection for the rf 2529 is very confusing
 622                  * in the legacy driver. Just default to antenna B until the
 623                  * legacy code can be properly translated into rt2x00 code.
 624                  */
 625         case ANTENNA_B:
 626         default:
 627                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA_CONTROL, 1);
 628                 rt2x00_set_field8(&r77, BBP_R77_RX_ANTENNA, 3);
 629                 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
 630                 break;
 631         }
 632
 633         rt61pci_bbp_write(rt2x00dev, 77, r77);
 634         rt61pci_bbp_write(rt2x00dev, 3, r3);
 635         rt61pci_bbp_write(rt2x00dev, 4, r4);
 636 }
 637
 638 struct antenna_sel {
 639         u8 word;
 640         /*
 641          * value[0] -> non-LNA
 642          * value[1] -> LNA
 643          */
 644         u8 value[2];
 645 };
 646
 647 static const struct antenna_sel antenna_sel_a[] = {
 648         { 96,  { 0x58, 0x78 } },
 649         { 104, { 0x38, 0x48 } },
 650         { 75,  { 0xfe, 0x80 } },
 651         { 86,  { 0xfe, 0x80 } },
 652         { 88,  { 0xfe, 0x80 } },
 653         { 35,  { 0x60, 0x60 } },
 654         { 97,  { 0x58, 0x58 } },
 655         { 98,  { 0x58, 0x58 } },
 656 };
 657
 658 static const struct antenna_sel antenna_sel_bg[] = {
 659         { 96,  { 0x48, 0x68 } },
 660         { 104, { 0x2c, 0x3c } },
 661         { 75,  { 0xfe, 0x80 } },
 662         { 86,  { 0xfe, 0x80 } },
 663         { 88,  { 0xfe, 0x80 } },
 664         { 35,  { 0x50, 0x50 } },
 665         { 97,  { 0x48, 0x48 } },
 666         { 98,  { 0x48, 0x48 } },
 667 };
 668
 669 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 670                                    struct antenna_setup *ant)
 671 {
 672         const struct antenna_sel *sel;
 673         unsigned int lna;
 674         unsigned int i;
 675         u32 reg;
 676
 677         /*
 678          * We should never come here because rt2x00lib is supposed
 679          * to catch this and send us the correct antenna explicitely.
 680          */
 681         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 682                ant->tx == ANTENNA_SW_DIVERSITY);
 683
 684         if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
 685                 sel = antenna_sel_a;
 686                 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
 687         } else {
 688                 sel = antenna_sel_bg;
 689                 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
 690         }
 691
 692         for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
 693                 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
 694
 695         rt2x00pci_register_read(rt2x00dev, PHY_CSR0, &reg);
 696
 697         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_BG,
 698                            rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
 699         rt2x00_set_field32(&reg, PHY_CSR0_PA_PE_A,
 700                            rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
 701
 702         rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
 703
 704         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
 705             rt2x00_rf(&rt2x00dev->chip, RF5325))
 706                 rt61pci_config_antenna_5x(rt2x00dev, ant);
 707         else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
 708                 rt61pci_config_antenna_2x(rt2x00dev, ant);
 709         else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
 710                 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
 711                         rt61pci_config_antenna_2x(rt2x00dev, ant);
 712                 else
 713                         rt61pci_config_antenna_2529(rt2x00dev, ant);
 714         }
 715 }
 716
 717 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
 718                                     struct rt2x00lib_conf *libconf)
 719 {
 720         u32 reg;
 721
 722         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
 723         rt2x00_set_field32(&reg, MAC_CSR9_SLOT_TIME, libconf->slot_time);
 724         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
 725
 726         rt2x00pci_register_read(rt2x00dev, MAC_CSR8, &reg);
 727         rt2x00_set_field32(&reg, MAC_CSR8_SIFS, libconf->sifs);
 728         rt2x00_set_field32(&reg, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
 729         rt2x00_set_field32(&reg, MAC_CSR8_EIFS, libconf->eifs);
 730         rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
 731
 732         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
 733         rt2x00_set_field32(&reg, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
 734         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
 735
 736         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
 737         rt2x00_set_field32(&reg, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
 738         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
 739
 740         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
 741         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_INTERVAL,
 742                            libconf->conf->beacon_int * 16);
 743         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
 744 }
 745
 746 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
 747                            struct rt2x00lib_conf *libconf,
 748                            const unsigned int flags)
 749 {
 750         if (flags & CONFIG_UPDATE_PHYMODE)
 751                 rt61pci_config_phymode(rt2x00dev, libconf->basic_rates);
 752         if (flags & CONFIG_UPDATE_CHANNEL)
 753                 rt61pci_config_channel(rt2x00dev, &libconf->rf,
 754                                        libconf->conf->power_level);
 755         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 756                 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level);
 757         if (flags & CONFIG_UPDATE_ANTENNA)
 758                 rt61pci_config_antenna(rt2x00dev, &libconf->ant);
 759         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 760                 rt61pci_config_duration(rt2x00dev, libconf);
 761 }
 762
 763 /*
 764  * Link tuning
 765  */
 766 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev,
 767                                struct link_qual *qual)
 768 {
 769         u32 reg;
 770
 771         /*
 772          * Update FCS error count from register.
 773          */
 774         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
 775         qual->rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
 776
 777         /*
 778          * Update False CCA count from register.
 779          */
 780         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
 781         qual->false_cca = rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
 782 }
 783
 784 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 785 {
 786         rt61pci_bbp_write(rt2x00dev, 17, 0x20);
 787         rt2x00dev->link.vgc_level = 0x20;
 788 }
 789
 790 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 791 {
 792         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 793         u8 r17;
 794         u8 up_bound;
 795         u8 low_bound;
 796
 797         rt61pci_bbp_read(rt2x00dev, 17, &r17);
 798
 799         /*
 800          * Determine r17 bounds.
 801          */
 802         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
 803                 low_bound = 0x28;
 804                 up_bound = 0x48;
 805                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
 806                         low_bound += 0x10;
 807                         up_bound += 0x10;
 808                 }
 809         } else {
 810                 low_bound = 0x20;
 811                 up_bound = 0x40;
 812                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
 813                         low_bound += 0x10;
 814                         up_bound += 0x10;
 815                 }
 816         }
 817
 818         /*
 819          * If we are not associated, we should go straight to the
 820          * dynamic CCA tuning.
 821          */
 822         if (!rt2x00dev->intf_associated)
 823                 goto dynamic_cca_tune;
 824
 825         /*
 826          * Special big-R17 for very short distance
 827          */
 828         if (rssi >= -35) {
 829                 if (r17 != 0x60)
 830                         rt61pci_bbp_write(rt2x00dev, 17, 0x60);
 831                 return;
 832         }
 833
 834         /*
 835          * Special big-R17 for short distance
 836          */
 837         if (rssi >= -58) {
 838                 if (r17 != up_bound)
 839                         rt61pci_bbp_write(rt2x00dev, 17, up_bound);
 840                 return;
 841         }
 842
 843         /*
 844          * Special big-R17 for middle-short distance
 845          */
 846         if (rssi >= -66) {
 847                 low_bound += 0x10;
 848                 if (r17 != low_bound)
 849                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
 850                 return;
 851         }
 852
 853         /*
 854          * Special mid-R17 for middle distance
 855          */
 856         if (rssi >= -74) {
 857                 low_bound += 0x08;
 858                 if (r17 != low_bound)
 859                         rt61pci_bbp_write(rt2x00dev, 17, low_bound);
 860                 return;
 861         }
 862
 863         /*
 864          * Special case: Change up_bound based on the rssi.
 865          * Lower up_bound when rssi is weaker then -74 dBm.
 866          */
 867         up_bound -= 2 * (-74 - rssi);
 868         if (low_bound > up_bound)
 869                 up_bound = low_bound;
 870
 871         if (r17 > up_bound) {
 872                 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
 873                 return;
 874         }
 875
 876 dynamic_cca_tune:
 877
 878         /*
 879          * r17 does not yet exceed upper limit, continue and base
 880          * the r17 tuning on the false CCA count.
 881          */
 882         if (rt2x00dev->link.qual.false_cca > 512 && r17 < up_bound) {
 883                 if (++r17 > up_bound)
 884                         r17 = up_bound;
 885                 rt61pci_bbp_write(rt2x00dev, 17, r17);
 886         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > low_bound) {
 887                 if (--r17 < low_bound)
 888                         r17 = low_bound;
 889                 rt61pci_bbp_write(rt2x00dev, 17, r17);
 890         }
 891 }
 892
 893 /*
 894  * Firmware functions
 895  */
 896 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
 897 {
 898         char *fw_name;
 899
 900         switch (rt2x00dev->chip.rt) {
 901         case RT2561:
 902                 fw_name = FIRMWARE_RT2561;
 903                 break;
 904         case RT2561s:
 905                 fw_name = FIRMWARE_RT2561s;
 906                 break;
 907         case RT2661:
 908                 fw_name = FIRMWARE_RT2661;
 909                 break;
 910         default:
 911                 fw_name = NULL;
 912                 break;
 913         }
 914
 915         return fw_name;
 916 }
 917
 918 static u16 rt61pci_get_firmware_crc(void *data, const size_t len)
 919 {
 920         u16 crc;
 921
 922         /*
 923          * Use the crc itu-t algorithm.
 924          * The last 2 bytes in the firmware array are the crc checksum itself,
 925          * this means that we should never pass those 2 bytes to the crc
 926          * algorithm.
 927          */
 928         crc = crc_itu_t(0, data, len - 2);
 929         crc = crc_itu_t_byte(crc, 0);
 930         crc = crc_itu_t_byte(crc, 0);
 931
 932         return crc;
 933 }
 934
 935 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
 936                                  const size_t len)
 937 {
 938         int i;
 939         u32 reg;
 940
 941         /*
 942          * Wait for stable hardware.
 943          */
 944         for (i = 0; i < 100; i++) {
 945                 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
 946                 if (reg)
 947                         break;
 948                 msleep(1);
 949         }
 950
 951         if (!reg) {
 952                 ERROR(rt2x00dev, "Unstable hardware.\n");
 953                 return -EBUSY;
 954         }
 955
 956         /*
 957          * Prepare MCU and mailbox for firmware loading.
 958          */
 959         reg = 0;
 960         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
 961         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 962         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
 963         rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 964         rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
 965
 966         /*
 967          * Write firmware to device.
 968          */
 969         reg = 0;
 970         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 1);
 971         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 1);
 972         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 973
 974         rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
 975                                       data, len);
 976
 977         rt2x00_set_field32(&reg, MCU_CNTL_CSR_SELECT_BANK, 0);
 978         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 979
 980         rt2x00_set_field32(&reg, MCU_CNTL_CSR_RESET, 0);
 981         rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
 982
 983         for (i = 0; i < 100; i++) {
 984                 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, &reg);
 985                 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
 986                         break;
 987                 msleep(1);
 988         }
 989
 990         if (i == 100) {
 991                 ERROR(rt2x00dev, "MCU Control register not ready.\n");
 992                 return -EBUSY;
 993         }
 994
 995         /*
 996          * Reset MAC and BBP registers.
 997          */
 998         reg = 0;
 999         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1000         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1001         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1002
1003         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1004         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1005         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1006         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1007
1008         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1009         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1010         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1011
1012         return 0;
1013 }
1014
1015 /*
1016  * Initialization functions.
1017  */
1018 static void rt61pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
1019                                  struct queue_entry *entry)
1020 {
1021         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1022         u32 word;
1023
1024         rt2x00_desc_read(entry_priv->desc, 5, &word);
1025         rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1026                            entry_priv->data_dma);
1027         rt2x00_desc_write(entry_priv->desc, 5, word);
1028
1029         rt2x00_desc_read(entry_priv->desc, 0, &word);
1030         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1031         rt2x00_desc_write(entry_priv->desc, 0, word);
1032 }
1033
1034 static void rt61pci_init_txentry(struct rt2x00_dev *rt2x00dev,
1035                                  struct queue_entry *entry)
1036 {
1037         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1038         u32 word;
1039
1040         rt2x00_desc_read(entry_priv->desc, 0, &word);
1041         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1042         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1043         rt2x00_desc_write(entry_priv->desc, 0, word);
1044 }
1045
1046 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev)
1047 {
1048         struct queue_entry_priv_pci *entry_priv;
1049         u32 reg;
1050
1051         /*
1052          * Initialize registers.
1053          */
1054         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, &reg);
1055         rt2x00_set_field32(&reg, TX_RING_CSR0_AC0_RING_SIZE,
1056                            rt2x00dev->tx[0].limit);
1057         rt2x00_set_field32(&reg, TX_RING_CSR0_AC1_RING_SIZE,
1058                            rt2x00dev->tx[1].limit);
1059         rt2x00_set_field32(&reg, TX_RING_CSR0_AC2_RING_SIZE,
1060                            rt2x00dev->tx[2].limit);
1061         rt2x00_set_field32(&reg, TX_RING_CSR0_AC3_RING_SIZE,
1062                            rt2x00dev->tx[3].limit);
1063         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1064
1065         rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, &reg);
1066         rt2x00_set_field32(&reg, TX_RING_CSR1_TXD_SIZE,
1067                            rt2x00dev->tx[0].desc_size / 4);
1068         rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1069
1070         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
1071         rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, &reg);
1072         rt2x00_set_field32(&reg, AC0_BASE_CSR_RING_REGISTER,
1073                            entry_priv->desc_dma);
1074         rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1075
1076         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
1077         rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, &reg);
1078         rt2x00_set_field32(&reg, AC1_BASE_CSR_RING_REGISTER,
1079                            entry_priv->desc_dma);
1080         rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1081
1082         entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
1083         rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, &reg);
1084         rt2x00_set_field32(&reg, AC2_BASE_CSR_RING_REGISTER,
1085                            entry_priv->desc_dma);
1086         rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1087
1088         entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
1089         rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, &reg);
1090         rt2x00_set_field32(&reg, AC3_BASE_CSR_RING_REGISTER,
1091                            entry_priv->desc_dma);
1092         rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1093
1094         rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, &reg);
1095         rt2x00_set_field32(&reg, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit);
1096         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_SIZE,
1097                            rt2x00dev->rx->desc_size / 4);
1098         rt2x00_set_field32(&reg, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1099         rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1100
1101         entry_priv = rt2x00dev->rx->entries[0].priv_data;
1102         rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, &reg);
1103         rt2x00_set_field32(&reg, RX_BASE_CSR_RING_REGISTER,
1104                            entry_priv->desc_dma);
1105         rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1106
1107         rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, &reg);
1108         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC0, 2);
1109         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC1, 2);
1110         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC2, 2);
1111         rt2x00_set_field32(&reg, TX_DMA_DST_CSR_DEST_AC3, 2);
1112         rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1113
1114         rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, &reg);
1115         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1116         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1117         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1118         rt2x00_set_field32(&reg, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1119         rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1120
1121         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1122         rt2x00_set_field32(&reg, RX_CNTL_CSR_LOAD_RXD, 1);
1123         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1124
1125         return 0;
1126 }
1127
1128 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1129 {
1130         u32 reg;
1131
1132         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1133         rt2x00_set_field32(&reg, TXRX_CSR0_AUTO_TX_SEQ, 1);
1134         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX, 0);
1135         rt2x00_set_field32(&reg, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1136         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1137
1138         rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, &reg);
1139         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1140         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID0_VALID, 1);
1141         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1142         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID1_VALID, 1);
1143         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1144         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID2_VALID, 1);
1145         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1146         rt2x00_set_field32(&reg, TXRX_CSR1_BBP_ID3_VALID, 1);
1147         rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1148
1149         /*
1150          * CCK TXD BBP registers
1151          */
1152         rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, &reg);
1153         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0, 13);
1154         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID0_VALID, 1);
1155         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1, 12);
1156         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID1_VALID, 1);
1157         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2, 11);
1158         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID2_VALID, 1);
1159         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3, 10);
1160         rt2x00_set_field32(&reg, TXRX_CSR2_BBP_ID3_VALID, 1);
1161         rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1162
1163         /*
1164          * OFDM TXD BBP registers
1165          */
1166         rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, &reg);
1167         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0, 7);
1168         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID0_VALID, 1);
1169         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1, 6);
1170         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID1_VALID, 1);
1171         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2, 5);
1172         rt2x00_set_field32(&reg, TXRX_CSR3_BBP_ID2_VALID, 1);
1173         rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1174
1175         rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, &reg);
1176         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_6MBS, 59);
1177         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_9MBS, 53);
1178         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_12MBS, 49);
1179         rt2x00_set_field32(&reg, TXRX_CSR7_ACK_CTS_18MBS, 46);
1180         rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1181
1182         rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, &reg);
1183         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_24MBS, 44);
1184         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_36MBS, 42);
1185         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_48MBS, 42);
1186         rt2x00_set_field32(&reg, TXRX_CSR8_ACK_CTS_54MBS, 42);
1187         rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1188
1189         rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1190
1191         rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1192
1193         rt2x00pci_register_read(rt2x00dev, MAC_CSR9, &reg);
1194         rt2x00_set_field32(&reg, MAC_CSR9_CW_SELECT, 0);
1195         rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1196
1197         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1198
1199         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1200                 return -EBUSY;
1201
1202         rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1203
1204         /*
1205          * Invalidate all Shared Keys (SEC_CSR0),
1206          * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1207          */
1208         rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1209         rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1210         rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1211
1212         rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1213         rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1214         rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1215         rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1216
1217         rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1218
1219         rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1220
1221         rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1222
1223         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, &reg);
1224         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC0_TX_OP, 0);
1225         rt2x00_set_field32(&reg, AC_TXOP_CSR0_AC1_TX_OP, 0);
1226         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1227
1228         rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, &reg);
1229         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC2_TX_OP, 192);
1230         rt2x00_set_field32(&reg, AC_TXOP_CSR1_AC3_TX_OP, 48);
1231         rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1232
1233         /*
1234          * Clear all beacons
1235          * For the Beacon base registers we only need to clear
1236          * the first byte since that byte contains the VALID and OWNER
1237          * bits which (when set to 0) will invalidate the entire beacon.
1238          */
1239         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
1240         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
1241         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
1242         rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
1243
1244         /*
1245          * We must clear the error counters.
1246          * These registers are cleared on read,
1247          * so we may pass a useless variable to store the value.
1248          */
1249         rt2x00pci_register_read(rt2x00dev, STA_CSR0, &reg);
1250         rt2x00pci_register_read(rt2x00dev, STA_CSR1, &reg);
1251         rt2x00pci_register_read(rt2x00dev, STA_CSR2, &reg);
1252
1253         /*
1254          * Reset MAC and BBP registers.
1255          */
1256         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1257         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 1);
1258         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 1);
1259         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1260
1261         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1262         rt2x00_set_field32(&reg, MAC_CSR1_SOFT_RESET, 0);
1263         rt2x00_set_field32(&reg, MAC_CSR1_BBP_RESET, 0);
1264         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1265
1266         rt2x00pci_register_read(rt2x00dev, MAC_CSR1, &reg);
1267         rt2x00_set_field32(&reg, MAC_CSR1_HOST_READY, 1);
1268         rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1269
1270         return 0;
1271 }
1272
1273 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
1274 {
1275         unsigned int i;
1276         u8 value;
1277
1278         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1279                 rt61pci_bbp_read(rt2x00dev, 0, &value);
1280                 if ((value != 0xff) && (value != 0x00))
1281                         return 0;
1282                 udelay(REGISTER_BUSY_DELAY);
1283         }
1284
1285         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1286         return -EACCES;
1287 }
1288
1289 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1290 {
1291         unsigned int i;
1292         u16 eeprom;
1293         u8 reg_id;
1294         u8 value;
1295
1296         if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev)))
1297                 return -EACCES;
1298
1299         rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1300         rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1301         rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1302         rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1303         rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1304         rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1305         rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1306         rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1307         rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1308         rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1309         rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1310         rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1311         rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1312         rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1313         rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1314         rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1315         rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1316         rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1317         rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1318         rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1319         rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1320         rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1321         rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1322         rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1323
1324         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1325                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1326
1327                 if (eeprom != 0xffff && eeprom != 0x0000) {
1328                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1329                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1330                         rt61pci_bbp_write(rt2x00dev, reg_id, value);
1331                 }
1332         }
1333
1334         return 0;
1335 }
1336
1337 /*
1338  * Device state switch handlers.
1339  */
1340 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1341                               enum dev_state state)
1342 {
1343         u32 reg;
1344
1345         rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, &reg);
1346         rt2x00_set_field32(&reg, TXRX_CSR0_DISABLE_RX,
1347                            (state == STATE_RADIO_RX_OFF) ||
1348                            (state == STATE_RADIO_RX_OFF_LINK));
1349         rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1350 }
1351
1352 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1353                                enum dev_state state)
1354 {
1355         int mask = (state == STATE_RADIO_IRQ_OFF);
1356         u32 reg;
1357
1358         /*
1359          * When interrupts are being enabled, the interrupt registers
1360          * should clear the register to assure a clean state.
1361          */
1362         if (state == STATE_RADIO_IRQ_ON) {
1363                 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1364                 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1365
1366                 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg);
1367                 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1368         }
1369
1370         /*
1371          * Only toggle the interrupts bits we are going to use.
1372          * Non-checked interrupt bits are disabled by default.
1373          */
1374         rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, &reg);
1375         rt2x00_set_field32(&reg, INT_MASK_CSR_TXDONE, mask);
1376         rt2x00_set_field32(&reg, INT_MASK_CSR_RXDONE, mask);
1377         rt2x00_set_field32(&reg, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1378         rt2x00_set_field32(&reg, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1379         rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1380
1381         rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, &reg);
1382         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_0, mask);
1383         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_1, mask);
1384         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_2, mask);
1385         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_3, mask);
1386         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_4, mask);
1387         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_5, mask);
1388         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_6, mask);
1389         rt2x00_set_field32(&reg, MCU_INT_MASK_CSR_7, mask);
1390         rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1391 }
1392
1393 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1394 {
1395         u32 reg;
1396
1397         /*
1398          * Initialize all registers.
1399          */
1400         if (unlikely(rt61pci_init_queues(rt2x00dev) ||
1401                      rt61pci_init_registers(rt2x00dev) ||
1402                      rt61pci_init_bbp(rt2x00dev)))
1403                 return -EIO;
1404
1405         /*
1406          * Enable RX.
1407          */
1408         rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, &reg);
1409         rt2x00_set_field32(&reg, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1410         rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1411
1412         return 0;
1413 }
1414
1415 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1416 {
1417         u32 reg;
1418
1419         rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1420
1421         /*
1422          * Disable synchronisation.
1423          */
1424         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1425
1426         /*
1427          * Cancel RX and TX.
1428          */
1429         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1430         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1431         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1432         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1433         rt2x00_set_field32(&reg, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1434         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1435 }
1436
1437 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1438 {
1439         u32 reg;
1440         unsigned int i;
1441         char put_to_sleep;
1442
1443         put_to_sleep = (state != STATE_AWAKE);
1444
1445         rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1446         rt2x00_set_field32(&reg, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1447         rt2x00_set_field32(&reg, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1448         rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1449
1450         /*
1451          * Device is not guaranteed to be in the requested state yet.
1452          * We must wait until the register indicates that the
1453          * device has entered the correct state.
1454          */
1455         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1456                 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, &reg);
1457                 state = rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1458                 if (state == !put_to_sleep)
1459                         return 0;
1460                 msleep(10);
1461         }
1462
1463         return -EBUSY;
1464 }
1465
1466 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1467                                     enum dev_state state)
1468 {
1469         int retval = 0;
1470
1471         switch (state) {
1472         case STATE_RADIO_ON:
1473                 retval = rt61pci_enable_radio(rt2x00dev);
1474                 break;
1475         case STATE_RADIO_OFF:
1476                 rt61pci_disable_radio(rt2x00dev);
1477                 break;
1478         case STATE_RADIO_RX_ON:
1479         case STATE_RADIO_RX_ON_LINK:
1480         case STATE_RADIO_RX_OFF:
1481         case STATE_RADIO_RX_OFF_LINK:
1482                 rt61pci_toggle_rx(rt2x00dev, state);
1483                 break;
1484         case STATE_RADIO_IRQ_ON:
1485         case STATE_RADIO_IRQ_OFF:
1486                 rt61pci_toggle_irq(rt2x00dev, state);
1487                 break;
1488         case STATE_DEEP_SLEEP:
1489         case STATE_SLEEP:
1490         case STATE_STANDBY:
1491         case STATE_AWAKE:
1492                 retval = rt61pci_set_state(rt2x00dev, state);
1493                 break;
1494         default:
1495                 retval = -ENOTSUPP;
1496                 break;
1497         }
1498
1499         if (unlikely(retval))
1500                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1501                       state, retval);
1502
1503         return retval;
1504 }
1505
1506 /*
1507  * TX descriptor initialization
1508  */
1509 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1510                                     struct sk_buff *skb,
1511                                     struct txentry_desc *txdesc)
1512 {
1513         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1514         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1515         __le32 *txd = skbdesc->desc;
1516         u32 word;
1517
1518         /*
1519          * Start writing the descriptor words.
1520          */
1521         rt2x00_desc_read(txd, 1, &word);
1522         rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, txdesc->queue);
1523         rt2x00_set_field32(&word, TXD_W1_AIFSN, txdesc->aifs);
1524         rt2x00_set_field32(&word, TXD_W1_CWMIN, txdesc->cw_min);
1525         rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
1526         rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1527         rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1528         rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1529         rt2x00_desc_write(txd, 1, word);
1530
1531         rt2x00_desc_read(txd, 2, &word);
1532         rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, txdesc->signal);
1533         rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, txdesc->service);
1534         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, txdesc->length_low);
1535         rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, txdesc->length_high);
1536         rt2x00_desc_write(txd, 2, word);
1537
1538         rt2x00_desc_read(txd, 5, &word);
1539         rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
1540         rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
1541                            skbdesc->entry->entry_idx);
1542         rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1543                            TXPOWER_TO_DEV(rt2x00dev->tx_power));
1544         rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1545         rt2x00_desc_write(txd, 5, word);
1546
1547         rt2x00_desc_read(txd, 6, &word);
1548         rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1549                            entry_priv->data_dma);
1550         rt2x00_desc_write(txd, 6, word);
1551
1552         if (skbdesc->desc_len > TXINFO_SIZE) {
1553                 rt2x00_desc_read(txd, 11, &word);
1554                 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
1555                 rt2x00_desc_write(txd, 11, word);
1556         }
1557
1558         rt2x00_desc_read(txd, 0, &word);
1559         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1560         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1561         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1562                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1563         rt2x00_set_field32(&word, TXD_W0_ACK,
1564                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1565         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1566                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1567         rt2x00_set_field32(&word, TXD_W0_OFDM,
1568                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1569         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1570         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1571                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1572         rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1573         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1574         rt2x00_set_field32(&word, TXD_W0_BURST,
1575                            test_bit(ENTRY_TXD_BURST, &txdesc->flags));
1576         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1577         rt2x00_desc_write(txd, 0, word);
1578 }
1579
1580 /*
1581  * TX data initialization
1582  */
1583 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1584                                   const enum data_queue_qid queue)
1585 {
1586         u32 reg;
1587
1588         if (queue == QID_BEACON) {
1589                 /*
1590                  * For Wi-Fi faily generated beacons between participating
1591                  * stations. Set TBTT phase adaptive adjustment step to 8us.
1592                  */
1593                 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1594
1595                 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
1596                 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1597                         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 1);
1598                         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 1);
1599                         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 1);
1600                         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1601                 }
1602                 return;
1603         }
1604
1605         rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, &reg);
1606         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
1607         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
1608         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
1609         rt2x00_set_field32(&reg, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
1610         rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1611 }
1612
1613 /*
1614  * RX control handlers
1615  */
1616 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1617 {
1618         u16 eeprom;
1619         u8 offset;
1620         u8 lna;
1621
1622         lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1623         switch (lna) {
1624         case 3:
1625                 offset = 90;
1626                 break;
1627         case 2:
1628                 offset = 74;
1629                 break;
1630         case 1:
1631                 offset = 64;
1632                 break;
1633         default:
1634                 return 0;
1635         }
1636
1637         if (rt2x00dev->rx_status.band == IEEE80211_BAND_5GHZ) {
1638                 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1639                         offset += 14;
1640
1641                 if (lna == 3 || lna == 2)
1642                         offset += 10;
1643
1644                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1645                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1646         } else {
1647                 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1648                         offset += 14;
1649
1650                 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1651                 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1652         }
1653
1654         return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1655 }
1656
1657 static void rt61pci_fill_rxdone(struct queue_entry *entry,
1658                                 struct rxdone_entry_desc *rxdesc)
1659 {
1660         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1661         u32 word0;
1662         u32 word1;
1663
1664         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1665         rt2x00_desc_read(entry_priv->desc, 1, &word1);
1666
1667         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1668                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1669
1670         /*
1671          * Obtain the status about this packet.
1672          * When frame was received with an OFDM bitrate,
1673          * the signal is the PLCP value. If it was received with
1674          * a CCK bitrate the signal is the rate in 100kbit/s.
1675          */
1676         rxdesc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1677         rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
1678         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1679
1680         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1681                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1682         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1683                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1684 }
1685
1686 /*
1687  * Interrupt functions.
1688  */
1689 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1690 {
1691         struct data_queue *queue;
1692         struct queue_entry *entry;
1693         struct queue_entry *entry_done;
1694         struct queue_entry_priv_pci *entry_priv;
1695         struct txdone_entry_desc txdesc;
1696         u32 word;
1697         u32 reg;
1698         u32 old_reg;
1699         int type;
1700         int index;
1701
1702         /*
1703          * During each loop we will compare the freshly read
1704          * STA_CSR4 register value with the value read from
1705          * the previous loop. If the 2 values are equal then
1706          * we should stop processing because the chance it
1707          * quite big that the device has been unplugged and
1708          * we risk going into an endless loop.
1709          */
1710         old_reg = 0;
1711
1712         while (1) {
1713                 rt2x00pci_register_read(rt2x00dev, STA_CSR4, &reg);
1714                 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1715                         break;
1716
1717                 if (old_reg == reg)
1718                         break;
1719                 old_reg = reg;
1720
1721                 /*
1722                  * Skip this entry when it contains an invalid
1723                  * queue identication number.
1724                  */
1725                 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1726                 queue = rt2x00queue_get_queue(rt2x00dev, type);
1727                 if (unlikely(!queue))
1728                         continue;
1729
1730                 /*
1731                  * Skip this entry when it contains an invalid
1732                  * index number.
1733                  */
1734                 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1735                 if (unlikely(index >= queue->limit))
1736                         continue;
1737
1738                 entry = &queue->entries[index];
1739                 entry_priv = entry->priv_data;
1740                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1741
1742                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1743                     !rt2x00_get_field32(word, TXD_W0_VALID))
1744                         return;
1745
1746                 entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1747                 while (entry != entry_done) {
1748                         /* Catch up.
1749                          * Just report any entries we missed as failed.
1750                          */
1751                         WARNING(rt2x00dev,
1752                                 "TX status report missed for entry %d\n",
1753                                 entry_done->entry_idx);
1754
1755                         txdesc.flags = 0;
1756                         __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
1757                         txdesc.retry = 0;
1758
1759                         rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
1760                         entry_done = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1761                 }
1762
1763                 /*
1764                  * Obtain the status about this packet.
1765                  */
1766                 txdesc.flags = 0;
1767                 switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
1768                 case 0: /* Success, maybe with retry */
1769                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1770                         break;
1771                 case 6: /* Failure, excessive retries */
1772                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1773                         /* Don't break, this is a failed frame! */
1774                 default: /* Failure */
1775                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1776                 }
1777                 txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1778
1779                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1780         }
1781 }
1782
1783 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1784 {
1785         struct rt2x00_dev *rt2x00dev = dev_instance;
1786         u32 reg_mcu;
1787         u32 reg;
1788
1789         /*
1790          * Get the interrupt sources & saved to local variable.
1791          * Write register value back to clear pending interrupts.
1792          */
1793         rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, &reg_mcu);
1794         rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1795
1796         rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, &reg);
1797         rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1798
1799         if (!reg && !reg_mcu)
1800                 return IRQ_NONE;
1801
1802         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1803                 return IRQ_HANDLED;
1804
1805         /*
1806          * Handle interrupts, walk through all bits
1807          * and run the tasks, the bits are checked in order of
1808          * priority.
1809          */
1810
1811         /*
1812          * 1 - Rx ring done interrupt.
1813          */
1814         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1815                 rt2x00pci_rxdone(rt2x00dev);
1816
1817         /*
1818          * 2 - Tx ring done interrupt.
1819          */
1820         if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1821                 rt61pci_txdone(rt2x00dev);
1822
1823         /*
1824          * 3 - Handle MCU command done.
1825          */
1826         if (reg_mcu)
1827                 rt2x00pci_register_write(rt2x00dev,
1828                                          M2H_CMD_DONE_CSR, 0xffffffff);
1829
1830         return IRQ_HANDLED;
1831 }
1832
1833 /*
1834  * Device probe functions.
1835  */
1836 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1837 {
1838         struct eeprom_93cx6 eeprom;
1839         u32 reg;
1840         u16 word;
1841         u8 *mac;
1842         s8 value;
1843
1844         rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, &reg);
1845
1846         eeprom.data = rt2x00dev;
1847         eeprom.register_read = rt61pci_eepromregister_read;
1848         eeprom.register_write = rt61pci_eepromregister_write;
1849         eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1850             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1851         eeprom.reg_data_in = 0;
1852         eeprom.reg_data_out = 0;
1853         eeprom.reg_data_clock = 0;
1854         eeprom.reg_chip_select = 0;
1855
1856         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1857                                EEPROM_SIZE / sizeof(u16));
1858
1859         /*
1860          * Start validation of the data that has been read.
1861          */
1862         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1863         if (!is_valid_ether_addr(mac)) {
1864                 DECLARE_MAC_BUF(macbuf);
1865
1866                 random_ether_addr(mac);
1867                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1868         }
1869
1870         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1871         if (word == 0xffff) {
1872                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1873                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1874                                    ANTENNA_B);
1875                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1876                                    ANTENNA_B);
1877                 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1878                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1879                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1880                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1881                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1882                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1883         }
1884
1885         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1886         if (word == 0xffff) {
1887                 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1888                 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1889                 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1890                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1891                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1892                 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1893                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1894                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1895         }
1896
1897         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
1898         if (word == 0xffff) {
1899                 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
1900                                    LED_MODE_DEFAULT);
1901                 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
1902                 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
1903         }
1904
1905         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
1906         if (word == 0xffff) {
1907                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
1908                 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
1909                 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
1910                 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
1911         }
1912
1913         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
1914         if (word == 0xffff) {
1915                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1916                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1917                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1918                 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
1919         } else {
1920                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
1921                 if (value < -10 || value > 10)
1922                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
1923                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
1924                 if (value < -10 || value > 10)
1925                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
1926                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
1927         }
1928
1929         rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
1930         if (word == 0xffff) {
1931                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1932                 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1933                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1934                 EEPROM(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word);
1935         } else {
1936                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
1937                 if (value < -10 || value > 10)
1938                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
1939                 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
1940                 if (value < -10 || value > 10)
1941                         rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
1942                 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
1943         }
1944
1945         return 0;
1946 }
1947
1948 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1949 {
1950         u32 reg;
1951         u16 value;
1952         u16 eeprom;
1953         u16 device;
1954
1955         /*
1956          * Read EEPROM word for configuration.
1957          */
1958         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1959
1960         /*
1961          * Identify RF chipset.
1962          * To determine the RT chip we have to read the
1963          * PCI header of the device.
1964          */
1965         pci_read_config_word(rt2x00dev_pci(rt2x00dev),
1966                              PCI_CONFIG_HEADER_DEVICE, &device);
1967         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1968         rt2x00pci_register_read(rt2x00dev, MAC_CSR0, &reg);
1969         rt2x00_set_chip(rt2x00dev, device, value, reg);
1970
1971         if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
1972             !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
1973             !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
1974             !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
1975                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1976                 return -ENODEV;
1977         }
1978
1979         /*
1980          * Determine number of antenna's.
1981          */
1982         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
1983                 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
1984
1985         /*
1986          * Identify default antenna configuration.
1987          */
1988         rt2x00dev->default_ant.tx =
1989             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1990         rt2x00dev->default_ant.rx =
1991             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1992
1993         /*
1994          * Read the Frame type.
1995          */
1996         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
1997                 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
1998
1999         /*
2000          * Detect if this device has an hardware controlled radio.
2001          */
2002 #ifdef CONFIG_RT61PCI_RFKILL
2003         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2004                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2005 #endif /* CONFIG_RT61PCI_RFKILL */
2006
2007         /*
2008          * Read frequency offset and RF programming sequence.
2009          */
2010         rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2011         if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2012                 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2013
2014         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2015
2016         /*
2017          * Read external LNA informations.
2018          */
2019         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2020
2021         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2022                 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2023         if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2024                 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2025
2026         /*
2027          * When working with a RF2529 chip without double antenna
2028          * the antenna settings should be gathered from the NIC
2029          * eeprom word.
2030          */
2031         if (rt2x00_rf(&rt2x00dev->chip, RF2529) &&
2032             !test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags)) {
2033                 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
2034                 case 0:
2035                         rt2x00dev->default_ant.tx = ANTENNA_B;
2036                         rt2x00dev->default_ant.rx = ANTENNA_A;
2037                         break;
2038                 case 1:
2039                         rt2x00dev->default_ant.tx = ANTENNA_B;
2040                         rt2x00dev->default_ant.rx = ANTENNA_B;
2041                         break;
2042                 case 2:
2043                         rt2x00dev->default_ant.tx = ANTENNA_A;
2044                         rt2x00dev->default_ant.rx = ANTENNA_A;
2045                         break;
2046                 case 3:
2047                         rt2x00dev->default_ant.tx = ANTENNA_A;
2048                         rt2x00dev->default_ant.rx = ANTENNA_B;
2049                         break;
2050                 }
2051
2052                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY))
2053                         rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY;
2054                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY))
2055                         rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY;
2056         }
2057
2058         /*
2059          * Store led settings, for correct led behaviour.
2060          * If the eeprom value is invalid,
2061          * switch to default led mode.
2062          */
2063 #ifdef CONFIG_RT61PCI_LEDS
2064         rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2065         value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2066
2067         rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
2068         rt2x00dev->led_radio.type = LED_TYPE_RADIO;
2069         rt2x00dev->led_radio.led_dev.brightness_set =
2070             rt61pci_brightness_set;
2071         rt2x00dev->led_radio.led_dev.blink_set =
2072             rt61pci_blink_set;
2073         rt2x00dev->led_radio.flags = LED_INITIALIZED;
2074
2075         rt2x00dev->led_assoc.rt2x00dev = rt2x00dev;
2076         rt2x00dev->led_assoc.type = LED_TYPE_ASSOC;
2077         rt2x00dev->led_assoc.led_dev.brightness_set =
2078             rt61pci_brightness_set;
2079         rt2x00dev->led_assoc.led_dev.blink_set =
2080             rt61pci_blink_set;
2081         rt2x00dev->led_assoc.flags = LED_INITIALIZED;
2082
2083         if (value == LED_MODE_SIGNAL_STRENGTH) {
2084                 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
2085                 rt2x00dev->led_qual.type = LED_TYPE_QUALITY;
2086                 rt2x00dev->led_qual.led_dev.brightness_set =
2087                     rt61pci_brightness_set;
2088                 rt2x00dev->led_qual.led_dev.blink_set =
2089                     rt61pci_blink_set;
2090                 rt2x00dev->led_qual.flags = LED_INITIALIZED;
2091         }
2092
2093         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
2094         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0,
2095                            rt2x00_get_field16(eeprom,
2096                                               EEPROM_LED_POLARITY_GPIO_0));
2097         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1,
2098                            rt2x00_get_field16(eeprom,
2099                                               EEPROM_LED_POLARITY_GPIO_1));
2100         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2,
2101                            rt2x00_get_field16(eeprom,
2102                                               EEPROM_LED_POLARITY_GPIO_2));
2103         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3,
2104                            rt2x00_get_field16(eeprom,
2105                                               EEPROM_LED_POLARITY_GPIO_3));
2106         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4,
2107                            rt2x00_get_field16(eeprom,
2108                                               EEPROM_LED_POLARITY_GPIO_4));
2109         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT,
2110                            rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2111         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG,
2112                            rt2x00_get_field16(eeprom,
2113                                               EEPROM_LED_POLARITY_RDY_G));
2114         rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A,
2115                            rt2x00_get_field16(eeprom,
2116                                               EEPROM_LED_POLARITY_RDY_A));
2117 #endif /* CONFIG_RT61PCI_LEDS */
2118
2119         return 0;
2120 }
2121
2122 /*
2123  * RF value list for RF5225 & RF5325
2124  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2125  */
2126 static const struct rf_channel rf_vals_noseq[] = {
2127         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2128         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2129         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2130         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2131         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2132         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2133         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2134         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2135         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2136         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2137         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2138         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2139         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2140         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2141
2142         /* 802.11 UNI / HyperLan 2 */
2143         { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2144         { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2145         { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2146         { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2147         { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2148         { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2149         { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2150         { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2151
2152         /* 802.11 HyperLan 2 */
2153         { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2154         { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2155         { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2156         { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2157         { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2158         { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2159         { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2160         { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2161         { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2162         { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2163
2164         /* 802.11 UNII */
2165         { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2166         { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2167         { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2168         { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2169         { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2170         { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2171
2172         /* MMAC(Japan)J52 ch 34,38,42,46 */
2173         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2174         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2175         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2176         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2177 };
2178
2179 /*
2180  * RF value list for RF5225 & RF5325
2181  * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2182  */
2183 static const struct rf_channel rf_vals_seq[] = {
2184         { 1,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2185         { 2,  0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2186         { 3,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2187         { 4,  0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2188         { 5,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2189         { 6,  0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2190         { 7,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2191         { 8,  0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2192         { 9,  0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2193         { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2194         { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2195         { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2196         { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2197         { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2198
2199         /* 802.11 UNI / HyperLan 2 */
2200         { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2201         { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2202         { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2203         { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2204         { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2205         { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2206         { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2207         { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2208
2209         /* 802.11 HyperLan 2 */
2210         { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2211         { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2212         { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2213         { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2214         { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2215         { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2216         { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2217         { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2218         { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2219         { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2220
2221         /* 802.11 UNII */
2222         { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2223         { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2224         { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2225         { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2226         { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2227         { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2228
2229         /* MMAC(Japan)J52 ch 34,38,42,46 */
2230         { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2231         { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2232         { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2233         { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2234 };
2235
2236 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2237 {
2238         struct hw_mode_spec *spec = &rt2x00dev->spec;
2239         u8 *txpower;
2240         unsigned int i;
2241
2242         /*
2243          * Initialize all hw fields.
2244          */
2245         rt2x00dev->hw->flags =
2246             IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2247             IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
2248             IEEE80211_HW_SIGNAL_DBM;
2249         rt2x00dev->hw->extra_tx_headroom = 0;
2250
2251         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2252         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2253                                 rt2x00_eeprom_addr(rt2x00dev,
2254                                                    EEPROM_MAC_ADDR_0));
2255
2256         /*
2257          * Convert tx_power array in eeprom.
2258          */
2259         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2260         for (i = 0; i < 14; i++)
2261                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2262
2263         /*
2264          * Initialize hw_mode information.
2265          */
2266         spec->supported_bands = SUPPORT_BAND_2GHZ;
2267         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
2268         spec->tx_power_a = NULL;
2269         spec->tx_power_bg = txpower;
2270         spec->tx_power_default = DEFAULT_TXPOWER;
2271
2272         if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2273                 spec->num_channels = 14;
2274                 spec->channels = rf_vals_noseq;
2275         } else {
2276                 spec->num_channels = 14;
2277                 spec->channels = rf_vals_seq;
2278         }
2279
2280         if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2281             rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2282                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
2283                 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2284
2285                 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2286                 for (i = 0; i < 14; i++)
2287                         txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2288
2289                 spec->tx_power_a = txpower;
2290         }
2291 }
2292
2293 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2294 {
2295         int retval;
2296
2297         /*
2298          * Allocate eeprom data.
2299          */
2300         retval = rt61pci_validate_eeprom(rt2x00dev);
2301         if (retval)
2302                 return retval;
2303
2304         retval = rt61pci_init_eeprom(rt2x00dev);
2305         if (retval)
2306                 return retval;
2307
2308         /*
2309          * Initialize hw specifications.
2310          */
2311         rt61pci_probe_hw_mode(rt2x00dev);
2312
2313         /*
2314          * This device requires firmware.
2315          */
2316         __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2317
2318         /*
2319          * Set the rssi offset.
2320          */
2321         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2322
2323         return 0;
2324 }
2325
2326 /*
2327  * IEEE80211 stack callback functions.
2328  */
2329 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2330                                    u32 short_retry, u32 long_retry)
2331 {
2332         struct rt2x00_dev *rt2x00dev = hw->priv;
2333         u32 reg;
2334
2335         rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, &reg);
2336         rt2x00_set_field32(&reg, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2337         rt2x00_set_field32(&reg, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2338         rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2339
2340         return 0;
2341 }
2342
2343 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2344 {
2345         struct rt2x00_dev *rt2x00dev = hw->priv;
2346         u64 tsf;
2347         u32 reg;
2348
2349         rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, &reg);
2350         tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2351         rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, &reg);
2352         tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2353
2354         return tsf;
2355 }
2356
2357 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
2358 {
2359         struct rt2x00_dev *rt2x00dev = hw->priv;
2360         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2361         struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
2362         struct queue_entry_priv_pci *entry_priv;
2363         struct skb_frame_desc *skbdesc;
2364         struct txentry_desc txdesc;
2365         unsigned int beacon_base;
2366         u32 reg;
2367
2368         if (unlikely(!intf->beacon))
2369                 return -ENOBUFS;
2370
2371         /*
2372          * Copy all TX descriptor information into txdesc,
2373          * after that we are free to use the skb->cb array
2374          * for our information.
2375          */
2376         intf->beacon->skb = skb;
2377         rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
2378
2379         entry_priv = intf->beacon->priv_data;
2380         memset(entry_priv->desc, 0, intf->beacon->queue->desc_size);
2381
2382         /*
2383          * Fill in skb descriptor
2384          */
2385         skbdesc = get_skb_frame_desc(skb);
2386         memset(skbdesc, 0, sizeof(*skbdesc));
2387         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
2388         skbdesc->data = skb->data;
2389         skbdesc->data_len = skb->len;
2390         skbdesc->desc = entry_priv->desc;
2391         skbdesc->desc_len = intf->beacon->queue->desc_size;
2392         skbdesc->entry = intf->beacon;
2393
2394         /*
2395          * Disable beaconing while we are reloading the beacon data,
2396          * otherwise we might be sending out invalid data.
2397          */
2398         rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, &reg);
2399         rt2x00_set_field32(&reg, TXRX_CSR9_TSF_TICKING, 0);
2400         rt2x00_set_field32(&reg, TXRX_CSR9_TBTT_ENABLE, 0);
2401         rt2x00_set_field32(&reg, TXRX_CSR9_BEACON_GEN, 0);
2402         rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
2403
2404         /*
2405          * Write entire beacon with descriptor to register,
2406          * and kick the beacon generator.
2407          */
2408         rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
2409         beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
2410         rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
2411                                       skbdesc->desc, skbdesc->desc_len);
2412         rt2x00pci_register_multiwrite(rt2x00dev,
2413                                       beacon_base + skbdesc->desc_len,
2414                                       skbdesc->data, skbdesc->data_len);
2415         rt61pci_kick_tx_queue(rt2x00dev, QID_BEACON);
2416
2417         return 0;
2418 }
2419
2420 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2421         .tx                     = rt2x00mac_tx,
2422         .start                  = rt2x00mac_start,
2423         .stop                   = rt2x00mac_stop,
2424         .add_interface          = rt2x00mac_add_interface,
2425         .remove_interface       = rt2x00mac_remove_interface,
2426         .config                 = rt2x00mac_config,
2427         .config_interface       = rt2x00mac_config_interface,
2428         .configure_filter       = rt2x00mac_configure_filter,
2429         .get_stats              = rt2x00mac_get_stats,
2430         .set_retry_limit        = rt61pci_set_retry_limit,
2431         .bss_info_changed       = rt2x00mac_bss_info_changed,
2432         .conf_tx                = rt2x00mac_conf_tx,
2433         .get_tx_stats           = rt2x00mac_get_tx_stats,
2434         .get_tsf                = rt61pci_get_tsf,
2435         .beacon_update          = rt61pci_beacon_update,
2436 };
2437
2438 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2439         .irq_handler            = rt61pci_interrupt,
2440         .probe_hw               = rt61pci_probe_hw,
2441         .get_firmware_name      = rt61pci_get_firmware_name,
2442         .get_firmware_crc       = rt61pci_get_firmware_crc,
2443         .load_firmware          = rt61pci_load_firmware,
2444         .initialize             = rt2x00pci_initialize,
2445         .uninitialize           = rt2x00pci_uninitialize,
2446         .init_rxentry           = rt61pci_init_rxentry,
2447         .init_txentry           = rt61pci_init_txentry,
2448         .set_device_state       = rt61pci_set_device_state,
2449         .rfkill_poll            = rt61pci_rfkill_poll,
2450         .link_stats             = rt61pci_link_stats,
2451         .reset_tuner            = rt61pci_reset_tuner,
2452         .link_tuner             = rt61pci_link_tuner,
2453         .write_tx_desc          = rt61pci_write_tx_desc,
2454         .write_tx_data          = rt2x00pci_write_tx_data,
2455         .kick_tx_queue          = rt61pci_kick_tx_queue,
2456         .fill_rxdone            = rt61pci_fill_rxdone,
2457         .config_filter          = rt61pci_config_filter,
2458         .config_intf            = rt61pci_config_intf,
2459         .config_erp             = rt61pci_config_erp,
2460         .config                 = rt61pci_config,
2461 };
2462
2463 static const struct data_queue_desc rt61pci_queue_rx = {
2464         .entry_num              = RX_ENTRIES,
2465         .data_size              = DATA_FRAME_SIZE,
2466         .desc_size              = RXD_DESC_SIZE,
2467         .priv_size              = sizeof(struct queue_entry_priv_pci),
2468 };
2469
2470 static const struct data_queue_desc rt61pci_queue_tx = {
2471         .entry_num              = TX_ENTRIES,
2472         .data_size              = DATA_FRAME_SIZE,
2473         .desc_size              = TXD_DESC_SIZE,
2474         .priv_size              = sizeof(struct queue_entry_priv_pci),
2475 };
2476
2477 static const struct data_queue_desc rt61pci_queue_bcn = {
2478         .entry_num              = 4 * BEACON_ENTRIES,
2479         .data_size              = 0, /* No DMA required for beacons */
2480         .desc_size              = TXINFO_SIZE,
2481         .priv_size              = sizeof(struct queue_entry_priv_pci),
2482 };
2483
2484 static const struct rt2x00_ops rt61pci_ops = {
2485         .name           = KBUILD_MODNAME,
2486         .max_sta_intf   = 1,
2487         .max_ap_intf    = 4,
2488         .eeprom_size    = EEPROM_SIZE,
2489         .rf_size        = RF_SIZE,
2490         .tx_queues      = NUM_TX_QUEUES,
2491         .rx             = &rt61pci_queue_rx,
2492         .tx             = &rt61pci_queue_tx,
2493         .bcn            = &rt61pci_queue_bcn,
2494         .lib            = &rt61pci_rt2x00_ops,
2495         .hw             = &rt61pci_mac80211_ops,
2496 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2497         .debugfs        = &rt61pci_rt2x00debug,
2498 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2499 };
2500
2501 /*
2502  * RT61pci module information.
2503  */
2504 static struct pci_device_id rt61pci_device_table[] = {
2505         /* RT2561s */
2506         { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2507         /* RT2561 v2 */
2508         { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2509         /* RT2661 */
2510         { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2511         { 0, }
2512 };
2513
2514 MODULE_AUTHOR(DRV_PROJECT);
2515 MODULE_VERSION(DRV_VERSION);
2516 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2517 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2518                         "PCI & PCMCIA chipset based cards");
2519 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2520 MODULE_FIRMWARE(FIRMWARE_RT2561);
2521 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2522 MODULE_FIRMWARE(FIRMWARE_RT2661);
2523 MODULE_LICENSE("GPL");
2524
2525 static struct pci_driver rt61pci_driver = {
2526         .name           = KBUILD_MODNAME,
2527         .id_table       = rt61pci_device_table,
2528         .probe          = rt2x00pci_probe,
2529         .remove         = __devexit_p(rt2x00pci_remove),
2530         .suspend        = rt2x00pci_suspend,
2531         .resume         = rt2x00pci_resume,
2532 };
2533
2534 static int __init rt61pci_init(void)
2535 {
2536         return pci_register_driver(&rt61pci_driver);
2537 }
2538
2539 static void __exit rt61pci_exit(void)
2540 {
2541         pci_unregister_driver(&rt61pci_driver);
2542 }
2543
2544 module_init(rt61pci_init);
2545 module_exit(rt61pci_exit);