2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: Data structures and registers for the rt2500usb module.
24 Supported chipsets: RT2570.
37 #define RF2525E 0x0005
43 #define RT2570_VERSION_B 2
44 #define RT2570_VERSION_C 3
45 #define RT2570_VERSION_D 4
49 * Defaul offset is required for RSSI <-> dBm conversion.
51 #define MAX_SIGNAL 100
53 #define DEFAULT_RSSI_OFFSET 120
56 * Register layout information.
58 #define CSR_REG_BASE 0x0400
59 #define CSR_REG_SIZE 0x0100
60 #define EEPROM_BASE 0x0000
61 #define EEPROM_SIZE 0x006a
62 #define BBP_SIZE 0x0060
63 #define RF_SIZE 0x0014
66 * Number of TX queues.
68 #define NUM_TX_QUEUES 2
71 * Control/Status Registers(CSR).
72 * Some values are set in TU, whereas 1 TU == 1024 us.
76 * MAC_CSR0: ASIC revision number.
78 #define MAC_CSR0 0x0400
81 * MAC_CSR1: System control.
82 * SOFT_RESET: Software reset, 1: reset, 0: normal.
83 * BBP_RESET: Hardware reset, 1: reset, 0, release.
84 * HOST_READY: Host ready after initialization.
86 #define MAC_CSR1 0x0402
87 #define MAC_CSR1_SOFT_RESET FIELD16(0x00000001)
88 #define MAC_CSR1_BBP_RESET FIELD16(0x00000002)
89 #define MAC_CSR1_HOST_READY FIELD16(0x00000004)
92 * MAC_CSR2: STA MAC register 0.
94 #define MAC_CSR2 0x0404
95 #define MAC_CSR2_BYTE0 FIELD16(0x00ff)
96 #define MAC_CSR2_BYTE1 FIELD16(0xff00)
99 * MAC_CSR3: STA MAC register 1.
101 #define MAC_CSR3 0x0406
102 #define MAC_CSR3_BYTE2 FIELD16(0x00ff)
103 #define MAC_CSR3_BYTE3 FIELD16(0xff00)
106 * MAC_CSR4: STA MAC register 2.
108 #define MAC_CSR4 0X0408
109 #define MAC_CSR4_BYTE4 FIELD16(0x00ff)
110 #define MAC_CSR4_BYTE5 FIELD16(0xff00)
113 * MAC_CSR5: BSSID register 0.
115 #define MAC_CSR5 0x040a
116 #define MAC_CSR5_BYTE0 FIELD16(0x00ff)
117 #define MAC_CSR5_BYTE1 FIELD16(0xff00)
120 * MAC_CSR6: BSSID register 1.
122 #define MAC_CSR6 0x040c
123 #define MAC_CSR6_BYTE2 FIELD16(0x00ff)
124 #define MAC_CSR6_BYTE3 FIELD16(0xff00)
127 * MAC_CSR7: BSSID register 2.
129 #define MAC_CSR7 0x040e
130 #define MAC_CSR7_BYTE4 FIELD16(0x00ff)
131 #define MAC_CSR7_BYTE5 FIELD16(0xff00)
134 * MAC_CSR8: Max frame length.
136 #define MAC_CSR8 0x0410
137 #define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
140 * Misc MAC_CSR registers.
141 * MAC_CSR9: Timer control.
142 * MAC_CSR10: Slot time.
145 * MAC_CSR13: Power mode0.
146 * MAC_CSR14: Power mode1.
147 * MAC_CSR15: Power saving transition0
148 * MAC_CSR16: Power saving transition1
150 #define MAC_CSR9 0x0412
151 #define MAC_CSR10 0x0414
152 #define MAC_CSR11 0x0416
153 #define MAC_CSR12 0x0418
154 #define MAC_CSR13 0x041a
155 #define MAC_CSR14 0x041c
156 #define MAC_CSR15 0x041e
157 #define MAC_CSR16 0x0420
160 * MAC_CSR17: Manual power control / status register.
161 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
162 * SET_STATE: Set state. Write 1 to trigger, self cleared.
163 * BBP_DESIRE_STATE: BBP desired state.
164 * RF_DESIRE_STATE: RF desired state.
165 * BBP_CURRENT_STATE: BBP current state.
166 * RF_CURRENT_STATE: RF current state.
167 * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared.
169 #define MAC_CSR17 0x0422
170 #define MAC_CSR17_SET_STATE FIELD16(0x0001)
171 #define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
172 #define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
173 #define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
174 #define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
175 #define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
178 * MAC_CSR18: Wakeup timer register.
179 * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU.
180 * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup.
181 * AUTO_WAKE: Enable auto wakeup / sleep mechanism.
183 #define MAC_CSR18 0x0424
184 #define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
185 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
186 #define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
189 * MAC_CSR19: GPIO control register.
191 #define MAC_CSR19 0x0426
194 * MAC_CSR20: LED control register.
195 * ACTIVITY: 0: idle, 1: active.
196 * LINK: 0: linkoff, 1: linkup.
197 * ACTIVITY_POLARITY: 0: active low, 1: active high.
199 #define MAC_CSR20 0x0428
200 #define MAC_CSR20_ACTIVITY FIELD16(0x0001)
201 #define MAC_CSR20_LINK FIELD16(0x0002)
202 #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
205 * MAC_CSR21: LED control register.
206 * ON_PERIOD: On period, default 70ms.
207 * OFF_PERIOD: Off period, default 30ms.
209 #define MAC_CSR21 0x042a
210 #define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
211 #define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
214 * Collision window control register.
216 #define MAC_CSR22 0x042c
219 * Transmit related CSRs.
220 * Some values are set in TU, whereas 1 TU == 1024 us.
224 * TXRX_CSR0: Security control register.
226 #define TXRX_CSR0 0x0440
227 #define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
228 #define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
229 #define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
232 * TXRX_CSR1: TX configuration.
233 * ACK_TIMEOUT: ACK Timeout in unit of 1-us.
234 * TSF_OFFSET: TSF offset in MAC header.
235 * AUTO_SEQUENCE: Let ASIC control frame sequence number.
237 #define TXRX_CSR1 0x0442
238 #define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
239 #define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
240 #define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
243 * TXRX_CSR2: RX control.
244 * DISABLE_RX: Disable rx engine.
245 * DROP_CRC: Drop crc error.
246 * DROP_PHYSICAL: Drop physical error.
247 * DROP_CONTROL: Drop control frame.
248 * DROP_NOT_TO_ME: Drop not to me unicast frame.
249 * DROP_TODS: Drop frame tods bit is true.
250 * DROP_VERSION_ERROR: Drop version error frame.
251 * DROP_MCAST: Drop multicast frames.
252 * DROP_BCAST: Drop broadcast frames.
254 #define TXRX_CSR2 0x0444
255 #define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
256 #define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
257 #define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
258 #define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
259 #define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
260 #define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
261 #define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
262 #define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200)
263 #define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400)
266 * RX BBP ID registers
267 * TXRX_CSR3: CCK RX BBP ID.
268 * TXRX_CSR4: OFDM RX BBP ID.
270 #define TXRX_CSR3 0x0446
271 #define TXRX_CSR4 0x0448
274 * TXRX_CSR5: CCK TX BBP ID0.
276 #define TXRX_CSR5 0x044a
277 #define TXRX_CSR5_BBP_ID0 FIELD16(0x007f)
278 #define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080)
279 #define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00)
280 #define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000)
283 * TXRX_CSR6: CCK TX BBP ID1.
285 #define TXRX_CSR6 0x044c
286 #define TXRX_CSR6_BBP_ID0 FIELD16(0x007f)
287 #define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080)
288 #define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00)
289 #define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000)
292 * TXRX_CSR7: OFDM TX BBP ID0.
294 #define TXRX_CSR7 0x044e
295 #define TXRX_CSR7_BBP_ID0 FIELD16(0x007f)
296 #define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080)
297 #define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00)
298 #define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
301 * TXRX_CSR5: OFDM TX BBP ID1.
303 #define TXRX_CSR8 0x0450
304 #define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
305 #define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080)
306 #define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00)
307 #define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000)
310 * TXRX_CSR9: TX ACK time-out.
312 #define TXRX_CSR9 0x0452
315 * TXRX_CSR10: Auto responder control.
317 #define TXRX_CSR10 0x0454
318 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
321 * TXRX_CSR11: Auto responder basic rate.
323 #define TXRX_CSR11 0x0456
326 * ACK/CTS time registers.
328 #define TXRX_CSR12 0x0458
329 #define TXRX_CSR13 0x045a
330 #define TXRX_CSR14 0x045c
331 #define TXRX_CSR15 0x045e
332 #define TXRX_CSR16 0x0460
333 #define TXRX_CSR17 0x0462
336 * TXRX_CSR18: Synchronization control register.
338 #define TXRX_CSR18 0x0464
339 #define TXRX_CSR18_OFFSET FIELD16(0x000f)
340 #define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
343 * TXRX_CSR19: Synchronization control register.
344 * TSF_COUNT: Enable TSF auto counting.
345 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
346 * TBCN: Enable Tbcn with reload value.
347 * BEACON_GEN: Enable beacon generator.
349 #define TXRX_CSR19 0x0466
350 #define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
351 #define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
352 #define TXRX_CSR19_TBCN FIELD16(0x0008)
353 #define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
356 * TXRX_CSR20: Tx BEACON offset time control register.
357 * OFFSET: In units of usec.
358 * BCN_EXPECT_WINDOW: Default: 2^CWmin
360 #define TXRX_CSR20 0x0468
361 #define TXRX_CSR20_OFFSET FIELD16(0x1fff)
362 #define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
367 #define TXRX_CSR21 0x046a
370 * Encryption related CSRs.
375 * SEC_CSR0-SEC_CSR7: Shared key 0, word 0-7
377 #define SEC_CSR0 0x0480
378 #define SEC_CSR1 0x0482
379 #define SEC_CSR2 0x0484
380 #define SEC_CSR3 0x0486
381 #define SEC_CSR4 0x0488
382 #define SEC_CSR5 0x048a
383 #define SEC_CSR6 0x048c
384 #define SEC_CSR7 0x048e
387 * SEC_CSR8-SEC_CSR15: Shared key 1, word 0-7
389 #define SEC_CSR8 0x0490
390 #define SEC_CSR9 0x0492
391 #define SEC_CSR10 0x0494
392 #define SEC_CSR11 0x0496
393 #define SEC_CSR12 0x0498
394 #define SEC_CSR13 0x049a
395 #define SEC_CSR14 0x049c
396 #define SEC_CSR15 0x049e
399 * SEC_CSR16-SEC_CSR23: Shared key 2, word 0-7
401 #define SEC_CSR16 0x04a0
402 #define SEC_CSR17 0x04a2
403 #define SEC_CSR18 0X04A4
404 #define SEC_CSR19 0x04a6
405 #define SEC_CSR20 0x04a8
406 #define SEC_CSR21 0x04aa
407 #define SEC_CSR22 0x04ac
408 #define SEC_CSR23 0x04ae
411 * SEC_CSR24-SEC_CSR31: Shared key 3, word 0-7
413 #define SEC_CSR24 0x04b0
414 #define SEC_CSR25 0x04b2
415 #define SEC_CSR26 0x04b4
416 #define SEC_CSR27 0x04b6
417 #define SEC_CSR28 0x04b8
418 #define SEC_CSR29 0x04ba
419 #define SEC_CSR30 0x04bc
420 #define SEC_CSR31 0x04be
423 * PHY control registers.
427 * PHY_CSR0: RF switching timing control.
429 #define PHY_CSR0 0x04c0
432 * PHY_CSR1: TX PA configuration.
434 #define PHY_CSR1 0x04c2
437 * MAC configuration registers.
441 * PHY_CSR2: TX MAC configuration.
442 * NOTE: Both register fields are complete dummy,
443 * documentation and legacy drivers are unclear un
444 * what this register means or what fields exists.
446 #define PHY_CSR2 0x04c4
447 #define PHY_CSR2_LNA FIELD16(0x0002)
448 #define PHY_CSR2_LNA_MODE FIELD16(0x3000)
451 * PHY_CSR3: RX MAC configuration.
453 #define PHY_CSR3 0x04c6
456 * PHY_CSR4: Interface configuration.
458 #define PHY_CSR4 0x04c8
459 #define PHY_CSR4_LOW_RF_LE FIELD16(0x0001)
462 * BBP pre-TX registers.
463 * PHY_CSR5: BBP pre-TX CCK.
465 #define PHY_CSR5 0x04ca
466 #define PHY_CSR5_CCK FIELD16(0x0003)
467 #define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
470 * BBP pre-TX registers.
471 * PHY_CSR6: BBP pre-TX OFDM.
473 #define PHY_CSR6 0x04cc
474 #define PHY_CSR6_OFDM FIELD16(0x0003)
475 #define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
478 * PHY_CSR7: BBP access register 0.
479 * BBP_DATA: BBP data.
480 * BBP_REG_ID: BBP register ID.
481 * BBP_READ_CONTROL: 0: write, 1: read.
483 #define PHY_CSR7 0x04ce
484 #define PHY_CSR7_DATA FIELD16(0x00ff)
485 #define PHY_CSR7_REG_ID FIELD16(0x7f00)
486 #define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
489 * PHY_CSR8: BBP access register 1.
490 * BBP_BUSY: ASIC is busy execute BBP programming.
492 #define PHY_CSR8 0x04d0
493 #define PHY_CSR8_BUSY FIELD16(0x0001)
496 * PHY_CSR9: RF access register.
497 * RF_VALUE: Register value + id to program into rf/if.
499 #define PHY_CSR9 0x04d2
500 #define PHY_CSR9_RF_VALUE FIELD16(0xffff)
503 * PHY_CSR10: RF access register.
504 * RF_VALUE: Register value + id to program into rf/if.
505 * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22).
506 * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
507 * RF_PLL_LD: Rf pll_ld status.
508 * RF_BUSY: 1: asic is busy execute rf programming.
510 #define PHY_CSR10 0x04d4
511 #define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
512 #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
513 #define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
514 #define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
515 #define PHY_CSR10_RF_BUSY FIELD16(0x8000)
518 * STA_CSR0: FCS error count.
519 * FCS_ERROR: FCS error count, cleared when read.
521 #define STA_CSR0 0x04e0
522 #define STA_CSR0_FCS_ERROR FIELD16(0xffff)
525 * STA_CSR1: PLCP error count.
527 #define STA_CSR1 0x04e2
530 * STA_CSR2: LONG error count.
532 #define STA_CSR2 0x04e4
535 * STA_CSR3: CCA false alarm.
536 * FALSE_CCA_ERROR: False CCA error count, cleared when read.
538 #define STA_CSR3 0x04e6
539 #define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff)
542 * STA_CSR4: RX FIFO overflow.
544 #define STA_CSR4 0x04e8
547 * STA_CSR5: Beacon sent counter.
549 #define STA_CSR5 0x04ea
552 * Statistics registers
554 #define STA_CSR6 0x04ec
555 #define STA_CSR7 0x04ee
556 #define STA_CSR8 0x04f0
557 #define STA_CSR9 0x04f2
558 #define STA_CSR10 0x04f4
562 * The wordsize of the BBP is 8 bits.
566 * R2: TX antenna control
568 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
569 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
572 * R14: RX antenna control
574 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
575 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
584 #define RF1_TUNER FIELD32(0x00020000)
589 #define RF3_TUNER FIELD32(0x00000100)
590 #define RF3_TXPOWER FIELD32(0x00003e00)
599 #define EEPROM_MAC_ADDR_0 0x0002
600 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
601 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
602 #define EEPROM_MAC_ADDR1 0x0003
603 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
604 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
605 #define EEPROM_MAC_ADDR_2 0x0004
606 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
607 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
611 * ANTENNA_NUM: Number of antenna's.
612 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
613 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
614 * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
615 * DYN_TXAGC: Dynamic TX AGC control.
616 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
617 * RF_TYPE: Rf_type of this adapter.
619 #define EEPROM_ANTENNA 0x000b
620 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
621 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
622 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
623 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
624 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
625 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
626 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
630 * CARDBUS_ACCEL: 0: enable, 1: disable.
631 * DYN_BBP_TUNE: 0: enable, 1: disable.
632 * CCK_TX_POWER: CCK TX power compensation.
634 #define EEPROM_NIC 0x000c
635 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
636 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
637 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
641 * GEO: Default geography setting for device.
643 #define EEPROM_GEOGRAPHY 0x000d
644 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
649 #define EEPROM_BBP_START 0x000e
650 #define EEPROM_BBP_SIZE 16
651 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
652 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
657 #define EEPROM_TXPOWER_START 0x001e
658 #define EEPROM_TXPOWER_SIZE 7
659 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
660 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
663 * EEPROM Tuning threshold
665 #define EEPROM_BBPTUNE 0x0030
666 #define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
669 * EEPROM BBP R24 Tuning.
671 #define EEPROM_BBPTUNE_R24 0x0031
672 #define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
673 #define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
676 * EEPROM BBP R25 Tuning.
678 #define EEPROM_BBPTUNE_R25 0x0032
679 #define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
680 #define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
683 * EEPROM BBP R24 Tuning.
685 #define EEPROM_BBPTUNE_R61 0x0033
686 #define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
687 #define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
690 * EEPROM BBP VGC Tuning.
692 #define EEPROM_BBPTUNE_VGC 0x0034
693 #define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
694 #define EEPROM_BBPTUNE_VGCLOWER FIELD16(0xff00)
697 * EEPROM BBP R17 Tuning.
699 #define EEPROM_BBPTUNE_R17 0x0035
700 #define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
701 #define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
704 * RSSI <-> dBm offset calibration
706 #define EEPROM_CALIBRATE_OFFSET 0x0036
707 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
710 * DMA descriptor defines.
712 #define TXD_DESC_SIZE ( 5 * sizeof(__le32) )
713 #define RXD_DESC_SIZE ( 4 * sizeof(__le32) )
716 * TX descriptor format for TX, PRIO, ATIM and Beacon Ring.
722 #define TXD_W0_PACKET_ID FIELD32(0x0000000f)
723 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
724 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
725 #define TXD_W0_ACK FIELD32(0x00000200)
726 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
727 #define TXD_W0_OFDM FIELD32(0x00000800)
728 #define TXD_W0_NEW_SEQ FIELD32(0x00001000)
729 #define TXD_W0_IFS FIELD32(0x00006000)
730 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
731 #define TXD_W0_CIPHER FIELD32(0x20000000)
732 #define TXD_W0_KEY_ID FIELD32(0xc0000000)
737 #define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
738 #define TXD_W1_AIFS FIELD32(0x000000c0)
739 #define TXD_W1_CWMIN FIELD32(0x00000f00)
740 #define TXD_W1_CWMAX FIELD32(0x0000f000)
743 * Word2: PLCP information
745 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
746 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
747 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
748 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
753 #define TXD_W3_IV FIELD32(0xffffffff)
758 #define TXD_W4_EIV FIELD32(0xffffffff)
761 * RX descriptor format for RX Ring.
767 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
768 #define RXD_W0_MULTICAST FIELD32(0x00000004)
769 #define RXD_W0_BROADCAST FIELD32(0x00000008)
770 #define RXD_W0_MY_BSS FIELD32(0x00000010)
771 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
772 #define RXD_W0_OFDM FIELD32(0x00000040)
773 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
774 #define RXD_W0_CIPHER FIELD32(0x00000100)
775 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
776 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
781 #define RXD_W1_RSSI FIELD32(0x000000ff)
782 #define RXD_W1_SIGNAL FIELD32(0x0000ff00)
787 #define RXD_W2_IV FIELD32(0xffffffff)
792 #define RXD_W3_EIV FIELD32(0xffffffff)
795 * Macro's for converting txpower from EEPROM to mac80211 value
796 * and from mac80211 value to register value.
798 #define MIN_TXPOWER 0
799 #define MAX_TXPOWER 31
800 #define DEFAULT_TXPOWER 24
802 #define TXPOWER_FROM_DEV(__txpower) \
804 ((__txpower) > MAX_TXPOWER) ? \
805 DEFAULT_TXPOWER : (__txpower); \
808 #define TXPOWER_TO_DEV(__txpower) \
810 ((__txpower) <= MIN_TXPOWER) ? MIN_TXPOWER : \
811 (((__txpower) >= MAX_TXPOWER) ? MAX_TXPOWER : \
815 #endif /* RT2500USB_H */