err.no Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2500pci_read_csr,
 209                 .write          = rt2500pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2500pci_bbp_read,
 221                 .write          = rt2500pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2500pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2500PCI_RFKILL
 235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2500pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2500PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2500PCI_LEDS
 247 static void rt2500pci_led_brightness(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         unsigned int activity =
 254             led->rt2x00dev->led_flags & LED_SUPPORT_ACTIVITY;
 255         u32 reg;
 256
 257         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 258
 259         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC) {
 260                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 261                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled && activity);
 262         }
 263
 264         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 265 }
 266 #else
 267 #define rt2500pci_led_brightness        NULL
 268 #endif /* CONFIG_RT2500PCI_LEDS */
 269
 270 /*
 271  * Configuration handlers.
 272  */
 273 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 274                                   struct rt2x00_intf *intf,
 275                                   struct rt2x00intf_conf *conf,
 276                                   const unsigned int flags)
 277 {
 278         struct data_queue *queue =
 279             rt2x00queue_get_queue(rt2x00dev, RT2X00_BCN_QUEUE_BEACON);
 280         unsigned int bcn_preload;
 281         u32 reg;
 282
 283         if (flags & CONFIG_UPDATE_TYPE) {
 284                 /*
 285                  * Enable beacon config
 286                  */
 287                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 288                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 289                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 290                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 291                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 292
 293                 /*
 294                  * Enable synchronisation.
 295                  */
 296                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 297                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 298                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 299                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 300                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 301         }
 302
 303         if (flags & CONFIG_UPDATE_MAC)
 304                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 305                                               conf->mac, sizeof(conf->mac));
 306
 307         if (flags & CONFIG_UPDATE_BSSID)
 308                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 309                                               conf->bssid, sizeof(conf->bssid));
 310 }
 311
 312 static int rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 313                                 struct rt2x00lib_erp *erp)
 314 {
 315         int preamble_mask;
 316         u32 reg;
 317
 318         /*
 319          * When short preamble is enabled, we should set bit 0x08
 320          */
 321         preamble_mask = erp->short_preamble << 3;
 322
 323         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 324         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 325                            erp->ack_timeout);
 326         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 327                            erp->ack_consume_time);
 328         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 329
 330         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 331         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 332         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 333         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 334         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 335
 336         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 337         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 338         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 339         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 340         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 341
 342         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 343         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 344         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 345         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 346         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 347
 348         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 349         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 350         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 351         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 352         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 353
 354         return 0;
 355 }
 356
 357 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 358                                      const int basic_rate_mask)
 359 {
 360         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 361 }
 362
 363 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 364                                      struct rf_channel *rf, const int txpower)
 365 {
 366         u8 r70;
 367
 368         /*
 369          * Set TXpower.
 370          */
 371         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 372
 373         /*
 374          * Switch on tuning bits.
 375          * For RT2523 devices we do not need to update the R1 register.
 376          */
 377         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 378                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 379         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 380
 381         /*
 382          * For RT2525 we should first set the channel to half band higher.
 383          */
 384         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 385                 static const u32 vals[] = {
 386                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 387                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 388                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 389                         0x00080d2e, 0x00080d3a
 390                 };
 391
 392                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 393                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 394                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 395                 if (rf->rf4)
 396                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 397         }
 398
 399         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 400         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 401         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 402         if (rf->rf4)
 403                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 404
 405         /*
 406          * Channel 14 requires the Japan filter bit to be set.
 407          */
 408         r70 = 0x46;
 409         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 410         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 411
 412         msleep(1);
 413
 414         /*
 415          * Switch off tuning bits.
 416          * For RT2523 devices we do not need to update the R1 register.
 417          */
 418         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 419                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 420                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 421         }
 422
 423         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 424         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 425
 426         /*
 427          * Clear false CRC during channel switch.
 428          */
 429         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 430 }
 431
 432 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 433                                      const int txpower)
 434 {
 435         u32 rf3;
 436
 437         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 438         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 439         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 440 }
 441
 442 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 443                                      struct antenna_setup *ant)
 444 {
 445         u32 reg;
 446         u8 r14;
 447         u8 r2;
 448
 449         /*
 450          * We should never come here because rt2x00lib is supposed
 451          * to catch this and send us the correct antenna explicitely.
 452          */
 453         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 454                ant->tx == ANTENNA_SW_DIVERSITY);
 455
 456         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 457         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 458         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 459
 460         /*
 461          * Configure the TX antenna.
 462          */
 463         switch (ant->tx) {
 464         case ANTENNA_A:
 465                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 466                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 467                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 468                 break;
 469         case ANTENNA_B:
 470         default:
 471                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 472                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 473                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 474                 break;
 475         }
 476
 477         /*
 478          * Configure the RX antenna.
 479          */
 480         switch (ant->rx) {
 481         case ANTENNA_A:
 482                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 483                 break;
 484         case ANTENNA_B:
 485         default:
 486                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 487                 break;
 488         }
 489
 490         /*
 491          * RT2525E and RT5222 need to flip TX I/Q
 492          */
 493         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 494             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 495                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 496                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 497                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 498
 499                 /*
 500                  * RT2525E does not need RX I/Q Flip.
 501                  */
 502                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 503                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 504         } else {
 505                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 506                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 507         }
 508
 509         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 510         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 511         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 512 }
 513
 514 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 515                                       struct rt2x00lib_conf *libconf)
 516 {
 517         u32 reg;
 518
 519         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 520         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 521         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 522
 523         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 524         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 525         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 526         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 527
 528         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 529         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 530         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 531         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 532
 533         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 534         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 535         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 536         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 537
 538         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 539         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 540                            libconf->conf->beacon_int * 16);
 541         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 542                            libconf->conf->beacon_int * 16);
 543         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 544 }
 545
 546 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 547                              struct rt2x00lib_conf *libconf,
 548                              const unsigned int flags)
 549 {
 550         if (flags & CONFIG_UPDATE_PHYMODE)
 551                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
 552         if (flags & CONFIG_UPDATE_CHANNEL)
 553                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 554                                          libconf->conf->power_level);
 555         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 556                 rt2500pci_config_txpower(rt2x00dev,
 557                                          libconf->conf->power_level);
 558         if (flags & CONFIG_UPDATE_ANTENNA)
 559                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
 560         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 561                 rt2500pci_config_duration(rt2x00dev, libconf);
 562 }
 563
 564 /*
 565  * Link tuning
 566  */
 567 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 568                                  struct link_qual *qual)
 569 {
 570         u32 reg;
 571
 572         /*
 573          * Update FCS error count from register.
 574          */
 575         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 576         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 577
 578         /*
 579          * Update False CCA count from register.
 580          */
 581         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 582         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 583 }
 584
 585 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 586 {
 587         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 588         rt2x00dev->link.vgc_level = 0x48;
 589 }
 590
 591 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 592 {
 593         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 594         u8 r17;
 595
 596         /*
 597          * To prevent collisions with MAC ASIC on chipsets
 598          * up to version C the link tuning should halt after 20
 599          * seconds while being associated.
 600          */
 601         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 602             rt2x00dev->intf_associated &&
 603             rt2x00dev->link.count > 20)
 604                 return;
 605
 606         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 607
 608         /*
 609          * Chipset versions C and lower should directly continue
 610          * to the dynamic CCA tuning. Chipset version D and higher
 611          * should go straight to dynamic CCA tuning when they
 612          * are not associated.
 613          */
 614         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 615             !rt2x00dev->intf_associated)
 616                 goto dynamic_cca_tune;
 617
 618         /*
 619          * A too low RSSI will cause too much false CCA which will
 620          * then corrupt the R17 tuning. To remidy this the tuning should
 621          * be stopped (While making sure the R17 value will not exceed limits)
 622          */
 623         if (rssi < -80 && rt2x00dev->link.count > 20) {
 624                 if (r17 >= 0x41) {
 625                         r17 = rt2x00dev->link.vgc_level;
 626                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 627                 }
 628                 return;
 629         }
 630
 631         /*
 632          * Special big-R17 for short distance
 633          */
 634         if (rssi >= -58) {
 635                 if (r17 != 0x50)
 636                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 637                 return;
 638         }
 639
 640         /*
 641          * Special mid-R17 for middle distance
 642          */
 643         if (rssi >= -74) {
 644                 if (r17 != 0x41)
 645                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 646                 return;
 647         }
 648
 649         /*
 650          * Leave short or middle distance condition, restore r17
 651          * to the dynamic tuning range.
 652          */
 653         if (r17 >= 0x41) {
 654                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 655                 return;
 656         }
 657
 658 dynamic_cca_tune:
 659
 660         /*
 661          * R17 is inside the dynamic tuning range,
 662          * start tuning the link based on the false cca counter.
 663          */
 664         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 665                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 666                 rt2x00dev->link.vgc_level = r17;
 667         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 668                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 669                 rt2x00dev->link.vgc_level = r17;
 670         }
 671 }
 672
 673 /*
 674  * Initialization functions.
 675  */
 676 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 677                                    struct queue_entry *entry)
 678 {
 679         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 680         u32 word;
 681
 682         rt2x00_desc_read(priv_rx->desc, 1, &word);
 683         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
 684         rt2x00_desc_write(priv_rx->desc, 1, word);
 685
 686         rt2x00_desc_read(priv_rx->desc, 0, &word);
 687         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 688         rt2x00_desc_write(priv_rx->desc, 0, word);
 689 }
 690
 691 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 692                                    struct queue_entry *entry)
 693 {
 694         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 695         u32 word;
 696
 697         rt2x00_desc_read(priv_tx->desc, 1, &word);
 698         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
 699         rt2x00_desc_write(priv_tx->desc, 1, word);
 700
 701         rt2x00_desc_read(priv_tx->desc, 0, &word);
 702         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 703         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 704         rt2x00_desc_write(priv_tx->desc, 0, word);
 705 }
 706
 707 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 708 {
 709         struct queue_entry_priv_pci_rx *priv_rx;
 710         struct queue_entry_priv_pci_tx *priv_tx;
 711         u32 reg;
 712
 713         /*
 714          * Initialize registers.
 715          */
 716         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 717         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 718         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 719         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 720         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 721         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 722
 723         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
 724         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 725         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 726                            priv_tx->desc_dma);
 727         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 728
 729         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
 730         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 731         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 732                            priv_tx->desc_dma);
 733         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 734
 735         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
 736         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 737         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 738                            priv_tx->desc_dma);
 739         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 740
 741         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
 742         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 743         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 744                            priv_tx->desc_dma);
 745         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 746
 747         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 748         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 749         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 750         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 751
 752         priv_rx = rt2x00dev->rx->entries[0].priv_data;
 753         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 754         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
 755         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 756
 757         return 0;
 758 }
 759
 760 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 761 {
 762         u32 reg;
 763
 764         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 765         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 766         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 767         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 768
 769         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 770         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 771         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 772         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 773         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 774
 775         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 776         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 777                            rt2x00dev->rx->data_size / 128);
 778         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 779
 780         /*
 781          * Always use CWmin and CWmax set in descriptor.
 782          */
 783         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 784         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 785         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 786
 787         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 788         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 789         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 790         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 791
 792         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 793
 794         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 795         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 796         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 797         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 798         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 799         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 800         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 801         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 802         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 803         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 804
 805         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 806         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 807         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 808         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 809         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 810         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 811
 812         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 813         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 814         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 815         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 816         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 817         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 818
 819         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 820         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 821         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 822         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 823         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 824         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 825
 826         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 827         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 828         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 829         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 830         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 831         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 832         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 833         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 834         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 835         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 836
 837         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 838         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 839         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 840         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 841         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 842         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 843         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 844         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 845         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 846
 847         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 848
 849         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 850         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 851
 852         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 853                 return -EBUSY;
 854
 855         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 856         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 857
 858         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 859         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 860         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 861
 862         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 863         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 864         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 865         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 866         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 867         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 868         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 869         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 870
 871         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 872
 873         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 874
 875         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 876         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 877         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 878         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 879         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 880
 881         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 882         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 883         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 884         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 885
 886         /*
 887          * We must clear the FCS and FIFO error count.
 888          * These registers are cleared on read,
 889          * so we may pass a useless variable to store the value.
 890          */
 891         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 892         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 893
 894         return 0;
 895 }
 896
 897 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 898 {
 899         unsigned int i;
 900         u16 eeprom;
 901         u8 reg_id;
 902         u8 value;
 903
 904         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 905                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 906                 if ((value != 0xff) && (value != 0x00))
 907                         goto continue_csr_init;
 908                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 909                 udelay(REGISTER_BUSY_DELAY);
 910         }
 911
 912         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 913         return -EACCES;
 914
 915 continue_csr_init:
 916         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 917         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 918         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 919         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 920         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 921         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 922         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 923         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 924         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 925         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 926         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 927         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 928         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 929         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 930         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 931         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 932         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 933         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 934         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 935         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 936         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 937         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 938         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 939         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 940         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 941         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 942         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 943         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
 944         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
 945         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
 946
 947         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 948                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 949
 950                 if (eeprom != 0xffff && eeprom != 0x0000) {
 951                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 952                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 953                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
 954                 }
 955         }
 956
 957         return 0;
 958 }
 959
 960 /*
 961  * Device state switch handlers.
 962  */
 963 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 964                                 enum dev_state state)
 965 {
 966         u32 reg;
 967
 968         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 969         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 970                            state == STATE_RADIO_RX_OFF);
 971         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 972 }
 973
 974 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 975                                  enum dev_state state)
 976 {
 977         int mask = (state == STATE_RADIO_IRQ_OFF);
 978         u32 reg;
 979
 980         /*
 981          * When interrupts are being enabled, the interrupt registers
 982          * should clear the register to assure a clean state.
 983          */
 984         if (state == STATE_RADIO_IRQ_ON) {
 985                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 986                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 987         }
 988
 989         /*
 990          * Only toggle the interrupts bits we are going to use.
 991          * Non-checked interrupt bits are disabled by default.
 992          */
 993         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 994         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 995         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 996         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 997         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 998         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 999         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1000 }
1001
1002 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1003 {
1004         /*
1005          * Initialize all registers.
1006          */
1007         if (rt2500pci_init_queues(rt2x00dev) ||
1008             rt2500pci_init_registers(rt2x00dev) ||
1009             rt2500pci_init_bbp(rt2x00dev)) {
1010                 ERROR(rt2x00dev, "Register initialization failed.\n");
1011                 return -EIO;
1012         }
1013
1014         /*
1015          * Enable interrupts.
1016          */
1017         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1018
1019         return 0;
1020 }
1021
1022 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1023 {
1024         u32 reg;
1025
1026         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1027
1028         /*
1029          * Disable synchronisation.
1030          */
1031         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1032
1033         /*
1034          * Cancel RX and TX.
1035          */
1036         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1037         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1038         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1039
1040         /*
1041          * Disable interrupts.
1042          */
1043         rt2500pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1044 }
1045
1046 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1047                                enum dev_state state)
1048 {
1049         u32 reg;
1050         unsigned int i;
1051         char put_to_sleep;
1052         char bbp_state;
1053         char rf_state;
1054
1055         put_to_sleep = (state != STATE_AWAKE);
1056
1057         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1058         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1059         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1060         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1061         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1062         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1063
1064         /*
1065          * Device is not guaranteed to be in the requested state yet.
1066          * We must wait until the register indicates that the
1067          * device has entered the correct state.
1068          */
1069         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1070                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1071                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1072                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1073                 if (bbp_state == state && rf_state == state)
1074                         return 0;
1075                 msleep(10);
1076         }
1077
1078         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1079                "current device state: bbp %d and rf %d.\n",
1080                state, bbp_state, rf_state);
1081
1082         return -EBUSY;
1083 }
1084
1085 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1086                                       enum dev_state state)
1087 {
1088         int retval = 0;
1089
1090         switch (state) {
1091         case STATE_RADIO_ON:
1092                 retval = rt2500pci_enable_radio(rt2x00dev);
1093                 break;
1094         case STATE_RADIO_OFF:
1095                 rt2500pci_disable_radio(rt2x00dev);
1096                 break;
1097         case STATE_RADIO_RX_ON:
1098         case STATE_RADIO_RX_ON_LINK:
1099                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
1100                 break;
1101         case STATE_RADIO_RX_OFF:
1102         case STATE_RADIO_RX_OFF_LINK:
1103                 rt2500pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
1104                 break;
1105         case STATE_DEEP_SLEEP:
1106         case STATE_SLEEP:
1107         case STATE_STANDBY:
1108         case STATE_AWAKE:
1109                 retval = rt2500pci_set_state(rt2x00dev, state);
1110                 break;
1111         default:
1112                 retval = -ENOTSUPP;
1113                 break;
1114         }
1115
1116         return retval;
1117 }
1118
1119 /*
1120  * TX descriptor initialization
1121  */
1122 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1123                                     struct sk_buff *skb,
1124                                     struct txentry_desc *txdesc,
1125                                     struct ieee80211_tx_control *control)
1126 {
1127         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1128         __le32 *txd = skbdesc->desc;
1129         u32 word;
1130
1131         /*
1132          * Start writing the descriptor words.
1133          */
1134         rt2x00_desc_read(txd, 2, &word);
1135         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1136         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1137         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1138         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1139         rt2x00_desc_write(txd, 2, word);
1140
1141         rt2x00_desc_read(txd, 3, &word);
1142         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1143         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1144         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1145         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1146         rt2x00_desc_write(txd, 3, word);
1147
1148         rt2x00_desc_read(txd, 10, &word);
1149         rt2x00_set_field32(&word, TXD_W10_RTS,
1150                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1151         rt2x00_desc_write(txd, 10, word);
1152
1153         rt2x00_desc_read(txd, 0, &word);
1154         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1155         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1156         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1157                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1158         rt2x00_set_field32(&word, TXD_W0_ACK,
1159                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1160         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1161                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1162         rt2x00_set_field32(&word, TXD_W0_OFDM,
1163                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1164         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1165         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1166         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1167                            !!(control->flags &
1168                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1169         rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
1170         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1171         rt2x00_desc_write(txd, 0, word);
1172 }
1173
1174 /*
1175  * TX data initialization
1176  */
1177 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1178                                     const unsigned int queue)
1179 {
1180         u32 reg;
1181
1182         if (queue == RT2X00_BCN_QUEUE_BEACON) {
1183                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1184                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1185                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1186                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1187                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1188                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1189                 }
1190                 return;
1191         }
1192
1193         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1194         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO,
1195                            (queue == IEEE80211_TX_QUEUE_DATA0));
1196         rt2x00_set_field32(&reg, TXCSR0_KICK_TX,
1197                            (queue == IEEE80211_TX_QUEUE_DATA1));
1198         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM,
1199                            (queue == RT2X00_BCN_QUEUE_ATIM));
1200         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1201 }
1202
1203 /*
1204  * RX control handlers
1205  */
1206 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1207                                   struct rxdone_entry_desc *rxdesc)
1208 {
1209         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1210         u32 word0;
1211         u32 word2;
1212
1213         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1214         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1215
1216         rxdesc->flags = 0;
1217         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1218                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1219         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1220                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1221
1222         /*
1223          * Obtain the status about this packet.
1224          * When frame was received with an OFDM bitrate,
1225          * the signal is the PLCP value. If it was received with
1226          * a CCK bitrate the signal is the rate in 100kbit/s.
1227          */
1228         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1229         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1230             entry->queue->rt2x00dev->rssi_offset;
1231         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1232
1233         rxdesc->dev_flags = 0;
1234         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1235                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1236         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1237                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1238 }
1239
1240 /*
1241  * Interrupt functions.
1242  */
1243 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1244                              const enum ieee80211_tx_queue queue_idx)
1245 {
1246         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1247         struct queue_entry_priv_pci_tx *priv_tx;
1248         struct queue_entry *entry;
1249         struct txdone_entry_desc txdesc;
1250         u32 word;
1251
1252         while (!rt2x00queue_empty(queue)) {
1253                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1254                 priv_tx = entry->priv_data;
1255                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1256
1257                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1258                     !rt2x00_get_field32(word, TXD_W0_VALID))
1259                         break;
1260
1261                 /*
1262                  * Obtain the status about this packet.
1263                  */
1264                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1265                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1266
1267                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1268         }
1269 }
1270
1271 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1272 {
1273         struct rt2x00_dev *rt2x00dev = dev_instance;
1274         u32 reg;
1275
1276         /*
1277          * Get the interrupt sources & saved to local variable.
1278          * Write register value back to clear pending interrupts.
1279          */
1280         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1281         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1282
1283         if (!reg)
1284                 return IRQ_NONE;
1285
1286         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1287                 return IRQ_HANDLED;
1288
1289         /*
1290          * Handle interrupts, walk through all bits
1291          * and run the tasks, the bits are checked in order of
1292          * priority.
1293          */
1294
1295         /*
1296          * 1 - Beacon timer expired interrupt.
1297          */
1298         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1299                 rt2x00lib_beacondone(rt2x00dev);
1300
1301         /*
1302          * 2 - Rx ring done interrupt.
1303          */
1304         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1305                 rt2x00pci_rxdone(rt2x00dev);
1306
1307         /*
1308          * 3 - Atim ring transmit done interrupt.
1309          */
1310         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1311                 rt2500pci_txdone(rt2x00dev, RT2X00_BCN_QUEUE_ATIM);
1312
1313         /*
1314          * 4 - Priority ring transmit done interrupt.
1315          */
1316         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1317                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1318
1319         /*
1320          * 5 - Tx ring transmit done interrupt.
1321          */
1322         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1323                 rt2500pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1324
1325         return IRQ_HANDLED;
1326 }
1327
1328 /*
1329  * Device probe functions.
1330  */
1331 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1332 {
1333         struct eeprom_93cx6 eeprom;
1334         u32 reg;
1335         u16 word;
1336         u8 *mac;
1337
1338         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1339
1340         eeprom.data = rt2x00dev;
1341         eeprom.register_read = rt2500pci_eepromregister_read;
1342         eeprom.register_write = rt2500pci_eepromregister_write;
1343         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1344             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1345         eeprom.reg_data_in = 0;
1346         eeprom.reg_data_out = 0;
1347         eeprom.reg_data_clock = 0;
1348         eeprom.reg_chip_select = 0;
1349
1350         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1351                                EEPROM_SIZE / sizeof(u16));
1352
1353         /*
1354          * Start validation of the data that has been read.
1355          */
1356         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1357         if (!is_valid_ether_addr(mac)) {
1358                 DECLARE_MAC_BUF(macbuf);
1359
1360                 random_ether_addr(mac);
1361                 EEPROM(rt2x00dev, "MAC: %s\n",
1362                        print_mac(macbuf, mac));
1363         }
1364
1365         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1366         if (word == 0xffff) {
1367                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1368                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1369                                    ANTENNA_SW_DIVERSITY);
1370                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1371                                    ANTENNA_SW_DIVERSITY);
1372                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1373                                    LED_MODE_DEFAULT);
1374                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1375                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1376                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1377                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1378                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1379         }
1380
1381         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1382         if (word == 0xffff) {
1383                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1384                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1385                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1386                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1387                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1388         }
1389
1390         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1391         if (word == 0xffff) {
1392                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1393                                    DEFAULT_RSSI_OFFSET);
1394                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1395                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1396         }
1397
1398         return 0;
1399 }
1400
1401 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1402 {
1403         u32 reg;
1404         u16 value;
1405         u16 eeprom;
1406
1407         /*
1408          * Read EEPROM word for configuration.
1409          */
1410         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1411
1412         /*
1413          * Identify RF chipset.
1414          */
1415         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1416         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1417         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1418
1419         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1420             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1421             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1422             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1423             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1424             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1425                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1426                 return -ENODEV;
1427         }
1428
1429         /*
1430          * Identify default antenna configuration.
1431          */
1432         rt2x00dev->default_ant.tx =
1433             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1434         rt2x00dev->default_ant.rx =
1435             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1436
1437         /*
1438          * Store led mode, for correct led behaviour.
1439          */
1440 #ifdef CONFIG_RT2500PCI_LEDS
1441         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1442
1443         switch (value) {
1444         case LED_MODE_ASUS:
1445         case LED_MODE_ALPHA:
1446         case LED_MODE_DEFAULT:
1447                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1448                 break;
1449         case LED_MODE_TXRX_ACTIVITY:
1450                 rt2x00dev->led_flags =
1451                     LED_SUPPORT_RADIO | LED_SUPPORT_ACTIVITY;
1452                 break;
1453         case LED_MODE_SIGNAL_STRENGTH:
1454                 rt2x00dev->led_flags = LED_SUPPORT_RADIO;
1455                 break;
1456         }
1457 #endif /* CONFIG_RT2500PCI_LEDS */
1458
1459         /*
1460          * Detect if this device has an hardware controlled radio.
1461          */
1462 #ifdef CONFIG_RT2500PCI_RFKILL
1463         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1464                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1465 #endif /* CONFIG_RT2500PCI_RFKILL */
1466
1467         /*
1468          * Check if the BBP tuning should be enabled.
1469          */
1470         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1471
1472         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1473                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1474
1475         /*
1476          * Read the RSSI <-> dBm offset information.
1477          */
1478         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1479         rt2x00dev->rssi_offset =
1480             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1481
1482         return 0;
1483 }
1484
1485 /*
1486  * RF value list for RF2522
1487  * Supports: 2.4 GHz
1488  */
1489 static const struct rf_channel rf_vals_bg_2522[] = {
1490         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1491         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1492         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1493         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1494         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1495         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1496         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1497         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1498         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1499         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1500         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1501         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1502         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1503         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1504 };
1505
1506 /*
1507  * RF value list for RF2523
1508  * Supports: 2.4 GHz
1509  */
1510 static const struct rf_channel rf_vals_bg_2523[] = {
1511         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1512         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1513         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1514         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1515         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1516         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1517         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1518         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1519         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1520         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1521         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1522         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1523         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1524         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1525 };
1526
1527 /*
1528  * RF value list for RF2524
1529  * Supports: 2.4 GHz
1530  */
1531 static const struct rf_channel rf_vals_bg_2524[] = {
1532         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1533         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1534         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1535         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1536         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1537         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1538         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1539         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1540         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1541         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1542         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1543         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1544         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1545         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1546 };
1547
1548 /*
1549  * RF value list for RF2525
1550  * Supports: 2.4 GHz
1551  */
1552 static const struct rf_channel rf_vals_bg_2525[] = {
1553         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1554         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1555         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1556         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1557         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1558         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1559         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1560         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1561         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1562         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1563         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1564         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1565         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1566         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1567 };
1568
1569 /*
1570  * RF value list for RF2525e
1571  * Supports: 2.4 GHz
1572  */
1573 static const struct rf_channel rf_vals_bg_2525e[] = {
1574         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1575         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1576         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1577         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1578         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1579         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1580         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1581         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1582         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1583         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1584         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1585         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1586         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1587         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1588 };
1589
1590 /*
1591  * RF value list for RF5222
1592  * Supports: 2.4 GHz & 5.2 GHz
1593  */
1594 static const struct rf_channel rf_vals_5222[] = {
1595         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1596         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1597         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1598         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1599         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1600         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1601         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1602         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1603         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1604         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1605         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1606         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1607         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1608         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1609
1610         /* 802.11 UNI / HyperLan 2 */
1611         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1612         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1613         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1614         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1615         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1616         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1617         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1618         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1619
1620         /* 802.11 HyperLan 2 */
1621         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1622         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1623         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1624         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1625         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1626         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1627         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1628         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1629         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1630         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1631
1632         /* 802.11 UNII */
1633         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1634         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1635         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1636         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1637         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1638 };
1639
1640 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1641 {
1642         struct hw_mode_spec *spec = &rt2x00dev->spec;
1643         u8 *txpower;
1644         unsigned int i;
1645
1646         /*
1647          * Initialize all hw fields.
1648          */
1649         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1650         rt2x00dev->hw->extra_tx_headroom = 0;
1651         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1652         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1653         rt2x00dev->hw->queues = 2;
1654
1655         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1656         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1657                                 rt2x00_eeprom_addr(rt2x00dev,
1658                                                    EEPROM_MAC_ADDR_0));
1659
1660         /*
1661          * Convert tx_power array in eeprom.
1662          */
1663         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1664         for (i = 0; i < 14; i++)
1665                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1666
1667         /*
1668          * Initialize hw_mode information.
1669          */
1670         spec->supported_bands = SUPPORT_BAND_2GHZ;
1671         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1672         spec->tx_power_a = NULL;
1673         spec->tx_power_bg = txpower;
1674         spec->tx_power_default = DEFAULT_TXPOWER;
1675
1676         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1677                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1678                 spec->channels = rf_vals_bg_2522;
1679         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1680                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1681                 spec->channels = rf_vals_bg_2523;
1682         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1683                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1684                 spec->channels = rf_vals_bg_2524;
1685         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1686                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1687                 spec->channels = rf_vals_bg_2525;
1688         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1689                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1690                 spec->channels = rf_vals_bg_2525e;
1691         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1692                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1693                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1694                 spec->channels = rf_vals_5222;
1695         }
1696 }
1697
1698 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1699 {
1700         int retval;
1701
1702         /*
1703          * Allocate eeprom data.
1704          */
1705         retval = rt2500pci_validate_eeprom(rt2x00dev);
1706         if (retval)
1707                 return retval;
1708
1709         retval = rt2500pci_init_eeprom(rt2x00dev);
1710         if (retval)
1711                 return retval;
1712
1713         /*
1714          * Initialize hw specifications.
1715          */
1716         rt2500pci_probe_hw_mode(rt2x00dev);
1717
1718         /*
1719          * This device requires the atim queue
1720          */
1721         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1722
1723         /*
1724          * Set the rssi offset.
1725          */
1726         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1727
1728         return 0;
1729 }
1730
1731 /*
1732  * IEEE80211 stack callback functions.
1733  */
1734 static void rt2500pci_configure_filter(struct ieee80211_hw *hw,
1735                                        unsigned int changed_flags,
1736                                        unsigned int *total_flags,
1737                                        int mc_count,
1738                                        struct dev_addr_list *mc_list)
1739 {
1740         struct rt2x00_dev *rt2x00dev = hw->priv;
1741         u32 reg;
1742
1743         /*
1744          * Mask off any flags we are going to ignore from
1745          * the total_flags field.
1746          */
1747         *total_flags &=
1748             FIF_ALLMULTI |
1749             FIF_FCSFAIL |
1750             FIF_PLCPFAIL |
1751             FIF_CONTROL |
1752             FIF_OTHER_BSS |
1753             FIF_PROMISC_IN_BSS;
1754
1755         /*
1756          * Apply some rules to the filters:
1757          * - Some filters imply different filters to be set.
1758          * - Some things we can't filter out at all.
1759          */
1760         if (mc_count)
1761                 *total_flags |= FIF_ALLMULTI;
1762         if (*total_flags & FIF_OTHER_BSS ||
1763             *total_flags & FIF_PROMISC_IN_BSS)
1764                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1765
1766         /*
1767          * Check if there is any work left for us.
1768          */
1769         if (rt2x00dev->packet_filter == *total_flags)
1770                 return;
1771         rt2x00dev->packet_filter = *total_flags;
1772
1773         /*
1774          * Start configuration steps.
1775          * Note that the version error will always be dropped
1776          * and broadcast frames will always be accepted since
1777          * there is no filter for it at this time.
1778          */
1779         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1780         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1781                            !(*total_flags & FIF_FCSFAIL));
1782         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1783                            !(*total_flags & FIF_PLCPFAIL));
1784         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1785                            !(*total_flags & FIF_CONTROL));
1786         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1787                            !(*total_flags & FIF_PROMISC_IN_BSS));
1788         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1789                            !(*total_flags & FIF_PROMISC_IN_BSS));
1790         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1791         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
1792                            !(*total_flags & FIF_ALLMULTI));
1793         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
1794         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1795 }
1796
1797 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1798                                      u32 short_retry, u32 long_retry)
1799 {
1800         struct rt2x00_dev *rt2x00dev = hw->priv;
1801         u32 reg;
1802
1803         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1804         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1805         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1806         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1807
1808         return 0;
1809 }
1810
1811 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1812 {
1813         struct rt2x00_dev *rt2x00dev = hw->priv;
1814         u64 tsf;
1815         u32 reg;
1816
1817         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1818         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1819         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1820         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1821
1822         return tsf;
1823 }
1824
1825 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1826                                    struct ieee80211_tx_control *control)
1827 {
1828         struct rt2x00_dev *rt2x00dev = hw->priv;
1829         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1830         struct queue_entry_priv_pci_tx *priv_tx;
1831         struct skb_frame_desc *skbdesc;
1832         u32 reg;
1833
1834         if (unlikely(!intf->beacon))
1835                 return -ENOBUFS;
1836
1837         priv_tx = intf->beacon->priv_data;
1838
1839         /*
1840          * Fill in skb descriptor
1841          */
1842         skbdesc = get_skb_frame_desc(skb);
1843         memset(skbdesc, 0, sizeof(*skbdesc));
1844         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1845         skbdesc->data = skb->data;
1846         skbdesc->data_len = skb->len;
1847         skbdesc->desc = priv_tx->desc;
1848         skbdesc->desc_len = intf->beacon->queue->desc_size;
1849         skbdesc->entry = intf->beacon;
1850
1851         /*
1852          * Disable beaconing while we are reloading the beacon data,
1853          * otherwise we might be sending out invalid data.
1854          */
1855         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1856         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1857         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1858         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1859         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1860
1861         /*
1862          * mac80211 doesn't provide the control->queue variable
1863          * for beacons. Set our own queue identification so
1864          * it can be used during descriptor initialization.
1865          */
1866         control->queue = RT2X00_BCN_QUEUE_BEACON;
1867         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1868
1869         /*
1870          * Enable beacon generation.
1871          * Write entire beacon with descriptor to register,
1872          * and kick the beacon generator.
1873          */
1874         memcpy(priv_tx->data, skb->data, skb->len);
1875         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, control->queue);
1876
1877         return 0;
1878 }
1879
1880 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1881 {
1882         struct rt2x00_dev *rt2x00dev = hw->priv;
1883         u32 reg;
1884
1885         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1886         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1887 }
1888
1889 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1890         .tx                     = rt2x00mac_tx,
1891         .start                  = rt2x00mac_start,
1892         .stop                   = rt2x00mac_stop,
1893         .add_interface          = rt2x00mac_add_interface,
1894         .remove_interface       = rt2x00mac_remove_interface,
1895         .config                 = rt2x00mac_config,
1896         .config_interface       = rt2x00mac_config_interface,
1897         .configure_filter       = rt2500pci_configure_filter,
1898         .get_stats              = rt2x00mac_get_stats,
1899         .set_retry_limit        = rt2500pci_set_retry_limit,
1900         .bss_info_changed       = rt2x00mac_bss_info_changed,
1901         .conf_tx                = rt2x00mac_conf_tx,
1902         .get_tx_stats           = rt2x00mac_get_tx_stats,
1903         .get_tsf                = rt2500pci_get_tsf,
1904         .beacon_update          = rt2500pci_beacon_update,
1905         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1906 };
1907
1908 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1909         .irq_handler            = rt2500pci_interrupt,
1910         .probe_hw               = rt2500pci_probe_hw,
1911         .initialize             = rt2x00pci_initialize,
1912         .uninitialize           = rt2x00pci_uninitialize,
1913         .init_rxentry           = rt2500pci_init_rxentry,
1914         .init_txentry           = rt2500pci_init_txentry,
1915         .set_device_state       = rt2500pci_set_device_state,
1916         .rfkill_poll            = rt2500pci_rfkill_poll,
1917         .link_stats             = rt2500pci_link_stats,
1918         .reset_tuner            = rt2500pci_reset_tuner,
1919         .link_tuner             = rt2500pci_link_tuner,
1920         .led_brightness         = rt2500pci_led_brightness,
1921         .write_tx_desc          = rt2500pci_write_tx_desc,
1922         .write_tx_data          = rt2x00pci_write_tx_data,
1923         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1924         .fill_rxdone            = rt2500pci_fill_rxdone,
1925         .config_intf            = rt2500pci_config_intf,
1926         .config_erp             = rt2500pci_config_erp,
1927         .config                 = rt2500pci_config,
1928 };
1929
1930 static const struct data_queue_desc rt2500pci_queue_rx = {
1931         .entry_num              = RX_ENTRIES,
1932         .data_size              = DATA_FRAME_SIZE,
1933         .desc_size              = RXD_DESC_SIZE,
1934         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1935 };
1936
1937 static const struct data_queue_desc rt2500pci_queue_tx = {
1938         .entry_num              = TX_ENTRIES,
1939         .data_size              = DATA_FRAME_SIZE,
1940         .desc_size              = TXD_DESC_SIZE,
1941         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1942 };
1943
1944 static const struct data_queue_desc rt2500pci_queue_bcn = {
1945         .entry_num              = BEACON_ENTRIES,
1946         .data_size              = MGMT_FRAME_SIZE,
1947         .desc_size              = TXD_DESC_SIZE,
1948         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1949 };
1950
1951 static const struct data_queue_desc rt2500pci_queue_atim = {
1952         .entry_num              = ATIM_ENTRIES,
1953         .data_size              = DATA_FRAME_SIZE,
1954         .desc_size              = TXD_DESC_SIZE,
1955         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1956 };
1957
1958 static const struct rt2x00_ops rt2500pci_ops = {
1959         .name           = KBUILD_MODNAME,
1960         .max_sta_intf   = 1,
1961         .max_ap_intf    = 1,
1962         .eeprom_size    = EEPROM_SIZE,
1963         .rf_size        = RF_SIZE,
1964         .rx             = &rt2500pci_queue_rx,
1965         .tx             = &rt2500pci_queue_tx,
1966         .bcn            = &rt2500pci_queue_bcn,
1967         .atim           = &rt2500pci_queue_atim,
1968         .lib            = &rt2500pci_rt2x00_ops,
1969         .hw             = &rt2500pci_mac80211_ops,
1970 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1971         .debugfs        = &rt2500pci_rt2x00debug,
1972 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1973 };
1974
1975 /*
1976  * RT2500pci module information.
1977  */
1978 static struct pci_device_id rt2500pci_device_table[] = {
1979         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1980         { 0, }
1981 };
1982
1983 MODULE_AUTHOR(DRV_PROJECT);
1984 MODULE_VERSION(DRV_VERSION);
1985 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1986 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1987 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1988 MODULE_LICENSE("GPL");
1989
1990 static struct pci_driver rt2500pci_driver = {
1991         .name           = KBUILD_MODNAME,
1992         .id_table       = rt2500pci_device_table,
1993         .probe          = rt2x00pci_probe,
1994         .remove         = __devexit_p(rt2x00pci_remove),
1995         .suspend        = rt2x00pci_suspend,
1996         .resume         = rt2x00pci_resume,
1997 };
1998
1999 static int __init rt2500pci_init(void)
2000 {
2001         return pci_register_driver(&rt2500pci_driver);
2002 }
2003
2004 static void __exit rt2500pci_exit(void)
2005 {
2006         pci_unregister_driver(&rt2500pci_driver);
2007 }
2008
2009 module_init(rt2500pci_init);
2010 module_exit(rt2500pci_exit);