err.no Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2400pci"
  31
  32 #include <linux/delay.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/init.h>
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/eeprom_93cx6.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2x00pci.h"
  42 #include "rt2400pci.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2x00pci_register_read and rt2x00pci_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  */
  57 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  58 {
  59         u32 reg;
  60         unsigned int i;
  61
  62         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  63                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  64                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  65                         break;
  66                 udelay(REGISTER_BUSY_DELAY);
  67         }
  68
  69         return reg;
  70 }
  71
  72 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  73                                 const unsigned int word, const u8 value)
  74 {
  75         u32 reg;
  76
  77         /*
  78          * Wait until the BBP becomes ready.
  79          */
  80         reg = rt2400pci_bbp_check(rt2x00dev);
  81         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  82                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  83                 return;
  84         }
  85
  86         /*
  87          * Write the data into the BBP.
  88          */
  89         reg = 0;
  90         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  91         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  92         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  93         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  94
  95         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  96 }
  97
  98 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  99                                const unsigned int word, u8 *value)
 100 {
 101         u32 reg;
 102
 103         /*
 104          * Wait until the BBP becomes ready.
 105          */
 106         reg = rt2400pci_bbp_check(rt2x00dev);
 107         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 108                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 109                 return;
 110         }
 111
 112         /*
 113          * Write the request into the BBP.
 114          */
 115         reg = 0;
 116         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 117         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 118         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 119
 120         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 121
 122         /*
 123          * Wait until the BBP becomes ready.
 124          */
 125         reg = rt2400pci_bbp_check(rt2x00dev);
 126         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 127                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 128                 *value = 0xff;
 129                 return;
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 133 }
 134
 135 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 136                                const unsigned int word, const u32 value)
 137 {
 138         u32 reg;
 139         unsigned int i;
 140
 141         if (!word)
 142                 return;
 143
 144         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 145                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 146                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 147                         goto rf_write;
 148                 udelay(REGISTER_BUSY_DELAY);
 149         }
 150
 151         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 152         return;
 153
 154 rf_write:
 155         reg = 0;
 156         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 157         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 158         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 159         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 160
 161         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 162         rt2x00_rf_write(rt2x00dev, word, value);
 163 }
 164
 165 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 173         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 174         eeprom->reg_data_clock =
 175             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 176         eeprom->reg_chip_select =
 177             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 178 }
 179
 180 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 181 {
 182         struct rt2x00_dev *rt2x00dev = eeprom->data;
 183         u32 reg = 0;
 184
 185         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 186         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 188                            !!eeprom->reg_data_clock);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 190                            !!eeprom->reg_chip_select);
 191
 192         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 196 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 197
 198 static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
 199                                const unsigned int word, u32 *data)
 200 {
 201         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 202 }
 203
 204 static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
 205                                 const unsigned int word, u32 data)
 206 {
 207         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 208 }
 209
 210 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 211         .owner  = THIS_MODULE,
 212         .csr    = {
 213                 .read           = rt2400pci_read_csr,
 214                 .write          = rt2400pci_write_csr,
 215                 .word_size      = sizeof(u32),
 216                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 217         },
 218         .eeprom = {
 219                 .read           = rt2x00_eeprom_read,
 220                 .write          = rt2x00_eeprom_write,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt2400pci_bbp_read,
 226                 .write          = rt2400pci_bbp_write,
 227                 .word_size      = sizeof(u8),
 228                 .word_count     = BBP_SIZE / sizeof(u8),
 229         },
 230         .rf     = {
 231                 .read           = rt2x00_rf_read,
 232                 .write          = rt2400pci_rf_write,
 233                 .word_size      = sizeof(u32),
 234                 .word_count     = RF_SIZE / sizeof(u32),
 235         },
 236 };
 237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 238
 239 #ifdef CONFIG_RT2400PCI_RFKILL
 240 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 241 {
 242         u32 reg;
 243
 244         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 245         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 246 }
 247 #endif /* CONFIG_RT2400PCI_RFKILL */
 248
 249 /*
 250  * Configuration handlers.
 251  */
 252 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
 253                                       __le32 *mac)
 254 {
 255         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
 256                                       (2 * sizeof(__le32)));
 257 }
 258
 259 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
 260                                    __le32 *bssid)
 261 {
 262         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
 263                                       (2 * sizeof(__le32)));
 264 }
 265
 266 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type)
 267 {
 268         struct interface *intf = &rt2x00dev->interface;
 269         u32 reg;
 270
 271         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 272
 273         /*
 274          * Enable beacon config
 275          */
 276         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 277         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 278                            PREAMBLE + get_duration(IEEE80211_HEADER, 2));
 279         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 280
 281         /*
 282          * Enable synchronisation.
 283          */
 284         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 285         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 286         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 287         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 288         if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
 289             is_interface_type(intf, IEEE80211_IF_TYPE_AP))
 290                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
 291         else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
 292                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
 293         else
 294                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 295         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 296 }
 297
 298 static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
 299 {
 300         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
 301         u32 reg;
 302         u32 preamble;
 303         u16 value;
 304
 305         if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
 306                 preamble = SHORT_PREAMBLE;
 307         else
 308                 preamble = PREAMBLE;
 309
 310         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
 311         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
 312
 313         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 314         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
 315                  SHORT_DIFS : DIFS) +
 316             PLCP + preamble + get_duration(ACK_SIZE, 10);
 317         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
 318         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
 319         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
 320         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 321
 322         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
 323
 324         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 325         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
 326         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 327         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 328         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 329
 330         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 331         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
 332         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 333         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 334         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 335
 336         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 337         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
 338         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 339         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 340         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 341
 342         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 343         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
 344         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 345         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 346         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 347 }
 348
 349 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 350                                      const int phymode)
 351 {
 352         struct ieee80211_hw_mode *mode;
 353         struct ieee80211_rate *rate;
 354
 355         rt2x00dev->curr_hwmode = HWMODE_B;
 356
 357         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
 358         rate = &mode->rates[mode->num_rates - 1];
 359
 360         rt2400pci_config_rate(rt2x00dev, rate->val2);
 361 }
 362
 363 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 364                                      const int index, const int channel)
 365 {
 366         struct rf_channel reg;
 367
 368         /*
 369          * Fill rf_reg structure.
 370          */
 371         memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
 372
 373         /*
 374          * Switch on tuning bits.
 375          */
 376         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
 377         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
 378
 379         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 380         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
 381         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 382
 383         /*
 384          * RF2420 chipset don't need any additional actions.
 385          */
 386         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 387                 return;
 388
 389         /*
 390          * For the RT2421 chipsets we need to write an invalid
 391          * reference clock rate to activate auto_tune.
 392          * After that we set the value back to the correct channel.
 393          */
 394         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 395         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 396         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 397
 398         msleep(1);
 399
 400         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 401         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
 402         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 403
 404         msleep(1);
 405
 406         /*
 407          * Switch off tuning bits.
 408          */
 409         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
 410         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
 411
 412         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 413         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 414
 415         /*
 416          * Clear false CRC during channel switch.
 417          */
 418         rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
 419 }
 420
 421 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 422 {
 423         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 424 }
 425
 426 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 427                                      int antenna_tx, int antenna_rx)
 428 {
 429         u8 r1;
 430         u8 r4;
 431
 432         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 433         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 434
 435         /*
 436          * Configure the TX antenna.
 437          */
 438         switch (antenna_tx) {
 439         case ANTENNA_SW_DIVERSITY:
 440         case ANTENNA_HW_DIVERSITY:
 441                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 442                 break;
 443         case ANTENNA_A:
 444                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 445                 break;
 446         case ANTENNA_B:
 447                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 448                 break;
 449         }
 450
 451         /*
 452          * Configure the RX antenna.
 453          */
 454         switch (antenna_rx) {
 455         case ANTENNA_SW_DIVERSITY:
 456         case ANTENNA_HW_DIVERSITY:
 457                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 458                 break;
 459         case ANTENNA_A:
 460                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 461                 break;
 462         case ANTENNA_B:
 463                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 464                 break;
 465         }
 466
 467         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 468         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 469 }
 470
 471 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 472                                       int short_slot_time, int beacon_int)
 473 {
 474         u32 reg;
 475
 476         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 477         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
 478                            short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
 479         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 480
 481         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 482         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
 483         rt2x00_set_field32(&reg, CSR18_PIFS,
 484                            short_slot_time ? SHORT_PIFS : PIFS);
 485         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 486
 487         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 488         rt2x00_set_field32(&reg, CSR19_DIFS,
 489                            short_slot_time ? SHORT_DIFS : DIFS);
 490         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
 491         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 492
 493         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 494         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 495         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 496         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 497
 498         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 499         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
 500         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
 501         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 502 }
 503
 504 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 505                              const unsigned int flags,
 506                              struct ieee80211_conf *conf)
 507 {
 508         int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
 509
 510         if (flags & CONFIG_UPDATE_PHYMODE)
 511                 rt2400pci_config_phymode(rt2x00dev, conf->phymode);
 512         if (flags & CONFIG_UPDATE_CHANNEL)
 513                 rt2400pci_config_channel(rt2x00dev, conf->channel_val,
 514                                          conf->channel);
 515         if (flags & CONFIG_UPDATE_TXPOWER)
 516                 rt2400pci_config_txpower(rt2x00dev, conf->power_level);
 517         if (flags & CONFIG_UPDATE_ANTENNA)
 518                 rt2400pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
 519                                          conf->antenna_sel_rx);
 520         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 521                 rt2400pci_config_duration(rt2x00dev, short_slot_time,
 522                                           conf->beacon_int);
 523 }
 524
 525 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 526                                 struct ieee80211_tx_queue_params *params)
 527 {
 528         u32 reg;
 529
 530         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 531         rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
 532         rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
 533         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 534 }
 535
 536 /*
 537  * LED functions.
 538  */
 539 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
 540 {
 541         u32 reg;
 542
 543         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 544
 545         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 546         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 547
 548         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 549                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 550                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 551         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 552                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 553                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 554         } else {
 555                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 556                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 557         }
 558
 559         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 560 }
 561
 562 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
 563 {
 564         u32 reg;
 565
 566         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 567         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 568         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 569         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 570 }
 571
 572 /*
 573  * Link tuning
 574  */
 575 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
 576 {
 577         u32 reg;
 578         u8 bbp;
 579
 580         /*
 581          * Update FCS error count from register.
 582          */
 583         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 584         rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 585
 586         /*
 587          * Update False CCA count from register.
 588          */
 589         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 590         rt2x00dev->link.false_cca = bbp;
 591 }
 592
 593 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 594 {
 595         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 596         rt2x00dev->link.vgc_level = 0x08;
 597 }
 598
 599 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 600 {
 601         u8 reg;
 602
 603         /*
 604          * The link tuner should not run longer then 60 seconds,
 605          * and should run once every 2 seconds.
 606          */
 607         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 608                 return;
 609
 610         /*
 611          * Base r13 link tuning on the false cca count.
 612          */
 613         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 614
 615         if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
 616                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 617                 rt2x00dev->link.vgc_level = reg;
 618         } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
 619                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 620                 rt2x00dev->link.vgc_level = reg;
 621         }
 622 }
 623
 624 /*
 625  * Initialization functions.
 626  */
 627 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 628 {
 629         struct data_ring *ring = rt2x00dev->rx;
 630         struct data_desc *rxd;
 631         unsigned int i;
 632         u32 word;
 633
 634         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 635
 636         for (i = 0; i < ring->stats.limit; i++) {
 637                 rxd = ring->entry[i].priv;
 638
 639                 rt2x00_desc_read(rxd, 2, &word);
 640                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 641                                    ring->data_size);
 642                 rt2x00_desc_write(rxd, 2, word);
 643
 644                 rt2x00_desc_read(rxd, 1, &word);
 645                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 646                                    ring->entry[i].data_dma);
 647                 rt2x00_desc_write(rxd, 1, word);
 648
 649                 rt2x00_desc_read(rxd, 0, &word);
 650                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 651                 rt2x00_desc_write(rxd, 0, word);
 652         }
 653
 654         rt2x00_ring_index_clear(rt2x00dev->rx);
 655 }
 656
 657 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
 658 {
 659         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
 660         struct data_desc *txd;
 661         unsigned int i;
 662         u32 word;
 663
 664         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 665
 666         for (i = 0; i < ring->stats.limit; i++) {
 667                 txd = ring->entry[i].priv;
 668
 669                 rt2x00_desc_read(txd, 1, &word);
 670                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 671                                    ring->entry[i].data_dma);
 672                 rt2x00_desc_write(txd, 1, word);
 673
 674                 rt2x00_desc_read(txd, 2, &word);
 675                 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 676                                    ring->data_size);
 677                 rt2x00_desc_write(txd, 2, word);
 678
 679                 rt2x00_desc_read(txd, 0, &word);
 680                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 681                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 682                 rt2x00_desc_write(txd, 0, word);
 683         }
 684
 685         rt2x00_ring_index_clear(ring);
 686 }
 687
 688 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
 689 {
 690         u32 reg;
 691
 692         /*
 693          * Initialize rings.
 694          */
 695         rt2400pci_init_rxring(rt2x00dev);
 696         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 697         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 698         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 699         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 700
 701         /*
 702          * Initialize registers.
 703          */
 704         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 705         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 706                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 707         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 708                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 709         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 710                            rt2x00dev->bcn[1].stats.limit);
 711         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 712                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 713         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 714
 715         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 716         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 717                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 718         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 719
 720         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 721         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 722                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 723         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 724
 725         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 726         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 727                            rt2x00dev->bcn[1].data_dma);
 728         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 729
 730         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 731         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 732                            rt2x00dev->bcn[0].data_dma);
 733         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 734
 735         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 736         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 737         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 738         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 739
 740         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 741         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 742                            rt2x00dev->rx->data_dma);
 743         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 744
 745         return 0;
 746 }
 747
 748 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 749 {
 750         u32 reg;
 751
 752         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 753         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 754         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 755         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 756
 757         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 758         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 759         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 760         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 761         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 762
 763         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 764         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 765                            (rt2x00dev->rx->data_size / 128));
 766         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 767
 768         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 769
 770         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 771         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 772         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 773         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 774         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 775         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 776
 777         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 778         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 779         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 780         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 781         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 782         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 783         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 784         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 785
 786         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 787
 788         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 789                 return -EBUSY;
 790
 791         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 792         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 793
 794         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 795         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 796         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 797
 798         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 799         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 800         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 801         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 802         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 803         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 804
 805         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 806         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 807         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 808         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 809         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 810
 811         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 812         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 813         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 814         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 815
 816         /*
 817          * We must clear the FCS and FIFO error count.
 818          * These registers are cleared on read,
 819          * so we may pass a useless variable to store the value.
 820          */
 821         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 822         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 823
 824         return 0;
 825 }
 826
 827 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 828 {
 829         unsigned int i;
 830         u16 eeprom;
 831         u8 reg_id;
 832         u8 value;
 833
 834         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 835                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 836                 if ((value != 0xff) && (value != 0x00))
 837                         goto continue_csr_init;
 838                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 839                 udelay(REGISTER_BUSY_DELAY);
 840         }
 841
 842         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 843         return -EACCES;
 844
 845 continue_csr_init:
 846         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 847         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 848         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 849         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 850         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 851         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 852         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 853         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 854         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 855         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 856         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 857         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 858         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 859         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 860
 861         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 862         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 863                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 864
 865                 if (eeprom != 0xffff && eeprom != 0x0000) {
 866                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 867                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 868                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 869                               reg_id, value);
 870                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 871                 }
 872         }
 873         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 874
 875         return 0;
 876 }
 877
 878 /*
 879  * Device state switch handlers.
 880  */
 881 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 882                                 enum dev_state state)
 883 {
 884         u32 reg;
 885
 886         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 887         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 888                            state == STATE_RADIO_RX_OFF);
 889         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 890 }
 891
 892 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 893                                  enum dev_state state)
 894 {
 895         int mask = (state == STATE_RADIO_IRQ_OFF);
 896         u32 reg;
 897
 898         /*
 899          * When interrupts are being enabled, the interrupt registers
 900          * should clear the register to assure a clean state.
 901          */
 902         if (state == STATE_RADIO_IRQ_ON) {
 903                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 904                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 905         }
 906
 907         /*
 908          * Only toggle the interrupts bits we are going to use.
 909          * Non-checked interrupt bits are disabled by default.
 910          */
 911         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 912         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 913         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 914         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 915         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 916         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 917         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 918 }
 919
 920 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 921 {
 922         /*
 923          * Initialize all registers.
 924          */
 925         if (rt2400pci_init_rings(rt2x00dev) ||
 926             rt2400pci_init_registers(rt2x00dev) ||
 927             rt2400pci_init_bbp(rt2x00dev)) {
 928                 ERROR(rt2x00dev, "Register initialization failed.\n");
 929                 return -EIO;
 930         }
 931
 932         /*
 933          * Enable interrupts.
 934          */
 935         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 936
 937         /*
 938          * Enable LED
 939          */
 940         rt2400pci_enable_led(rt2x00dev);
 941
 942         return 0;
 943 }
 944
 945 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 946 {
 947         u32 reg;
 948
 949         /*
 950          * Disable LED
 951          */
 952         rt2400pci_disable_led(rt2x00dev);
 953
 954         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 955
 956         /*
 957          * Disable synchronisation.
 958          */
 959         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 960
 961         /*
 962          * Cancel RX and TX.
 963          */
 964         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 965         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 966         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 967
 968         /*
 969          * Disable interrupts.
 970          */
 971         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 972 }
 973
 974 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 975                                enum dev_state state)
 976 {
 977         u32 reg;
 978         unsigned int i;
 979         char put_to_sleep;
 980         char bbp_state;
 981         char rf_state;
 982
 983         put_to_sleep = (state != STATE_AWAKE);
 984
 985         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 986         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 987         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 988         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 989         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 990         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 991
 992         /*
 993          * Device is not guaranteed to be in the requested state yet.
 994          * We must wait until the register indicates that the
 995          * device has entered the correct state.
 996          */
 997         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 998                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 999                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1000                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1001                 if (bbp_state == state && rf_state == state)
1002                         return 0;
1003                 msleep(10);
1004         }
1005
1006         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1007                "current device state: bbp %d and rf %d.\n",
1008                state, bbp_state, rf_state);
1009
1010         return -EBUSY;
1011 }
1012
1013 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1014                                       enum dev_state state)
1015 {
1016         int retval = 0;
1017
1018         switch (state) {
1019         case STATE_RADIO_ON:
1020                 retval = rt2400pci_enable_radio(rt2x00dev);
1021                 break;
1022         case STATE_RADIO_OFF:
1023                 rt2400pci_disable_radio(rt2x00dev);
1024                 break;
1025         case STATE_RADIO_RX_ON:
1026         case STATE_RADIO_RX_OFF:
1027                 rt2400pci_toggle_rx(rt2x00dev, state);
1028                 break;
1029         case STATE_DEEP_SLEEP:
1030         case STATE_SLEEP:
1031         case STATE_STANDBY:
1032         case STATE_AWAKE:
1033                 retval = rt2400pci_set_state(rt2x00dev, state);
1034                 break;
1035         default:
1036                 retval = -ENOTSUPP;
1037                 break;
1038         }
1039
1040         return retval;
1041 }
1042
1043 /*
1044  * TX descriptor initialization
1045  */
1046 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1047                                     struct data_desc *txd,
1048                                     struct txdata_entry_desc *desc,
1049                                     struct ieee80211_hdr *ieee80211hdr,
1050                                     unsigned int length,
1051                                     struct ieee80211_tx_control *control)
1052 {
1053         u32 word;
1054         u32 signal = 0;
1055         u32 service = 0;
1056         u32 length_high = 0;
1057         u32 length_low = 0;
1058
1059         /*
1060          * The PLCP values should be treated as if they
1061          * were BBP values.
1062          */
1063         rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1064         rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1065         rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1066
1067         rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1068         rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1069         rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1070
1071         rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1072         rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1073         rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1074
1075         rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1076         rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1077         rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1078
1079         /*
1080          * Start writing the descriptor words.
1081          */
1082         rt2x00_desc_read(txd, 2, &word);
1083         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1084         rt2x00_desc_write(txd, 2, word);
1085
1086         rt2x00_desc_read(txd, 3, &word);
1087         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1088         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1089         rt2x00_desc_write(txd, 3, word);
1090
1091         rt2x00_desc_read(txd, 4, &word);
1092         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1093         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1094         rt2x00_desc_write(txd, 4, word);
1095
1096         rt2x00_desc_read(txd, 0, &word);
1097         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1098         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1099         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1100                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1101         rt2x00_set_field32(&word, TXD_W0_ACK,
1102                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1103         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1104                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1105         rt2x00_set_field32(&word, TXD_W0_RTS,
1106                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1107         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1108         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1109                            !!(control->flags &
1110                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1111         rt2x00_desc_write(txd, 0, word);
1112 }
1113
1114 /*
1115  * TX data initialization
1116  */
1117 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1118                                     unsigned int queue)
1119 {
1120         u32 reg;
1121
1122         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1123                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1124                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1125                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1126                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1127                 }
1128                 return;
1129         }
1130
1131         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1132         if (queue == IEEE80211_TX_QUEUE_DATA0)
1133                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1134         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1135                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1136         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1137                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1138         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1139 }
1140
1141 /*
1142  * RX control handlers
1143  */
1144 static void rt2400pci_fill_rxdone(struct data_entry *entry,
1145                                   struct rxdata_entry_desc *desc)
1146 {
1147         struct data_desc *rxd = entry->priv;
1148         u32 word0;
1149         u32 word2;
1150
1151         rt2x00_desc_read(rxd, 0, &word0);
1152         rt2x00_desc_read(rxd, 2, &word2);
1153
1154         desc->flags = 0;
1155         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1156                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1157         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1158                 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1159
1160         /*
1161          * Obtain the status about this packet.
1162          */
1163         desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1164         desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1165             entry->ring->rt2x00dev->rssi_offset;
1166         desc->ofdm = 0;
1167         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1168 }
1169
1170 /*
1171  * Interrupt functions.
1172  */
1173 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1174 {
1175         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1176         struct data_entry *entry;
1177         struct data_desc *txd;
1178         u32 word;
1179         int tx_status;
1180         int retry;
1181
1182         while (!rt2x00_ring_empty(ring)) {
1183                 entry = rt2x00_get_data_entry_done(ring);
1184                 txd = entry->priv;
1185                 rt2x00_desc_read(txd, 0, &word);
1186
1187                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1188                     !rt2x00_get_field32(word, TXD_W0_VALID))
1189                         break;
1190
1191                 /*
1192                  * Obtain the status about this packet.
1193                  */
1194                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1195                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1196
1197                 rt2x00lib_txdone(entry, tx_status, retry);
1198
1199                 /*
1200                  * Make this entry available for reuse.
1201                  */
1202                 entry->flags = 0;
1203                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1204                 rt2x00_desc_write(txd, 0, word);
1205                 rt2x00_ring_index_done_inc(ring);
1206         }
1207
1208         /*
1209          * If the data ring was full before the txdone handler
1210          * we must make sure the packet queue in the mac80211 stack
1211          * is reenabled when the txdone handler has finished.
1212          */
1213         entry = ring->entry;
1214         if (!rt2x00_ring_full(ring))
1215                 ieee80211_wake_queue(rt2x00dev->hw,
1216                                      entry->tx_status.control.queue);
1217 }
1218
1219 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1220 {
1221         struct rt2x00_dev *rt2x00dev = dev_instance;
1222         u32 reg;
1223
1224         /*
1225          * Get the interrupt sources & saved to local variable.
1226          * Write register value back to clear pending interrupts.
1227          */
1228         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1229         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1230
1231         if (!reg)
1232                 return IRQ_NONE;
1233
1234         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1235                 return IRQ_HANDLED;
1236
1237         /*
1238          * Handle interrupts, walk through all bits
1239          * and run the tasks, the bits are checked in order of
1240          * priority.
1241          */
1242
1243         /*
1244          * 1 - Beacon timer expired interrupt.
1245          */
1246         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1247                 rt2x00lib_beacondone(rt2x00dev);
1248
1249         /*
1250          * 2 - Rx ring done interrupt.
1251          */
1252         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1253                 rt2x00pci_rxdone(rt2x00dev);
1254
1255         /*
1256          * 3 - Atim ring transmit done interrupt.
1257          */
1258         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1259                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1260
1261         /*
1262          * 4 - Priority ring transmit done interrupt.
1263          */
1264         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1265                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1266
1267         /*
1268          * 5 - Tx ring transmit done interrupt.
1269          */
1270         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1271                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1272
1273         return IRQ_HANDLED;
1274 }
1275
1276 /*
1277  * Device probe functions.
1278  */
1279 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1280 {
1281         struct eeprom_93cx6 eeprom;
1282         u32 reg;
1283         u16 word;
1284         u8 *mac;
1285
1286         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1287
1288         eeprom.data = rt2x00dev;
1289         eeprom.register_read = rt2400pci_eepromregister_read;
1290         eeprom.register_write = rt2400pci_eepromregister_write;
1291         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1292             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1293         eeprom.reg_data_in = 0;
1294         eeprom.reg_data_out = 0;
1295         eeprom.reg_data_clock = 0;
1296         eeprom.reg_chip_select = 0;
1297
1298         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1299                                EEPROM_SIZE / sizeof(u16));
1300
1301         /*
1302          * Start validation of the data that has been read.
1303          */
1304         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1305         if (!is_valid_ether_addr(mac)) {
1306                 DECLARE_MAC_BUF(macbuf);
1307
1308                 random_ether_addr(mac);
1309                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1310         }
1311
1312         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1313         if (word == 0xffff) {
1314                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1315                 return -EINVAL;
1316         }
1317
1318         return 0;
1319 }
1320
1321 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1322 {
1323         u32 reg;
1324         u16 value;
1325         u16 eeprom;
1326
1327         /*
1328          * Read EEPROM word for configuration.
1329          */
1330         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1331
1332         /*
1333          * Identify RF chipset.
1334          */
1335         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1336         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1337         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1338
1339         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1340             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1341                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1342                 return -ENODEV;
1343         }
1344
1345         /*
1346          * Identify default antenna configuration.
1347          */
1348         rt2x00dev->hw->conf.antenna_sel_tx =
1349             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1350         rt2x00dev->hw->conf.antenna_sel_rx =
1351             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1352
1353         /*
1354          * Store led mode, for correct led behaviour.
1355          */
1356         rt2x00dev->led_mode =
1357             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1358
1359         /*
1360          * Detect if this device has an hardware controlled radio.
1361          */
1362         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1363                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1364
1365         /*
1366          * Check if the BBP tuning should be enabled.
1367          */
1368         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1369                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1370
1371         return 0;
1372 }
1373
1374 /*
1375  * RF value list for RF2420 & RF2421
1376  * Supports: 2.4 GHz
1377  */
1378 static const struct rf_channel rf_vals_bg[] = {
1379         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1380         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1381         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1382         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1383         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1384         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1385         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1386         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1387         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1388         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1389         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1390         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1391         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1392         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1393 };
1394
1395 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1396 {
1397         struct hw_mode_spec *spec = &rt2x00dev->spec;
1398         u8 *txpower;
1399         unsigned int i;
1400
1401         /*
1402          * Initialize all hw fields.
1403          */
1404         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1405         rt2x00dev->hw->extra_tx_headroom = 0;
1406         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1407         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1408         rt2x00dev->hw->queues = 2;
1409
1410         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1411         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1412                                 rt2x00_eeprom_addr(rt2x00dev,
1413                                                    EEPROM_MAC_ADDR_0));
1414
1415         /*
1416          * Convert tx_power array in eeprom.
1417          */
1418         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1419         for (i = 0; i < 14; i++)
1420                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1421
1422         /*
1423          * Initialize hw_mode information.
1424          */
1425         spec->num_modes = 1;
1426         spec->num_rates = 4;
1427         spec->tx_power_a = NULL;
1428         spec->tx_power_bg = txpower;
1429         spec->tx_power_default = DEFAULT_TXPOWER;
1430
1431         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1432         spec->channels = rf_vals_bg;
1433 }
1434
1435 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1436 {
1437         int retval;
1438
1439         /*
1440          * Allocate eeprom data.
1441          */
1442         retval = rt2400pci_validate_eeprom(rt2x00dev);
1443         if (retval)
1444                 return retval;
1445
1446         retval = rt2400pci_init_eeprom(rt2x00dev);
1447         if (retval)
1448                 return retval;
1449
1450         /*
1451          * Initialize hw specifications.
1452          */
1453         rt2400pci_probe_hw_mode(rt2x00dev);
1454
1455         /*
1456          * This device requires the beacon ring
1457          */
1458         __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1459
1460         /*
1461          * Set the rssi offset.
1462          */
1463         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1464
1465         return 0;
1466 }
1467
1468 /*
1469  * IEEE80211 stack callback functions.
1470  */
1471 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1472                                        unsigned int changed_flags,
1473                                        unsigned int *total_flags,
1474                                        int mc_count,
1475                                        struct dev_addr_list *mc_list)
1476 {
1477         struct rt2x00_dev *rt2x00dev = hw->priv;
1478         struct interface *intf = &rt2x00dev->interface;
1479         u32 reg;
1480
1481         /*
1482          * Mask off any flags we are going to ignore from
1483          * the total_flags field.
1484          */
1485         *total_flags &=
1486             FIF_ALLMULTI |
1487             FIF_FCSFAIL |
1488             FIF_PLCPFAIL |
1489             FIF_CONTROL |
1490             FIF_OTHER_BSS |
1491             FIF_PROMISC_IN_BSS;
1492
1493         /*
1494          * Apply some rules to the filters:
1495          * - Some filters imply different filters to be set.
1496          * - Some things we can't filter out at all.
1497          * - Some filters are set based on interface type.
1498          */
1499         *total_flags |= FIF_ALLMULTI;
1500         if (*total_flags & FIF_OTHER_BSS ||
1501             *total_flags & FIF_PROMISC_IN_BSS)
1502                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1503         if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1504                 *total_flags |= FIF_PROMISC_IN_BSS;
1505
1506         /*
1507          * Check if there is any work left for us.
1508          */
1509         if (intf->filter == *total_flags)
1510                 return;
1511         intf->filter = *total_flags;
1512
1513         /*
1514          * Start configuration steps.
1515          * Note that the version error will always be dropped
1516          * since there is no filter for it at this time.
1517          */
1518         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1519         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1520                            !(*total_flags & FIF_FCSFAIL));
1521         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1522                            !(*total_flags & FIF_PLCPFAIL));
1523         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1524                            !(*total_flags & FIF_CONTROL));
1525         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1526                            !(*total_flags & FIF_PROMISC_IN_BSS));
1527         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1528                            !(*total_flags & FIF_PROMISC_IN_BSS));
1529         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1530         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1531 }
1532
1533 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1534                                      u32 short_retry, u32 long_retry)
1535 {
1536         struct rt2x00_dev *rt2x00dev = hw->priv;
1537         u32 reg;
1538
1539         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1540         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1541         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1542         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1543
1544         return 0;
1545 }
1546
1547 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1548                              int queue,
1549                              const struct ieee80211_tx_queue_params *params)
1550 {
1551         struct rt2x00_dev *rt2x00dev = hw->priv;
1552
1553         /*
1554          * We don't support variating cw_min and cw_max variables
1555          * per queue. So by default we only configure the TX queue,
1556          * and ignore all other configurations.
1557          */
1558         if (queue != IEEE80211_TX_QUEUE_DATA0)
1559                 return -EINVAL;
1560
1561         if (rt2x00mac_conf_tx(hw, queue, params))
1562                 return -EINVAL;
1563
1564         /*
1565          * Write configuration to register.
1566          */
1567         rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1568
1569         return 0;
1570 }
1571
1572 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1573 {
1574         struct rt2x00_dev *rt2x00dev = hw->priv;
1575         u64 tsf;
1576         u32 reg;
1577
1578         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1579         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1580         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1581         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1582
1583         return tsf;
1584 }
1585
1586 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1587 {
1588         struct rt2x00_dev *rt2x00dev = hw->priv;
1589
1590         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1591         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1592 }
1593
1594 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1595 {
1596         struct rt2x00_dev *rt2x00dev = hw->priv;
1597         u32 reg;
1598
1599         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1600         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1601 }
1602
1603 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1604         .tx                     = rt2x00mac_tx,
1605         .start                  = rt2x00mac_start,
1606         .stop                   = rt2x00mac_stop,
1607         .add_interface          = rt2x00mac_add_interface,
1608         .remove_interface       = rt2x00mac_remove_interface,
1609         .config                 = rt2x00mac_config,
1610         .config_interface       = rt2x00mac_config_interface,
1611         .configure_filter       = rt2400pci_configure_filter,
1612         .get_stats              = rt2x00mac_get_stats,
1613         .set_retry_limit        = rt2400pci_set_retry_limit,
1614         .conf_tx                = rt2400pci_conf_tx,
1615         .get_tx_stats           = rt2x00mac_get_tx_stats,
1616         .get_tsf                = rt2400pci_get_tsf,
1617         .reset_tsf              = rt2400pci_reset_tsf,
1618         .beacon_update          = rt2x00pci_beacon_update,
1619         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1620 };
1621
1622 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1623         .irq_handler            = rt2400pci_interrupt,
1624         .probe_hw               = rt2400pci_probe_hw,
1625         .initialize             = rt2x00pci_initialize,
1626         .uninitialize           = rt2x00pci_uninitialize,
1627         .set_device_state       = rt2400pci_set_device_state,
1628 #ifdef CONFIG_RT2400PCI_RFKILL
1629         .rfkill_poll            = rt2400pci_rfkill_poll,
1630 #endif /* CONFIG_RT2400PCI_RFKILL */
1631         .link_stats             = rt2400pci_link_stats,
1632         .reset_tuner            = rt2400pci_reset_tuner,
1633         .link_tuner             = rt2400pci_link_tuner,
1634         .write_tx_desc          = rt2400pci_write_tx_desc,
1635         .write_tx_data          = rt2x00pci_write_tx_data,
1636         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1637         .fill_rxdone            = rt2400pci_fill_rxdone,
1638         .config_mac_addr        = rt2400pci_config_mac_addr,
1639         .config_bssid           = rt2400pci_config_bssid,
1640         .config_type            = rt2400pci_config_type,
1641         .config                 = rt2400pci_config,
1642 };
1643
1644 static const struct rt2x00_ops rt2400pci_ops = {
1645         .name           = DRV_NAME,
1646         .rxd_size       = RXD_DESC_SIZE,
1647         .txd_size       = TXD_DESC_SIZE,
1648         .eeprom_size    = EEPROM_SIZE,
1649         .rf_size        = RF_SIZE,
1650         .lib            = &rt2400pci_rt2x00_ops,
1651         .hw             = &rt2400pci_mac80211_ops,
1652 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1653         .debugfs        = &rt2400pci_rt2x00debug,
1654 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1655 };
1656
1657 /*
1658  * RT2400pci module information.
1659  */
1660 static struct pci_device_id rt2400pci_device_table[] = {
1661         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1662         { 0, }
1663 };
1664
1665 MODULE_AUTHOR(DRV_PROJECT);
1666 MODULE_VERSION(DRV_VERSION);
1667 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1668 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1669 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1670 MODULE_LICENSE("GPL");
1671
1672 static struct pci_driver rt2400pci_driver = {
1673         .name           = DRV_NAME,
1674         .id_table       = rt2400pci_device_table,
1675         .probe          = rt2x00pci_probe,
1676         .remove         = __devexit_p(rt2x00pci_remove),
1677         .suspend        = rt2x00pci_suspend,
1678         .resume         = rt2x00pci_resume,
1679 };
1680
1681 static int __init rt2400pci_init(void)
1682 {
1683         return pci_register_driver(&rt2400pci_driver);
1684 }
1685
1686 static void __exit rt2400pci_exit(void)
1687 {
1688         pci_unregister_driver(&rt2400pci_driver);
1689 }
1690
1691 module_init(rt2400pci_init);
1692 module_exit(rt2400pci_exit);