err.no Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2400pci"
  31
  32 #include <linux/delay.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/init.h>
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/eeprom_93cx6.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2x00pci.h"
  42 #include "rt2400pci.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2x00pci_register_read and rt2x00pci_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  */
  57 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  58 {
  59         u32 reg;
  60         unsigned int i;
  61
  62         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  63                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  64                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  65                         break;
  66                 udelay(REGISTER_BUSY_DELAY);
  67         }
  68
  69         return reg;
  70 }
  71
  72 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  73                                 const unsigned int word, const u8 value)
  74 {
  75         u32 reg;
  76
  77         /*
  78          * Wait until the BBP becomes ready.
  79          */
  80         reg = rt2400pci_bbp_check(rt2x00dev);
  81         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  82                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  83                 return;
  84         }
  85
  86         /*
  87          * Write the data into the BBP.
  88          */
  89         reg = 0;
  90         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  91         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  92         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  93         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  94
  95         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  96 }
  97
  98 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  99                                const unsigned int word, u8 *value)
 100 {
 101         u32 reg;
 102
 103         /*
 104          * Wait until the BBP becomes ready.
 105          */
 106         reg = rt2400pci_bbp_check(rt2x00dev);
 107         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 108                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 109                 return;
 110         }
 111
 112         /*
 113          * Write the request into the BBP.
 114          */
 115         reg = 0;
 116         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 117         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 118         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 119
 120         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 121
 122         /*
 123          * Wait until the BBP becomes ready.
 124          */
 125         reg = rt2400pci_bbp_check(rt2x00dev);
 126         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 127                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 128                 *value = 0xff;
 129                 return;
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 133 }
 134
 135 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 136                                const unsigned int word, const u32 value)
 137 {
 138         u32 reg;
 139         unsigned int i;
 140
 141         if (!word)
 142                 return;
 143
 144         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 145                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 146                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 147                         goto rf_write;
 148                 udelay(REGISTER_BUSY_DELAY);
 149         }
 150
 151         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 152         return;
 153
 154 rf_write:
 155         reg = 0;
 156         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 157         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 158         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 159         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 160
 161         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 162         rt2x00_rf_write(rt2x00dev, word, value);
 163 }
 164
 165 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 173         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 174         eeprom->reg_data_clock =
 175             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 176         eeprom->reg_chip_select =
 177             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 178 }
 179
 180 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 181 {
 182         struct rt2x00_dev *rt2x00dev = eeprom->data;
 183         u32 reg = 0;
 184
 185         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 186         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 188                            !!eeprom->reg_data_clock);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 190                            !!eeprom->reg_chip_select);
 191
 192         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 196 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 197
 198 static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
 199                                const unsigned int word, u32 *data)
 200 {
 201         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 202 }
 203
 204 static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
 205                                 const unsigned int word, u32 data)
 206 {
 207         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 208 }
 209
 210 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 211         .owner  = THIS_MODULE,
 212         .csr    = {
 213                 .read           = rt2400pci_read_csr,
 214                 .write          = rt2400pci_write_csr,
 215                 .word_size      = sizeof(u32),
 216                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 217         },
 218         .eeprom = {
 219                 .read           = rt2x00_eeprom_read,
 220                 .write          = rt2x00_eeprom_write,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt2400pci_bbp_read,
 226                 .write          = rt2400pci_bbp_write,
 227                 .word_size      = sizeof(u8),
 228                 .word_count     = BBP_SIZE / sizeof(u8),
 229         },
 230         .rf     = {
 231                 .read           = rt2x00_rf_read,
 232                 .write          = rt2400pci_rf_write,
 233                 .word_size      = sizeof(u32),
 234                 .word_count     = RF_SIZE / sizeof(u32),
 235         },
 236 };
 237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 238
 239 #ifdef CONFIG_RT2400PCI_RFKILL
 240 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 241 {
 242         u32 reg;
 243
 244         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 245         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 246 }
 247 #endif /* CONFIG_RT2400PCI_RFKILL */
 248
 249 /*
 250  * Configuration handlers.
 251  */
 252 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
 253 {
 254         __le32 reg[2];
 255
 256         memset(&reg, 0, sizeof(reg));
 257         memcpy(&reg, addr, ETH_ALEN);
 258
 259         /*
 260          * The MAC address is passed to us as an array of bytes,
 261          * that array is little endian, so no need for byte ordering.
 262          */
 263         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, &reg, sizeof(reg));
 264 }
 265
 266 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
 267 {
 268         __le32 reg[2];
 269
 270         memset(&reg, 0, sizeof(reg));
 271         memcpy(&reg, bssid, ETH_ALEN);
 272
 273         /*
 274          * The BSSID is passed to us as an array of bytes,
 275          * that array is little endian, so no need for byte ordering.
 276          */
 277         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, &reg, sizeof(reg));
 278 }
 279
 280 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type)
 281 {
 282         struct interface *intf = &rt2x00dev->interface;
 283         u32 reg;
 284
 285         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 286
 287         /*
 288          * Enable beacon config
 289          */
 290         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 291         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 292                            PREAMBLE + get_duration(IEEE80211_HEADER, 2));
 293         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 294
 295         /*
 296          * Enable synchronisation.
 297          */
 298         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 299         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 300         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 301         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 302         if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
 303             is_interface_type(intf, IEEE80211_IF_TYPE_AP))
 304                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 2);
 305         else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
 306                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 1);
 307         else
 308                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
 309         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 310 }
 311
 312 static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
 313 {
 314         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
 315         u32 reg;
 316         u32 preamble;
 317         u16 value;
 318
 319         if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
 320                 preamble = SHORT_PREAMBLE;
 321         else
 322                 preamble = PREAMBLE;
 323
 324         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
 325         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
 326
 327         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 328         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
 329                  SHORT_DIFS : DIFS) +
 330             PLCP + preamble + get_duration(ACK_SIZE, 10);
 331         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
 332         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
 333         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
 334         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 335
 336         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
 337
 338         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 339         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
 340         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 341         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 342         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 343
 344         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 345         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
 346         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 347         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 348         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 349
 350         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 351         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
 352         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 353         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 354         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 355
 356         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 357         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
 358         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 359         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 360         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 361 }
 362
 363 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 364                                      const int phymode)
 365 {
 366         struct ieee80211_hw_mode *mode;
 367         struct ieee80211_rate *rate;
 368
 369         rt2x00dev->curr_hwmode = HWMODE_B;
 370
 371         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
 372         rate = &mode->rates[mode->num_rates - 1];
 373
 374         rt2400pci_config_rate(rt2x00dev, rate->val2);
 375 }
 376
 377 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 378                                      const int index, const int channel)
 379 {
 380         struct rf_channel reg;
 381
 382         /*
 383          * Fill rf_reg structure.
 384          */
 385         memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
 386
 387         /*
 388          * Switch on tuning bits.
 389          */
 390         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
 391         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
 392
 393         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 394         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
 395         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 396
 397         /*
 398          * RF2420 chipset don't need any additional actions.
 399          */
 400         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 401                 return;
 402
 403         /*
 404          * For the RT2421 chipsets we need to write an invalid
 405          * reference clock rate to activate auto_tune.
 406          * After that we set the value back to the correct channel.
 407          */
 408         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 409         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 410         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 411
 412         msleep(1);
 413
 414         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 415         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
 416         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 417
 418         msleep(1);
 419
 420         /*
 421          * Switch off tuning bits.
 422          */
 423         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
 424         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
 425
 426         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 427         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 428
 429         /*
 430          * Clear false CRC during channel switch.
 431          */
 432         rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
 433 }
 434
 435 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 436 {
 437         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 438 }
 439
 440 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 441                                      int antenna_tx, int antenna_rx)
 442 {
 443         u8 r1;
 444         u8 r4;
 445
 446         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 447         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 448
 449         /*
 450          * Configure the TX antenna.
 451          */
 452         switch (antenna_tx) {
 453         case ANTENNA_SW_DIVERSITY:
 454         case ANTENNA_HW_DIVERSITY:
 455                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 456                 break;
 457         case ANTENNA_A:
 458                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 459                 break;
 460         case ANTENNA_B:
 461                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 462                 break;
 463         }
 464
 465         /*
 466          * Configure the RX antenna.
 467          */
 468         switch (antenna_rx) {
 469         case ANTENNA_SW_DIVERSITY:
 470         case ANTENNA_HW_DIVERSITY:
 471                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 472                 break;
 473         case ANTENNA_A:
 474                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 475                 break;
 476         case ANTENNA_B:
 477                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 478                 break;
 479         }
 480
 481         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 482         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 483 }
 484
 485 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 486                                       int short_slot_time, int beacon_int)
 487 {
 488         u32 reg;
 489
 490         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 491         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
 492                            short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
 493         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 494
 495         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 496         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
 497         rt2x00_set_field32(&reg, CSR18_PIFS,
 498                            short_slot_time ? SHORT_PIFS : PIFS);
 499         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 500
 501         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 502         rt2x00_set_field32(&reg, CSR19_DIFS,
 503                            short_slot_time ? SHORT_DIFS : DIFS);
 504         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
 505         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 506
 507         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 508         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 509         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 510         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 511
 512         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 513         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
 514         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
 515         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 516 }
 517
 518 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 519                              const unsigned int flags,
 520                              struct ieee80211_conf *conf)
 521 {
 522         int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
 523
 524         if (flags & CONFIG_UPDATE_PHYMODE)
 525                 rt2400pci_config_phymode(rt2x00dev, conf->phymode);
 526         if (flags & CONFIG_UPDATE_CHANNEL)
 527                 rt2400pci_config_channel(rt2x00dev, conf->channel_val,
 528                                          conf->channel);
 529         if (flags & CONFIG_UPDATE_TXPOWER)
 530                 rt2400pci_config_txpower(rt2x00dev, conf->power_level);
 531         if (flags & CONFIG_UPDATE_ANTENNA)
 532                 rt2400pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
 533                                          conf->antenna_sel_rx);
 534         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 535                 rt2400pci_config_duration(rt2x00dev, short_slot_time,
 536                                           conf->beacon_int);
 537 }
 538
 539 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 540                                 struct ieee80211_tx_queue_params *params)
 541 {
 542         u32 reg;
 543
 544         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 545         rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
 546         rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
 547         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 548 }
 549
 550 /*
 551  * LED functions.
 552  */
 553 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
 554 {
 555         u32 reg;
 556
 557         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 558
 559         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 560         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 561
 562         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 563                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 564                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 565         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 566                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 567                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 568         } else {
 569                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 570                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 571         }
 572
 573         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 574 }
 575
 576 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
 577 {
 578         u32 reg;
 579
 580         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 581         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 582         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 583         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 584 }
 585
 586 /*
 587  * Link tuning
 588  */
 589 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
 590 {
 591         u32 reg;
 592         u8 bbp;
 593
 594         /*
 595          * Update FCS error count from register.
 596          */
 597         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 598         rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 599
 600         /*
 601          * Update False CCA count from register.
 602          */
 603         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 604         rt2x00dev->link.false_cca = bbp;
 605 }
 606
 607 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 608 {
 609         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 610         rt2x00dev->link.vgc_level = 0x08;
 611 }
 612
 613 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 614 {
 615         u8 reg;
 616
 617         /*
 618          * The link tuner should not run longer then 60 seconds,
 619          * and should run once every 2 seconds.
 620          */
 621         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 622                 return;
 623
 624         /*
 625          * Base r13 link tuning on the false cca count.
 626          */
 627         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 628
 629         if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
 630                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 631                 rt2x00dev->link.vgc_level = reg;
 632         } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
 633                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 634                 rt2x00dev->link.vgc_level = reg;
 635         }
 636 }
 637
 638 /*
 639  * Initialization functions.
 640  */
 641 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 642 {
 643         struct data_ring *ring = rt2x00dev->rx;
 644         struct data_desc *rxd;
 645         unsigned int i;
 646         u32 word;
 647
 648         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 649
 650         for (i = 0; i < ring->stats.limit; i++) {
 651                 rxd = ring->entry[i].priv;
 652
 653                 rt2x00_desc_read(rxd, 2, &word);
 654                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 655                                    ring->data_size);
 656                 rt2x00_desc_write(rxd, 2, word);
 657
 658                 rt2x00_desc_read(rxd, 1, &word);
 659                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 660                                    ring->entry[i].data_dma);
 661                 rt2x00_desc_write(rxd, 1, word);
 662
 663                 rt2x00_desc_read(rxd, 0, &word);
 664                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 665                 rt2x00_desc_write(rxd, 0, word);
 666         }
 667
 668         rt2x00_ring_index_clear(rt2x00dev->rx);
 669 }
 670
 671 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
 672 {
 673         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
 674         struct data_desc *txd;
 675         unsigned int i;
 676         u32 word;
 677
 678         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 679
 680         for (i = 0; i < ring->stats.limit; i++) {
 681                 txd = ring->entry[i].priv;
 682
 683                 rt2x00_desc_read(txd, 1, &word);
 684                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 685                                    ring->entry[i].data_dma);
 686                 rt2x00_desc_write(txd, 1, word);
 687
 688                 rt2x00_desc_read(txd, 2, &word);
 689                 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 690                                    ring->data_size);
 691                 rt2x00_desc_write(txd, 2, word);
 692
 693                 rt2x00_desc_read(txd, 0, &word);
 694                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 695                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 696                 rt2x00_desc_write(txd, 0, word);
 697         }
 698
 699         rt2x00_ring_index_clear(ring);
 700 }
 701
 702 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
 703 {
 704         u32 reg;
 705
 706         /*
 707          * Initialize rings.
 708          */
 709         rt2400pci_init_rxring(rt2x00dev);
 710         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 711         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 712         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 713         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 714
 715         /*
 716          * Initialize registers.
 717          */
 718         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 719         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 720                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 721         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 722                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 723         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 724                            rt2x00dev->bcn[1].stats.limit);
 725         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 726                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 727         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 728
 729         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 730         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 731                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 732         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 733
 734         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 735         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 736                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 737         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 738
 739         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 740         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 741                            rt2x00dev->bcn[1].data_dma);
 742         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 743
 744         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 745         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 746                            rt2x00dev->bcn[0].data_dma);
 747         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 748
 749         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 750         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 751         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 752         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 753
 754         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 755         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 756                            rt2x00dev->rx->data_dma);
 757         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 758
 759         return 0;
 760 }
 761
 762 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 763 {
 764         u32 reg;
 765
 766         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 767         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 768         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 769         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 770
 771         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 772         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 773         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 774         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 775         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 776
 777         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 778         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 779                            (rt2x00dev->rx->data_size / 128));
 780         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 781
 782         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 783
 784         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 785         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 786         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 787         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 788         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 789         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 790
 791         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 792         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 793         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 794         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 795         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 796         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 797         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 798         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 799
 800         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 801
 802         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 803                 return -EBUSY;
 804
 805         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 806         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 807
 808         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 809         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 810         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 811
 812         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 813         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 814         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 815         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 816         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 817         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 818
 819         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 820         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 821         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 822         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 823         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 824
 825         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 826         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 827         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 828         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 829
 830         /*
 831          * We must clear the FCS and FIFO error count.
 832          * These registers are cleared on read,
 833          * so we may pass a useless variable to store the value.
 834          */
 835         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 836         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 837
 838         return 0;
 839 }
 840
 841 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 842 {
 843         unsigned int i;
 844         u16 eeprom;
 845         u8 reg_id;
 846         u8 value;
 847
 848         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 849                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 850                 if ((value != 0xff) && (value != 0x00))
 851                         goto continue_csr_init;
 852                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 853                 udelay(REGISTER_BUSY_DELAY);
 854         }
 855
 856         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 857         return -EACCES;
 858
 859 continue_csr_init:
 860         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 861         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 862         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 863         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 864         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 865         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 866         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 867         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 868         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 869         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 870         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 871         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 872         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 873         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 874
 875         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 876         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 877                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 878
 879                 if (eeprom != 0xffff && eeprom != 0x0000) {
 880                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 881                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 882                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 883                               reg_id, value);
 884                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 885                 }
 886         }
 887         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 888
 889         return 0;
 890 }
 891
 892 /*
 893  * Device state switch handlers.
 894  */
 895 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 896                                 enum dev_state state)
 897 {
 898         u32 reg;
 899
 900         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 901         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 902                            state == STATE_RADIO_RX_OFF);
 903         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 904 }
 905
 906 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 907                                  enum dev_state state)
 908 {
 909         int mask = (state == STATE_RADIO_IRQ_OFF);
 910         u32 reg;
 911
 912         /*
 913          * When interrupts are being enabled, the interrupt registers
 914          * should clear the register to assure a clean state.
 915          */
 916         if (state == STATE_RADIO_IRQ_ON) {
 917                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 918                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 919         }
 920
 921         /*
 922          * Only toggle the interrupts bits we are going to use.
 923          * Non-checked interrupt bits are disabled by default.
 924          */
 925         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 926         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 927         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 928         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 929         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 930         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 931         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 932 }
 933
 934 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 935 {
 936         /*
 937          * Initialize all registers.
 938          */
 939         if (rt2400pci_init_rings(rt2x00dev) ||
 940             rt2400pci_init_registers(rt2x00dev) ||
 941             rt2400pci_init_bbp(rt2x00dev)) {
 942                 ERROR(rt2x00dev, "Register initialization failed.\n");
 943                 return -EIO;
 944         }
 945
 946         /*
 947          * Enable interrupts.
 948          */
 949         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 950
 951         /*
 952          * Enable LED
 953          */
 954         rt2400pci_enable_led(rt2x00dev);
 955
 956         return 0;
 957 }
 958
 959 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 960 {
 961         u32 reg;
 962
 963         /*
 964          * Disable LED
 965          */
 966         rt2400pci_disable_led(rt2x00dev);
 967
 968         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 969
 970         /*
 971          * Disable synchronisation.
 972          */
 973         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 974
 975         /*
 976          * Cancel RX and TX.
 977          */
 978         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 979         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 980         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 981
 982         /*
 983          * Disable interrupts.
 984          */
 985         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 986 }
 987
 988 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 989                                enum dev_state state)
 990 {
 991         u32 reg;
 992         unsigned int i;
 993         char put_to_sleep;
 994         char bbp_state;
 995         char rf_state;
 996
 997         put_to_sleep = (state != STATE_AWAKE);
 998
 999         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1000         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1001         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1002         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1003         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1004         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1005
1006         /*
1007          * Device is not guaranteed to be in the requested state yet.
1008          * We must wait until the register indicates that the
1009          * device has entered the correct state.
1010          */
1011         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1012                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1013                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1014                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1015                 if (bbp_state == state && rf_state == state)
1016                         return 0;
1017                 msleep(10);
1018         }
1019
1020         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1021                "current device state: bbp %d and rf %d.\n",
1022                state, bbp_state, rf_state);
1023
1024         return -EBUSY;
1025 }
1026
1027 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1028                                       enum dev_state state)
1029 {
1030         int retval = 0;
1031
1032         switch (state) {
1033         case STATE_RADIO_ON:
1034                 retval = rt2400pci_enable_radio(rt2x00dev);
1035                 break;
1036         case STATE_RADIO_OFF:
1037                 rt2400pci_disable_radio(rt2x00dev);
1038                 break;
1039         case STATE_RADIO_RX_ON:
1040         case STATE_RADIO_RX_OFF:
1041                 rt2400pci_toggle_rx(rt2x00dev, state);
1042                 break;
1043         case STATE_DEEP_SLEEP:
1044         case STATE_SLEEP:
1045         case STATE_STANDBY:
1046         case STATE_AWAKE:
1047                 retval = rt2400pci_set_state(rt2x00dev, state);
1048                 break;
1049         default:
1050                 retval = -ENOTSUPP;
1051                 break;
1052         }
1053
1054         return retval;
1055 }
1056
1057 /*
1058  * TX descriptor initialization
1059  */
1060 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1061                                     struct data_desc *txd,
1062                                     struct txdata_entry_desc *desc,
1063                                     struct ieee80211_hdr *ieee80211hdr,
1064                                     unsigned int length,
1065                                     struct ieee80211_tx_control *control)
1066 {
1067         u32 word;
1068         u32 signal = 0;
1069         u32 service = 0;
1070         u32 length_high = 0;
1071         u32 length_low = 0;
1072
1073         /*
1074          * The PLCP values should be treated as if they
1075          * were BBP values.
1076          */
1077         rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1078         rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1079         rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1080
1081         rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1082         rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1083         rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1084
1085         rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1086         rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1087         rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1088
1089         rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1090         rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1091         rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1092
1093         /*
1094          * Start writing the descriptor words.
1095          */
1096         rt2x00_desc_read(txd, 2, &word);
1097         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1098         rt2x00_desc_write(txd, 2, word);
1099
1100         rt2x00_desc_read(txd, 3, &word);
1101         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1102         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1103         rt2x00_desc_write(txd, 3, word);
1104
1105         rt2x00_desc_read(txd, 4, &word);
1106         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1107         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1108         rt2x00_desc_write(txd, 4, word);
1109
1110         rt2x00_desc_read(txd, 0, &word);
1111         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1112         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1113         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1114                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1115         rt2x00_set_field32(&word, TXD_W0_ACK,
1116                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1117         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1118                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1119         rt2x00_set_field32(&word, TXD_W0_RTS,
1120                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1121         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1122         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1123                            !!(control->flags &
1124                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1125         rt2x00_desc_write(txd, 0, word);
1126 }
1127
1128 /*
1129  * TX data initialization
1130  */
1131 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1132                                     unsigned int queue)
1133 {
1134         u32 reg;
1135
1136         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1137                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1138                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1139                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1140                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1141                 }
1142                 return;
1143         }
1144
1145         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1146         if (queue == IEEE80211_TX_QUEUE_DATA0)
1147                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1148         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1149                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1150         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1151                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1152         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1153 }
1154
1155 /*
1156  * RX control handlers
1157  */
1158 static void rt2400pci_fill_rxdone(struct data_entry *entry,
1159                                   struct rxdata_entry_desc *desc)
1160 {
1161         struct data_desc *rxd = entry->priv;
1162         u32 word0;
1163         u32 word2;
1164
1165         rt2x00_desc_read(rxd, 0, &word0);
1166         rt2x00_desc_read(rxd, 2, &word2);
1167
1168         desc->flags = 0;
1169         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1170                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1171         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1172                 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1173
1174         /*
1175          * Obtain the status about this packet.
1176          */
1177         desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1178         desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1179             entry->ring->rt2x00dev->rssi_offset;
1180         desc->ofdm = 0;
1181         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1182 }
1183
1184 /*
1185  * Interrupt functions.
1186  */
1187 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1188 {
1189         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1190         struct data_entry *entry;
1191         struct data_desc *txd;
1192         u32 word;
1193         int tx_status;
1194         int retry;
1195
1196         while (!rt2x00_ring_empty(ring)) {
1197                 entry = rt2x00_get_data_entry_done(ring);
1198                 txd = entry->priv;
1199                 rt2x00_desc_read(txd, 0, &word);
1200
1201                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1202                     !rt2x00_get_field32(word, TXD_W0_VALID))
1203                         break;
1204
1205                 /*
1206                  * Obtain the status about this packet.
1207                  */
1208                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1209                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1210
1211                 rt2x00lib_txdone(entry, tx_status, retry);
1212
1213                 /*
1214                  * Make this entry available for reuse.
1215                  */
1216                 entry->flags = 0;
1217                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1218                 rt2x00_desc_write(txd, 0, word);
1219                 rt2x00_ring_index_done_inc(ring);
1220         }
1221
1222         /*
1223          * If the data ring was full before the txdone handler
1224          * we must make sure the packet queue in the mac80211 stack
1225          * is reenabled when the txdone handler has finished.
1226          */
1227         entry = ring->entry;
1228         if (!rt2x00_ring_full(ring))
1229                 ieee80211_wake_queue(rt2x00dev->hw,
1230                                      entry->tx_status.control.queue);
1231 }
1232
1233 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1234 {
1235         struct rt2x00_dev *rt2x00dev = dev_instance;
1236         u32 reg;
1237
1238         /*
1239          * Get the interrupt sources & saved to local variable.
1240          * Write register value back to clear pending interrupts.
1241          */
1242         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1243         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1244
1245         if (!reg)
1246                 return IRQ_NONE;
1247
1248         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1249                 return IRQ_HANDLED;
1250
1251         /*
1252          * Handle interrupts, walk through all bits
1253          * and run the tasks, the bits are checked in order of
1254          * priority.
1255          */
1256
1257         /*
1258          * 1 - Beacon timer expired interrupt.
1259          */
1260         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1261                 rt2x00lib_beacondone(rt2x00dev);
1262
1263         /*
1264          * 2 - Rx ring done interrupt.
1265          */
1266         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1267                 rt2x00pci_rxdone(rt2x00dev);
1268
1269         /*
1270          * 3 - Atim ring transmit done interrupt.
1271          */
1272         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1273                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1274
1275         /*
1276          * 4 - Priority ring transmit done interrupt.
1277          */
1278         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1279                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1280
1281         /*
1282          * 5 - Tx ring transmit done interrupt.
1283          */
1284         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1285                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1286
1287         return IRQ_HANDLED;
1288 }
1289
1290 /*
1291  * Device probe functions.
1292  */
1293 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1294 {
1295         struct eeprom_93cx6 eeprom;
1296         u32 reg;
1297         u16 word;
1298         u8 *mac;
1299
1300         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1301
1302         eeprom.data = rt2x00dev;
1303         eeprom.register_read = rt2400pci_eepromregister_read;
1304         eeprom.register_write = rt2400pci_eepromregister_write;
1305         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1306             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1307         eeprom.reg_data_in = 0;
1308         eeprom.reg_data_out = 0;
1309         eeprom.reg_data_clock = 0;
1310         eeprom.reg_chip_select = 0;
1311
1312         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1313                                EEPROM_SIZE / sizeof(u16));
1314
1315         /*
1316          * Start validation of the data that has been read.
1317          */
1318         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1319         if (!is_valid_ether_addr(mac)) {
1320                 DECLARE_MAC_BUF(macbuf);
1321
1322                 random_ether_addr(mac);
1323                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1324         }
1325
1326         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1327         if (word == 0xffff) {
1328                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1329                 return -EINVAL;
1330         }
1331
1332         return 0;
1333 }
1334
1335 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1336 {
1337         u32 reg;
1338         u16 value;
1339         u16 eeprom;
1340
1341         /*
1342          * Read EEPROM word for configuration.
1343          */
1344         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1345
1346         /*
1347          * Identify RF chipset.
1348          */
1349         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1350         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1351         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1352
1353         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1354             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1355                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1356                 return -ENODEV;
1357         }
1358
1359         /*
1360          * Identify default antenna configuration.
1361          */
1362         rt2x00dev->hw->conf.antenna_sel_tx =
1363             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1364         rt2x00dev->hw->conf.antenna_sel_rx =
1365             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1366
1367         /*
1368          * Store led mode, for correct led behaviour.
1369          */
1370         rt2x00dev->led_mode =
1371             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1372
1373         /*
1374          * Detect if this device has an hardware controlled radio.
1375          */
1376         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1377                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1378
1379         /*
1380          * Check if the BBP tuning should be enabled.
1381          */
1382         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1383                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1384
1385         return 0;
1386 }
1387
1388 /*
1389  * RF value list for RF2420 & RF2421
1390  * Supports: 2.4 GHz
1391  */
1392 static const struct rf_channel rf_vals_bg[] = {
1393         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1394         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1395         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1396         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1397         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1398         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1399         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1400         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1401         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1402         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1403         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1404         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1405         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1406         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1407 };
1408
1409 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1410 {
1411         struct hw_mode_spec *spec = &rt2x00dev->spec;
1412         u8 *txpower;
1413         unsigned int i;
1414
1415         /*
1416          * Initialize all hw fields.
1417          */
1418         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1419         rt2x00dev->hw->extra_tx_headroom = 0;
1420         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1421         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1422         rt2x00dev->hw->queues = 2;
1423
1424         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1425         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1426                                 rt2x00_eeprom_addr(rt2x00dev,
1427                                                    EEPROM_MAC_ADDR_0));
1428
1429         /*
1430          * Convert tx_power array in eeprom.
1431          */
1432         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1433         for (i = 0; i < 14; i++)
1434                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1435
1436         /*
1437          * Initialize hw_mode information.
1438          */
1439         spec->num_modes = 1;
1440         spec->num_rates = 4;
1441         spec->tx_power_a = NULL;
1442         spec->tx_power_bg = txpower;
1443         spec->tx_power_default = DEFAULT_TXPOWER;
1444
1445         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1446         spec->channels = rf_vals_bg;
1447 }
1448
1449 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1450 {
1451         int retval;
1452
1453         /*
1454          * Allocate eeprom data.
1455          */
1456         retval = rt2400pci_validate_eeprom(rt2x00dev);
1457         if (retval)
1458                 return retval;
1459
1460         retval = rt2400pci_init_eeprom(rt2x00dev);
1461         if (retval)
1462                 return retval;
1463
1464         /*
1465          * Initialize hw specifications.
1466          */
1467         rt2400pci_probe_hw_mode(rt2x00dev);
1468
1469         /*
1470          * This device requires the beacon ring
1471          */
1472         __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1473
1474         /*
1475          * Set the rssi offset.
1476          */
1477         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1478
1479         return 0;
1480 }
1481
1482 /*
1483  * IEEE80211 stack callback functions.
1484  */
1485 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1486                                        unsigned int changed_flags,
1487                                        unsigned int *total_flags,
1488                                        int mc_count,
1489                                        struct dev_addr_list *mc_list)
1490 {
1491         struct rt2x00_dev *rt2x00dev = hw->priv;
1492         struct interface *intf = &rt2x00dev->interface;
1493         u32 reg;
1494
1495         /*
1496          * Mask off any flags we are going to ignore from
1497          * the total_flags field.
1498          */
1499         *total_flags &=
1500             FIF_ALLMULTI |
1501             FIF_FCSFAIL |
1502             FIF_PLCPFAIL |
1503             FIF_CONTROL |
1504             FIF_OTHER_BSS |
1505             FIF_PROMISC_IN_BSS;
1506
1507         /*
1508          * Apply some rules to the filters:
1509          * - Some filters imply different filters to be set.
1510          * - Some things we can't filter out at all.
1511          * - Some filters are set based on interface type.
1512          */
1513         *total_flags |= FIF_ALLMULTI;
1514         if (changed_flags & FIF_OTHER_BSS ||
1515             changed_flags & FIF_PROMISC_IN_BSS)
1516                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1517         if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1518                 *total_flags |= FIF_PROMISC_IN_BSS;
1519
1520         /*
1521          * Check if there is any work left for us.
1522          */
1523         if (intf->filter == *total_flags)
1524                 return;
1525         intf->filter = *total_flags;
1526
1527         /*
1528          * Start configuration steps.
1529          * Note that the version error will always be dropped
1530          * since there is no filter for it at this time.
1531          */
1532         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1533         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1534                            !(*total_flags & FIF_FCSFAIL));
1535         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1536                            !(*total_flags & FIF_PLCPFAIL));
1537         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1538                            !(*total_flags & FIF_CONTROL));
1539         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1540                            !(*total_flags & FIF_PROMISC_IN_BSS));
1541         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1542                            !(*total_flags & FIF_PROMISC_IN_BSS));
1543         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1544         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1545 }
1546
1547 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1548                                      u32 short_retry, u32 long_retry)
1549 {
1550         struct rt2x00_dev *rt2x00dev = hw->priv;
1551         u32 reg;
1552
1553         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1554         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1555         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1556         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1557
1558         return 0;
1559 }
1560
1561 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1562                              int queue,
1563                              const struct ieee80211_tx_queue_params *params)
1564 {
1565         struct rt2x00_dev *rt2x00dev = hw->priv;
1566
1567         /*
1568          * We don't support variating cw_min and cw_max variables
1569          * per queue. So by default we only configure the TX queue,
1570          * and ignore all other configurations.
1571          */
1572         if (queue != IEEE80211_TX_QUEUE_DATA0)
1573                 return -EINVAL;
1574
1575         if (rt2x00mac_conf_tx(hw, queue, params))
1576                 return -EINVAL;
1577
1578         /*
1579          * Write configuration to register.
1580          */
1581         rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1582
1583         return 0;
1584 }
1585
1586 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1587 {
1588         struct rt2x00_dev *rt2x00dev = hw->priv;
1589         u64 tsf;
1590         u32 reg;
1591
1592         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1593         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1594         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1595         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1596
1597         return tsf;
1598 }
1599
1600 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1601 {
1602         struct rt2x00_dev *rt2x00dev = hw->priv;
1603
1604         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1605         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1606 }
1607
1608 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1609 {
1610         struct rt2x00_dev *rt2x00dev = hw->priv;
1611         u32 reg;
1612
1613         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1614         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1615 }
1616
1617 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1618         .tx                     = rt2x00mac_tx,
1619         .start                  = rt2x00mac_start,
1620         .stop                   = rt2x00mac_stop,
1621         .add_interface          = rt2x00mac_add_interface,
1622         .remove_interface       = rt2x00mac_remove_interface,
1623         .config                 = rt2x00mac_config,
1624         .config_interface       = rt2x00mac_config_interface,
1625         .configure_filter       = rt2400pci_configure_filter,
1626         .get_stats              = rt2x00mac_get_stats,
1627         .set_retry_limit        = rt2400pci_set_retry_limit,
1628         .conf_tx                = rt2400pci_conf_tx,
1629         .get_tx_stats           = rt2x00mac_get_tx_stats,
1630         .get_tsf                = rt2400pci_get_tsf,
1631         .reset_tsf              = rt2400pci_reset_tsf,
1632         .beacon_update          = rt2x00pci_beacon_update,
1633         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1634 };
1635
1636 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1637         .irq_handler            = rt2400pci_interrupt,
1638         .probe_hw               = rt2400pci_probe_hw,
1639         .initialize             = rt2x00pci_initialize,
1640         .uninitialize           = rt2x00pci_uninitialize,
1641         .set_device_state       = rt2400pci_set_device_state,
1642 #ifdef CONFIG_RT2400PCI_RFKILL
1643         .rfkill_poll            = rt2400pci_rfkill_poll,
1644 #endif /* CONFIG_RT2400PCI_RFKILL */
1645         .link_stats             = rt2400pci_link_stats,
1646         .reset_tuner            = rt2400pci_reset_tuner,
1647         .link_tuner             = rt2400pci_link_tuner,
1648         .write_tx_desc          = rt2400pci_write_tx_desc,
1649         .write_tx_data          = rt2x00pci_write_tx_data,
1650         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1651         .fill_rxdone            = rt2400pci_fill_rxdone,
1652         .config_mac_addr        = rt2400pci_config_mac_addr,
1653         .config_bssid           = rt2400pci_config_bssid,
1654         .config_type            = rt2400pci_config_type,
1655         .config                 = rt2400pci_config,
1656 };
1657
1658 static const struct rt2x00_ops rt2400pci_ops = {
1659         .name           = DRV_NAME,
1660         .rxd_size       = RXD_DESC_SIZE,
1661         .txd_size       = TXD_DESC_SIZE,
1662         .eeprom_size    = EEPROM_SIZE,
1663         .rf_size        = RF_SIZE,
1664         .lib            = &rt2400pci_rt2x00_ops,
1665         .hw             = &rt2400pci_mac80211_ops,
1666 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1667         .debugfs        = &rt2400pci_rt2x00debug,
1668 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1669 };
1670
1671 /*
1672  * RT2400pci module information.
1673  */
1674 static struct pci_device_id rt2400pci_device_table[] = {
1675         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1676         { 0, }
1677 };
1678
1679 MODULE_AUTHOR(DRV_PROJECT);
1680 MODULE_VERSION(DRV_VERSION);
1681 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1682 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1683 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1684 MODULE_LICENSE("GPL");
1685
1686 static struct pci_driver rt2400pci_driver = {
1687         .name           = DRV_NAME,
1688         .id_table       = rt2400pci_device_table,
1689         .probe          = rt2x00pci_probe,
1690         .remove         = __devexit_p(rt2x00pci_remove),
1691         .suspend        = rt2x00pci_suspend,
1692         .resume         = rt2x00pci_resume,
1693 };
1694
1695 static int __init rt2400pci_init(void)
1696 {
1697         return pci_register_driver(&rt2400pci_driver);
1698 }
1699
1700 static void __exit rt2400pci_exit(void)
1701 {
1702         pci_unregister_driver(&rt2400pci_driver);
1703 }
1704
1705 module_init(rt2400pci_init);
1706 module_exit(rt2400pci_exit);