err.no Git - linux-2.6/blob - drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2400pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2400pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2400pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2400pci_read_csr,
 209                 .write          = rt2400pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2400pci_bbp_read,
 221                 .write          = rt2400pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2400pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2400PCI_RFKILL
 235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2400pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2400PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2400PCI_LEDS
 247 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         u32 reg;
 254
 255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 256
 257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 259         else if (led->type == LED_TYPE_ACTIVITY)
 260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 261
 262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 263 }
 264
 265 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 266                                unsigned long *delay_on,
 267                                unsigned long *delay_off)
 268 {
 269         struct rt2x00_led *led =
 270             container_of(led_cdev, struct rt2x00_led, led_dev);
 271         u32 reg;
 272
 273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 277
 278         return 0;
 279 }
 280 #endif /* CONFIG_RT2400PCI_LEDS */
 281
 282 /*
 283  * Configuration handlers.
 284  */
 285 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 286                                     const unsigned int filter_flags)
 287 {
 288         u32 reg;
 289
 290         /*
 291          * Start configuration steps.
 292          * Note that the version error will always be dropped
 293          * since there is no filter for it at this time.
 294          */
 295         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 296         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 297                            !(filter_flags & FIF_FCSFAIL));
 298         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 299                            !(filter_flags & FIF_PLCPFAIL));
 300         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 301                            !(filter_flags & FIF_CONTROL));
 302         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 303                            !(filter_flags & FIF_PROMISC_IN_BSS));
 304         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 305                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 306                            !rt2x00dev->intf_ap_count);
 307         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 308         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 309 }
 310
 311 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 312                                   struct rt2x00_intf *intf,
 313                                   struct rt2x00intf_conf *conf,
 314                                   const unsigned int flags)
 315 {
 316         unsigned int bcn_preload;
 317         u32 reg;
 318
 319         if (flags & CONFIG_UPDATE_TYPE) {
 320                 /*
 321                  * Enable beacon config
 322                  */
 323                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 324                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 325                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 326                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 327
 328                 /*
 329                  * Enable synchronisation.
 330                  */
 331                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 332                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 333                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 334                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 335                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 336         }
 337
 338         if (flags & CONFIG_UPDATE_MAC)
 339                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 340                                               conf->mac, sizeof(conf->mac));
 341
 342         if (flags & CONFIG_UPDATE_BSSID)
 343                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 344                                               conf->bssid, sizeof(conf->bssid));
 345 }
 346
 347 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 348                                  struct rt2x00lib_erp *erp)
 349 {
 350         int preamble_mask;
 351         u32 reg;
 352
 353         /*
 354          * When short preamble is enabled, we should set bit 0x08
 355          */
 356         preamble_mask = erp->short_preamble << 3;
 357
 358         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 359         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 360                            erp->ack_timeout);
 361         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 362                            erp->ack_consume_time);
 363         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 364
 365         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 366         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 367         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 368         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 369         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 370
 371         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 372         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 373         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 374         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 375         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 376
 377         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 378         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 379         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 380         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 381         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 382
 383         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 384         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 385         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 386         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 387         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 388 }
 389
 390 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 391                                      const int basic_rate_mask)
 392 {
 393         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 394 }
 395
 396 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 397                                      struct rf_channel *rf)
 398 {
 399         /*
 400          * Switch on tuning bits.
 401          */
 402         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 403         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 404
 405         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 406         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 407         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 408
 409         /*
 410          * RF2420 chipset don't need any additional actions.
 411          */
 412         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 413                 return;
 414
 415         /*
 416          * For the RT2421 chipsets we need to write an invalid
 417          * reference clock rate to activate auto_tune.
 418          * After that we set the value back to the correct channel.
 419          */
 420         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 421         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 422         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 423
 424         msleep(1);
 425
 426         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 427         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 428         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 429
 430         msleep(1);
 431
 432         /*
 433          * Switch off tuning bits.
 434          */
 435         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 436         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 437
 438         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 439         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 440
 441         /*
 442          * Clear false CRC during channel switch.
 443          */
 444         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 445 }
 446
 447 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 448 {
 449         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 450 }
 451
 452 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 453                                      struct antenna_setup *ant)
 454 {
 455         u8 r1;
 456         u8 r4;
 457
 458         /*
 459          * We should never come here because rt2x00lib is supposed
 460          * to catch this and send us the correct antenna explicitely.
 461          */
 462         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 463                ant->tx == ANTENNA_SW_DIVERSITY);
 464
 465         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 466         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 467
 468         /*
 469          * Configure the TX antenna.
 470          */
 471         switch (ant->tx) {
 472         case ANTENNA_HW_DIVERSITY:
 473                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 474                 break;
 475         case ANTENNA_A:
 476                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 477                 break;
 478         case ANTENNA_B:
 479         default:
 480                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 481                 break;
 482         }
 483
 484         /*
 485          * Configure the RX antenna.
 486          */
 487         switch (ant->rx) {
 488         case ANTENNA_HW_DIVERSITY:
 489                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 490                 break;
 491         case ANTENNA_A:
 492                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 493                 break;
 494         case ANTENNA_B:
 495         default:
 496                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 497                 break;
 498         }
 499
 500         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 501         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 502 }
 503
 504 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 505                                       struct rt2x00lib_conf *libconf)
 506 {
 507         u32 reg;
 508
 509         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 510         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 511         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 512
 513         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 514         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 515         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 516         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 517
 518         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 519         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 520         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 521         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 522
 523         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 524         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 525         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 526         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 527
 528         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 529         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 530                            libconf->conf->beacon_int * 16);
 531         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 532                            libconf->conf->beacon_int * 16);
 533         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 534 }
 535
 536 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 537                              struct rt2x00lib_conf *libconf,
 538                              const unsigned int flags)
 539 {
 540         if (flags & CONFIG_UPDATE_PHYMODE)
 541                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
 542         if (flags & CONFIG_UPDATE_CHANNEL)
 543                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 544         if (flags & CONFIG_UPDATE_TXPOWER)
 545                 rt2400pci_config_txpower(rt2x00dev,
 546                                          libconf->conf->power_level);
 547         if (flags & CONFIG_UPDATE_ANTENNA)
 548                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
 549         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 550                 rt2400pci_config_duration(rt2x00dev, libconf);
 551 }
 552
 553 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 554                                 const int cw_min, const int cw_max)
 555 {
 556         u32 reg;
 557
 558         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 559         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 560         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 561         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 562 }
 563
 564 /*
 565  * Link tuning
 566  */
 567 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 568                                  struct link_qual *qual)
 569 {
 570         u32 reg;
 571         u8 bbp;
 572
 573         /*
 574          * Update FCS error count from register.
 575          */
 576         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 577         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 578
 579         /*
 580          * Update False CCA count from register.
 581          */
 582         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 583         qual->false_cca = bbp;
 584 }
 585
 586 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 587 {
 588         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 589         rt2x00dev->link.vgc_level = 0x08;
 590 }
 591
 592 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 593 {
 594         u8 reg;
 595
 596         /*
 597          * The link tuner should not run longer then 60 seconds,
 598          * and should run once every 2 seconds.
 599          */
 600         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 601                 return;
 602
 603         /*
 604          * Base r13 link tuning on the false cca count.
 605          */
 606         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 607
 608         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 609                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 610                 rt2x00dev->link.vgc_level = reg;
 611         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 612                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 613                 rt2x00dev->link.vgc_level = reg;
 614         }
 615 }
 616
 617 /*
 618  * Initialization functions.
 619  */
 620 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 621                                    struct queue_entry *entry)
 622 {
 623         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
 624         u32 word;
 625
 626         rt2x00_desc_read(priv_rx->desc, 2, &word);
 627         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 628                            entry->queue->data_size);
 629         rt2x00_desc_write(priv_rx->desc, 2, word);
 630
 631         rt2x00_desc_read(priv_rx->desc, 1, &word);
 632         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, priv_rx->data_dma);
 633         rt2x00_desc_write(priv_rx->desc, 1, word);
 634
 635         rt2x00_desc_read(priv_rx->desc, 0, &word);
 636         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 637         rt2x00_desc_write(priv_rx->desc, 0, word);
 638 }
 639
 640 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 641                                    struct queue_entry *entry)
 642 {
 643         struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
 644         u32 word;
 645
 646         rt2x00_desc_read(priv_tx->desc, 1, &word);
 647         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, priv_tx->data_dma);
 648         rt2x00_desc_write(priv_tx->desc, 1, word);
 649
 650         rt2x00_desc_read(priv_tx->desc, 2, &word);
 651         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 652                            entry->queue->data_size);
 653         rt2x00_desc_write(priv_tx->desc, 2, word);
 654
 655         rt2x00_desc_read(priv_tx->desc, 0, &word);
 656         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 657         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 658         rt2x00_desc_write(priv_tx->desc, 0, word);
 659 }
 660
 661 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 662 {
 663         struct queue_entry_priv_pci_rx *priv_rx;
 664         struct queue_entry_priv_pci_tx *priv_tx;
 665         u32 reg;
 666
 667         /*
 668          * Initialize registers.
 669          */
 670         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 671         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 672         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 673         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 674         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 675         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 676
 677         priv_tx = rt2x00dev->tx[1].entries[0].priv_data;
 678         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 679         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 680                            priv_tx->desc_dma);
 681         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 682
 683         priv_tx = rt2x00dev->tx[0].entries[0].priv_data;
 684         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 685         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 686                            priv_tx->desc_dma);
 687         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 688
 689         priv_tx = rt2x00dev->bcn[1].entries[0].priv_data;
 690         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 691         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 692                            priv_tx->desc_dma);
 693         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 694
 695         priv_tx = rt2x00dev->bcn[0].entries[0].priv_data;
 696         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 697         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 698                            priv_tx->desc_dma);
 699         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 700
 701         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 702         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 703         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 704         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 705
 706         priv_rx = rt2x00dev->rx->entries[0].priv_data;
 707         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 708         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER, priv_rx->desc_dma);
 709         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 710
 711         return 0;
 712 }
 713
 714 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 715 {
 716         u32 reg;
 717
 718         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 719         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 720         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 721         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 722
 723         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 724         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 725         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 726         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 727         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 728
 729         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 730         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 731                            (rt2x00dev->rx->data_size / 128));
 732         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 733
 734         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 735
 736         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 737         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 738         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 739         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 740         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 741         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 742
 743         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 744         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 745         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 746         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 747         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 748         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 749         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 750         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 751
 752         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 753
 754         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 755                 return -EBUSY;
 756
 757         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 758         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 759
 760         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 761         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 762         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 763
 764         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 765         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 766         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 767         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 768         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 769         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 770
 771         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 772         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 773         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 774         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 775         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 776
 777         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 778         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 779         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 780         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 781
 782         /*
 783          * We must clear the FCS and FIFO error count.
 784          * These registers are cleared on read,
 785          * so we may pass a useless variable to store the value.
 786          */
 787         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 788         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 789
 790         return 0;
 791 }
 792
 793 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 794 {
 795         unsigned int i;
 796         u16 eeprom;
 797         u8 reg_id;
 798         u8 value;
 799
 800         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 801                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 802                 if ((value != 0xff) && (value != 0x00))
 803                         goto continue_csr_init;
 804                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 805                 udelay(REGISTER_BUSY_DELAY);
 806         }
 807
 808         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 809         return -EACCES;
 810
 811 continue_csr_init:
 812         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 813         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 814         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 815         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 816         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 817         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 818         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 819         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 820         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 821         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 822         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 823         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 824         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 825         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 826
 827         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 828                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 829
 830                 if (eeprom != 0xffff && eeprom != 0x0000) {
 831                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 832                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 833                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 834                 }
 835         }
 836
 837         return 0;
 838 }
 839
 840 /*
 841  * Device state switch handlers.
 842  */
 843 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 844                                 enum dev_state state)
 845 {
 846         u32 reg;
 847
 848         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 849         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 850                            state == STATE_RADIO_RX_OFF);
 851         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 852 }
 853
 854 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 855                                  enum dev_state state)
 856 {
 857         int mask = (state == STATE_RADIO_IRQ_OFF);
 858         u32 reg;
 859
 860         /*
 861          * When interrupts are being enabled, the interrupt registers
 862          * should clear the register to assure a clean state.
 863          */
 864         if (state == STATE_RADIO_IRQ_ON) {
 865                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 866                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 867         }
 868
 869         /*
 870          * Only toggle the interrupts bits we are going to use.
 871          * Non-checked interrupt bits are disabled by default.
 872          */
 873         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 874         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 875         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 876         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 877         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 878         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 879         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 880 }
 881
 882 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 883 {
 884         /*
 885          * Initialize all registers.
 886          */
 887         if (rt2400pci_init_queues(rt2x00dev) ||
 888             rt2400pci_init_registers(rt2x00dev) ||
 889             rt2400pci_init_bbp(rt2x00dev)) {
 890                 ERROR(rt2x00dev, "Register initialization failed.\n");
 891                 return -EIO;
 892         }
 893
 894         /*
 895          * Enable interrupts.
 896          */
 897         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 898
 899         return 0;
 900 }
 901
 902 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 903 {
 904         u32 reg;
 905
 906         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 907
 908         /*
 909          * Disable synchronisation.
 910          */
 911         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 912
 913         /*
 914          * Cancel RX and TX.
 915          */
 916         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 917         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 918         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 919
 920         /*
 921          * Disable interrupts.
 922          */
 923         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 924 }
 925
 926 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 927                                enum dev_state state)
 928 {
 929         u32 reg;
 930         unsigned int i;
 931         char put_to_sleep;
 932         char bbp_state;
 933         char rf_state;
 934
 935         put_to_sleep = (state != STATE_AWAKE);
 936
 937         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 938         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 939         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 940         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 941         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 942         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 943
 944         /*
 945          * Device is not guaranteed to be in the requested state yet.
 946          * We must wait until the register indicates that the
 947          * device has entered the correct state.
 948          */
 949         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 950                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 951                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 952                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 953                 if (bbp_state == state && rf_state == state)
 954                         return 0;
 955                 msleep(10);
 956         }
 957
 958         NOTICE(rt2x00dev, "Device failed to enter state %d, "
 959                "current device state: bbp %d and rf %d.\n",
 960                state, bbp_state, rf_state);
 961
 962         return -EBUSY;
 963 }
 964
 965 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 966                                       enum dev_state state)
 967 {
 968         int retval = 0;
 969
 970         switch (state) {
 971         case STATE_RADIO_ON:
 972                 retval = rt2400pci_enable_radio(rt2x00dev);
 973                 break;
 974         case STATE_RADIO_OFF:
 975                 rt2400pci_disable_radio(rt2x00dev);
 976                 break;
 977         case STATE_RADIO_RX_ON:
 978         case STATE_RADIO_RX_ON_LINK:
 979                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_ON);
 980                 break;
 981         case STATE_RADIO_RX_OFF:
 982         case STATE_RADIO_RX_OFF_LINK:
 983                 rt2400pci_toggle_rx(rt2x00dev, STATE_RADIO_RX_OFF);
 984                 break;
 985         case STATE_DEEP_SLEEP:
 986         case STATE_SLEEP:
 987         case STATE_STANDBY:
 988         case STATE_AWAKE:
 989                 retval = rt2400pci_set_state(rt2x00dev, state);
 990                 break;
 991         default:
 992                 retval = -ENOTSUPP;
 993                 break;
 994         }
 995
 996         return retval;
 997 }
 998
 999 /*
1000  * TX descriptor initialization
1001  */
1002 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1003                                     struct sk_buff *skb,
1004                                     struct txentry_desc *txdesc,
1005                                     struct ieee80211_tx_control *control)
1006 {
1007         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1008         __le32 *txd = skbdesc->desc;
1009         u32 word;
1010
1011         /*
1012          * Start writing the descriptor words.
1013          */
1014         rt2x00_desc_read(txd, 2, &word);
1015         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
1016         rt2x00_desc_write(txd, 2, word);
1017
1018         rt2x00_desc_read(txd, 3, &word);
1019         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1020         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1021         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1022         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1023         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1024         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1025         rt2x00_desc_write(txd, 3, word);
1026
1027         rt2x00_desc_read(txd, 4, &word);
1028         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1029         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1030         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1031         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1032         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1033         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1034         rt2x00_desc_write(txd, 4, word);
1035
1036         rt2x00_desc_read(txd, 0, &word);
1037         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1038         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1039         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1040                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1041         rt2x00_set_field32(&word, TXD_W0_ACK,
1042                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1043         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1044                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1045         rt2x00_set_field32(&word, TXD_W0_RTS,
1046                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1047         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1048         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1049                            !!(control->flags &
1050                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1051         rt2x00_desc_write(txd, 0, word);
1052 }
1053
1054 /*
1055  * TX data initialization
1056  */
1057 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1058                                     const enum data_queue_qid queue)
1059 {
1060         u32 reg;
1061
1062         if (queue == QID_BEACON) {
1063                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1064                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1065                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1066                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1067                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1068                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1069                 }
1070                 return;
1071         }
1072
1073         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1074         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1075         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1076         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1077         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1078 }
1079
1080 /*
1081  * RX control handlers
1082  */
1083 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1084                                   struct rxdone_entry_desc *rxdesc)
1085 {
1086         struct queue_entry_priv_pci_rx *priv_rx = entry->priv_data;
1087         u32 word0;
1088         u32 word2;
1089         u32 word3;
1090
1091         rt2x00_desc_read(priv_rx->desc, 0, &word0);
1092         rt2x00_desc_read(priv_rx->desc, 2, &word2);
1093         rt2x00_desc_read(priv_rx->desc, 3, &word3);
1094
1095         rxdesc->flags = 0;
1096         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1097                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1098         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1099                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1100
1101         /*
1102          * Obtain the status about this packet.
1103          * The signal is the PLCP value, and needs to be stripped
1104          * of the preamble bit (0x08).
1105          */
1106         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1107         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1108             entry->queue->rt2x00dev->rssi_offset;
1109         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1110
1111         rxdesc->dev_flags = RXDONE_SIGNAL_PLCP;
1112         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1113                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1114 }
1115
1116 /*
1117  * Interrupt functions.
1118  */
1119 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1120                              const enum data_queue_qid queue_idx)
1121 {
1122         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1123         struct queue_entry_priv_pci_tx *priv_tx;
1124         struct queue_entry *entry;
1125         struct txdone_entry_desc txdesc;
1126         u32 word;
1127
1128         while (!rt2x00queue_empty(queue)) {
1129                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1130                 priv_tx = entry->priv_data;
1131                 rt2x00_desc_read(priv_tx->desc, 0, &word);
1132
1133                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1134                     !rt2x00_get_field32(word, TXD_W0_VALID))
1135                         break;
1136
1137                 /*
1138                  * Obtain the status about this packet.
1139                  */
1140                 txdesc.status = rt2x00_get_field32(word, TXD_W0_RESULT);
1141                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1142
1143                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1144         }
1145 }
1146
1147 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1148 {
1149         struct rt2x00_dev *rt2x00dev = dev_instance;
1150         u32 reg;
1151
1152         /*
1153          * Get the interrupt sources & saved to local variable.
1154          * Write register value back to clear pending interrupts.
1155          */
1156         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1157         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1158
1159         if (!reg)
1160                 return IRQ_NONE;
1161
1162         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1163                 return IRQ_HANDLED;
1164
1165         /*
1166          * Handle interrupts, walk through all bits
1167          * and run the tasks, the bits are checked in order of
1168          * priority.
1169          */
1170
1171         /*
1172          * 1 - Beacon timer expired interrupt.
1173          */
1174         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1175                 rt2x00lib_beacondone(rt2x00dev);
1176
1177         /*
1178          * 2 - Rx ring done interrupt.
1179          */
1180         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1181                 rt2x00pci_rxdone(rt2x00dev);
1182
1183         /*
1184          * 3 - Atim ring transmit done interrupt.
1185          */
1186         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1187                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1188
1189         /*
1190          * 4 - Priority ring transmit done interrupt.
1191          */
1192         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1193                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1194
1195         /*
1196          * 5 - Tx ring transmit done interrupt.
1197          */
1198         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1199                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1200
1201         return IRQ_HANDLED;
1202 }
1203
1204 /*
1205  * Device probe functions.
1206  */
1207 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1208 {
1209         struct eeprom_93cx6 eeprom;
1210         u32 reg;
1211         u16 word;
1212         u8 *mac;
1213
1214         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1215
1216         eeprom.data = rt2x00dev;
1217         eeprom.register_read = rt2400pci_eepromregister_read;
1218         eeprom.register_write = rt2400pci_eepromregister_write;
1219         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1220             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1221         eeprom.reg_data_in = 0;
1222         eeprom.reg_data_out = 0;
1223         eeprom.reg_data_clock = 0;
1224         eeprom.reg_chip_select = 0;
1225
1226         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1227                                EEPROM_SIZE / sizeof(u16));
1228
1229         /*
1230          * Start validation of the data that has been read.
1231          */
1232         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1233         if (!is_valid_ether_addr(mac)) {
1234                 DECLARE_MAC_BUF(macbuf);
1235
1236                 random_ether_addr(mac);
1237                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1238         }
1239
1240         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1241         if (word == 0xffff) {
1242                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1243                 return -EINVAL;
1244         }
1245
1246         return 0;
1247 }
1248
1249 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1250 {
1251         u32 reg;
1252         u16 value;
1253         u16 eeprom;
1254
1255         /*
1256          * Read EEPROM word for configuration.
1257          */
1258         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1259
1260         /*
1261          * Identify RF chipset.
1262          */
1263         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1264         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1265         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1266
1267         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1268             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1269                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1270                 return -ENODEV;
1271         }
1272
1273         /*
1274          * Identify default antenna configuration.
1275          */
1276         rt2x00dev->default_ant.tx =
1277             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1278         rt2x00dev->default_ant.rx =
1279             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1280
1281         /*
1282          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1283          * I am not 100% sure about this, but the legacy drivers do not
1284          * indicate antenna swapping in software is required when
1285          * diversity is enabled.
1286          */
1287         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1288                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1289         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1290                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1291
1292         /*
1293          * Store led mode, for correct led behaviour.
1294          */
1295 #ifdef CONFIG_RT2400PCI_LEDS
1296         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1297
1298         rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1299         rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1300         rt2x00dev->led_radio.led_dev.brightness_set =
1301             rt2400pci_brightness_set;
1302         rt2x00dev->led_radio.led_dev.blink_set =
1303             rt2400pci_blink_set;
1304         rt2x00dev->led_radio.flags = LED_INITIALIZED;
1305
1306         if (value == LED_MODE_TXRX_ACTIVITY) {
1307                 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1308                 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1309                 rt2x00dev->led_qual.led_dev.brightness_set =
1310                     rt2400pci_brightness_set;
1311                 rt2x00dev->led_qual.led_dev.blink_set =
1312                     rt2400pci_blink_set;
1313                 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1314         }
1315 #endif /* CONFIG_RT2400PCI_LEDS */
1316
1317         /*
1318          * Detect if this device has an hardware controlled radio.
1319          */
1320 #ifdef CONFIG_RT2400PCI_RFKILL
1321         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1322                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1323 #endif /* CONFIG_RT2400PCI_RFKILL */
1324
1325         /*
1326          * Check if the BBP tuning should be enabled.
1327          */
1328         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1329                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1330
1331         return 0;
1332 }
1333
1334 /*
1335  * RF value list for RF2420 & RF2421
1336  * Supports: 2.4 GHz
1337  */
1338 static const struct rf_channel rf_vals_bg[] = {
1339         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1340         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1341         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1342         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1343         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1344         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1345         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1346         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1347         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1348         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1349         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1350         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1351         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1352         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1353 };
1354
1355 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1356 {
1357         struct hw_mode_spec *spec = &rt2x00dev->spec;
1358         u8 *txpower;
1359         unsigned int i;
1360
1361         /*
1362          * Initialize all hw fields.
1363          */
1364         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1365         rt2x00dev->hw->extra_tx_headroom = 0;
1366         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1367         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1368         rt2x00dev->hw->queues = 2;
1369
1370         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1371         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1372                                 rt2x00_eeprom_addr(rt2x00dev,
1373                                                    EEPROM_MAC_ADDR_0));
1374
1375         /*
1376          * Convert tx_power array in eeprom.
1377          */
1378         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1379         for (i = 0; i < 14; i++)
1380                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1381
1382         /*
1383          * Initialize hw_mode information.
1384          */
1385         spec->supported_bands = SUPPORT_BAND_2GHZ;
1386         spec->supported_rates = SUPPORT_RATE_CCK;
1387         spec->tx_power_a = NULL;
1388         spec->tx_power_bg = txpower;
1389         spec->tx_power_default = DEFAULT_TXPOWER;
1390
1391         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1392         spec->channels = rf_vals_bg;
1393 }
1394
1395 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1396 {
1397         int retval;
1398
1399         /*
1400          * Allocate eeprom data.
1401          */
1402         retval = rt2400pci_validate_eeprom(rt2x00dev);
1403         if (retval)
1404                 return retval;
1405
1406         retval = rt2400pci_init_eeprom(rt2x00dev);
1407         if (retval)
1408                 return retval;
1409
1410         /*
1411          * Initialize hw specifications.
1412          */
1413         rt2400pci_probe_hw_mode(rt2x00dev);
1414
1415         /*
1416          * This device requires the atim queue
1417          */
1418         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1419
1420         /*
1421          * Set the rssi offset.
1422          */
1423         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1424
1425         return 0;
1426 }
1427
1428 /*
1429  * IEEE80211 stack callback functions.
1430  */
1431 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1432                                      u32 short_retry, u32 long_retry)
1433 {
1434         struct rt2x00_dev *rt2x00dev = hw->priv;
1435         u32 reg;
1436
1437         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1438         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1439         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1440         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1441
1442         return 0;
1443 }
1444
1445 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1446                              const struct ieee80211_tx_queue_params *params)
1447 {
1448         struct rt2x00_dev *rt2x00dev = hw->priv;
1449
1450         /*
1451          * We don't support variating cw_min and cw_max variables
1452          * per queue. So by default we only configure the TX queue,
1453          * and ignore all other configurations.
1454          */
1455         if (queue != 0)
1456                 return -EINVAL;
1457
1458         if (rt2x00mac_conf_tx(hw, queue, params))
1459                 return -EINVAL;
1460
1461         /*
1462          * Write configuration to register.
1463          */
1464         rt2400pci_config_cw(rt2x00dev,
1465                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1466
1467         return 0;
1468 }
1469
1470 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1471 {
1472         struct rt2x00_dev *rt2x00dev = hw->priv;
1473         u64 tsf;
1474         u32 reg;
1475
1476         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1477         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1478         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1479         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1480
1481         return tsf;
1482 }
1483
1484 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
1485                                    struct ieee80211_tx_control *control)
1486 {
1487         struct rt2x00_dev *rt2x00dev = hw->priv;
1488         struct rt2x00_intf *intf = vif_to_intf(control->vif);
1489         struct queue_entry_priv_pci_tx *priv_tx;
1490         struct skb_frame_desc *skbdesc;
1491         u32 reg;
1492
1493         if (unlikely(!intf->beacon))
1494                 return -ENOBUFS;
1495         priv_tx = intf->beacon->priv_data;
1496
1497         /*
1498          * Fill in skb descriptor
1499          */
1500         skbdesc = get_skb_frame_desc(skb);
1501         memset(skbdesc, 0, sizeof(*skbdesc));
1502         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1503         skbdesc->data = skb->data;
1504         skbdesc->data_len = skb->len;
1505         skbdesc->desc = priv_tx->desc;
1506         skbdesc->desc_len = intf->beacon->queue->desc_size;
1507         skbdesc->entry = intf->beacon;
1508
1509         /*
1510          * Disable beaconing while we are reloading the beacon data,
1511          * otherwise we might be sending out invalid data.
1512          */
1513         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1514         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1515         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1516         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1517         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1518
1519         /*
1520          * Enable beacon generation.
1521          * Write entire beacon with descriptor to register,
1522          * and kick the beacon generator.
1523          */
1524         rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
1525         memcpy(priv_tx->data, skb->data, skb->len);
1526         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1527
1528         return 0;
1529 }
1530
1531 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1532 {
1533         struct rt2x00_dev *rt2x00dev = hw->priv;
1534         u32 reg;
1535
1536         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1537         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1538 }
1539
1540 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1541         .tx                     = rt2x00mac_tx,
1542         .start                  = rt2x00mac_start,
1543         .stop                   = rt2x00mac_stop,
1544         .add_interface          = rt2x00mac_add_interface,
1545         .remove_interface       = rt2x00mac_remove_interface,
1546         .config                 = rt2x00mac_config,
1547         .config_interface       = rt2x00mac_config_interface,
1548         .configure_filter       = rt2x00mac_configure_filter,
1549         .get_stats              = rt2x00mac_get_stats,
1550         .set_retry_limit        = rt2400pci_set_retry_limit,
1551         .bss_info_changed       = rt2x00mac_bss_info_changed,
1552         .conf_tx                = rt2400pci_conf_tx,
1553         .get_tx_stats           = rt2x00mac_get_tx_stats,
1554         .get_tsf                = rt2400pci_get_tsf,
1555         .beacon_update          = rt2400pci_beacon_update,
1556         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1557 };
1558
1559 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1560         .irq_handler            = rt2400pci_interrupt,
1561         .probe_hw               = rt2400pci_probe_hw,
1562         .initialize             = rt2x00pci_initialize,
1563         .uninitialize           = rt2x00pci_uninitialize,
1564         .init_rxentry           = rt2400pci_init_rxentry,
1565         .init_txentry           = rt2400pci_init_txentry,
1566         .set_device_state       = rt2400pci_set_device_state,
1567         .rfkill_poll            = rt2400pci_rfkill_poll,
1568         .link_stats             = rt2400pci_link_stats,
1569         .reset_tuner            = rt2400pci_reset_tuner,
1570         .link_tuner             = rt2400pci_link_tuner,
1571         .write_tx_desc          = rt2400pci_write_tx_desc,
1572         .write_tx_data          = rt2x00pci_write_tx_data,
1573         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1574         .fill_rxdone            = rt2400pci_fill_rxdone,
1575         .config_filter          = rt2400pci_config_filter,
1576         .config_intf            = rt2400pci_config_intf,
1577         .config_erp             = rt2400pci_config_erp,
1578         .config                 = rt2400pci_config,
1579 };
1580
1581 static const struct data_queue_desc rt2400pci_queue_rx = {
1582         .entry_num              = RX_ENTRIES,
1583         .data_size              = DATA_FRAME_SIZE,
1584         .desc_size              = RXD_DESC_SIZE,
1585         .priv_size              = sizeof(struct queue_entry_priv_pci_rx),
1586 };
1587
1588 static const struct data_queue_desc rt2400pci_queue_tx = {
1589         .entry_num              = TX_ENTRIES,
1590         .data_size              = DATA_FRAME_SIZE,
1591         .desc_size              = TXD_DESC_SIZE,
1592         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1593 };
1594
1595 static const struct data_queue_desc rt2400pci_queue_bcn = {
1596         .entry_num              = BEACON_ENTRIES,
1597         .data_size              = MGMT_FRAME_SIZE,
1598         .desc_size              = TXD_DESC_SIZE,
1599         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1600 };
1601
1602 static const struct data_queue_desc rt2400pci_queue_atim = {
1603         .entry_num              = ATIM_ENTRIES,
1604         .data_size              = DATA_FRAME_SIZE,
1605         .desc_size              = TXD_DESC_SIZE,
1606         .priv_size              = sizeof(struct queue_entry_priv_pci_tx),
1607 };
1608
1609 static const struct rt2x00_ops rt2400pci_ops = {
1610         .name           = KBUILD_MODNAME,
1611         .max_sta_intf   = 1,
1612         .max_ap_intf    = 1,
1613         .eeprom_size    = EEPROM_SIZE,
1614         .rf_size        = RF_SIZE,
1615         .rx             = &rt2400pci_queue_rx,
1616         .tx             = &rt2400pci_queue_tx,
1617         .bcn            = &rt2400pci_queue_bcn,
1618         .atim           = &rt2400pci_queue_atim,
1619         .lib            = &rt2400pci_rt2x00_ops,
1620         .hw             = &rt2400pci_mac80211_ops,
1621 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1622         .debugfs        = &rt2400pci_rt2x00debug,
1623 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1624 };
1625
1626 /*
1627  * RT2400pci module information.
1628  */
1629 static struct pci_device_id rt2400pci_device_table[] = {
1630         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1631         { 0, }
1632 };
1633
1634 MODULE_AUTHOR(DRV_PROJECT);
1635 MODULE_VERSION(DRV_VERSION);
1636 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1637 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1638 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1639 MODULE_LICENSE("GPL");
1640
1641 static struct pci_driver rt2400pci_driver = {
1642         .name           = KBUILD_MODNAME,
1643         .id_table       = rt2400pci_device_table,
1644         .probe          = rt2x00pci_probe,
1645         .remove         = __devexit_p(rt2x00pci_remove),
1646         .suspend        = rt2x00pci_suspend,
1647         .resume         = rt2x00pci_resume,
1648 };
1649
1650 static int __init rt2400pci_init(void)
1651 {
1652         return pci_register_driver(&rt2400pci_driver);
1653 }
1654
1655 static void __exit rt2400pci_exit(void)
1656 {
1657         pci_unregister_driver(&rt2400pci_driver);
1658 }
1659
1660 module_init(rt2400pci_init);
1661 module_exit(rt2400pci_exit);