err.no Git - linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-core.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  * Tomas Winkler <tomas.winkler@intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *****************************************************************************/
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/version.h>
  32 #include <net/mac80211.h>
  33
  34 struct iwl_priv; /* FIXME: remove */
  35 #include "iwl-debug.h"
  36 #include "iwl-eeprom.h"
  37 #include "iwl-dev.h" /* FIXME: remove */
  38 #include "iwl-core.h"
  39 #include "iwl-io.h"
  40 #include "iwl-rfkill.h"
  41 #include "iwl-power.h"
  42
  43
  44 MODULE_DESCRIPTION("iwl core");
  45 MODULE_VERSION(IWLWIFI_VERSION);
  46 MODULE_AUTHOR(DRV_COPYRIGHT);
  47 MODULE_LICENSE("GPL");
  48
  49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np)    \
  50         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,      \
  51                                     IWL_RATE_SISO_##s##M_PLCP, \
  52                                     IWL_RATE_MIMO2_##s##M_PLCP,\
  53                                     IWL_RATE_MIMO3_##s##M_PLCP,\
  54                                     IWL_RATE_##r##M_IEEE,      \
  55                                     IWL_RATE_##ip##M_INDEX,    \
  56                                     IWL_RATE_##in##M_INDEX,    \
  57                                     IWL_RATE_##rp##M_INDEX,    \
  58                                     IWL_RATE_##rn##M_INDEX,    \
  59                                     IWL_RATE_##pp##M_INDEX,    \
  60                                     IWL_RATE_##np##M_INDEX }
  61
  62 /*
  63  * Parameter order:
  64  *   rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  65  *
  66  * If there isn't a valid next or previous rate then INV is used which
  67  * maps to IWL_RATE_INVALID
  68  *
  69  */
  70 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  71         IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  72         IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  73         IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  74         IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18),      /* 11mbps */
  75         IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  76         IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11),       /*  9mbps */
  77         IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  78         IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  79         IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  80         IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  81         IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  82         IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  83         IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  84         /* FIXME:RS:          ^^    should be INV (legacy) */
  85 };
  86 EXPORT_SYMBOL(iwl_rates);
  87
  88 /**
  89  * translate ucode response to mac80211 tx status control values
  90  */
  91 void iwl_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
  92                                   struct ieee80211_tx_info *control)
  93 {
  94         int rate_index;
  95
  96         control->antenna_sel_tx =
  97                 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS);
  98         if (rate_n_flags & RATE_MCS_HT_MSK)
  99                 control->flags |= IEEE80211_TX_CTL_OFDM_HT;
 100         if (rate_n_flags & RATE_MCS_GF_MSK)
 101                 control->flags |= IEEE80211_TX_CTL_GREEN_FIELD;
 102         if (rate_n_flags & RATE_MCS_FAT_MSK)
 103                 control->flags |= IEEE80211_TX_CTL_40_MHZ_WIDTH;
 104         if (rate_n_flags & RATE_MCS_DUP_MSK)
 105                 control->flags |= IEEE80211_TX_CTL_DUP_DATA;
 106         if (rate_n_flags & RATE_MCS_SGI_MSK)
 107                 control->flags |= IEEE80211_TX_CTL_SHORT_GI;
 108         rate_index = iwl_hwrate_to_plcp_idx(rate_n_flags);
 109         if (control->band == IEEE80211_BAND_5GHZ)
 110                 rate_index -= IWL_FIRST_OFDM_RATE;
 111         control->tx_rate_idx = rate_index;
 112 }
 113 EXPORT_SYMBOL(iwl_hwrate_to_tx_control);
 114
 115 int iwl_hwrate_to_plcp_idx(u32 rate_n_flags)
 116 {
 117         int idx = 0;
 118
 119         /* HT rate format */
 120         if (rate_n_flags & RATE_MCS_HT_MSK) {
 121                 idx = (rate_n_flags & 0xff);
 122
 123                 if (idx >= IWL_RATE_MIMO2_6M_PLCP)
 124                         idx = idx - IWL_RATE_MIMO2_6M_PLCP;
 125
 126                 idx += IWL_FIRST_OFDM_RATE;
 127                 /* skip 9M not supported in ht*/
 128                 if (idx >= IWL_RATE_9M_INDEX)
 129                         idx += 1;
 130                 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
 131                         return idx;
 132
 133         /* legacy rate format, search for match in table */
 134         } else {
 135                 for (idx = 0; idx < ARRAY_SIZE(iwl_rates); idx++)
 136                         if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
 137                                 return idx;
 138         }
 139
 140         return -1;
 141 }
 142 EXPORT_SYMBOL(iwl_hwrate_to_plcp_idx);
 143
 144
 145
 146 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
 147 EXPORT_SYMBOL(iwl_bcast_addr);
 148
 149
 150 /* This function both allocates and initializes hw and priv. */
 151 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
 152                 struct ieee80211_ops *hw_ops)
 153 {
 154         struct iwl_priv *priv;
 155
 156         /* mac80211 allocates memory for this device instance, including
 157          *   space for this driver's private structure */
 158         struct ieee80211_hw *hw =
 159                 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
 160         if (hw == NULL) {
 161                 IWL_ERROR("Can not allocate network device\n");
 162                 goto out;
 163         }
 164
 165         priv = hw->priv;
 166         priv->hw = hw;
 167
 168 out:
 169         return hw;
 170 }
 171 EXPORT_SYMBOL(iwl_alloc_all);
 172
 173 void iwl_hw_detect(struct iwl_priv *priv)
 174 {
 175         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
 176         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
 177         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
 178 }
 179 EXPORT_SYMBOL(iwl_hw_detect);
 180
 181 /* Tell nic where to find the "keep warm" buffer */
 182 int iwl_kw_init(struct iwl_priv *priv)
 183 {
 184         unsigned long flags;
 185         int ret;
 186
 187         spin_lock_irqsave(&priv->lock, flags);
 188         ret = iwl_grab_nic_access(priv);
 189         if (ret)
 190                 goto out;
 191
 192         iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
 193                              priv->kw.dma_addr >> 4);
 194         iwl_release_nic_access(priv);
 195 out:
 196         spin_unlock_irqrestore(&priv->lock, flags);
 197         return ret;
 198 }
 199
 200 int iwl_kw_alloc(struct iwl_priv *priv)
 201 {
 202         struct pci_dev *dev = priv->pci_dev;
 203         struct iwl_kw *kw = &priv->kw;
 204
 205         kw->size = IWL_KW_SIZE;
 206         kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
 207         if (!kw->v_addr)
 208                 return -ENOMEM;
 209
 210         return 0;
 211 }
 212
 213 /**
 214  * iwl_kw_free - Free the "keep warm" buffer
 215  */
 216 void iwl_kw_free(struct iwl_priv *priv)
 217 {
 218         struct pci_dev *dev = priv->pci_dev;
 219         struct iwl_kw *kw = &priv->kw;
 220
 221         if (kw->v_addr) {
 222                 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
 223                 memset(kw, 0, sizeof(*kw));
 224         }
 225 }
 226
 227 int iwl_hw_nic_init(struct iwl_priv *priv)
 228 {
 229         unsigned long flags;
 230         struct iwl_rx_queue *rxq = &priv->rxq;
 231         int ret;
 232
 233         /* nic_init */
 234         spin_lock_irqsave(&priv->lock, flags);
 235         priv->cfg->ops->lib->apm_ops.init(priv);
 236         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
 237         spin_unlock_irqrestore(&priv->lock, flags);
 238
 239         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
 240
 241         priv->cfg->ops->lib->apm_ops.config(priv);
 242
 243         /* Allocate the RX queue, or reset if it is already allocated */
 244         if (!rxq->bd) {
 245                 ret = iwl_rx_queue_alloc(priv);
 246                 if (ret) {
 247                         IWL_ERROR("Unable to initialize Rx queue\n");
 248                         return -ENOMEM;
 249                 }
 250         } else
 251                 iwl_rx_queue_reset(priv, rxq);
 252
 253         iwl_rx_replenish(priv);
 254
 255         iwl_rx_init(priv, rxq);
 256
 257         spin_lock_irqsave(&priv->lock, flags);
 258
 259         rxq->need_update = 1;
 260         iwl_rx_queue_update_write_ptr(priv, rxq);
 261
 262         spin_unlock_irqrestore(&priv->lock, flags);
 263
 264         /* Allocate and init all Tx and Command queues */
 265         ret = iwl_txq_ctx_reset(priv);
 266         if (ret)
 267                 return ret;
 268
 269         set_bit(STATUS_INIT, &priv->status);
 270
 271         return 0;
 272 }
 273 EXPORT_SYMBOL(iwl_hw_nic_init);
 274
 275 /**
 276  * iwlcore_clear_stations_table - Clear the driver's station table
 277  *
 278  * NOTE:  This does not clear or otherwise alter the device's station table.
 279  */
 280 void iwlcore_clear_stations_table(struct iwl_priv *priv)
 281 {
 282         unsigned long flags;
 283
 284         spin_lock_irqsave(&priv->sta_lock, flags);
 285
 286         priv->num_stations = 0;
 287         if (iwl_is_alive(priv) &&
 288             iwl_send_cmd_pdu_async(priv, REPLY_REMOVE_ALL_STA, 0, NULL, NULL))
 289                 IWL_ERROR("Couldn't clear the station table\n");
 290
 291         memset(priv->stations, 0, sizeof(priv->stations));
 292
 293         spin_unlock_irqrestore(&priv->sta_lock, flags);
 294 }
 295 EXPORT_SYMBOL(iwlcore_clear_stations_table);
 296
 297 void iwl_reset_qos(struct iwl_priv *priv)
 298 {
 299         u16 cw_min = 15;
 300         u16 cw_max = 1023;
 301         u8 aifs = 2;
 302         u8 is_legacy = 0;
 303         unsigned long flags;
 304         int i;
 305
 306         spin_lock_irqsave(&priv->lock, flags);
 307         priv->qos_data.qos_active = 0;
 308
 309         if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
 310                 if (priv->qos_data.qos_enable)
 311                         priv->qos_data.qos_active = 1;
 312                 if (!(priv->active_rate & 0xfff0)) {
 313                         cw_min = 31;
 314                         is_legacy = 1;
 315                 }
 316         } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
 317                 if (priv->qos_data.qos_enable)
 318                         priv->qos_data.qos_active = 1;
 319         } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
 320                 cw_min = 31;
 321                 is_legacy = 1;
 322         }
 323
 324         if (priv->qos_data.qos_active)
 325                 aifs = 3;
 326
 327         priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
 328         priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
 329         priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
 330         priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
 331         priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
 332
 333         if (priv->qos_data.qos_active) {
 334                 i = 1;
 335                 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
 336                 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
 337                 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
 338                 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 339                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 340
 341                 i = 2;
 342                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 343                         cpu_to_le16((cw_min + 1) / 2 - 1);
 344                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 345                         cpu_to_le16(cw_max);
 346                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 347                 if (is_legacy)
 348                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 349                                 cpu_to_le16(6016);
 350                 else
 351                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 352                                 cpu_to_le16(3008);
 353                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 354
 355                 i = 3;
 356                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 357                         cpu_to_le16((cw_min + 1) / 4 - 1);
 358                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 359                         cpu_to_le16((cw_max + 1) / 2 - 1);
 360                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 361                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 362                 if (is_legacy)
 363                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 364                                 cpu_to_le16(3264);
 365                 else
 366                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 367                                 cpu_to_le16(1504);
 368         } else {
 369                 for (i = 1; i < 4; i++) {
 370                         priv->qos_data.def_qos_parm.ac[i].cw_min =
 371                                 cpu_to_le16(cw_min);
 372                         priv->qos_data.def_qos_parm.ac[i].cw_max =
 373                                 cpu_to_le16(cw_max);
 374                         priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
 375                         priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 376                         priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 377                 }
 378         }
 379         IWL_DEBUG_QOS("set QoS to default \n");
 380
 381         spin_unlock_irqrestore(&priv->lock, flags);
 382 }
 383 EXPORT_SYMBOL(iwl_reset_qos);
 384
 385 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
 386 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
 387 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
 388                               struct ieee80211_ht_info *ht_info,
 389                               enum ieee80211_band band)
 390 {
 391         u16 max_bit_rate = 0;
 392         u8 rx_chains_num = priv->hw_params.rx_chains_num;
 393         u8 tx_chains_num = priv->hw_params.tx_chains_num;
 394
 395         ht_info->cap = 0;
 396         memset(ht_info->supp_mcs_set, 0, 16);
 397
 398         ht_info->ht_supported = 1;
 399
 400         ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
 401         ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
 402         ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
 403                              (IWL_MIMO_PS_NONE << 2));
 404
 405         max_bit_rate = MAX_BIT_RATE_20_MHZ;
 406         if (priv->hw_params.fat_channel & BIT(band)) {
 407                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
 408                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
 409                 ht_info->supp_mcs_set[4] = 0x01;
 410                 max_bit_rate = MAX_BIT_RATE_40_MHZ;
 411         }
 412
 413         if (priv->cfg->mod_params->amsdu_size_8K)
 414                 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
 415
 416         ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
 417         ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
 418
 419         ht_info->supp_mcs_set[0] = 0xFF;
 420         if (rx_chains_num >= 2)
 421                 ht_info->supp_mcs_set[1] = 0xFF;
 422         if (rx_chains_num >= 3)
 423                 ht_info->supp_mcs_set[2] = 0xFF;
 424
 425         /* Highest supported Rx data rate */
 426         max_bit_rate *= rx_chains_num;
 427         ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
 428         ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
 429
 430         /* Tx MCS capabilities */
 431         ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
 432         if (tx_chains_num != rx_chains_num) {
 433                 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
 434                 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
 435         }
 436 }
 437
 438 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
 439                               struct ieee80211_rate *rates)
 440 {
 441         int i;
 442
 443         for (i = 0; i < IWL_RATE_COUNT; i++) {
 444                 rates[i].bitrate = iwl_rates[i].ieee * 5;
 445                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
 446                 rates[i].hw_value_short = i;
 447                 rates[i].flags = 0;
 448                 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
 449                         /*
 450                          * If CCK != 1M then set short preamble rate flag.
 451                          */
 452                         rates[i].flags |=
 453                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
 454                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
 455                 }
 456         }
 457 }
 458
 459 /**
 460  * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
 461  */
 462 static int iwlcore_init_geos(struct iwl_priv *priv)
 463 {
 464         struct iwl_channel_info *ch;
 465         struct ieee80211_supported_band *sband;
 466         struct ieee80211_channel *channels;
 467         struct ieee80211_channel *geo_ch;
 468         struct ieee80211_rate *rates;
 469         int i = 0;
 470
 471         if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
 472             priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
 473                 IWL_DEBUG_INFO("Geography modes already initialized.\n");
 474                 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 475                 return 0;
 476         }
 477
 478         channels = kzalloc(sizeof(struct ieee80211_channel) *
 479                            priv->channel_count, GFP_KERNEL);
 480         if (!channels)
 481                 return -ENOMEM;
 482
 483         rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
 484                         GFP_KERNEL);
 485         if (!rates) {
 486                 kfree(channels);
 487                 return -ENOMEM;
 488         }
 489
 490         /* 5.2GHz channels start after the 2.4GHz channels */
 491         sband = &priv->bands[IEEE80211_BAND_5GHZ];
 492         sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
 493         /* just OFDM */
 494         sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
 495         sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
 496
 497         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
 498
 499         sband = &priv->bands[IEEE80211_BAND_2GHZ];
 500         sband->channels = channels;
 501         /* OFDM & CCK */
 502         sband->bitrates = rates;
 503         sband->n_bitrates = IWL_RATE_COUNT;
 504
 505         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
 506
 507         priv->ieee_channels = channels;
 508         priv->ieee_rates = rates;
 509
 510         iwlcore_init_hw_rates(priv, rates);
 511
 512         for (i = 0;  i < priv->channel_count; i++) {
 513                 ch = &priv->channel_info[i];
 514
 515                 /* FIXME: might be removed if scan is OK */
 516                 if (!is_channel_valid(ch))
 517                         continue;
 518
 519                 if (is_channel_a_band(ch))
 520                         sband =  &priv->bands[IEEE80211_BAND_5GHZ];
 521                 else
 522                         sband =  &priv->bands[IEEE80211_BAND_2GHZ];
 523
 524                 geo_ch = &sband->channels[sband->n_channels++];
 525
 526                 geo_ch->center_freq =
 527                                 ieee80211_channel_to_frequency(ch->channel);
 528                 geo_ch->max_power = ch->max_power_avg;
 529                 geo_ch->max_antenna_gain = 0xff;
 530                 geo_ch->hw_value = ch->channel;
 531
 532                 if (is_channel_valid(ch)) {
 533                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
 534                                 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
 535
 536                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
 537                                 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 538
 539                         if (ch->flags & EEPROM_CHANNEL_RADAR)
 540                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
 541
 542                         geo_ch->flags |= ch->fat_extension_channel;
 543
 544                         if (ch->max_power_avg > priv->tx_power_channel_lmt)
 545                                 priv->tx_power_channel_lmt = ch->max_power_avg;
 546                 } else {
 547                         geo_ch->flags |= IEEE80211_CHAN_DISABLED;
 548                 }
 549
 550                 /* Save flags for reg domain usage */
 551                 geo_ch->orig_flags = geo_ch->flags;
 552
 553                 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
 554                                 ch->channel, geo_ch->center_freq,
 555                                 is_channel_a_band(ch) ?  "5.2" : "2.4",
 556                                 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
 557                                 "restricted" : "valid",
 558                                  geo_ch->flags);
 559         }
 560
 561         if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
 562              priv->cfg->sku & IWL_SKU_A) {
 563                 printk(KERN_INFO DRV_NAME
 564                        ": Incorrectly detected BG card as ABG.  Please send "
 565                        "your PCI ID 0x%04X:0x%04X to maintainer.\n",
 566                        priv->pci_dev->device, priv->pci_dev->subsystem_device);
 567                 priv->cfg->sku &= ~IWL_SKU_A;
 568         }
 569
 570         printk(KERN_INFO DRV_NAME
 571                ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
 572                priv->bands[IEEE80211_BAND_2GHZ].n_channels,
 573                priv->bands[IEEE80211_BAND_5GHZ].n_channels);
 574
 575
 576         set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 577
 578         return 0;
 579 }
 580
 581 /*
 582  * iwlcore_free_geos - undo allocations in iwlcore_init_geos
 583  */
 584 static void iwlcore_free_geos(struct iwl_priv *priv)
 585 {
 586         kfree(priv->ieee_channels);
 587         kfree(priv->ieee_rates);
 588         clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
 589 }
 590
 591 static u8 is_single_rx_stream(struct iwl_priv *priv)
 592 {
 593         return !priv->current_ht_config.is_ht ||
 594                ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
 595                 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
 596                priv->ps_mode == IWL_MIMO_PS_STATIC;
 597 }
 598
 599 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
 600                                    enum ieee80211_band band,
 601                                    u16 channel, u8 extension_chan_offset)
 602 {
 603         const struct iwl_channel_info *ch_info;
 604
 605         ch_info = iwl_get_channel_info(priv, band, channel);
 606         if (!is_channel_valid(ch_info))
 607                 return 0;
 608
 609         if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
 610                 return !(ch_info->fat_extension_channel &
 611                                         IEEE80211_CHAN_NO_FAT_ABOVE);
 612         else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
 613                 return !(ch_info->fat_extension_channel &
 614                                         IEEE80211_CHAN_NO_FAT_BELOW);
 615
 616         return 0;
 617 }
 618
 619 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
 620                              struct ieee80211_ht_info *sta_ht_inf)
 621 {
 622         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
 623
 624         if ((!iwl_ht_conf->is_ht) ||
 625            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
 626            (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
 627                 return 0;
 628
 629         if (sta_ht_inf) {
 630                 if ((!sta_ht_inf->ht_supported) ||
 631                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
 632                         return 0;
 633         }
 634
 635         return iwl_is_channel_extension(priv, priv->band,
 636                                          iwl_ht_conf->control_channel,
 637                                          iwl_ht_conf->extension_chan_offset);
 638 }
 639 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
 640
 641 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
 642 {
 643         struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
 644         u32 val;
 645
 646         if (!ht_info->is_ht)
 647                 return;
 648
 649         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
 650         if (iwl_is_fat_tx_allowed(priv, NULL))
 651                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 652         else
 653                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
 654                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
 655
 656         if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
 657                 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
 658                                 le16_to_cpu(rxon->channel),
 659                                 ht_info->control_channel);
 660                 return;
 661         }
 662
 663         /* Note: control channel is opposite of extension channel */
 664         switch (ht_info->extension_chan_offset) {
 665         case IEEE80211_HT_IE_CHA_SEC_ABOVE:
 666                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
 667                 break;
 668         case IEEE80211_HT_IE_CHA_SEC_BELOW:
 669                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
 670                 break;
 671         case IEEE80211_HT_IE_CHA_SEC_NONE:
 672         default:
 673                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 674                 break;
 675         }
 676
 677         val = ht_info->ht_protection;
 678
 679         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
 680
 681         iwl_set_rxon_chain(priv);
 682
 683         IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
 684                         "rxon flags 0x%X operation mode :0x%X "
 685                         "extension channel offset 0x%x "
 686                         "control chan %d\n",
 687                         ht_info->supp_mcs_set[0],
 688                         ht_info->supp_mcs_set[1],
 689                         ht_info->supp_mcs_set[2],
 690                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
 691                         ht_info->extension_chan_offset,
 692                         ht_info->control_channel);
 693         return;
 694 }
 695 EXPORT_SYMBOL(iwl_set_rxon_ht);
 696
 697 /*
 698  * Determine how many receiver/antenna chains to use.
 699  * More provides better reception via diversity.  Fewer saves power.
 700  * MIMO (dual stream) requires at least 2, but works better with 3.
 701  * This does not determine *which* chains to use, just how many.
 702  */
 703 static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
 704                                         u8 *idle_state, u8 *rx_state)
 705 {
 706         u8 is_single = is_single_rx_stream(priv);
 707         u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
 708
 709         /* # of Rx chains to use when expecting MIMO. */
 710         if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
 711                 *rx_state = 2;
 712         else
 713                 *rx_state = 3;
 714
 715         /* # Rx chains when idling and maybe trying to save power */
 716         switch (priv->ps_mode) {
 717         case IWL_MIMO_PS_STATIC:
 718         case IWL_MIMO_PS_DYNAMIC:
 719                 *idle_state = (is_cam) ? 2 : 1;
 720                 break;
 721         case IWL_MIMO_PS_NONE:
 722                 *idle_state = (is_cam) ? *rx_state : 1;
 723                 break;
 724         default:
 725                 *idle_state = 1;
 726                 break;
 727         }
 728
 729         return 0;
 730 }
 731
 732 /**
 733  * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
 734  *
 735  * Selects how many and which Rx receivers/antennas/chains to use.
 736  * This should not be used for scan command ... it puts data in wrong place.
 737  */
 738 void iwl_set_rxon_chain(struct iwl_priv *priv)
 739 {
 740         u8 is_single = is_single_rx_stream(priv);
 741         u8 idle_state, rx_state;
 742
 743         priv->staging_rxon.rx_chain = 0;
 744         rx_state = idle_state = 3;
 745
 746         /* Tell uCode which antennas are actually connected.
 747          * Before first association, we assume all antennas are connected.
 748          * Just after first association, iwl_chain_noise_calibration()
 749          *    checks which antennas actually *are* connected. */
 750         priv->staging_rxon.rx_chain |=
 751                     cpu_to_le16(priv->hw_params.valid_rx_ant <<
 752                                                  RXON_RX_CHAIN_VALID_POS);
 753
 754         /* How many receivers should we use? */
 755         iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
 756         priv->staging_rxon.rx_chain |=
 757                 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
 758         priv->staging_rxon.rx_chain |=
 759                 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
 760
 761         if (!is_single && (rx_state >= 2) &&
 762             !test_bit(STATUS_POWER_PMI, &priv->status))
 763                 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
 764         else
 765                 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
 766
 767         IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
 768 }
 769 EXPORT_SYMBOL(iwl_set_rxon_chain);
 770
 771 /**
 772  * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
 773  * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
 774  * @channel: Any channel valid for the requested phymode
 775
 776  * In addition to setting the staging RXON, priv->phymode is also set.
 777  *
 778  * NOTE:  Does not commit to the hardware; it sets appropriate bit fields
 779  * in the staging RXON flag structure based on the phymode
 780  */
 781 int iwl_set_rxon_channel(struct iwl_priv *priv,
 782                                 enum ieee80211_band band,
 783                                 u16 channel)
 784 {
 785         if (!iwl_get_channel_info(priv, band, channel)) {
 786                 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
 787                                channel, band);
 788                 return -EINVAL;
 789         }
 790
 791         if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
 792             (priv->band == band))
 793                 return 0;
 794
 795         priv->staging_rxon.channel = cpu_to_le16(channel);
 796         if (band == IEEE80211_BAND_5GHZ)
 797                 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
 798         else
 799                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
 800
 801         priv->band = band;
 802
 803         IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
 804
 805         return 0;
 806 }
 807 EXPORT_SYMBOL(iwl_set_rxon_channel);
 808
 809 int iwl_setup_mac(struct iwl_priv *priv)
 810 {
 811         int ret;
 812         struct ieee80211_hw *hw = priv->hw;
 813         hw->rate_control_algorithm = "iwl-4965-rs";
 814
 815         /* Tell mac80211 our characteristics */
 816         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
 817                     IEEE80211_HW_SIGNAL_DBM |
 818                     IEEE80211_HW_NOISE_DBM;
 819         /* Default value; 4 EDCA QOS priorities */
 820         hw->queues = 4;
 821         /* Enhanced value; more queues, to support 11n aggregation */
 822         hw->ampdu_queues = 12;
 823
 824         hw->conf.beacon_int = 100;
 825
 826         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
 827                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 828                         &priv->bands[IEEE80211_BAND_2GHZ];
 829         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
 830                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 831                         &priv->bands[IEEE80211_BAND_5GHZ];
 832
 833         ret = ieee80211_register_hw(priv->hw);
 834         if (ret) {
 835                 IWL_ERROR("Failed to register hw (error %d)\n", ret);
 836                 return ret;
 837         }
 838         priv->mac80211_registered = 1;
 839
 840         return 0;
 841 }
 842 EXPORT_SYMBOL(iwl_setup_mac);
 843
 844
 845 int iwl_init_drv(struct iwl_priv *priv)
 846 {
 847         int ret;
 848         int i;
 849
 850         priv->retry_rate = 1;
 851         priv->ibss_beacon = NULL;
 852
 853         spin_lock_init(&priv->lock);
 854         spin_lock_init(&priv->power_data.lock);
 855         spin_lock_init(&priv->sta_lock);
 856         spin_lock_init(&priv->hcmd_lock);
 857         spin_lock_init(&priv->lq_mngr.lock);
 858
 859         for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
 860                 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
 861
 862         INIT_LIST_HEAD(&priv->free_frames);
 863
 864         mutex_init(&priv->mutex);
 865
 866         /* Clear the driver's (not device's) station table */
 867         iwlcore_clear_stations_table(priv);
 868
 869         priv->data_retry_limit = -1;
 870         priv->ieee_channels = NULL;
 871         priv->ieee_rates = NULL;
 872         priv->band = IEEE80211_BAND_2GHZ;
 873
 874         priv->iw_mode = IEEE80211_IF_TYPE_STA;
 875
 876         priv->use_ant_b_for_management_frame = 1; /* start with ant B */
 877         priv->ps_mode = IWL_MIMO_PS_NONE;
 878
 879         /* Choose which receivers/antennas to use */
 880         iwl_set_rxon_chain(priv);
 881         iwl_init_scan_params(priv);
 882
 883         if (priv->cfg->mod_params->enable_qos)
 884                 priv->qos_data.qos_enable = 1;
 885
 886         iwl_reset_qos(priv);
 887
 888         priv->qos_data.qos_active = 0;
 889         priv->qos_data.qos_cap.val = 0;
 890
 891         iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
 892
 893         priv->rates_mask = IWL_RATES_MASK;
 894         /* If power management is turned on, default to AC mode */
 895         priv->power_mode = IWL_POWER_AC;
 896         priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MAX;
 897
 898         ret = iwl_init_channel_map(priv);
 899         if (ret) {
 900                 IWL_ERROR("initializing regulatory failed: %d\n", ret);
 901                 goto err;
 902         }
 903
 904         ret = iwlcore_init_geos(priv);
 905         if (ret) {
 906                 IWL_ERROR("initializing geos failed: %d\n", ret);
 907                 goto err_free_channel_map;
 908         }
 909
 910         return 0;
 911
 912 err_free_channel_map:
 913         iwl_free_channel_map(priv);
 914 err:
 915         return ret;
 916 }
 917 EXPORT_SYMBOL(iwl_init_drv);
 918
 919 void iwl_free_calib_results(struct iwl_priv *priv)
 920 {
 921         kfree(priv->calib_results.lo_res);
 922         priv->calib_results.lo_res = NULL;
 923         priv->calib_results.lo_res_len = 0;
 924
 925         kfree(priv->calib_results.tx_iq_res);
 926         priv->calib_results.tx_iq_res = NULL;
 927         priv->calib_results.tx_iq_res_len = 0;
 928
 929         kfree(priv->calib_results.tx_iq_perd_res);
 930         priv->calib_results.tx_iq_perd_res = NULL;
 931         priv->calib_results.tx_iq_perd_res_len = 0;
 932 }
 933 EXPORT_SYMBOL(iwl_free_calib_results);
 934
 935 int iwl_set_tx_power(struct iwl_priv *priv, s8 tx_power, bool force)
 936 {
 937         int ret = 0;
 938         if (tx_power < IWL_TX_POWER_TARGET_POWER_MIN) {
 939                 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
 940                             priv->tx_power_user_lmt);
 941                 return -EINVAL;
 942         }
 943
 944         if (tx_power > IWL_TX_POWER_TARGET_POWER_MAX) {
 945                 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
 946                             priv->tx_power_user_lmt);
 947                 return -EINVAL;
 948         }
 949
 950         if (priv->tx_power_user_lmt != tx_power)
 951                 force = true;
 952
 953         priv->tx_power_user_lmt = tx_power;
 954
 955         if (force && priv->cfg->ops->lib->send_tx_power)
 956                 ret = priv->cfg->ops->lib->send_tx_power(priv);
 957
 958         return ret;
 959 }
 960 EXPORT_SYMBOL(iwl_set_tx_power);
 961
 962
 963 void iwl_uninit_drv(struct iwl_priv *priv)
 964 {
 965         iwl_free_calib_results(priv);
 966         iwlcore_free_geos(priv);
 967         iwl_free_channel_map(priv);
 968         kfree(priv->scan);
 969 }
 970 EXPORT_SYMBOL(iwl_uninit_drv);
 971
 972 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
 973 {
 974         u32 stat_flags = 0;
 975         struct iwl_host_cmd cmd = {
 976                 .id = REPLY_STATISTICS_CMD,
 977                 .meta.flags = flags,
 978                 .len = sizeof(stat_flags),
 979                 .data = (u8 *) &stat_flags,
 980         };
 981         return iwl_send_cmd(priv, &cmd);
 982 }
 983 EXPORT_SYMBOL(iwl_send_statistics_request);
 984
 985 /**
 986  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 987  *   using sample data 100 bytes apart.  If these sample points are good,
 988  *   it's a pretty good bet that everything between them is good, too.
 989  */
 990 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
 991 {
 992         u32 val;
 993         int ret = 0;
 994         u32 errcnt = 0;
 995         u32 i;
 996
 997         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
 998
 999         ret = iwl_grab_nic_access(priv);
1000         if (ret)
1001                 return ret;
1002
1003         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
1004                 /* read data comes through single port, auto-incr addr */
1005                 /* NOTE: Use the debugless read so we don't flood kernel log
1006                  * if IWL_DL_IO is set */
1007                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
1008                         i + RTC_INST_LOWER_BOUND);
1009                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1010                 if (val != le32_to_cpu(*image)) {
1011                         ret = -EIO;
1012                         errcnt++;
1013                         if (errcnt >= 3)
1014                                 break;
1015                 }
1016         }
1017
1018         iwl_release_nic_access(priv);
1019
1020         return ret;
1021 }
1022
1023 /**
1024  * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
1025  *     looking at all data.
1026  */
1027 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
1028                                  u32 len)
1029 {
1030         u32 val;
1031         u32 save_len = len;
1032         int ret = 0;
1033         u32 errcnt;
1034
1035         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
1036
1037         ret = iwl_grab_nic_access(priv);
1038         if (ret)
1039                 return ret;
1040
1041         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
1042
1043         errcnt = 0;
1044         for (; len > 0; len -= sizeof(u32), image++) {
1045                 /* read data comes through single port, auto-incr addr */
1046                 /* NOTE: Use the debugless read so we don't flood kernel log
1047                  * if IWL_DL_IO is set */
1048                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
1049                 if (val != le32_to_cpu(*image)) {
1050                         IWL_ERROR("uCode INST section is invalid at "
1051                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
1052                                   save_len - len, val, le32_to_cpu(*image));
1053                         ret = -EIO;
1054                         errcnt++;
1055                         if (errcnt >= 20)
1056                                 break;
1057                 }
1058         }
1059
1060         iwl_release_nic_access(priv);
1061
1062         if (!errcnt)
1063                 IWL_DEBUG_INFO
1064                     ("ucode image in INSTRUCTION memory is good\n");
1065
1066         return ret;
1067 }
1068
1069 /**
1070  * iwl_verify_ucode - determine which instruction image is in SRAM,
1071  *    and verify its contents
1072  */
1073 int iwl_verify_ucode(struct iwl_priv *priv)
1074 {
1075         __le32 *image;
1076         u32 len;
1077         int ret;
1078
1079         /* Try bootstrap */
1080         image = (__le32 *)priv->ucode_boot.v_addr;
1081         len = priv->ucode_boot.len;
1082         ret = iwlcore_verify_inst_sparse(priv, image, len);
1083         if (!ret) {
1084                 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1085                 return 0;
1086         }
1087
1088         /* Try initialize */
1089         image = (__le32 *)priv->ucode_init.v_addr;
1090         len = priv->ucode_init.len;
1091         ret = iwlcore_verify_inst_sparse(priv, image, len);
1092         if (!ret) {
1093                 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1094                 return 0;
1095         }
1096
1097         /* Try runtime/protocol */
1098         image = (__le32 *)priv->ucode_code.v_addr;
1099         len = priv->ucode_code.len;
1100         ret = iwlcore_verify_inst_sparse(priv, image, len);
1101         if (!ret) {
1102                 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1103                 return 0;
1104         }
1105
1106         IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1107
1108         /* Since nothing seems to match, show first several data entries in
1109          * instruction SRAM, so maybe visual inspection will give a clue.
1110          * Selection of bootstrap image (vs. other images) is arbitrary. */
1111         image = (__le32 *)priv->ucode_boot.v_addr;
1112         len = priv->ucode_boot.len;
1113         ret = iwl_verify_inst_full(priv, image, len);
1114
1115         return ret;
1116 }
1117 EXPORT_SYMBOL(iwl_verify_ucode);
1118
1119
1120 static const char *desc_lookup(int i)
1121 {
1122         switch (i) {
1123         case 1:
1124                 return "FAIL";
1125         case 2:
1126                 return "BAD_PARAM";
1127         case 3:
1128                 return "BAD_CHECKSUM";
1129         case 4:
1130                 return "NMI_INTERRUPT";
1131         case 5:
1132                 return "SYSASSERT";
1133         case 6:
1134                 return "FATAL_ERROR";
1135         }
1136
1137         return "UNKNOWN";
1138 }
1139
1140 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1141 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1142
1143 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1144 {
1145         u32 data2, line;
1146         u32 desc, time, count, base, data1;
1147         u32 blink1, blink2, ilink1, ilink2;
1148         int ret;
1149
1150         if (priv->ucode_type == UCODE_INIT)
1151                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1152         else
1153                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1154
1155         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1156                 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1157                 return;
1158         }
1159
1160         ret = iwl_grab_nic_access(priv);
1161         if (ret) {
1162                 IWL_WARNING("Can not read from adapter at this time.\n");
1163                 return;
1164         }
1165
1166         count = iwl_read_targ_mem(priv, base);
1167
1168         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1169                 IWL_ERROR("Start IWL Error Log Dump:\n");
1170                 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1171         }
1172
1173         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1174         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1175         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1176         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1177         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1178         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1179         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1180         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1181         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1182
1183         IWL_ERROR("Desc        Time       "
1184                 "data1      data2      line\n");
1185         IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1186                 desc_lookup(desc), desc, time, data1, data2, line);
1187         IWL_ERROR("blink1  blink2  ilink1  ilink2\n");
1188         IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1189                 ilink1, ilink2);
1190
1191         iwl_release_nic_access(priv);
1192 }
1193 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1194
1195 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1196
1197 /**
1198  * iwl_print_event_log - Dump error event log to syslog
1199  *
1200  * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1201  */
1202 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1203                                 u32 num_events, u32 mode)
1204 {
1205         u32 i;
1206         u32 base;       /* SRAM byte address of event log header */
1207         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1208         u32 ptr;        /* SRAM byte address of log data */
1209         u32 ev, time, data; /* event log data */
1210
1211         if (num_events == 0)
1212                 return;
1213         if (priv->ucode_type == UCODE_INIT)
1214                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1215         else
1216                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1217
1218         if (mode == 0)
1219                 event_size = 2 * sizeof(u32);
1220         else
1221                 event_size = 3 * sizeof(u32);
1222
1223         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1224
1225         /* "time" is actually "data" for mode 0 (no timestamp).
1226         * place event id # at far right for easier visual parsing. */
1227         for (i = 0; i < num_events; i++) {
1228                 ev = iwl_read_targ_mem(priv, ptr);
1229                 ptr += sizeof(u32);
1230                 time = iwl_read_targ_mem(priv, ptr);
1231                 ptr += sizeof(u32);
1232                 if (mode == 0) {
1233                         /* data, ev */
1234                         IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1235                 } else {
1236                         data = iwl_read_targ_mem(priv, ptr);
1237                         ptr += sizeof(u32);
1238                         IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1239                                         time, data, ev);
1240                 }
1241         }
1242 }
1243 EXPORT_SYMBOL(iwl_print_event_log);
1244
1245
1246 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1247 {
1248         int ret;
1249         u32 base;       /* SRAM byte address of event log header */
1250         u32 capacity;   /* event log capacity in # entries */
1251         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
1252         u32 num_wraps;  /* # times uCode wrapped to top of log */
1253         u32 next_entry; /* index of next entry to be written by uCode */
1254         u32 size;       /* # entries that we'll print */
1255
1256         if (priv->ucode_type == UCODE_INIT)
1257                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1258         else
1259                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1260
1261         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1262                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1263                 return;
1264         }
1265
1266         ret = iwl_grab_nic_access(priv);
1267         if (ret) {
1268                 IWL_WARNING("Can not read from adapter at this time.\n");
1269                 return;
1270         }
1271
1272         /* event log header */
1273         capacity = iwl_read_targ_mem(priv, base);
1274         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1275         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1276         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1277
1278         size = num_wraps ? capacity : next_entry;
1279
1280         /* bail out if nothing in log */
1281         if (size == 0) {
1282                 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1283                 iwl_release_nic_access(priv);
1284                 return;
1285         }
1286
1287         IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1288                         size, num_wraps);
1289
1290         /* if uCode has wrapped back to top of log, start at the oldest entry,
1291          * i.e the next one that uCode would fill. */
1292         if (num_wraps)
1293                 iwl_print_event_log(priv, next_entry,
1294                                         capacity - next_entry, mode);
1295         /* (then/else) start at top of log */
1296         iwl_print_event_log(priv, 0, next_entry, mode);
1297
1298         iwl_release_nic_access(priv);
1299 }
1300 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1301
1302 void iwl_rf_kill_ct_config(struct iwl_priv *priv)
1303 {
1304         struct iwl_ct_kill_config cmd;
1305         unsigned long flags;
1306         int ret = 0;
1307
1308         spin_lock_irqsave(&priv->lock, flags);
1309         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1310                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1311         spin_unlock_irqrestore(&priv->lock, flags);
1312
1313         cmd.critical_temperature_R =
1314                 cpu_to_le32(priv->hw_params.ct_kill_threshold);
1315
1316         ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1317                                sizeof(cmd), &cmd);
1318         if (ret)
1319                 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1320         else
1321                 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded, "
1322                         "critical temperature is %d\n",
1323                         cmd.critical_temperature_R);
1324 }
1325 EXPORT_SYMBOL(iwl_rf_kill_ct_config);
1326
1327 /*
1328  * CARD_STATE_CMD
1329  *
1330  * Use: Sets the device's internal card state to enable, disable, or halt
1331  *
1332  * When in the 'enable' state the card operates as normal.
1333  * When in the 'disable' state, the card enters into a low power mode.
1334  * When in the 'halt' state, the card is shut down and must be fully
1335  * restarted to come back on.
1336  */
1337 static int iwl_send_card_state(struct iwl_priv *priv, u32 flags, u8 meta_flag)
1338 {
1339         struct iwl_host_cmd cmd = {
1340                 .id = REPLY_CARD_STATE_CMD,
1341                 .len = sizeof(u32),
1342                 .data = &flags,
1343                 .meta.flags = meta_flag,
1344         };
1345
1346         return iwl_send_cmd(priv, &cmd);
1347 }
1348
1349 void iwl_radio_kill_sw_disable_radio(struct iwl_priv *priv)
1350 {
1351         unsigned long flags;
1352
1353         if (test_bit(STATUS_RF_KILL_SW, &priv->status))
1354                 return;
1355
1356         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO OFF\n");
1357
1358         iwl_scan_cancel(priv);
1359         /* FIXME: This is a workaround for AP */
1360         if (priv->iw_mode != IEEE80211_IF_TYPE_AP) {
1361                 spin_lock_irqsave(&priv->lock, flags);
1362                 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
1363                             CSR_UCODE_SW_BIT_RFKILL);
1364                 spin_unlock_irqrestore(&priv->lock, flags);
1365                 /* call the host command only if no hw rf-kill set */
1366                 if (!test_bit(STATUS_RF_KILL_HW, &priv->status) &&
1367                     iwl_is_ready(priv))
1368                         iwl_send_card_state(priv,
1369                                 CARD_STATE_CMD_DISABLE, 0);
1370                 set_bit(STATUS_RF_KILL_SW, &priv->status);
1371                         /* make sure mac80211 stop sending Tx frame */
1372                 if (priv->mac80211_registered)
1373                         ieee80211_stop_queues(priv->hw);
1374         }
1375 }
1376 EXPORT_SYMBOL(iwl_radio_kill_sw_disable_radio);
1377
1378 int iwl_radio_kill_sw_enable_radio(struct iwl_priv *priv)
1379 {
1380         unsigned long flags;
1381
1382         if (!test_bit(STATUS_RF_KILL_SW, &priv->status))
1383                 return 0;
1384
1385         IWL_DEBUG_RF_KILL("Manual SW RF KILL set to: RADIO ON\n");
1386
1387         spin_lock_irqsave(&priv->lock, flags);
1388         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1389
1390         clear_bit(STATUS_RF_KILL_SW, &priv->status);
1391         spin_unlock_irqrestore(&priv->lock, flags);
1392
1393         /* wake up ucode */
1394         msleep(10);
1395
1396         spin_lock_irqsave(&priv->lock, flags);
1397         iwl_read32(priv, CSR_UCODE_DRV_GP1);
1398         if (!iwl_grab_nic_access(priv))
1399                 iwl_release_nic_access(priv);
1400         spin_unlock_irqrestore(&priv->lock, flags);
1401
1402         if (test_bit(STATUS_RF_KILL_HW, &priv->status)) {
1403                 IWL_DEBUG_RF_KILL("Can not turn radio back on - "
1404                                   "disabled by HW switch\n");
1405                 return 0;
1406         }
1407
1408         if (priv->is_open)
1409                 queue_work(priv->workqueue, &priv->restart);
1410         return 1;
1411 }
1412 EXPORT_SYMBOL(iwl_radio_kill_sw_enable_radio);