err.no Git - linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-core.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  * Tomas Winkler <tomas.winkler@intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *****************************************************************************/
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/version.h>
  32 #include <net/mac80211.h>
  33
  34 struct iwl_priv; /* FIXME: remove */
  35 #include "iwl-debug.h"
  36 #include "iwl-eeprom.h"
  37 #include "iwl-dev.h" /* FIXME: remove */
  38 #include "iwl-core.h"
  39 #include "iwl-io.h"
  40 #include "iwl-rfkill.h"
  41 #include "iwl-power.h"
  42
  43
  44 MODULE_DESCRIPTION("iwl core");
  45 MODULE_VERSION(IWLWIFI_VERSION);
  46 MODULE_AUTHOR(DRV_COPYRIGHT);
  47 MODULE_LICENSE("GPL");
  48
  49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np)    \
  50         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,      \
  51                                     IWL_RATE_SISO_##s##M_PLCP, \
  52                                     IWL_RATE_MIMO2_##s##M_PLCP,\
  53                                     IWL_RATE_MIMO3_##s##M_PLCP,\
  54                                     IWL_RATE_##r##M_IEEE,      \
  55                                     IWL_RATE_##ip##M_INDEX,    \
  56                                     IWL_RATE_##in##M_INDEX,    \
  57                                     IWL_RATE_##rp##M_INDEX,    \
  58                                     IWL_RATE_##rn##M_INDEX,    \
  59                                     IWL_RATE_##pp##M_INDEX,    \
  60                                     IWL_RATE_##np##M_INDEX }
  61
  62 /*
  63  * Parameter order:
  64  *   rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  65  *
  66  * If there isn't a valid next or previous rate then INV is used which
  67  * maps to IWL_RATE_INVALID
  68  *
  69  */
  70 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  71         IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  72         IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  73         IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  74         IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18),      /* 11mbps */
  75         IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  76         IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11),       /*  9mbps */
  77         IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  78         IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  79         IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  80         IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  81         IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  82         IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  83         IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  84         /* FIXME:RS:          ^^    should be INV (legacy) */
  85 };
  86 EXPORT_SYMBOL(iwl_rates);
  87
  88
  89 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  90 EXPORT_SYMBOL(iwl_bcast_addr);
  91
  92
  93 /* This function both allocates and initializes hw and priv. */
  94 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  95                 struct ieee80211_ops *hw_ops)
  96 {
  97         struct iwl_priv *priv;
  98
  99         /* mac80211 allocates memory for this device instance, including
 100          *   space for this driver's private structure */
 101         struct ieee80211_hw *hw =
 102                 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
 103         if (hw == NULL) {
 104                 IWL_ERROR("Can not allocate network device\n");
 105                 goto out;
 106         }
 107
 108         priv = hw->priv;
 109         priv->hw = hw;
 110
 111 out:
 112         return hw;
 113 }
 114 EXPORT_SYMBOL(iwl_alloc_all);
 115
 116 void iwl_hw_detect(struct iwl_priv *priv)
 117 {
 118         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
 119         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
 120         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
 121 }
 122 EXPORT_SYMBOL(iwl_hw_detect);
 123
 124 /* Tell nic where to find the "keep warm" buffer */
 125 int iwl_kw_init(struct iwl_priv *priv)
 126 {
 127         unsigned long flags;
 128         int ret;
 129
 130         spin_lock_irqsave(&priv->lock, flags);
 131         ret = iwl_grab_nic_access(priv);
 132         if (ret)
 133                 goto out;
 134
 135         iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
 136                              priv->kw.dma_addr >> 4);
 137         iwl_release_nic_access(priv);
 138 out:
 139         spin_unlock_irqrestore(&priv->lock, flags);
 140         return ret;
 141 }
 142
 143 int iwl_kw_alloc(struct iwl_priv *priv)
 144 {
 145         struct pci_dev *dev = priv->pci_dev;
 146         struct iwl_kw *kw = &priv->kw;
 147
 148         kw->size = IWL_KW_SIZE;
 149         kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
 150         if (!kw->v_addr)
 151                 return -ENOMEM;
 152
 153         return 0;
 154 }
 155
 156 /**
 157  * iwl_kw_free - Free the "keep warm" buffer
 158  */
 159 void iwl_kw_free(struct iwl_priv *priv)
 160 {
 161         struct pci_dev *dev = priv->pci_dev;
 162         struct iwl_kw *kw = &priv->kw;
 163
 164         if (kw->v_addr) {
 165                 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
 166                 memset(kw, 0, sizeof(*kw));
 167         }
 168 }
 169
 170 int iwl_hw_nic_init(struct iwl_priv *priv)
 171 {
 172         unsigned long flags;
 173         struct iwl_rx_queue *rxq = &priv->rxq;
 174         int ret;
 175
 176         /* nic_init */
 177         spin_lock_irqsave(&priv->lock, flags);
 178         priv->cfg->ops->lib->apm_ops.init(priv);
 179         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
 180         spin_unlock_irqrestore(&priv->lock, flags);
 181
 182         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
 183
 184         priv->cfg->ops->lib->apm_ops.config(priv);
 185
 186         /* Allocate the RX queue, or reset if it is already allocated */
 187         if (!rxq->bd) {
 188                 ret = iwl_rx_queue_alloc(priv);
 189                 if (ret) {
 190                         IWL_ERROR("Unable to initialize Rx queue\n");
 191                         return -ENOMEM;
 192                 }
 193         } else
 194                 iwl_rx_queue_reset(priv, rxq);
 195
 196         iwl_rx_replenish(priv);
 197
 198         iwl_rx_init(priv, rxq);
 199
 200         spin_lock_irqsave(&priv->lock, flags);
 201
 202         rxq->need_update = 1;
 203         iwl_rx_queue_update_write_ptr(priv, rxq);
 204
 205         spin_unlock_irqrestore(&priv->lock, flags);
 206
 207         /* Allocate and init all Tx and Command queues */
 208         ret = iwl_txq_ctx_reset(priv);
 209         if (ret)
 210                 return ret;
 211
 212         set_bit(STATUS_INIT, &priv->status);
 213
 214         return 0;
 215 }
 216 EXPORT_SYMBOL(iwl_hw_nic_init);
 217
 218 /**
 219  * iwlcore_clear_stations_table - Clear the driver's station table
 220  *
 221  * NOTE:  This does not clear or otherwise alter the device's station table.
 222  */
 223 void iwlcore_clear_stations_table(struct iwl_priv *priv)
 224 {
 225         unsigned long flags;
 226
 227         spin_lock_irqsave(&priv->sta_lock, flags);
 228
 229         priv->num_stations = 0;
 230         memset(priv->stations, 0, sizeof(priv->stations));
 231
 232         spin_unlock_irqrestore(&priv->sta_lock, flags);
 233 }
 234 EXPORT_SYMBOL(iwlcore_clear_stations_table);
 235
 236 void iwl_reset_qos(struct iwl_priv *priv)
 237 {
 238         u16 cw_min = 15;
 239         u16 cw_max = 1023;
 240         u8 aifs = 2;
 241         u8 is_legacy = 0;
 242         unsigned long flags;
 243         int i;
 244
 245         spin_lock_irqsave(&priv->lock, flags);
 246         priv->qos_data.qos_active = 0;
 247
 248         if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
 249                 if (priv->qos_data.qos_enable)
 250                         priv->qos_data.qos_active = 1;
 251                 if (!(priv->active_rate & 0xfff0)) {
 252                         cw_min = 31;
 253                         is_legacy = 1;
 254                 }
 255         } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
 256                 if (priv->qos_data.qos_enable)
 257                         priv->qos_data.qos_active = 1;
 258         } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
 259                 cw_min = 31;
 260                 is_legacy = 1;
 261         }
 262
 263         if (priv->qos_data.qos_active)
 264                 aifs = 3;
 265
 266         priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
 267         priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
 268         priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
 269         priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
 270         priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
 271
 272         if (priv->qos_data.qos_active) {
 273                 i = 1;
 274                 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
 275                 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
 276                 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
 277                 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 278                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 279
 280                 i = 2;
 281                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 282                         cpu_to_le16((cw_min + 1) / 2 - 1);
 283                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 284                         cpu_to_le16(cw_max);
 285                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 286                 if (is_legacy)
 287                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 288                                 cpu_to_le16(6016);
 289                 else
 290                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 291                                 cpu_to_le16(3008);
 292                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 293
 294                 i = 3;
 295                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 296                         cpu_to_le16((cw_min + 1) / 4 - 1);
 297                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 298                         cpu_to_le16((cw_max + 1) / 2 - 1);
 299                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 300                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 301                 if (is_legacy)
 302                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 303                                 cpu_to_le16(3264);
 304                 else
 305                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 306                                 cpu_to_le16(1504);
 307         } else {
 308                 for (i = 1; i < 4; i++) {
 309                         priv->qos_data.def_qos_parm.ac[i].cw_min =
 310                                 cpu_to_le16(cw_min);
 311                         priv->qos_data.def_qos_parm.ac[i].cw_max =
 312                                 cpu_to_le16(cw_max);
 313                         priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
 314                         priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 315                         priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 316                 }
 317         }
 318         IWL_DEBUG_QOS("set QoS to default \n");
 319
 320         spin_unlock_irqrestore(&priv->lock, flags);
 321 }
 322 EXPORT_SYMBOL(iwl_reset_qos);
 323
 324 #ifdef CONFIG_IWL4965_HT
 325 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
 326 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
 327 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
 328                               struct ieee80211_ht_info *ht_info,
 329                               enum ieee80211_band band)
 330 {
 331         u16 max_bit_rate = 0;
 332         u8 rx_chains_num = priv->hw_params.rx_chains_num;
 333         u8 tx_chains_num = priv->hw_params.tx_chains_num;
 334
 335         ht_info->cap = 0;
 336         memset(ht_info->supp_mcs_set, 0, 16);
 337
 338         ht_info->ht_supported = 1;
 339
 340         ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
 341         ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
 342         ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
 343                              (IWL_MIMO_PS_NONE << 2));
 344
 345         max_bit_rate = MAX_BIT_RATE_20_MHZ;
 346         if (priv->hw_params.fat_channel & BIT(band)) {
 347                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
 348                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
 349                 ht_info->supp_mcs_set[4] = 0x01;
 350                 max_bit_rate = MAX_BIT_RATE_40_MHZ;
 351         }
 352
 353         if (priv->cfg->mod_params->amsdu_size_8K)
 354                 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
 355
 356         ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
 357         ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
 358
 359         ht_info->supp_mcs_set[0] = 0xFF;
 360         if (rx_chains_num >= 2)
 361                 ht_info->supp_mcs_set[1] = 0xFF;
 362         if (rx_chains_num >= 3)
 363                 ht_info->supp_mcs_set[2] = 0xFF;
 364
 365         /* Highest supported Rx data rate */
 366         max_bit_rate *= rx_chains_num;
 367         ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
 368         ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
 369
 370         /* Tx MCS capabilities */
 371         ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
 372         if (tx_chains_num != rx_chains_num) {
 373                 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
 374                 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
 375         }
 376 }
 377 #else
 378 static inline void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
 379                               struct ieee80211_ht_info *ht_info,
 380                               enum ieee80211_band band)
 381 {
 382 }
 383 #endif /* CONFIG_IWL4965_HT */
 384
 385 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
 386                               struct ieee80211_rate *rates)
 387 {
 388         int i;
 389
 390         for (i = 0; i < IWL_RATE_COUNT; i++) {
 391                 rates[i].bitrate = iwl_rates[i].ieee * 5;
 392                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
 393                 rates[i].hw_value_short = i;
 394                 rates[i].flags = 0;
 395                 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
 396                         /*
 397                          * If CCK != 1M then set short preamble rate flag.
 398                          */
 399                         rates[i].flags |=
 400                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
 401                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
 402                 }
 403         }
 404 }
 405
 406 /**
 407  * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
 408  */
 409 static int iwlcore_init_geos(struct iwl_priv *priv)
 410 {
 411         struct iwl_channel_info *ch;
 412         struct ieee80211_supported_band *sband;
 413         struct ieee80211_channel *channels;
 414         struct ieee80211_channel *geo_ch;
 415         struct ieee80211_rate *rates;
 416         int i = 0;
 417
 418         if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
 419             priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
 420                 IWL_DEBUG_INFO("Geography modes already initialized.\n");
 421                 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 422                 return 0;
 423         }
 424
 425         channels = kzalloc(sizeof(struct ieee80211_channel) *
 426                            priv->channel_count, GFP_KERNEL);
 427         if (!channels)
 428                 return -ENOMEM;
 429
 430         rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
 431                         GFP_KERNEL);
 432         if (!rates) {
 433                 kfree(channels);
 434                 return -ENOMEM;
 435         }
 436
 437         /* 5.2GHz channels start after the 2.4GHz channels */
 438         sband = &priv->bands[IEEE80211_BAND_5GHZ];
 439         sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
 440         /* just OFDM */
 441         sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
 442         sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
 443
 444         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
 445
 446         sband = &priv->bands[IEEE80211_BAND_2GHZ];
 447         sband->channels = channels;
 448         /* OFDM & CCK */
 449         sband->bitrates = rates;
 450         sband->n_bitrates = IWL_RATE_COUNT;
 451
 452         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
 453
 454         priv->ieee_channels = channels;
 455         priv->ieee_rates = rates;
 456
 457         iwlcore_init_hw_rates(priv, rates);
 458
 459         for (i = 0;  i < priv->channel_count; i++) {
 460                 ch = &priv->channel_info[i];
 461
 462                 /* FIXME: might be removed if scan is OK */
 463                 if (!is_channel_valid(ch))
 464                         continue;
 465
 466                 if (is_channel_a_band(ch))
 467                         sband =  &priv->bands[IEEE80211_BAND_5GHZ];
 468                 else
 469                         sband =  &priv->bands[IEEE80211_BAND_2GHZ];
 470
 471                 geo_ch = &sband->channels[sband->n_channels++];
 472
 473                 geo_ch->center_freq =
 474                                 ieee80211_channel_to_frequency(ch->channel);
 475                 geo_ch->max_power = ch->max_power_avg;
 476                 geo_ch->max_antenna_gain = 0xff;
 477                 geo_ch->hw_value = ch->channel;
 478
 479                 if (is_channel_valid(ch)) {
 480                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
 481                                 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
 482
 483                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
 484                                 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 485
 486                         if (ch->flags & EEPROM_CHANNEL_RADAR)
 487                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
 488
 489                         if (ch->max_power_avg > priv->max_channel_txpower_limit)
 490                                 priv->max_channel_txpower_limit =
 491                                     ch->max_power_avg;
 492                 } else {
 493                         geo_ch->flags |= IEEE80211_CHAN_DISABLED;
 494                 }
 495
 496                 /* Save flags for reg domain usage */
 497                 geo_ch->orig_flags = geo_ch->flags;
 498
 499                 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0%X\n",
 500                                 ch->channel, geo_ch->center_freq,
 501                                 is_channel_a_band(ch) ?  "5.2" : "2.4",
 502                                 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
 503                                 "restricted" : "valid",
 504                                  geo_ch->flags);
 505         }
 506
 507         if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
 508              priv->cfg->sku & IWL_SKU_A) {
 509                 printk(KERN_INFO DRV_NAME
 510                        ": Incorrectly detected BG card as ABG.  Please send "
 511                        "your PCI ID 0x%04X:0x%04X to maintainer.\n",
 512                        priv->pci_dev->device, priv->pci_dev->subsystem_device);
 513                 priv->cfg->sku &= ~IWL_SKU_A;
 514         }
 515
 516         printk(KERN_INFO DRV_NAME
 517                ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
 518                priv->bands[IEEE80211_BAND_2GHZ].n_channels,
 519                priv->bands[IEEE80211_BAND_5GHZ].n_channels);
 520
 521
 522         set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 523
 524         return 0;
 525 }
 526
 527 /*
 528  * iwlcore_free_geos - undo allocations in iwlcore_init_geos
 529  */
 530 static void iwlcore_free_geos(struct iwl_priv *priv)
 531 {
 532         kfree(priv->ieee_channels);
 533         kfree(priv->ieee_rates);
 534         clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
 535 }
 536
 537 #ifdef CONFIG_IWL4965_HT
 538 static u8 is_single_rx_stream(struct iwl_priv *priv)
 539 {
 540         return !priv->current_ht_config.is_ht ||
 541                ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
 542                 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
 543                priv->ps_mode == IWL_MIMO_PS_STATIC;
 544 }
 545 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
 546                                    enum ieee80211_band band,
 547                                    u16 channel, u8 extension_chan_offset)
 548 {
 549         const struct iwl_channel_info *ch_info;
 550
 551         ch_info = iwl_get_channel_info(priv, band, channel);
 552         if (!is_channel_valid(ch_info))
 553                 return 0;
 554
 555         if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
 556                 return 0;
 557
 558         if ((ch_info->fat_extension_channel == extension_chan_offset) ||
 559             (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
 560                 return 1;
 561
 562         return 0;
 563 }
 564
 565 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
 566                              struct ieee80211_ht_info *sta_ht_inf)
 567 {
 568         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
 569
 570         if ((!iwl_ht_conf->is_ht) ||
 571            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
 572            (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
 573                 return 0;
 574
 575         if (sta_ht_inf) {
 576                 if ((!sta_ht_inf->ht_supported) ||
 577                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
 578                         return 0;
 579         }
 580
 581         return iwl_is_channel_extension(priv, priv->band,
 582                                          iwl_ht_conf->control_channel,
 583                                          iwl_ht_conf->extension_chan_offset);
 584 }
 585 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
 586
 587 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
 588 {
 589         struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
 590         u32 val;
 591
 592         if (!ht_info->is_ht)
 593                 return;
 594
 595         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
 596         if (iwl_is_fat_tx_allowed(priv, NULL))
 597                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 598         else
 599                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
 600                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
 601
 602         if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
 603                 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
 604                                 le16_to_cpu(rxon->channel),
 605                                 ht_info->control_channel);
 606                 rxon->channel = cpu_to_le16(ht_info->control_channel);
 607                 return;
 608         }
 609
 610         /* Note: control channel is opposite of extension channel */
 611         switch (ht_info->extension_chan_offset) {
 612         case IWL_EXT_CHANNEL_OFFSET_ABOVE:
 613                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
 614                 break;
 615         case IWL_EXT_CHANNEL_OFFSET_BELOW:
 616                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
 617                 break;
 618         case IWL_EXT_CHANNEL_OFFSET_NONE:
 619         default:
 620                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 621                 break;
 622         }
 623
 624         val = ht_info->ht_protection;
 625
 626         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
 627
 628         iwl_set_rxon_chain(priv);
 629
 630         IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
 631                         "rxon flags 0x%X operation mode :0x%X "
 632                         "extension channel offset 0x%x "
 633                         "control chan %d\n",
 634                         ht_info->supp_mcs_set[0],
 635                         ht_info->supp_mcs_set[1],
 636                         ht_info->supp_mcs_set[2],
 637                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
 638                         ht_info->extension_chan_offset,
 639                         ht_info->control_channel);
 640         return;
 641 }
 642 EXPORT_SYMBOL(iwl_set_rxon_ht);
 643
 644 #else
 645 static inline u8 is_single_rx_stream(struct iwl_priv *priv)
 646 {
 647         return 1;
 648 }
 649 #endif  /*CONFIG_IWL4965_HT */
 650
 651 /*
 652  * Determine how many receiver/antenna chains to use.
 653  * More provides better reception via diversity.  Fewer saves power.
 654  * MIMO (dual stream) requires at least 2, but works better with 3.
 655  * This does not determine *which* chains to use, just how many.
 656  */
 657 static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
 658                                         u8 *idle_state, u8 *rx_state)
 659 {
 660         u8 is_single = is_single_rx_stream(priv);
 661         u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
 662
 663         /* # of Rx chains to use when expecting MIMO. */
 664         if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
 665                 *rx_state = 2;
 666         else
 667                 *rx_state = 3;
 668
 669         /* # Rx chains when idling and maybe trying to save power */
 670         switch (priv->ps_mode) {
 671         case IWL_MIMO_PS_STATIC:
 672         case IWL_MIMO_PS_DYNAMIC:
 673                 *idle_state = (is_cam) ? 2 : 1;
 674                 break;
 675         case IWL_MIMO_PS_NONE:
 676                 *idle_state = (is_cam) ? *rx_state : 1;
 677                 break;
 678         default:
 679                 *idle_state = 1;
 680                 break;
 681         }
 682
 683         return 0;
 684 }
 685
 686 /**
 687  * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
 688  *
 689  * Selects how many and which Rx receivers/antennas/chains to use.
 690  * This should not be used for scan command ... it puts data in wrong place.
 691  */
 692 void iwl_set_rxon_chain(struct iwl_priv *priv)
 693 {
 694         u8 is_single = is_single_rx_stream(priv);
 695         u8 idle_state, rx_state;
 696
 697         priv->staging_rxon.rx_chain = 0;
 698         rx_state = idle_state = 3;
 699
 700         /* Tell uCode which antennas are actually connected.
 701          * Before first association, we assume all antennas are connected.
 702          * Just after first association, iwl_chain_noise_calibration()
 703          *    checks which antennas actually *are* connected. */
 704         priv->staging_rxon.rx_chain |=
 705                     cpu_to_le16(priv->hw_params.valid_rx_ant <<
 706                                                  RXON_RX_CHAIN_VALID_POS);
 707
 708         /* How many receivers should we use? */
 709         iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
 710         priv->staging_rxon.rx_chain |=
 711                 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
 712         priv->staging_rxon.rx_chain |=
 713                 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
 714
 715         if (!is_single && (rx_state >= 2) &&
 716             !test_bit(STATUS_POWER_PMI, &priv->status))
 717                 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
 718         else
 719                 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
 720
 721         IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
 722 }
 723 EXPORT_SYMBOL(iwl_set_rxon_chain);
 724
 725 /**
 726  * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
 727  * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
 728  * @channel: Any channel valid for the requested phymode
 729
 730  * In addition to setting the staging RXON, priv->phymode is also set.
 731  *
 732  * NOTE:  Does not commit to the hardware; it sets appropriate bit fields
 733  * in the staging RXON flag structure based on the phymode
 734  */
 735 int iwl_set_rxon_channel(struct iwl_priv *priv,
 736                                 enum ieee80211_band band,
 737                                 u16 channel)
 738 {
 739         if (!iwl_get_channel_info(priv, band, channel)) {
 740                 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
 741                                channel, band);
 742                 return -EINVAL;
 743         }
 744
 745         if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
 746             (priv->band == band))
 747                 return 0;
 748
 749         priv->staging_rxon.channel = cpu_to_le16(channel);
 750         if (band == IEEE80211_BAND_5GHZ)
 751                 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
 752         else
 753                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
 754
 755         priv->band = band;
 756
 757         IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
 758
 759         return 0;
 760 }
 761 EXPORT_SYMBOL(iwl_set_rxon_channel);
 762
 763 int iwl_setup_mac(struct iwl_priv *priv)
 764 {
 765         int ret;
 766         struct ieee80211_hw *hw = priv->hw;
 767         hw->rate_control_algorithm = "iwl-4965-rs";
 768
 769         /* Tell mac80211 our characteristics */
 770         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
 771                     IEEE80211_HW_SIGNAL_DBM |
 772                     IEEE80211_HW_NOISE_DBM;
 773         /* Default value; 4 EDCA QOS priorities */
 774         hw->queues = 4;
 775 #ifdef CONFIG_IWL4965_HT
 776         /* Enhanced value; more queues, to support 11n aggregation */
 777         hw->ampdu_queues = 12;
 778 #endif /* CONFIG_IWL4965_HT */
 779
 780         hw->conf.beacon_int = 100;
 781
 782         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
 783                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 784                         &priv->bands[IEEE80211_BAND_2GHZ];
 785         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
 786                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 787                         &priv->bands[IEEE80211_BAND_5GHZ];
 788
 789         ret = ieee80211_register_hw(priv->hw);
 790         if (ret) {
 791                 IWL_ERROR("Failed to register hw (error %d)\n", ret);
 792                 return ret;
 793         }
 794         priv->mac80211_registered = 1;
 795
 796         return 0;
 797 }
 798 EXPORT_SYMBOL(iwl_setup_mac);
 799
 800
 801 int iwl_init_drv(struct iwl_priv *priv)
 802 {
 803         int ret;
 804         int i;
 805
 806         priv->retry_rate = 1;
 807         priv->ibss_beacon = NULL;
 808
 809         spin_lock_init(&priv->lock);
 810         spin_lock_init(&priv->power_data.lock);
 811         spin_lock_init(&priv->sta_lock);
 812         spin_lock_init(&priv->hcmd_lock);
 813         spin_lock_init(&priv->lq_mngr.lock);
 814
 815         for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
 816                 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
 817
 818         INIT_LIST_HEAD(&priv->free_frames);
 819
 820         mutex_init(&priv->mutex);
 821
 822         /* Clear the driver's (not device's) station table */
 823         iwlcore_clear_stations_table(priv);
 824
 825         priv->data_retry_limit = -1;
 826         priv->ieee_channels = NULL;
 827         priv->ieee_rates = NULL;
 828         priv->band = IEEE80211_BAND_2GHZ;
 829
 830         priv->iw_mode = IEEE80211_IF_TYPE_STA;
 831
 832         priv->use_ant_b_for_management_frame = 1; /* start with ant B */
 833         priv->ps_mode = IWL_MIMO_PS_NONE;
 834
 835         /* Choose which receivers/antennas to use */
 836         iwl_set_rxon_chain(priv);
 837
 838         if (priv->cfg->mod_params->enable_qos)
 839                 priv->qos_data.qos_enable = 1;
 840
 841         iwl_reset_qos(priv);
 842
 843         priv->qos_data.qos_active = 0;
 844         priv->qos_data.qos_cap.val = 0;
 845
 846         iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
 847
 848         priv->rates_mask = IWL_RATES_MASK;
 849         /* If power management is turned on, default to AC mode */
 850         priv->power_mode = IWL_POWER_AC;
 851         priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
 852
 853         ret = iwl_init_channel_map(priv);
 854         if (ret) {
 855                 IWL_ERROR("initializing regulatory failed: %d\n", ret);
 856                 goto err;
 857         }
 858
 859         ret = iwlcore_init_geos(priv);
 860         if (ret) {
 861                 IWL_ERROR("initializing geos failed: %d\n", ret);
 862                 goto err_free_channel_map;
 863         }
 864
 865         return 0;
 866
 867 err_free_channel_map:
 868         iwl_free_channel_map(priv);
 869 err:
 870         return ret;
 871 }
 872 EXPORT_SYMBOL(iwl_init_drv);
 873
 874
 875 void iwl_uninit_drv(struct iwl_priv *priv)
 876 {
 877         iwlcore_free_geos(priv);
 878         iwl_free_channel_map(priv);
 879 }
 880 EXPORT_SYMBOL(iwl_uninit_drv);
 881
 882 /* Low level driver call this function to update iwlcore with
 883  * driver status.
 884  */
 885 int iwlcore_low_level_notify(struct iwl_priv *priv,
 886                               enum iwlcore_card_notify notify)
 887 {
 888         int ret;
 889         switch (notify) {
 890         case IWLCORE_INIT_EVT:
 891                 ret = iwl_rfkill_init(priv);
 892                 if (ret)
 893                         IWL_ERROR("Unable to initialize RFKILL system. "
 894                                   "Ignoring error: %d\n", ret);
 895                 iwl_power_initialize(priv);
 896                 break;
 897         case IWLCORE_START_EVT:
 898                 iwl_power_update_mode(priv, 1);
 899                 break;
 900         case IWLCORE_STOP_EVT:
 901                 break;
 902         case IWLCORE_REMOVE_EVT:
 903                 iwl_rfkill_unregister(priv);
 904                 break;
 905         }
 906
 907         return 0;
 908 }
 909 EXPORT_SYMBOL(iwlcore_low_level_notify);
 910
 911 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
 912 {
 913         u32 stat_flags = 0;
 914         struct iwl_host_cmd cmd = {
 915                 .id = REPLY_STATISTICS_CMD,
 916                 .meta.flags = flags,
 917                 .len = sizeof(stat_flags),
 918                 .data = (u8 *) &stat_flags,
 919         };
 920         return iwl_send_cmd(priv, &cmd);
 921 }
 922 EXPORT_SYMBOL(iwl_send_statistics_request);
 923
 924 /**
 925  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 926  *   using sample data 100 bytes apart.  If these sample points are good,
 927  *   it's a pretty good bet that everything between them is good, too.
 928  */
 929 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
 930 {
 931         u32 val;
 932         int ret = 0;
 933         u32 errcnt = 0;
 934         u32 i;
 935
 936         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
 937
 938         ret = iwl_grab_nic_access(priv);
 939         if (ret)
 940                 return ret;
 941
 942         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
 943                 /* read data comes through single port, auto-incr addr */
 944                 /* NOTE: Use the debugless read so we don't flood kernel log
 945                  * if IWL_DL_IO is set */
 946                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
 947                         i + RTC_INST_LOWER_BOUND);
 948                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 949                 if (val != le32_to_cpu(*image)) {
 950                         ret = -EIO;
 951                         errcnt++;
 952                         if (errcnt >= 3)
 953                                 break;
 954                 }
 955         }
 956
 957         iwl_release_nic_access(priv);
 958
 959         return ret;
 960 }
 961
 962 /**
 963  * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
 964  *     looking at all data.
 965  */
 966 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
 967                                  u32 len)
 968 {
 969         u32 val;
 970         u32 save_len = len;
 971         int ret = 0;
 972         u32 errcnt;
 973
 974         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
 975
 976         ret = iwl_grab_nic_access(priv);
 977         if (ret)
 978                 return ret;
 979
 980         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
 981
 982         errcnt = 0;
 983         for (; len > 0; len -= sizeof(u32), image++) {
 984                 /* read data comes through single port, auto-incr addr */
 985                 /* NOTE: Use the debugless read so we don't flood kernel log
 986                  * if IWL_DL_IO is set */
 987                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 988                 if (val != le32_to_cpu(*image)) {
 989                         IWL_ERROR("uCode INST section is invalid at "
 990                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
 991                                   save_len - len, val, le32_to_cpu(*image));
 992                         ret = -EIO;
 993                         errcnt++;
 994                         if (errcnt >= 20)
 995                                 break;
 996                 }
 997         }
 998
 999         iwl_release_nic_access(priv);
1000
1001         if (!errcnt)
1002                 IWL_DEBUG_INFO
1003                     ("ucode image in INSTRUCTION memory is good\n");
1004
1005         return ret;
1006 }
1007
1008 /**
1009  * iwl_verify_ucode - determine which instruction image is in SRAM,
1010  *    and verify its contents
1011  */
1012 int iwl_verify_ucode(struct iwl_priv *priv)
1013 {
1014         __le32 *image;
1015         u32 len;
1016         int ret;
1017
1018         /* Try bootstrap */
1019         image = (__le32 *)priv->ucode_boot.v_addr;
1020         len = priv->ucode_boot.len;
1021         ret = iwlcore_verify_inst_sparse(priv, image, len);
1022         if (!ret) {
1023                 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1024                 return 0;
1025         }
1026
1027         /* Try initialize */
1028         image = (__le32 *)priv->ucode_init.v_addr;
1029         len = priv->ucode_init.len;
1030         ret = iwlcore_verify_inst_sparse(priv, image, len);
1031         if (!ret) {
1032                 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1033                 return 0;
1034         }
1035
1036         /* Try runtime/protocol */
1037         image = (__le32 *)priv->ucode_code.v_addr;
1038         len = priv->ucode_code.len;
1039         ret = iwlcore_verify_inst_sparse(priv, image, len);
1040         if (!ret) {
1041                 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1042                 return 0;
1043         }
1044
1045         IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1046
1047         /* Since nothing seems to match, show first several data entries in
1048          * instruction SRAM, so maybe visual inspection will give a clue.
1049          * Selection of bootstrap image (vs. other images) is arbitrary. */
1050         image = (__le32 *)priv->ucode_boot.v_addr;
1051         len = priv->ucode_boot.len;
1052         ret = iwl_verify_inst_full(priv, image, len);
1053
1054         return ret;
1055 }
1056 EXPORT_SYMBOL(iwl_verify_ucode);
1057
1058
1059 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1060
1061 /**
1062  * iwl_print_event_log - Dump error event log to syslog
1063  *
1064  * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1065  */
1066 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1067                                 u32 num_events, u32 mode)
1068 {
1069         u32 i;
1070         u32 base;       /* SRAM byte address of event log header */
1071         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1072         u32 ptr;        /* SRAM byte address of log data */
1073         u32 ev, time, data; /* event log data */
1074
1075         if (num_events == 0)
1076                 return;
1077
1078         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1079
1080         if (mode == 0)
1081                 event_size = 2 * sizeof(u32);
1082         else
1083                 event_size = 3 * sizeof(u32);
1084
1085         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1086
1087         /* "time" is actually "data" for mode 0 (no timestamp).
1088         * place event id # at far right for easier visual parsing. */
1089         for (i = 0; i < num_events; i++) {
1090                 ev = iwl_read_targ_mem(priv, ptr);
1091                 ptr += sizeof(u32);
1092                 time = iwl_read_targ_mem(priv, ptr);
1093                 ptr += sizeof(u32);
1094                 if (mode == 0)
1095                         IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
1096                 else {
1097                         data = iwl_read_targ_mem(priv, ptr);
1098                         ptr += sizeof(u32);
1099                         IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
1100                 }
1101         }
1102 }
1103 EXPORT_SYMBOL(iwl_print_event_log);
1104
1105
1106 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1107 {
1108         int rc;
1109         u32 base;       /* SRAM byte address of event log header */
1110         u32 capacity;   /* event log capacity in # entries */
1111         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
1112         u32 num_wraps;  /* # times uCode wrapped to top of log */
1113         u32 next_entry; /* index of next entry to be written by uCode */
1114         u32 size;       /* # entries that we'll print */
1115
1116         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1117         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1118                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1119                 return;
1120         }
1121
1122         rc = iwl_grab_nic_access(priv);
1123         if (rc) {
1124                 IWL_WARNING("Can not read from adapter at this time.\n");
1125                 return;
1126         }
1127
1128         /* event log header */
1129         capacity = iwl_read_targ_mem(priv, base);
1130         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1131         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1132         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1133
1134         size = num_wraps ? capacity : next_entry;
1135
1136         /* bail out if nothing in log */
1137         if (size == 0) {
1138                 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1139                 iwl_release_nic_access(priv);
1140                 return;
1141         }
1142
1143         IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1144                         size, num_wraps);
1145
1146         /* if uCode has wrapped back to top of log, start at the oldest entry,
1147          * i.e the next one that uCode would fill. */
1148         if (num_wraps)
1149                 iwl_print_event_log(priv, next_entry,
1150                                         capacity - next_entry, mode);
1151         /* (then/else) start at top of log */
1152         iwl_print_event_log(priv, 0, next_entry, mode);
1153
1154         iwl_release_nic_access(priv);
1155 }
1156 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1157
1158