1 /******************************************************************************
5 * Copyright(c) 2008 Intel Corporation. All rights reserved.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
24 * Contact Information:
25 * Tomas Winkler <tomas.winkler@intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *****************************************************************************/
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/version.h>
32 #include <net/mac80211.h>
34 struct iwl_priv; /* FIXME: remove */
35 #include "iwl-debug.h"
36 #include "iwl-eeprom.h"
37 #include "iwl-dev.h" /* FIXME: remove */
40 #include "iwl-rfkill.h"
41 #include "iwl-power.h"
44 MODULE_DESCRIPTION("iwl core");
45 MODULE_VERSION(IWLWIFI_VERSION);
46 MODULE_AUTHOR(DRV_COPYRIGHT);
47 MODULE_LICENSE("GPL");
49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
50 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
51 IWL_RATE_SISO_##s##M_PLCP, \
52 IWL_RATE_MIMO2_##s##M_PLCP,\
53 IWL_RATE_MIMO3_##s##M_PLCP,\
54 IWL_RATE_##r##M_IEEE, \
55 IWL_RATE_##ip##M_INDEX, \
56 IWL_RATE_##in##M_INDEX, \
57 IWL_RATE_##rp##M_INDEX, \
58 IWL_RATE_##rn##M_INDEX, \
59 IWL_RATE_##pp##M_INDEX, \
60 IWL_RATE_##np##M_INDEX }
64 * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
66 * If there isn't a valid next or previous rate then INV is used which
67 * maps to IWL_RATE_INVALID
70 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
71 IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
72 IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
73 IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
74 IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
75 IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
76 IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
77 IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
78 IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
79 IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
80 IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
81 IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
82 IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
83 IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
84 /* FIXME:RS: ^^ should be INV (legacy) */
86 EXPORT_SYMBOL(iwl_rates);
89 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
90 EXPORT_SYMBOL(iwl_bcast_addr);
93 /* This function both allocates and initializes hw and priv. */
94 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
95 struct ieee80211_ops *hw_ops)
97 struct iwl_priv *priv;
99 /* mac80211 allocates memory for this device instance, including
100 * space for this driver's private structure */
101 struct ieee80211_hw *hw =
102 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
104 IWL_ERROR("Can not allocate network device\n");
114 EXPORT_SYMBOL(iwl_alloc_all);
116 void iwl_hw_detect(struct iwl_priv *priv)
118 priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
119 priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
120 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
122 EXPORT_SYMBOL(iwl_hw_detect);
124 /* Tell nic where to find the "keep warm" buffer */
125 int iwl_kw_init(struct iwl_priv *priv)
130 spin_lock_irqsave(&priv->lock, flags);
131 ret = iwl_grab_nic_access(priv);
135 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
136 priv->kw.dma_addr >> 4);
137 iwl_release_nic_access(priv);
139 spin_unlock_irqrestore(&priv->lock, flags);
143 int iwl_kw_alloc(struct iwl_priv *priv)
145 struct pci_dev *dev = priv->pci_dev;
146 struct iwl_kw *kw = &priv->kw;
148 kw->size = IWL_KW_SIZE;
149 kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
157 * iwl_kw_free - Free the "keep warm" buffer
159 void iwl_kw_free(struct iwl_priv *priv)
161 struct pci_dev *dev = priv->pci_dev;
162 struct iwl_kw *kw = &priv->kw;
165 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
166 memset(kw, 0, sizeof(*kw));
170 int iwl_hw_nic_init(struct iwl_priv *priv)
173 struct iwl_rx_queue *rxq = &priv->rxq;
177 spin_lock_irqsave(&priv->lock, flags);
178 priv->cfg->ops->lib->apm_ops.init(priv);
179 iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
180 spin_unlock_irqrestore(&priv->lock, flags);
182 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
184 priv->cfg->ops->lib->apm_ops.config(priv);
186 /* Allocate the RX queue, or reset if it is already allocated */
188 ret = iwl_rx_queue_alloc(priv);
190 IWL_ERROR("Unable to initialize Rx queue\n");
194 iwl_rx_queue_reset(priv, rxq);
196 iwl_rx_replenish(priv);
198 iwl_rx_init(priv, rxq);
200 spin_lock_irqsave(&priv->lock, flags);
202 rxq->need_update = 1;
203 iwl_rx_queue_update_write_ptr(priv, rxq);
205 spin_unlock_irqrestore(&priv->lock, flags);
207 /* Allocate and init all Tx and Command queues */
208 ret = iwl_txq_ctx_reset(priv);
212 set_bit(STATUS_INIT, &priv->status);
216 EXPORT_SYMBOL(iwl_hw_nic_init);
219 * iwlcore_clear_stations_table - Clear the driver's station table
221 * NOTE: This does not clear or otherwise alter the device's station table.
223 void iwlcore_clear_stations_table(struct iwl_priv *priv)
227 spin_lock_irqsave(&priv->sta_lock, flags);
229 priv->num_stations = 0;
230 memset(priv->stations, 0, sizeof(priv->stations));
232 spin_unlock_irqrestore(&priv->sta_lock, flags);
234 EXPORT_SYMBOL(iwlcore_clear_stations_table);
236 void iwl_reset_qos(struct iwl_priv *priv)
245 spin_lock_irqsave(&priv->lock, flags);
246 priv->qos_data.qos_active = 0;
248 if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
249 if (priv->qos_data.qos_enable)
250 priv->qos_data.qos_active = 1;
251 if (!(priv->active_rate & 0xfff0)) {
255 } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
256 if (priv->qos_data.qos_enable)
257 priv->qos_data.qos_active = 1;
258 } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
263 if (priv->qos_data.qos_active)
266 priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
267 priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
268 priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
269 priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
270 priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
272 if (priv->qos_data.qos_active) {
274 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
275 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
276 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
277 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
278 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
281 priv->qos_data.def_qos_parm.ac[i].cw_min =
282 cpu_to_le16((cw_min + 1) / 2 - 1);
283 priv->qos_data.def_qos_parm.ac[i].cw_max =
285 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
287 priv->qos_data.def_qos_parm.ac[i].edca_txop =
290 priv->qos_data.def_qos_parm.ac[i].edca_txop =
292 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
295 priv->qos_data.def_qos_parm.ac[i].cw_min =
296 cpu_to_le16((cw_min + 1) / 4 - 1);
297 priv->qos_data.def_qos_parm.ac[i].cw_max =
298 cpu_to_le16((cw_max + 1) / 2 - 1);
299 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
300 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
302 priv->qos_data.def_qos_parm.ac[i].edca_txop =
305 priv->qos_data.def_qos_parm.ac[i].edca_txop =
308 for (i = 1; i < 4; i++) {
309 priv->qos_data.def_qos_parm.ac[i].cw_min =
311 priv->qos_data.def_qos_parm.ac[i].cw_max =
313 priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
314 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
315 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
318 IWL_DEBUG_QOS("set QoS to default \n");
320 spin_unlock_irqrestore(&priv->lock, flags);
322 EXPORT_SYMBOL(iwl_reset_qos);
324 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
325 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
326 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
327 struct ieee80211_ht_info *ht_info,
328 enum ieee80211_band band)
330 u16 max_bit_rate = 0;
331 u8 rx_chains_num = priv->hw_params.rx_chains_num;
332 u8 tx_chains_num = priv->hw_params.tx_chains_num;
335 memset(ht_info->supp_mcs_set, 0, 16);
337 ht_info->ht_supported = 1;
339 ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
340 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
341 ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
342 (IWL_MIMO_PS_NONE << 2));
344 max_bit_rate = MAX_BIT_RATE_20_MHZ;
345 if (priv->hw_params.fat_channel & BIT(band)) {
346 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
347 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
348 ht_info->supp_mcs_set[4] = 0x01;
349 max_bit_rate = MAX_BIT_RATE_40_MHZ;
352 if (priv->cfg->mod_params->amsdu_size_8K)
353 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
355 ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
356 ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
358 ht_info->supp_mcs_set[0] = 0xFF;
359 if (rx_chains_num >= 2)
360 ht_info->supp_mcs_set[1] = 0xFF;
361 if (rx_chains_num >= 3)
362 ht_info->supp_mcs_set[2] = 0xFF;
364 /* Highest supported Rx data rate */
365 max_bit_rate *= rx_chains_num;
366 ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
367 ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
369 /* Tx MCS capabilities */
370 ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
371 if (tx_chains_num != rx_chains_num) {
372 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
373 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
377 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
378 struct ieee80211_rate *rates)
382 for (i = 0; i < IWL_RATE_COUNT; i++) {
383 rates[i].bitrate = iwl_rates[i].ieee * 5;
384 rates[i].hw_value = i; /* Rate scaling will work on indexes */
385 rates[i].hw_value_short = i;
387 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
389 * If CCK != 1M then set short preamble rate flag.
392 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
393 0 : IEEE80211_RATE_SHORT_PREAMBLE;
399 * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
401 static int iwlcore_init_geos(struct iwl_priv *priv)
403 struct iwl_channel_info *ch;
404 struct ieee80211_supported_band *sband;
405 struct ieee80211_channel *channels;
406 struct ieee80211_channel *geo_ch;
407 struct ieee80211_rate *rates;
410 if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
411 priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
412 IWL_DEBUG_INFO("Geography modes already initialized.\n");
413 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
417 channels = kzalloc(sizeof(struct ieee80211_channel) *
418 priv->channel_count, GFP_KERNEL);
422 rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
429 /* 5.2GHz channels start after the 2.4GHz channels */
430 sband = &priv->bands[IEEE80211_BAND_5GHZ];
431 sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
433 sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
434 sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
436 iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
438 sband = &priv->bands[IEEE80211_BAND_2GHZ];
439 sband->channels = channels;
441 sband->bitrates = rates;
442 sband->n_bitrates = IWL_RATE_COUNT;
444 iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
446 priv->ieee_channels = channels;
447 priv->ieee_rates = rates;
449 iwlcore_init_hw_rates(priv, rates);
451 for (i = 0; i < priv->channel_count; i++) {
452 ch = &priv->channel_info[i];
454 /* FIXME: might be removed if scan is OK */
455 if (!is_channel_valid(ch))
458 if (is_channel_a_band(ch))
459 sband = &priv->bands[IEEE80211_BAND_5GHZ];
461 sband = &priv->bands[IEEE80211_BAND_2GHZ];
463 geo_ch = &sband->channels[sband->n_channels++];
465 geo_ch->center_freq =
466 ieee80211_channel_to_frequency(ch->channel);
467 geo_ch->max_power = ch->max_power_avg;
468 geo_ch->max_antenna_gain = 0xff;
469 geo_ch->hw_value = ch->channel;
471 if (is_channel_valid(ch)) {
472 if (!(ch->flags & EEPROM_CHANNEL_IBSS))
473 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
475 if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
476 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
478 if (ch->flags & EEPROM_CHANNEL_RADAR)
479 geo_ch->flags |= IEEE80211_CHAN_RADAR;
481 geo_ch->flags |= ch->fat_extension_channel;
483 if (ch->max_power_avg > priv->max_channel_txpower_limit)
484 priv->max_channel_txpower_limit =
487 geo_ch->flags |= IEEE80211_CHAN_DISABLED;
490 /* Save flags for reg domain usage */
491 geo_ch->orig_flags = geo_ch->flags;
493 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
494 ch->channel, geo_ch->center_freq,
495 is_channel_a_band(ch) ? "5.2" : "2.4",
496 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
497 "restricted" : "valid",
501 if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
502 priv->cfg->sku & IWL_SKU_A) {
503 printk(KERN_INFO DRV_NAME
504 ": Incorrectly detected BG card as ABG. Please send "
505 "your PCI ID 0x%04X:0x%04X to maintainer.\n",
506 priv->pci_dev->device, priv->pci_dev->subsystem_device);
507 priv->cfg->sku &= ~IWL_SKU_A;
510 printk(KERN_INFO DRV_NAME
511 ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
512 priv->bands[IEEE80211_BAND_2GHZ].n_channels,
513 priv->bands[IEEE80211_BAND_5GHZ].n_channels);
516 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
522 * iwlcore_free_geos - undo allocations in iwlcore_init_geos
524 static void iwlcore_free_geos(struct iwl_priv *priv)
526 kfree(priv->ieee_channels);
527 kfree(priv->ieee_rates);
528 clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
531 static u8 is_single_rx_stream(struct iwl_priv *priv)
533 return !priv->current_ht_config.is_ht ||
534 ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
535 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
536 priv->ps_mode == IWL_MIMO_PS_STATIC;
539 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
540 enum ieee80211_band band,
541 u16 channel, u8 extension_chan_offset)
543 const struct iwl_channel_info *ch_info;
545 ch_info = iwl_get_channel_info(priv, band, channel);
546 if (!is_channel_valid(ch_info))
549 if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
550 return !(ch_info->fat_extension_channel &
551 IEEE80211_CHAN_NO_FAT_ABOVE);
552 else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
553 return !(ch_info->fat_extension_channel &
554 IEEE80211_CHAN_NO_FAT_BELOW);
559 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
560 struct ieee80211_ht_info *sta_ht_inf)
562 struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
564 if ((!iwl_ht_conf->is_ht) ||
565 (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
566 (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
570 if ((!sta_ht_inf->ht_supported) ||
571 (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
575 return iwl_is_channel_extension(priv, priv->band,
576 iwl_ht_conf->control_channel,
577 iwl_ht_conf->extension_chan_offset);
579 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
581 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
583 struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
589 /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
590 if (iwl_is_fat_tx_allowed(priv, NULL))
591 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
593 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
594 RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
596 if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
597 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
598 le16_to_cpu(rxon->channel),
599 ht_info->control_channel);
600 rxon->channel = cpu_to_le16(ht_info->control_channel);
604 /* Note: control channel is opposite of extension channel */
605 switch (ht_info->extension_chan_offset) {
606 case IEEE80211_HT_IE_CHA_SEC_ABOVE:
607 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
609 case IEEE80211_HT_IE_CHA_SEC_BELOW:
610 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
612 case IEEE80211_HT_IE_CHA_SEC_NONE:
614 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
618 val = ht_info->ht_protection;
620 rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
622 iwl_set_rxon_chain(priv);
624 IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
625 "rxon flags 0x%X operation mode :0x%X "
626 "extension channel offset 0x%x "
628 ht_info->supp_mcs_set[0],
629 ht_info->supp_mcs_set[1],
630 ht_info->supp_mcs_set[2],
631 le32_to_cpu(rxon->flags), ht_info->ht_protection,
632 ht_info->extension_chan_offset,
633 ht_info->control_channel);
636 EXPORT_SYMBOL(iwl_set_rxon_ht);
639 * Determine how many receiver/antenna chains to use.
640 * More provides better reception via diversity. Fewer saves power.
641 * MIMO (dual stream) requires at least 2, but works better with 3.
642 * This does not determine *which* chains to use, just how many.
644 static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
645 u8 *idle_state, u8 *rx_state)
647 u8 is_single = is_single_rx_stream(priv);
648 u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
650 /* # of Rx chains to use when expecting MIMO. */
651 if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
656 /* # Rx chains when idling and maybe trying to save power */
657 switch (priv->ps_mode) {
658 case IWL_MIMO_PS_STATIC:
659 case IWL_MIMO_PS_DYNAMIC:
660 *idle_state = (is_cam) ? 2 : 1;
662 case IWL_MIMO_PS_NONE:
663 *idle_state = (is_cam) ? *rx_state : 1;
674 * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
676 * Selects how many and which Rx receivers/antennas/chains to use.
677 * This should not be used for scan command ... it puts data in wrong place.
679 void iwl_set_rxon_chain(struct iwl_priv *priv)
681 u8 is_single = is_single_rx_stream(priv);
682 u8 idle_state, rx_state;
684 priv->staging_rxon.rx_chain = 0;
685 rx_state = idle_state = 3;
687 /* Tell uCode which antennas are actually connected.
688 * Before first association, we assume all antennas are connected.
689 * Just after first association, iwl_chain_noise_calibration()
690 * checks which antennas actually *are* connected. */
691 priv->staging_rxon.rx_chain |=
692 cpu_to_le16(priv->hw_params.valid_rx_ant <<
693 RXON_RX_CHAIN_VALID_POS);
695 /* How many receivers should we use? */
696 iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
697 priv->staging_rxon.rx_chain |=
698 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
699 priv->staging_rxon.rx_chain |=
700 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
702 if (!is_single && (rx_state >= 2) &&
703 !test_bit(STATUS_POWER_PMI, &priv->status))
704 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
706 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
708 IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
710 EXPORT_SYMBOL(iwl_set_rxon_chain);
713 * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
714 * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
715 * @channel: Any channel valid for the requested phymode
717 * In addition to setting the staging RXON, priv->phymode is also set.
719 * NOTE: Does not commit to the hardware; it sets appropriate bit fields
720 * in the staging RXON flag structure based on the phymode
722 int iwl_set_rxon_channel(struct iwl_priv *priv,
723 enum ieee80211_band band,
726 if (!iwl_get_channel_info(priv, band, channel)) {
727 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
732 if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
733 (priv->band == band))
736 priv->staging_rxon.channel = cpu_to_le16(channel);
737 if (band == IEEE80211_BAND_5GHZ)
738 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
740 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
744 IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
748 EXPORT_SYMBOL(iwl_set_rxon_channel);
750 int iwl_setup_mac(struct iwl_priv *priv)
753 struct ieee80211_hw *hw = priv->hw;
754 hw->rate_control_algorithm = "iwl-4965-rs";
756 /* Tell mac80211 our characteristics */
757 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
758 IEEE80211_HW_SIGNAL_DBM |
759 IEEE80211_HW_NOISE_DBM;
760 /* Default value; 4 EDCA QOS priorities */
762 /* Enhanced value; more queues, to support 11n aggregation */
763 hw->ampdu_queues = 12;
765 hw->conf.beacon_int = 100;
767 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
768 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
769 &priv->bands[IEEE80211_BAND_2GHZ];
770 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
771 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
772 &priv->bands[IEEE80211_BAND_5GHZ];
774 ret = ieee80211_register_hw(priv->hw);
776 IWL_ERROR("Failed to register hw (error %d)\n", ret);
779 priv->mac80211_registered = 1;
783 EXPORT_SYMBOL(iwl_setup_mac);
786 int iwl_init_drv(struct iwl_priv *priv)
791 priv->retry_rate = 1;
792 priv->ibss_beacon = NULL;
794 spin_lock_init(&priv->lock);
795 spin_lock_init(&priv->power_data.lock);
796 spin_lock_init(&priv->sta_lock);
797 spin_lock_init(&priv->hcmd_lock);
798 spin_lock_init(&priv->lq_mngr.lock);
800 for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
801 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
803 INIT_LIST_HEAD(&priv->free_frames);
805 mutex_init(&priv->mutex);
807 /* Clear the driver's (not device's) station table */
808 iwlcore_clear_stations_table(priv);
810 priv->data_retry_limit = -1;
811 priv->ieee_channels = NULL;
812 priv->ieee_rates = NULL;
813 priv->band = IEEE80211_BAND_2GHZ;
815 priv->iw_mode = IEEE80211_IF_TYPE_STA;
817 priv->use_ant_b_for_management_frame = 1; /* start with ant B */
818 priv->ps_mode = IWL_MIMO_PS_NONE;
820 /* Choose which receivers/antennas to use */
821 iwl_set_rxon_chain(priv);
823 if (priv->cfg->mod_params->enable_qos)
824 priv->qos_data.qos_enable = 1;
828 priv->qos_data.qos_active = 0;
829 priv->qos_data.qos_cap.val = 0;
831 iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
833 priv->rates_mask = IWL_RATES_MASK;
834 /* If power management is turned on, default to AC mode */
835 priv->power_mode = IWL_POWER_AC;
836 priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
838 ret = iwl_init_channel_map(priv);
840 IWL_ERROR("initializing regulatory failed: %d\n", ret);
844 ret = iwlcore_init_geos(priv);
846 IWL_ERROR("initializing geos failed: %d\n", ret);
847 goto err_free_channel_map;
852 err_free_channel_map:
853 iwl_free_channel_map(priv);
857 EXPORT_SYMBOL(iwl_init_drv);
859 void iwl_free_calib_results(struct iwl_priv *priv)
861 kfree(priv->calib_results.lo_res);
862 priv->calib_results.lo_res = NULL;
863 priv->calib_results.lo_res_len = 0;
865 kfree(priv->calib_results.tx_iq_res);
866 priv->calib_results.tx_iq_res = NULL;
867 priv->calib_results.tx_iq_res_len = 0;
869 kfree(priv->calib_results.tx_iq_perd_res);
870 priv->calib_results.tx_iq_perd_res = NULL;
871 priv->calib_results.tx_iq_perd_res_len = 0;
873 EXPORT_SYMBOL(iwl_free_calib_results);
875 void iwl_uninit_drv(struct iwl_priv *priv)
877 iwl_free_calib_results(priv);
878 iwlcore_free_geos(priv);
879 iwl_free_channel_map(priv);
882 EXPORT_SYMBOL(iwl_uninit_drv);
884 /* Low level driver call this function to update iwlcore with
887 int iwlcore_low_level_notify(struct iwl_priv *priv,
888 enum iwlcore_card_notify notify)
892 case IWLCORE_INIT_EVT:
893 ret = iwl_rfkill_init(priv);
895 IWL_ERROR("Unable to initialize RFKILL system. "
896 "Ignoring error: %d\n", ret);
897 iwl_power_initialize(priv);
899 case IWLCORE_START_EVT:
900 iwl_power_update_mode(priv, 1);
902 case IWLCORE_STOP_EVT:
904 case IWLCORE_REMOVE_EVT:
905 iwl_rfkill_unregister(priv);
911 EXPORT_SYMBOL(iwlcore_low_level_notify);
913 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
916 struct iwl_host_cmd cmd = {
917 .id = REPLY_STATISTICS_CMD,
919 .len = sizeof(stat_flags),
920 .data = (u8 *) &stat_flags,
922 return iwl_send_cmd(priv, &cmd);
924 EXPORT_SYMBOL(iwl_send_statistics_request);
927 * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
928 * using sample data 100 bytes apart. If these sample points are good,
929 * it's a pretty good bet that everything between them is good, too.
931 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
938 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
940 ret = iwl_grab_nic_access(priv);
944 for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
945 /* read data comes through single port, auto-incr addr */
946 /* NOTE: Use the debugless read so we don't flood kernel log
947 * if IWL_DL_IO is set */
948 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
949 i + RTC_INST_LOWER_BOUND);
950 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
951 if (val != le32_to_cpu(*image)) {
959 iwl_release_nic_access(priv);
965 * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
966 * looking at all data.
968 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
976 IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
978 ret = iwl_grab_nic_access(priv);
982 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
985 for (; len > 0; len -= sizeof(u32), image++) {
986 /* read data comes through single port, auto-incr addr */
987 /* NOTE: Use the debugless read so we don't flood kernel log
988 * if IWL_DL_IO is set */
989 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
990 if (val != le32_to_cpu(*image)) {
991 IWL_ERROR("uCode INST section is invalid at "
992 "offset 0x%x, is 0x%x, s/b 0x%x\n",
993 save_len - len, val, le32_to_cpu(*image));
1001 iwl_release_nic_access(priv);
1005 ("ucode image in INSTRUCTION memory is good\n");
1011 * iwl_verify_ucode - determine which instruction image is in SRAM,
1012 * and verify its contents
1014 int iwl_verify_ucode(struct iwl_priv *priv)
1021 image = (__le32 *)priv->ucode_boot.v_addr;
1022 len = priv->ucode_boot.len;
1023 ret = iwlcore_verify_inst_sparse(priv, image, len);
1025 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1029 /* Try initialize */
1030 image = (__le32 *)priv->ucode_init.v_addr;
1031 len = priv->ucode_init.len;
1032 ret = iwlcore_verify_inst_sparse(priv, image, len);
1034 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1038 /* Try runtime/protocol */
1039 image = (__le32 *)priv->ucode_code.v_addr;
1040 len = priv->ucode_code.len;
1041 ret = iwlcore_verify_inst_sparse(priv, image, len);
1043 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1047 IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1049 /* Since nothing seems to match, show first several data entries in
1050 * instruction SRAM, so maybe visual inspection will give a clue.
1051 * Selection of bootstrap image (vs. other images) is arbitrary. */
1052 image = (__le32 *)priv->ucode_boot.v_addr;
1053 len = priv->ucode_boot.len;
1054 ret = iwl_verify_inst_full(priv, image, len);
1058 EXPORT_SYMBOL(iwl_verify_ucode);
1061 static const char *desc_lookup(int i)
1069 return "BAD_CHECKSUM";
1071 return "NMI_INTERRUPT";
1075 return "FATAL_ERROR";
1081 #define ERROR_START_OFFSET (1 * sizeof(u32))
1082 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1084 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1087 u32 desc, time, count, base, data1;
1088 u32 blink1, blink2, ilink1, ilink2;
1091 if (priv->ucode_type == UCODE_INIT)
1092 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1094 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1096 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1097 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1101 ret = iwl_grab_nic_access(priv);
1103 IWL_WARNING("Can not read from adapter at this time.\n");
1107 count = iwl_read_targ_mem(priv, base);
1109 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1110 IWL_ERROR("Start IWL Error Log Dump:\n");
1111 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1114 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1115 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1116 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1117 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1118 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1119 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1120 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1121 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1122 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1124 IWL_ERROR("Desc Time "
1125 "data1 data2 line\n");
1126 IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1127 desc_lookup(desc), desc, time, data1, data2, line);
1128 IWL_ERROR("blink1 blink2 ilink1 ilink2\n");
1129 IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1132 iwl_release_nic_access(priv);
1134 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1136 #define EVENT_START_OFFSET (4 * sizeof(u32))
1139 * iwl_print_event_log - Dump error event log to syslog
1141 * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1143 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1144 u32 num_events, u32 mode)
1147 u32 base; /* SRAM byte address of event log header */
1148 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1149 u32 ptr; /* SRAM byte address of log data */
1150 u32 ev, time, data; /* event log data */
1152 if (num_events == 0)
1154 if (priv->ucode_type == UCODE_INIT)
1155 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1157 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1160 event_size = 2 * sizeof(u32);
1162 event_size = 3 * sizeof(u32);
1164 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1166 /* "time" is actually "data" for mode 0 (no timestamp).
1167 * place event id # at far right for easier visual parsing. */
1168 for (i = 0; i < num_events; i++) {
1169 ev = iwl_read_targ_mem(priv, ptr);
1171 time = iwl_read_targ_mem(priv, ptr);
1174 IWL_ERROR("0x%08x\t%04u\n", time, ev); /* data, ev */
1176 data = iwl_read_targ_mem(priv, ptr);
1178 IWL_ERROR("%010u\t0x%08x\t%04u\n", time, data, ev);
1182 EXPORT_SYMBOL(iwl_print_event_log);
1185 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1188 u32 base; /* SRAM byte address of event log header */
1189 u32 capacity; /* event log capacity in # entries */
1190 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1191 u32 num_wraps; /* # times uCode wrapped to top of log */
1192 u32 next_entry; /* index of next entry to be written by uCode */
1193 u32 size; /* # entries that we'll print */
1195 if (priv->ucode_type == UCODE_INIT)
1196 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1198 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1200 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1201 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1205 ret = iwl_grab_nic_access(priv);
1207 IWL_WARNING("Can not read from adapter at this time.\n");
1211 /* event log header */
1212 capacity = iwl_read_targ_mem(priv, base);
1213 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1214 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1215 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1217 size = num_wraps ? capacity : next_entry;
1219 /* bail out if nothing in log */
1221 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1222 iwl_release_nic_access(priv);
1226 IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1229 /* if uCode has wrapped back to top of log, start at the oldest entry,
1230 * i.e the next one that uCode would fill. */
1232 iwl_print_event_log(priv, next_entry,
1233 capacity - next_entry, mode);
1234 /* (then/else) start at top of log */
1235 iwl_print_event_log(priv, 0, next_entry, mode);
1237 iwl_release_nic_access(priv);
1239 EXPORT_SYMBOL(iwl_dump_nic_event_log);