err.no Git - linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-core.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  * Tomas Winkler <tomas.winkler@intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *****************************************************************************/
  28
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/version.h>
  32 #include <net/mac80211.h>
  33
  34 struct iwl_priv; /* FIXME: remove */
  35 #include "iwl-debug.h"
  36 #include "iwl-eeprom.h"
  37 #include "iwl-dev.h" /* FIXME: remove */
  38 #include "iwl-core.h"
  39 #include "iwl-io.h"
  40 #include "iwl-rfkill.h"
  41 #include "iwl-power.h"
  42
  43
  44 MODULE_DESCRIPTION("iwl core");
  45 MODULE_VERSION(IWLWIFI_VERSION);
  46 MODULE_AUTHOR(DRV_COPYRIGHT);
  47 MODULE_LICENSE("GPL");
  48
  49 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np)    \
  50         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,      \
  51                                     IWL_RATE_SISO_##s##M_PLCP, \
  52                                     IWL_RATE_MIMO2_##s##M_PLCP,\
  53                                     IWL_RATE_MIMO3_##s##M_PLCP,\
  54                                     IWL_RATE_##r##M_IEEE,      \
  55                                     IWL_RATE_##ip##M_INDEX,    \
  56                                     IWL_RATE_##in##M_INDEX,    \
  57                                     IWL_RATE_##rp##M_INDEX,    \
  58                                     IWL_RATE_##rn##M_INDEX,    \
  59                                     IWL_RATE_##pp##M_INDEX,    \
  60                                     IWL_RATE_##np##M_INDEX }
  61
  62 /*
  63  * Parameter order:
  64  *   rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  65  *
  66  * If there isn't a valid next or previous rate then INV is used which
  67  * maps to IWL_RATE_INVALID
  68  *
  69  */
  70 const struct iwl_rate_info iwl_rates[IWL_RATE_COUNT] = {
  71         IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  72         IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  73         IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  74         IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18),      /* 11mbps */
  75         IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  76         IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11),       /*  9mbps */
  77         IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  78         IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  79         IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  80         IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  81         IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  82         IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  83         IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  84         /* FIXME:RS:          ^^    should be INV (legacy) */
  85 };
  86 EXPORT_SYMBOL(iwl_rates);
  87
  88
  89 const u8 iwl_bcast_addr[ETH_ALEN] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
  90 EXPORT_SYMBOL(iwl_bcast_addr);
  91
  92
  93 /* This function both allocates and initializes hw and priv. */
  94 struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg,
  95                 struct ieee80211_ops *hw_ops)
  96 {
  97         struct iwl_priv *priv;
  98
  99         /* mac80211 allocates memory for this device instance, including
 100          *   space for this driver's private structure */
 101         struct ieee80211_hw *hw =
 102                 ieee80211_alloc_hw(sizeof(struct iwl_priv), hw_ops);
 103         if (hw == NULL) {
 104                 IWL_ERROR("Can not allocate network device\n");
 105                 goto out;
 106         }
 107
 108         priv = hw->priv;
 109         priv->hw = hw;
 110
 111 out:
 112         return hw;
 113 }
 114 EXPORT_SYMBOL(iwl_alloc_all);
 115
 116 void iwl_hw_detect(struct iwl_priv *priv)
 117 {
 118         priv->hw_rev = _iwl_read32(priv, CSR_HW_REV);
 119         priv->hw_wa_rev = _iwl_read32(priv, CSR_HW_REV_WA_REG);
 120         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &priv->rev_id);
 121 }
 122 EXPORT_SYMBOL(iwl_hw_detect);
 123
 124 /* Tell nic where to find the "keep warm" buffer */
 125 int iwl_kw_init(struct iwl_priv *priv)
 126 {
 127         unsigned long flags;
 128         int ret;
 129
 130         spin_lock_irqsave(&priv->lock, flags);
 131         ret = iwl_grab_nic_access(priv);
 132         if (ret)
 133                 goto out;
 134
 135         iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG,
 136                              priv->kw.dma_addr >> 4);
 137         iwl_release_nic_access(priv);
 138 out:
 139         spin_unlock_irqrestore(&priv->lock, flags);
 140         return ret;
 141 }
 142
 143 int iwl_kw_alloc(struct iwl_priv *priv)
 144 {
 145         struct pci_dev *dev = priv->pci_dev;
 146         struct iwl_kw *kw = &priv->kw;
 147
 148         kw->size = IWL_KW_SIZE;
 149         kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
 150         if (!kw->v_addr)
 151                 return -ENOMEM;
 152
 153         return 0;
 154 }
 155
 156 /**
 157  * iwl_kw_free - Free the "keep warm" buffer
 158  */
 159 void iwl_kw_free(struct iwl_priv *priv)
 160 {
 161         struct pci_dev *dev = priv->pci_dev;
 162         struct iwl_kw *kw = &priv->kw;
 163
 164         if (kw->v_addr) {
 165                 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
 166                 memset(kw, 0, sizeof(*kw));
 167         }
 168 }
 169
 170 int iwl_hw_nic_init(struct iwl_priv *priv)
 171 {
 172         unsigned long flags;
 173         struct iwl_rx_queue *rxq = &priv->rxq;
 174         int ret;
 175
 176         /* nic_init */
 177         spin_lock_irqsave(&priv->lock, flags);
 178         priv->cfg->ops->lib->apm_ops.init(priv);
 179         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
 180         spin_unlock_irqrestore(&priv->lock, flags);
 181
 182         ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
 183
 184         priv->cfg->ops->lib->apm_ops.config(priv);
 185
 186         /* Allocate the RX queue, or reset if it is already allocated */
 187         if (!rxq->bd) {
 188                 ret = iwl_rx_queue_alloc(priv);
 189                 if (ret) {
 190                         IWL_ERROR("Unable to initialize Rx queue\n");
 191                         return -ENOMEM;
 192                 }
 193         } else
 194                 iwl_rx_queue_reset(priv, rxq);
 195
 196         iwl_rx_replenish(priv);
 197
 198         iwl_rx_init(priv, rxq);
 199
 200         spin_lock_irqsave(&priv->lock, flags);
 201
 202         rxq->need_update = 1;
 203         iwl_rx_queue_update_write_ptr(priv, rxq);
 204
 205         spin_unlock_irqrestore(&priv->lock, flags);
 206
 207         /* Allocate and init all Tx and Command queues */
 208         ret = iwl_txq_ctx_reset(priv);
 209         if (ret)
 210                 return ret;
 211
 212         set_bit(STATUS_INIT, &priv->status);
 213
 214         return 0;
 215 }
 216 EXPORT_SYMBOL(iwl_hw_nic_init);
 217
 218 /**
 219  * iwlcore_clear_stations_table - Clear the driver's station table
 220  *
 221  * NOTE:  This does not clear or otherwise alter the device's station table.
 222  */
 223 void iwlcore_clear_stations_table(struct iwl_priv *priv)
 224 {
 225         unsigned long flags;
 226
 227         spin_lock_irqsave(&priv->sta_lock, flags);
 228
 229         priv->num_stations = 0;
 230         memset(priv->stations, 0, sizeof(priv->stations));
 231
 232         spin_unlock_irqrestore(&priv->sta_lock, flags);
 233 }
 234 EXPORT_SYMBOL(iwlcore_clear_stations_table);
 235
 236 void iwl_reset_qos(struct iwl_priv *priv)
 237 {
 238         u16 cw_min = 15;
 239         u16 cw_max = 1023;
 240         u8 aifs = 2;
 241         u8 is_legacy = 0;
 242         unsigned long flags;
 243         int i;
 244
 245         spin_lock_irqsave(&priv->lock, flags);
 246         priv->qos_data.qos_active = 0;
 247
 248         if (priv->iw_mode == IEEE80211_IF_TYPE_IBSS) {
 249                 if (priv->qos_data.qos_enable)
 250                         priv->qos_data.qos_active = 1;
 251                 if (!(priv->active_rate & 0xfff0)) {
 252                         cw_min = 31;
 253                         is_legacy = 1;
 254                 }
 255         } else if (priv->iw_mode == IEEE80211_IF_TYPE_AP) {
 256                 if (priv->qos_data.qos_enable)
 257                         priv->qos_data.qos_active = 1;
 258         } else if (!(priv->staging_rxon.flags & RXON_FLG_SHORT_SLOT_MSK)) {
 259                 cw_min = 31;
 260                 is_legacy = 1;
 261         }
 262
 263         if (priv->qos_data.qos_active)
 264                 aifs = 3;
 265
 266         priv->qos_data.def_qos_parm.ac[0].cw_min = cpu_to_le16(cw_min);
 267         priv->qos_data.def_qos_parm.ac[0].cw_max = cpu_to_le16(cw_max);
 268         priv->qos_data.def_qos_parm.ac[0].aifsn = aifs;
 269         priv->qos_data.def_qos_parm.ac[0].edca_txop = 0;
 270         priv->qos_data.def_qos_parm.ac[0].reserved1 = 0;
 271
 272         if (priv->qos_data.qos_active) {
 273                 i = 1;
 274                 priv->qos_data.def_qos_parm.ac[i].cw_min = cpu_to_le16(cw_min);
 275                 priv->qos_data.def_qos_parm.ac[i].cw_max = cpu_to_le16(cw_max);
 276                 priv->qos_data.def_qos_parm.ac[i].aifsn = 7;
 277                 priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 278                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 279
 280                 i = 2;
 281                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 282                         cpu_to_le16((cw_min + 1) / 2 - 1);
 283                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 284                         cpu_to_le16(cw_max);
 285                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 286                 if (is_legacy)
 287                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 288                                 cpu_to_le16(6016);
 289                 else
 290                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 291                                 cpu_to_le16(3008);
 292                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 293
 294                 i = 3;
 295                 priv->qos_data.def_qos_parm.ac[i].cw_min =
 296                         cpu_to_le16((cw_min + 1) / 4 - 1);
 297                 priv->qos_data.def_qos_parm.ac[i].cw_max =
 298                         cpu_to_le16((cw_max + 1) / 2 - 1);
 299                 priv->qos_data.def_qos_parm.ac[i].aifsn = 2;
 300                 priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 301                 if (is_legacy)
 302                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 303                                 cpu_to_le16(3264);
 304                 else
 305                         priv->qos_data.def_qos_parm.ac[i].edca_txop =
 306                                 cpu_to_le16(1504);
 307         } else {
 308                 for (i = 1; i < 4; i++) {
 309                         priv->qos_data.def_qos_parm.ac[i].cw_min =
 310                                 cpu_to_le16(cw_min);
 311                         priv->qos_data.def_qos_parm.ac[i].cw_max =
 312                                 cpu_to_le16(cw_max);
 313                         priv->qos_data.def_qos_parm.ac[i].aifsn = aifs;
 314                         priv->qos_data.def_qos_parm.ac[i].edca_txop = 0;
 315                         priv->qos_data.def_qos_parm.ac[i].reserved1 = 0;
 316                 }
 317         }
 318         IWL_DEBUG_QOS("set QoS to default \n");
 319
 320         spin_unlock_irqrestore(&priv->lock, flags);
 321 }
 322 EXPORT_SYMBOL(iwl_reset_qos);
 323
 324 #define MAX_BIT_RATE_40_MHZ 0x96; /* 150 Mbps */
 325 #define MAX_BIT_RATE_20_MHZ 0x48; /* 72 Mbps */
 326 static void iwlcore_init_ht_hw_capab(const struct iwl_priv *priv,
 327                               struct ieee80211_ht_info *ht_info,
 328                               enum ieee80211_band band)
 329 {
 330         u16 max_bit_rate = 0;
 331         u8 rx_chains_num = priv->hw_params.rx_chains_num;
 332         u8 tx_chains_num = priv->hw_params.tx_chains_num;
 333
 334         ht_info->cap = 0;
 335         memset(ht_info->supp_mcs_set, 0, 16);
 336
 337         ht_info->ht_supported = 1;
 338
 339         ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
 340         ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
 341         ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
 342                              (IWL_MIMO_PS_NONE << 2));
 343
 344         max_bit_rate = MAX_BIT_RATE_20_MHZ;
 345         if (priv->hw_params.fat_channel & BIT(band)) {
 346                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
 347                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
 348                 ht_info->supp_mcs_set[4] = 0x01;
 349                 max_bit_rate = MAX_BIT_RATE_40_MHZ;
 350         }
 351
 352         if (priv->cfg->mod_params->amsdu_size_8K)
 353                 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
 354
 355         ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
 356         ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
 357
 358         ht_info->supp_mcs_set[0] = 0xFF;
 359         if (rx_chains_num >= 2)
 360                 ht_info->supp_mcs_set[1] = 0xFF;
 361         if (rx_chains_num >= 3)
 362                 ht_info->supp_mcs_set[2] = 0xFF;
 363
 364         /* Highest supported Rx data rate */
 365         max_bit_rate *= rx_chains_num;
 366         ht_info->supp_mcs_set[10] = (u8)(max_bit_rate & 0x00FF);
 367         ht_info->supp_mcs_set[11] = (u8)((max_bit_rate & 0xFF00) >> 8);
 368
 369         /* Tx MCS capabilities */
 370         ht_info->supp_mcs_set[12] = IEEE80211_HT_CAP_MCS_TX_DEFINED;
 371         if (tx_chains_num != rx_chains_num) {
 372                 ht_info->supp_mcs_set[12] |= IEEE80211_HT_CAP_MCS_TX_RX_DIFF;
 373                 ht_info->supp_mcs_set[12] |= ((tx_chains_num - 1) << 2);
 374         }
 375 }
 376
 377 static void iwlcore_init_hw_rates(struct iwl_priv *priv,
 378                               struct ieee80211_rate *rates)
 379 {
 380         int i;
 381
 382         for (i = 0; i < IWL_RATE_COUNT; i++) {
 383                 rates[i].bitrate = iwl_rates[i].ieee * 5;
 384                 rates[i].hw_value = i; /* Rate scaling will work on indexes */
 385                 rates[i].hw_value_short = i;
 386                 rates[i].flags = 0;
 387                 if ((i > IWL_LAST_OFDM_RATE) || (i < IWL_FIRST_OFDM_RATE)) {
 388                         /*
 389                          * If CCK != 1M then set short preamble rate flag.
 390                          */
 391                         rates[i].flags |=
 392                                 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
 393                                         0 : IEEE80211_RATE_SHORT_PREAMBLE;
 394                 }
 395         }
 396 }
 397
 398 /**
 399  * iwlcore_init_geos - Initialize mac80211's geo/channel info based from eeprom
 400  */
 401 static int iwlcore_init_geos(struct iwl_priv *priv)
 402 {
 403         struct iwl_channel_info *ch;
 404         struct ieee80211_supported_band *sband;
 405         struct ieee80211_channel *channels;
 406         struct ieee80211_channel *geo_ch;
 407         struct ieee80211_rate *rates;
 408         int i = 0;
 409
 410         if (priv->bands[IEEE80211_BAND_2GHZ].n_bitrates ||
 411             priv->bands[IEEE80211_BAND_5GHZ].n_bitrates) {
 412                 IWL_DEBUG_INFO("Geography modes already initialized.\n");
 413                 set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 414                 return 0;
 415         }
 416
 417         channels = kzalloc(sizeof(struct ieee80211_channel) *
 418                            priv->channel_count, GFP_KERNEL);
 419         if (!channels)
 420                 return -ENOMEM;
 421
 422         rates = kzalloc((sizeof(struct ieee80211_rate) * (IWL_RATE_COUNT + 1)),
 423                         GFP_KERNEL);
 424         if (!rates) {
 425                 kfree(channels);
 426                 return -ENOMEM;
 427         }
 428
 429         /* 5.2GHz channels start after the 2.4GHz channels */
 430         sband = &priv->bands[IEEE80211_BAND_5GHZ];
 431         sband->channels = &channels[ARRAY_SIZE(iwl_eeprom_band_1)];
 432         /* just OFDM */
 433         sband->bitrates = &rates[IWL_FIRST_OFDM_RATE];
 434         sband->n_bitrates = IWL_RATE_COUNT - IWL_FIRST_OFDM_RATE;
 435
 436         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_5GHZ);
 437
 438         sband = &priv->bands[IEEE80211_BAND_2GHZ];
 439         sband->channels = channels;
 440         /* OFDM & CCK */
 441         sband->bitrates = rates;
 442         sband->n_bitrates = IWL_RATE_COUNT;
 443
 444         iwlcore_init_ht_hw_capab(priv, &sband->ht_info, IEEE80211_BAND_2GHZ);
 445
 446         priv->ieee_channels = channels;
 447         priv->ieee_rates = rates;
 448
 449         iwlcore_init_hw_rates(priv, rates);
 450
 451         for (i = 0;  i < priv->channel_count; i++) {
 452                 ch = &priv->channel_info[i];
 453
 454                 /* FIXME: might be removed if scan is OK */
 455                 if (!is_channel_valid(ch))
 456                         continue;
 457
 458                 if (is_channel_a_band(ch))
 459                         sband =  &priv->bands[IEEE80211_BAND_5GHZ];
 460                 else
 461                         sband =  &priv->bands[IEEE80211_BAND_2GHZ];
 462
 463                 geo_ch = &sband->channels[sband->n_channels++];
 464
 465                 geo_ch->center_freq =
 466                                 ieee80211_channel_to_frequency(ch->channel);
 467                 geo_ch->max_power = ch->max_power_avg;
 468                 geo_ch->max_antenna_gain = 0xff;
 469                 geo_ch->hw_value = ch->channel;
 470
 471                 if (is_channel_valid(ch)) {
 472                         if (!(ch->flags & EEPROM_CHANNEL_IBSS))
 473                                 geo_ch->flags |= IEEE80211_CHAN_NO_IBSS;
 474
 475                         if (!(ch->flags & EEPROM_CHANNEL_ACTIVE))
 476                                 geo_ch->flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 477
 478                         if (ch->flags & EEPROM_CHANNEL_RADAR)
 479                                 geo_ch->flags |= IEEE80211_CHAN_RADAR;
 480
 481                         geo_ch->flags |= ch->fat_extension_channel;
 482
 483                         if (ch->max_power_avg > priv->max_channel_txpower_limit)
 484                                 priv->max_channel_txpower_limit =
 485                                     ch->max_power_avg;
 486                 } else {
 487                         geo_ch->flags |= IEEE80211_CHAN_DISABLED;
 488                 }
 489
 490                 /* Save flags for reg domain usage */
 491                 geo_ch->orig_flags = geo_ch->flags;
 492
 493                 IWL_DEBUG_INFO("Channel %d Freq=%d[%sGHz] %s flag=0x%X\n",
 494                                 ch->channel, geo_ch->center_freq,
 495                                 is_channel_a_band(ch) ?  "5.2" : "2.4",
 496                                 geo_ch->flags & IEEE80211_CHAN_DISABLED ?
 497                                 "restricted" : "valid",
 498                                  geo_ch->flags);
 499         }
 500
 501         if ((priv->bands[IEEE80211_BAND_5GHZ].n_channels == 0) &&
 502              priv->cfg->sku & IWL_SKU_A) {
 503                 printk(KERN_INFO DRV_NAME
 504                        ": Incorrectly detected BG card as ABG.  Please send "
 505                        "your PCI ID 0x%04X:0x%04X to maintainer.\n",
 506                        priv->pci_dev->device, priv->pci_dev->subsystem_device);
 507                 priv->cfg->sku &= ~IWL_SKU_A;
 508         }
 509
 510         printk(KERN_INFO DRV_NAME
 511                ": Tunable channels: %d 802.11bg, %d 802.11a channels\n",
 512                priv->bands[IEEE80211_BAND_2GHZ].n_channels,
 513                priv->bands[IEEE80211_BAND_5GHZ].n_channels);
 514
 515
 516         set_bit(STATUS_GEO_CONFIGURED, &priv->status);
 517
 518         return 0;
 519 }
 520
 521 /*
 522  * iwlcore_free_geos - undo allocations in iwlcore_init_geos
 523  */
 524 static void iwlcore_free_geos(struct iwl_priv *priv)
 525 {
 526         kfree(priv->ieee_channels);
 527         kfree(priv->ieee_rates);
 528         clear_bit(STATUS_GEO_CONFIGURED, &priv->status);
 529 }
 530
 531 static u8 is_single_rx_stream(struct iwl_priv *priv)
 532 {
 533         return !priv->current_ht_config.is_ht ||
 534                ((priv->current_ht_config.supp_mcs_set[1] == 0) &&
 535                 (priv->current_ht_config.supp_mcs_set[2] == 0)) ||
 536                priv->ps_mode == IWL_MIMO_PS_STATIC;
 537 }
 538
 539 static u8 iwl_is_channel_extension(struct iwl_priv *priv,
 540                                    enum ieee80211_band band,
 541                                    u16 channel, u8 extension_chan_offset)
 542 {
 543         const struct iwl_channel_info *ch_info;
 544
 545         ch_info = iwl_get_channel_info(priv, band, channel);
 546         if (!is_channel_valid(ch_info))
 547                 return 0;
 548
 549         if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_ABOVE)
 550                 return !(ch_info->fat_extension_channel &
 551                                         IEEE80211_CHAN_NO_FAT_ABOVE);
 552         else if (extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_BELOW)
 553                 return !(ch_info->fat_extension_channel &
 554                                         IEEE80211_CHAN_NO_FAT_BELOW);
 555
 556         return 0;
 557 }
 558
 559 u8 iwl_is_fat_tx_allowed(struct iwl_priv *priv,
 560                              struct ieee80211_ht_info *sta_ht_inf)
 561 {
 562         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
 563
 564         if ((!iwl_ht_conf->is_ht) ||
 565            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
 566            (iwl_ht_conf->extension_chan_offset == IEEE80211_HT_IE_CHA_SEC_NONE))
 567                 return 0;
 568
 569         if (sta_ht_inf) {
 570                 if ((!sta_ht_inf->ht_supported) ||
 571                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
 572                         return 0;
 573         }
 574
 575         return iwl_is_channel_extension(priv, priv->band,
 576                                          iwl_ht_conf->control_channel,
 577                                          iwl_ht_conf->extension_chan_offset);
 578 }
 579 EXPORT_SYMBOL(iwl_is_fat_tx_allowed);
 580
 581 void iwl_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
 582 {
 583         struct iwl_rxon_cmd *rxon = &priv->staging_rxon;
 584         u32 val;
 585
 586         if (!ht_info->is_ht)
 587                 return;
 588
 589         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
 590         if (iwl_is_fat_tx_allowed(priv, NULL))
 591                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 592         else
 593                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
 594                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
 595
 596         if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
 597                 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
 598                                 le16_to_cpu(rxon->channel),
 599                                 ht_info->control_channel);
 600                 return;
 601         }
 602
 603         /* Note: control channel is opposite of extension channel */
 604         switch (ht_info->extension_chan_offset) {
 605         case IEEE80211_HT_IE_CHA_SEC_ABOVE:
 606                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
 607                 break;
 608         case IEEE80211_HT_IE_CHA_SEC_BELOW:
 609                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
 610                 break;
 611         case IEEE80211_HT_IE_CHA_SEC_NONE:
 612         default:
 613                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
 614                 break;
 615         }
 616
 617         val = ht_info->ht_protection;
 618
 619         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
 620
 621         iwl_set_rxon_chain(priv);
 622
 623         IWL_DEBUG_ASSOC("supported HT rate 0x%X 0x%X 0x%X "
 624                         "rxon flags 0x%X operation mode :0x%X "
 625                         "extension channel offset 0x%x "
 626                         "control chan %d\n",
 627                         ht_info->supp_mcs_set[0],
 628                         ht_info->supp_mcs_set[1],
 629                         ht_info->supp_mcs_set[2],
 630                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
 631                         ht_info->extension_chan_offset,
 632                         ht_info->control_channel);
 633         return;
 634 }
 635 EXPORT_SYMBOL(iwl_set_rxon_ht);
 636
 637 /*
 638  * Determine how many receiver/antenna chains to use.
 639  * More provides better reception via diversity.  Fewer saves power.
 640  * MIMO (dual stream) requires at least 2, but works better with 3.
 641  * This does not determine *which* chains to use, just how many.
 642  */
 643 static int iwlcore_get_rx_chain_counter(struct iwl_priv *priv,
 644                                         u8 *idle_state, u8 *rx_state)
 645 {
 646         u8 is_single = is_single_rx_stream(priv);
 647         u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
 648
 649         /* # of Rx chains to use when expecting MIMO. */
 650         if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
 651                 *rx_state = 2;
 652         else
 653                 *rx_state = 3;
 654
 655         /* # Rx chains when idling and maybe trying to save power */
 656         switch (priv->ps_mode) {
 657         case IWL_MIMO_PS_STATIC:
 658         case IWL_MIMO_PS_DYNAMIC:
 659                 *idle_state = (is_cam) ? 2 : 1;
 660                 break;
 661         case IWL_MIMO_PS_NONE:
 662                 *idle_state = (is_cam) ? *rx_state : 1;
 663                 break;
 664         default:
 665                 *idle_state = 1;
 666                 break;
 667         }
 668
 669         return 0;
 670 }
 671
 672 /**
 673  * iwl_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
 674  *
 675  * Selects how many and which Rx receivers/antennas/chains to use.
 676  * This should not be used for scan command ... it puts data in wrong place.
 677  */
 678 void iwl_set_rxon_chain(struct iwl_priv *priv)
 679 {
 680         u8 is_single = is_single_rx_stream(priv);
 681         u8 idle_state, rx_state;
 682
 683         priv->staging_rxon.rx_chain = 0;
 684         rx_state = idle_state = 3;
 685
 686         /* Tell uCode which antennas are actually connected.
 687          * Before first association, we assume all antennas are connected.
 688          * Just after first association, iwl_chain_noise_calibration()
 689          *    checks which antennas actually *are* connected. */
 690         priv->staging_rxon.rx_chain |=
 691                     cpu_to_le16(priv->hw_params.valid_rx_ant <<
 692                                                  RXON_RX_CHAIN_VALID_POS);
 693
 694         /* How many receivers should we use? */
 695         iwlcore_get_rx_chain_counter(priv, &idle_state, &rx_state);
 696         priv->staging_rxon.rx_chain |=
 697                 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
 698         priv->staging_rxon.rx_chain |=
 699                 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
 700
 701         if (!is_single && (rx_state >= 2) &&
 702             !test_bit(STATUS_POWER_PMI, &priv->status))
 703                 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
 704         else
 705                 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
 706
 707         IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
 708 }
 709 EXPORT_SYMBOL(iwl_set_rxon_chain);
 710
 711 /**
 712  * iwlcore_set_rxon_channel - Set the phymode and channel values in staging RXON
 713  * @phymode: MODE_IEEE80211A sets to 5.2GHz; all else set to 2.4GHz
 714  * @channel: Any channel valid for the requested phymode
 715
 716  * In addition to setting the staging RXON, priv->phymode is also set.
 717  *
 718  * NOTE:  Does not commit to the hardware; it sets appropriate bit fields
 719  * in the staging RXON flag structure based on the phymode
 720  */
 721 int iwl_set_rxon_channel(struct iwl_priv *priv,
 722                                 enum ieee80211_band band,
 723                                 u16 channel)
 724 {
 725         if (!iwl_get_channel_info(priv, band, channel)) {
 726                 IWL_DEBUG_INFO("Could not set channel to %d [%d]\n",
 727                                channel, band);
 728                 return -EINVAL;
 729         }
 730
 731         if ((le16_to_cpu(priv->staging_rxon.channel) == channel) &&
 732             (priv->band == band))
 733                 return 0;
 734
 735         priv->staging_rxon.channel = cpu_to_le16(channel);
 736         if (band == IEEE80211_BAND_5GHZ)
 737                 priv->staging_rxon.flags &= ~RXON_FLG_BAND_24G_MSK;
 738         else
 739                 priv->staging_rxon.flags |= RXON_FLG_BAND_24G_MSK;
 740
 741         priv->band = band;
 742
 743         IWL_DEBUG_INFO("Staging channel set to %d [%d]\n", channel, band);
 744
 745         return 0;
 746 }
 747 EXPORT_SYMBOL(iwl_set_rxon_channel);
 748
 749 int iwl_setup_mac(struct iwl_priv *priv)
 750 {
 751         int ret;
 752         struct ieee80211_hw *hw = priv->hw;
 753         hw->rate_control_algorithm = "iwl-4965-rs";
 754
 755         /* Tell mac80211 our characteristics */
 756         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
 757                     IEEE80211_HW_SIGNAL_DBM |
 758                     IEEE80211_HW_NOISE_DBM;
 759         /* Default value; 4 EDCA QOS priorities */
 760         hw->queues = 4;
 761         /* Enhanced value; more queues, to support 11n aggregation */
 762         hw->ampdu_queues = 12;
 763
 764         hw->conf.beacon_int = 100;
 765
 766         if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
 767                 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
 768                         &priv->bands[IEEE80211_BAND_2GHZ];
 769         if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
 770                 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
 771                         &priv->bands[IEEE80211_BAND_5GHZ];
 772
 773         ret = ieee80211_register_hw(priv->hw);
 774         if (ret) {
 775                 IWL_ERROR("Failed to register hw (error %d)\n", ret);
 776                 return ret;
 777         }
 778         priv->mac80211_registered = 1;
 779
 780         return 0;
 781 }
 782 EXPORT_SYMBOL(iwl_setup_mac);
 783
 784
 785 int iwl_init_drv(struct iwl_priv *priv)
 786 {
 787         int ret;
 788         int i;
 789
 790         priv->retry_rate = 1;
 791         priv->ibss_beacon = NULL;
 792
 793         spin_lock_init(&priv->lock);
 794         spin_lock_init(&priv->power_data.lock);
 795         spin_lock_init(&priv->sta_lock);
 796         spin_lock_init(&priv->hcmd_lock);
 797         spin_lock_init(&priv->lq_mngr.lock);
 798
 799         for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
 800                 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
 801
 802         INIT_LIST_HEAD(&priv->free_frames);
 803
 804         mutex_init(&priv->mutex);
 805
 806         /* Clear the driver's (not device's) station table */
 807         iwlcore_clear_stations_table(priv);
 808
 809         priv->data_retry_limit = -1;
 810         priv->ieee_channels = NULL;
 811         priv->ieee_rates = NULL;
 812         priv->band = IEEE80211_BAND_2GHZ;
 813
 814         priv->iw_mode = IEEE80211_IF_TYPE_STA;
 815
 816         priv->use_ant_b_for_management_frame = 1; /* start with ant B */
 817         priv->ps_mode = IWL_MIMO_PS_NONE;
 818
 819         /* Choose which receivers/antennas to use */
 820         iwl_set_rxon_chain(priv);
 821
 822         if (priv->cfg->mod_params->enable_qos)
 823                 priv->qos_data.qos_enable = 1;
 824
 825         iwl_reset_qos(priv);
 826
 827         priv->qos_data.qos_active = 0;
 828         priv->qos_data.qos_cap.val = 0;
 829
 830         iwl_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
 831
 832         priv->rates_mask = IWL_RATES_MASK;
 833         /* If power management is turned on, default to AC mode */
 834         priv->power_mode = IWL_POWER_AC;
 835         priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
 836
 837         ret = iwl_init_channel_map(priv);
 838         if (ret) {
 839                 IWL_ERROR("initializing regulatory failed: %d\n", ret);
 840                 goto err;
 841         }
 842
 843         ret = iwlcore_init_geos(priv);
 844         if (ret) {
 845                 IWL_ERROR("initializing geos failed: %d\n", ret);
 846                 goto err_free_channel_map;
 847         }
 848
 849         return 0;
 850
 851 err_free_channel_map:
 852         iwl_free_channel_map(priv);
 853 err:
 854         return ret;
 855 }
 856 EXPORT_SYMBOL(iwl_init_drv);
 857
 858 void iwl_free_calib_results(struct iwl_priv *priv)
 859 {
 860         kfree(priv->calib_results.lo_res);
 861         priv->calib_results.lo_res = NULL;
 862         priv->calib_results.lo_res_len = 0;
 863
 864         kfree(priv->calib_results.tx_iq_res);
 865         priv->calib_results.tx_iq_res = NULL;
 866         priv->calib_results.tx_iq_res_len = 0;
 867
 868         kfree(priv->calib_results.tx_iq_perd_res);
 869         priv->calib_results.tx_iq_perd_res = NULL;
 870         priv->calib_results.tx_iq_perd_res_len = 0;
 871 }
 872 EXPORT_SYMBOL(iwl_free_calib_results);
 873
 874 void iwl_uninit_drv(struct iwl_priv *priv)
 875 {
 876         iwl_free_calib_results(priv);
 877         iwlcore_free_geos(priv);
 878         iwl_free_channel_map(priv);
 879         kfree(priv->scan);
 880 }
 881 EXPORT_SYMBOL(iwl_uninit_drv);
 882
 883 /* Low level driver call this function to update iwlcore with
 884  * driver status.
 885  */
 886 int iwlcore_low_level_notify(struct iwl_priv *priv,
 887                               enum iwlcore_card_notify notify)
 888 {
 889         int ret;
 890         switch (notify) {
 891         case IWLCORE_INIT_EVT:
 892                 ret = iwl_rfkill_init(priv);
 893                 if (ret)
 894                         IWL_ERROR("Unable to initialize RFKILL system. "
 895                                   "Ignoring error: %d\n", ret);
 896                 iwl_power_initialize(priv);
 897                 break;
 898         case IWLCORE_START_EVT:
 899                 iwl_power_update_mode(priv, 1);
 900                 break;
 901         case IWLCORE_STOP_EVT:
 902                 break;
 903         case IWLCORE_REMOVE_EVT:
 904                 iwl_rfkill_unregister(priv);
 905                 break;
 906         }
 907
 908         return 0;
 909 }
 910 EXPORT_SYMBOL(iwlcore_low_level_notify);
 911
 912 int iwl_send_statistics_request(struct iwl_priv *priv, u8 flags)
 913 {
 914         u32 stat_flags = 0;
 915         struct iwl_host_cmd cmd = {
 916                 .id = REPLY_STATISTICS_CMD,
 917                 .meta.flags = flags,
 918                 .len = sizeof(stat_flags),
 919                 .data = (u8 *) &stat_flags,
 920         };
 921         return iwl_send_cmd(priv, &cmd);
 922 }
 923 EXPORT_SYMBOL(iwl_send_statistics_request);
 924
 925 /**
 926  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 927  *   using sample data 100 bytes apart.  If these sample points are good,
 928  *   it's a pretty good bet that everything between them is good, too.
 929  */
 930 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv, __le32 *image, u32 len)
 931 {
 932         u32 val;
 933         int ret = 0;
 934         u32 errcnt = 0;
 935         u32 i;
 936
 937         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
 938
 939         ret = iwl_grab_nic_access(priv);
 940         if (ret)
 941                 return ret;
 942
 943         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
 944                 /* read data comes through single port, auto-incr addr */
 945                 /* NOTE: Use the debugless read so we don't flood kernel log
 946                  * if IWL_DL_IO is set */
 947                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
 948                         i + RTC_INST_LOWER_BOUND);
 949                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 950                 if (val != le32_to_cpu(*image)) {
 951                         ret = -EIO;
 952                         errcnt++;
 953                         if (errcnt >= 3)
 954                                 break;
 955                 }
 956         }
 957
 958         iwl_release_nic_access(priv);
 959
 960         return ret;
 961 }
 962
 963 /**
 964  * iwlcore_verify_inst_full - verify runtime uCode image in card vs. host,
 965  *     looking at all data.
 966  */
 967 static int iwl_verify_inst_full(struct iwl_priv *priv, __le32 *image,
 968                                  u32 len)
 969 {
 970         u32 val;
 971         u32 save_len = len;
 972         int ret = 0;
 973         u32 errcnt;
 974
 975         IWL_DEBUG_INFO("ucode inst image size is %u\n", len);
 976
 977         ret = iwl_grab_nic_access(priv);
 978         if (ret)
 979                 return ret;
 980
 981         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, RTC_INST_LOWER_BOUND);
 982
 983         errcnt = 0;
 984         for (; len > 0; len -= sizeof(u32), image++) {
 985                 /* read data comes through single port, auto-incr addr */
 986                 /* NOTE: Use the debugless read so we don't flood kernel log
 987                  * if IWL_DL_IO is set */
 988                 val = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
 989                 if (val != le32_to_cpu(*image)) {
 990                         IWL_ERROR("uCode INST section is invalid at "
 991                                   "offset 0x%x, is 0x%x, s/b 0x%x\n",
 992                                   save_len - len, val, le32_to_cpu(*image));
 993                         ret = -EIO;
 994                         errcnt++;
 995                         if (errcnt >= 20)
 996                                 break;
 997                 }
 998         }
 999
1000         iwl_release_nic_access(priv);
1001
1002         if (!errcnt)
1003                 IWL_DEBUG_INFO
1004                     ("ucode image in INSTRUCTION memory is good\n");
1005
1006         return ret;
1007 }
1008
1009 /**
1010  * iwl_verify_ucode - determine which instruction image is in SRAM,
1011  *    and verify its contents
1012  */
1013 int iwl_verify_ucode(struct iwl_priv *priv)
1014 {
1015         __le32 *image;
1016         u32 len;
1017         int ret;
1018
1019         /* Try bootstrap */
1020         image = (__le32 *)priv->ucode_boot.v_addr;
1021         len = priv->ucode_boot.len;
1022         ret = iwlcore_verify_inst_sparse(priv, image, len);
1023         if (!ret) {
1024                 IWL_DEBUG_INFO("Bootstrap uCode is good in inst SRAM\n");
1025                 return 0;
1026         }
1027
1028         /* Try initialize */
1029         image = (__le32 *)priv->ucode_init.v_addr;
1030         len = priv->ucode_init.len;
1031         ret = iwlcore_verify_inst_sparse(priv, image, len);
1032         if (!ret) {
1033                 IWL_DEBUG_INFO("Initialize uCode is good in inst SRAM\n");
1034                 return 0;
1035         }
1036
1037         /* Try runtime/protocol */
1038         image = (__le32 *)priv->ucode_code.v_addr;
1039         len = priv->ucode_code.len;
1040         ret = iwlcore_verify_inst_sparse(priv, image, len);
1041         if (!ret) {
1042                 IWL_DEBUG_INFO("Runtime uCode is good in inst SRAM\n");
1043                 return 0;
1044         }
1045
1046         IWL_ERROR("NO VALID UCODE IMAGE IN INSTRUCTION SRAM!!\n");
1047
1048         /* Since nothing seems to match, show first several data entries in
1049          * instruction SRAM, so maybe visual inspection will give a clue.
1050          * Selection of bootstrap image (vs. other images) is arbitrary. */
1051         image = (__le32 *)priv->ucode_boot.v_addr;
1052         len = priv->ucode_boot.len;
1053         ret = iwl_verify_inst_full(priv, image, len);
1054
1055         return ret;
1056 }
1057 EXPORT_SYMBOL(iwl_verify_ucode);
1058
1059
1060 static const char *desc_lookup(int i)
1061 {
1062         switch (i) {
1063         case 1:
1064                 return "FAIL";
1065         case 2:
1066                 return "BAD_PARAM";
1067         case 3:
1068                 return "BAD_CHECKSUM";
1069         case 4:
1070                 return "NMI_INTERRUPT";
1071         case 5:
1072                 return "SYSASSERT";
1073         case 6:
1074                 return "FATAL_ERROR";
1075         }
1076
1077         return "UNKNOWN";
1078 }
1079
1080 #define ERROR_START_OFFSET  (1 * sizeof(u32))
1081 #define ERROR_ELEM_SIZE     (7 * sizeof(u32))
1082
1083 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1084 {
1085         u32 data2, line;
1086         u32 desc, time, count, base, data1;
1087         u32 blink1, blink2, ilink1, ilink2;
1088         int ret;
1089
1090         if (priv->ucode_type == UCODE_INIT)
1091                 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1092         else
1093                 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1094
1095         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1096                 IWL_ERROR("Not valid error log pointer 0x%08X\n", base);
1097                 return;
1098         }
1099
1100         ret = iwl_grab_nic_access(priv);
1101         if (ret) {
1102                 IWL_WARNING("Can not read from adapter at this time.\n");
1103                 return;
1104         }
1105
1106         count = iwl_read_targ_mem(priv, base);
1107
1108         if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1109                 IWL_ERROR("Start IWL Error Log Dump:\n");
1110                 IWL_ERROR("Status: 0x%08lX, count: %d\n", priv->status, count);
1111         }
1112
1113         desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1114         blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1115         blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1116         ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1117         ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1118         data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1119         data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1120         line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1121         time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1122
1123         IWL_ERROR("Desc        Time       "
1124                 "data1      data2      line\n");
1125         IWL_ERROR("%-13s (#%d) %010u 0x%08X 0x%08X %u\n",
1126                 desc_lookup(desc), desc, time, data1, data2, line);
1127         IWL_ERROR("blink1  blink2  ilink1  ilink2\n");
1128         IWL_ERROR("0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1129                 ilink1, ilink2);
1130
1131         iwl_release_nic_access(priv);
1132 }
1133 EXPORT_SYMBOL(iwl_dump_nic_error_log);
1134
1135 #define EVENT_START_OFFSET  (4 * sizeof(u32))
1136
1137 /**
1138  * iwl_print_event_log - Dump error event log to syslog
1139  *
1140  * NOTE: Must be called with iwl4965_grab_nic_access() already obtained!
1141  */
1142 void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1143                                 u32 num_events, u32 mode)
1144 {
1145         u32 i;
1146         u32 base;       /* SRAM byte address of event log header */
1147         u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1148         u32 ptr;        /* SRAM byte address of log data */
1149         u32 ev, time, data; /* event log data */
1150
1151         if (num_events == 0)
1152                 return;
1153         if (priv->ucode_type == UCODE_INIT)
1154                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1155         else
1156                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1157
1158         if (mode == 0)
1159                 event_size = 2 * sizeof(u32);
1160         else
1161                 event_size = 3 * sizeof(u32);
1162
1163         ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1164
1165         /* "time" is actually "data" for mode 0 (no timestamp).
1166         * place event id # at far right for easier visual parsing. */
1167         for (i = 0; i < num_events; i++) {
1168                 ev = iwl_read_targ_mem(priv, ptr);
1169                 ptr += sizeof(u32);
1170                 time = iwl_read_targ_mem(priv, ptr);
1171                 ptr += sizeof(u32);
1172                 if (mode == 0) {
1173                         /* data, ev */
1174                         IWL_ERROR("EVT_LOG:0x%08x:%04u\n", time, ev);
1175                 } else {
1176                         data = iwl_read_targ_mem(priv, ptr);
1177                         ptr += sizeof(u32);
1178                         IWL_ERROR("EVT_LOGT:%010u:0x%08x:%04u\n",
1179                                         time, data, ev);
1180                 }
1181         }
1182 }
1183 EXPORT_SYMBOL(iwl_print_event_log);
1184
1185
1186 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1187 {
1188         int ret;
1189         u32 base;       /* SRAM byte address of event log header */
1190         u32 capacity;   /* event log capacity in # entries */
1191         u32 mode;       /* 0 - no timestamp, 1 - timestamp recorded */
1192         u32 num_wraps;  /* # times uCode wrapped to top of log */
1193         u32 next_entry; /* index of next entry to be written by uCode */
1194         u32 size;       /* # entries that we'll print */
1195
1196         if (priv->ucode_type == UCODE_INIT)
1197                 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1198         else
1199                 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1200
1201         if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1202                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
1203                 return;
1204         }
1205
1206         ret = iwl_grab_nic_access(priv);
1207         if (ret) {
1208                 IWL_WARNING("Can not read from adapter at this time.\n");
1209                 return;
1210         }
1211
1212         /* event log header */
1213         capacity = iwl_read_targ_mem(priv, base);
1214         mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1215         num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1216         next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1217
1218         size = num_wraps ? capacity : next_entry;
1219
1220         /* bail out if nothing in log */
1221         if (size == 0) {
1222                 IWL_ERROR("Start IWL Event Log Dump: nothing in log\n");
1223                 iwl_release_nic_access(priv);
1224                 return;
1225         }
1226
1227         IWL_ERROR("Start IWL Event Log Dump: display count %d, wraps %d\n",
1228                         size, num_wraps);
1229
1230         /* if uCode has wrapped back to top of log, start at the oldest entry,
1231          * i.e the next one that uCode would fill. */
1232         if (num_wraps)
1233                 iwl_print_event_log(priv, next_entry,
1234                                         capacity - next_entry, mode);
1235         /* (then/else) start at top of log */
1236         iwl_print_event_log(priv, 0, next_entry, mode);
1237
1238         iwl_release_nic_access(priv);
1239 }
1240 EXPORT_SYMBOL(iwl_dump_nic_event_log);
1241
1242