1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62 *****************************************************************************/
64 #ifndef __iwl_4965_hw_h__
65 #define __iwl_4965_hw_h__
67 /* uCode queue management definitions */
68 #define IWL_CMD_QUEUE_NUM 4
69 #define IWL_CMD_FIFO_NUM 4
70 #define IWL_BACK_QUEUE_FIRST_ID 7
73 #define IWL_CCK_RATES 4
74 #define IWL_OFDM_RATES 8
76 #define IWL_HT_RATES 16
78 #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
81 #define SHORT_SLOT_TIME 9
82 #define LONG_SLOT_TIME 20
85 #define IWL_RSSI_OFFSET 44
88 * This file defines EEPROM related constants, enums, and inline functions.
92 #define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
93 #define IWL_EEPROM_ACCESS_DELAY 10 /* uSec */
94 /* EEPROM field values */
95 #define ANTENNA_SWITCH_NORMAL 0
96 #define ANTENNA_SWITCH_INVERSE 1
99 EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
100 EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
102 EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
103 EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
104 EEPROM_CHANNEL_WIDE = (1 << 5),
105 EEPROM_CHANNEL_NARROW = (1 << 6),
106 EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
109 /* EEPROM field lengths */
110 #define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
112 /* EEPROM field lengths */
113 #define EEPROM_BOARD_PBA_NUMBER_LENGTH 11
114 #define EEPROM_REGULATORY_SKU_ID_LENGTH 4
115 #define EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH 14
116 #define EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH 13
117 #define EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH 12
118 #define EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH 11
119 #define EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH 6
121 #define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS_LENGTH 7
122 #define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS_LENGTH 11
123 #define EEPROM_REGULATORY_CHANNELS_LENGTH ( \
124 EEPROM_REGULATORY_BAND1_CHANNELS_LENGTH + \
125 EEPROM_REGULATORY_BAND2_CHANNELS_LENGTH + \
126 EEPROM_REGULATORY_BAND3_CHANNELS_LENGTH + \
127 EEPROM_REGULATORY_BAND4_CHANNELS_LENGTH + \
128 EEPROM_REGULATORY_BAND5_CHANNELS_LENGTH + \
129 EEPROM_REGULATORY_BAND_24_FAT_CHANNELS_LENGTH + \
130 EEPROM_REGULATORY_BAND_52_FAT_CHANNELS_LENGTH)
132 #define EEPROM_REGULATORY_NUMBER_OF_BANDS 5
134 /* SKU Capabilities */
135 #define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
136 #define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
137 #define EEPROM_SKU_CAP_OP_MODE_MRC (1 << 7)
139 /* *regulatory* channel data from eeprom, one for each channel */
140 struct iwl_eeprom_channel {
141 u8 flags; /* flags copied from EEPROM */
142 s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
143 } __attribute__ ((packed));
146 * Mapping of a Tx power level, at factory calibration temperature,
147 * to a radio/DSP gain table index.
148 * One for each of 5 "sample" power levels in each band.
149 * v_det is measured at the factory, using the 3945's built-in power amplifier
150 * (PA) output voltage detector. This same detector is used during Tx of
151 * long packets in normal operation to provide feedback as to proper output
153 * Data copied from EEPROM.
155 struct iwl_eeprom_txpower_sample {
156 u8 gain_index; /* index into power (gain) setup table ... */
157 s8 power; /* ... for this pwr level for this chnl group */
158 u16 v_det; /* PA output voltage */
159 } __attribute__ ((packed));
162 * Mappings of Tx power levels -> nominal radio/DSP gain table indexes.
163 * One for each channel group (a.k.a. "band") (1 for BG, 4 for A).
164 * Tx power setup code interpolates between the 5 "sample" power levels
165 * to determine the nominal setup for a requested power level.
166 * Data copied from EEPROM.
167 * DO NOT ALTER THIS STRUCTURE!!!
169 struct iwl_eeprom_txpower_group {
170 struct iwl_eeprom_txpower_sample samples[5]; /* 5 power levels */
171 s32 a, b, c, d, e; /* coefficients for voltage->power
172 * formula (signed) */
173 s32 Fa, Fb, Fc, Fd, Fe; /* these modify coeffs based on
174 * frequency (signed) */
175 s8 saturation_power; /* highest power possible by h/w in this
177 u8 group_channel; /* "representative" channel # in this band */
178 s16 temperature; /* h/w temperature at factory calib this band
180 } __attribute__ ((packed));
183 * Temperature-based Tx-power compensation data, not band-specific.
184 * These coefficients are use to modify a/b/c/d/e coeffs based on
185 * difference between current temperature and factory calib temperature.
186 * Data copied from EEPROM.
188 struct iwl_eeprom_temperature_corr {
194 } __attribute__ ((packed));
196 #define EEPROM_TX_POWER_TX_CHAINS (2)
197 #define EEPROM_TX_POWER_BANDS (8)
198 #define EEPROM_TX_POWER_MEASUREMENTS (3)
199 #define EEPROM_TX_POWER_VERSION (2)
200 #define EEPROM_TX_POWER_VERSION_NEW (5)
202 struct iwl_eeprom_calib_measure {
207 } __attribute__ ((packed));
209 struct iwl_eeprom_calib_ch_info {
211 struct iwl_eeprom_calib_measure measurements[EEPROM_TX_POWER_TX_CHAINS]
212 [EEPROM_TX_POWER_MEASUREMENTS];
213 } __attribute__ ((packed));
215 struct iwl_eeprom_calib_subband_info {
218 struct iwl_eeprom_calib_ch_info ch1;
219 struct iwl_eeprom_calib_ch_info ch2;
220 } __attribute__ ((packed));
222 struct iwl_eeprom_calib_info {
223 u8 saturation_power24;
224 u8 saturation_power52;
225 s16 voltage; /* signed */
226 struct iwl_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
227 } __attribute__ ((packed));
232 #define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
233 u16 device_id; /* abs.ofs: 16 */
235 #define EEPROM_PMC (2*0x0A) /* 2 bytes */
236 u16 pmc; /* abs.ofs: 20 */
238 #define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
239 u8 mac_address[6]; /* abs.ofs: 42 */
241 #define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
242 u16 board_revision; /* abs.ofs: 106 */
244 #define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
245 u8 board_pba_number[9]; /* abs.ofs: 119 */
247 #define EEPROM_VERSION (2*0x44) /* 2 bytes */
248 u16 version; /* abs.ofs: 136 */
249 #define EEPROM_SKU_CAP (2*0x45) /* 1 bytes */
250 u8 sku_cap; /* abs.ofs: 138 */
251 #define EEPROM_LEDS_MODE (2*0x45+1) /* 1 bytes */
252 u8 leds_mode; /* abs.ofs: 139 */
253 #define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
255 #define EEPROM_WOWLAN_MODE (2*0x47) /* 2 bytes */
256 u16 wowlan_mode; /* abs.ofs: 142 */
257 #define EEPROM_LEDS_TIME_INTERVAL (2*0x48) /* 2 bytes */
258 u16 leds_time_interval; /* abs.ofs: 144 */
259 #define EEPROM_LEDS_OFF_TIME (2*0x49) /* 1 bytes */
260 u8 leds_off_time; /* abs.ofs: 146 */
261 #define EEPROM_LEDS_ON_TIME (2*0x49+1) /* 1 bytes */
262 u8 leds_on_time; /* abs.ofs: 147 */
263 #define EEPROM_ALMGOR_M_VERSION (2*0x4A) /* 1 bytes */
264 u8 almgor_m_version; /* abs.ofs: 148 */
265 #define EEPROM_ANTENNA_SWITCH_TYPE (2*0x4A+1) /* 1 bytes */
266 u8 antenna_switch_type; /* abs.ofs: 149 */
268 #define EEPROM_4965_BOARD_REVISION (2*0x4F) /* 2 bytes */
269 u16 board_revision_4965; /* abs.ofs: 158 */
271 #define EEPROM_4965_BOARD_PBA (2*0x56+1) /* 9 bytes */
272 u8 board_pba_number_4965[9]; /* abs.ofs: 173 */
274 #define EEPROM_REGULATORY_SKU_ID (2*0x60) /* 4 bytes */
275 u8 sku_id[4]; /* abs.ofs: 192 */
276 #define EEPROM_REGULATORY_BAND_1 (2*0x62) /* 2 bytes */
277 u16 band_1_count; /* abs.ofs: 196 */
278 #define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63) /* 28 bytes */
279 struct iwl_eeprom_channel band_1_channels[14]; /* abs.ofs: 196 */
280 #define EEPROM_REGULATORY_BAND_2 (2*0x71) /* 2 bytes */
281 u16 band_2_count; /* abs.ofs: 226 */
282 #define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72) /* 26 bytes */
283 struct iwl_eeprom_channel band_2_channels[13]; /* abs.ofs: 228 */
284 #define EEPROM_REGULATORY_BAND_3 (2*0x7F) /* 2 bytes */
285 u16 band_3_count; /* abs.ofs: 254 */
286 #define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80) /* 24 bytes */
287 struct iwl_eeprom_channel band_3_channels[12]; /* abs.ofs: 256 */
288 #define EEPROM_REGULATORY_BAND_4 (2*0x8C) /* 2 bytes */
289 u16 band_4_count; /* abs.ofs: 280 */
290 #define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D) /* 22 bytes */
291 struct iwl_eeprom_channel band_4_channels[11]; /* abs.ofs: 282 */
292 #define EEPROM_REGULATORY_BAND_5 (2*0x98) /* 2 bytes */
293 u16 band_5_count; /* abs.ofs: 304 */
294 #define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99) /* 12 bytes */
295 struct iwl_eeprom_channel band_5_channels[6]; /* abs.ofs: 306 */
298 #define EEPROM_REGULATORY_BAND_24_FAT_CHANNELS (2*0xA0) /* 14 bytes */
299 struct iwl_eeprom_channel band_24_channels[7]; /* abs.ofs: 320 */
301 #define EEPROM_REGULATORY_BAND_52_FAT_CHANNELS (2*0xA8) /* 22 bytes */
302 struct iwl_eeprom_channel band_52_channels[11]; /* abs.ofs: 336 */
304 #define EEPROM_CALIB_VERSION_OFFSET (2*0xB6) /* 2 bytes */
305 u16 calib_version; /* abs.ofs: 364 */
307 #define EEPROM_SATURATION_POWER_OFFSET (2*0xB8) /* 2 bytes */
308 u16 satruation_power; /* abs.ofs: 368 */
310 #define EEPROM_IWL_CALIB_TXPOWER_OFFSET (2*0xE8) /* 48 bytes */
311 struct iwl_eeprom_calib_info calib_info; /* abs.ofs: 464 */
313 u8 reserved16[140]; /* fill out to full 1024 byte block */
316 } __attribute__ ((packed));
318 #define IWL_EEPROM_IMAGE_SIZE 1024
321 #include "iwl-4965-commands.h"
323 #define PCI_LINK_CTRL 0x0F0
324 #define PCI_POWER_SOURCE 0x0C8
325 #define PCI_REG_WUM8 0x0E8
326 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
328 /*=== CSR (control and status registers) ===*/
329 #define CSR_BASE (0x000)
331 #define CSR_SW_VER (CSR_BASE+0x000)
332 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
333 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
334 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
335 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
336 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
337 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
338 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
339 #define CSR_GP_CNTRL (CSR_BASE+0x024)
340 #define CSR_HW_REV (CSR_BASE+0x028)
341 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
342 #define CSR_EEPROM_GP (CSR_BASE+0x030)
343 #define CSR_GP_UCODE (CSR_BASE+0x044)
344 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
345 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
346 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
347 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
348 #define CSR_LED_REG (CSR_BASE+0x094)
349 #define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0)
350 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
351 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
352 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
354 /* HW I/F configuration */
355 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
356 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
357 #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
358 #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
359 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
360 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
361 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
363 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
364 * acknowledged (reset) by host writing "1" to flagged bits. */
365 #define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
366 #define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */
367 #define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */
368 #define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */
369 #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
370 #define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */
371 #define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */
372 #define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */
373 #define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */
374 #define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */
375 #define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */
377 #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
378 CSR_INT_BIT_HW_ERR | \
379 CSR_INT_BIT_FH_TX | \
380 CSR_INT_BIT_SW_ERR | \
381 CSR_INT_BIT_RF_KILL | \
382 CSR_INT_BIT_SW_RX | \
383 CSR_INT_BIT_WAKEUP | \
386 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
387 #define CSR_FH_INT_BIT_ERR (1<<31) /* Error */
388 #define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */
389 #define CSR_FH_INT_BIT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
390 #define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */
391 #define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */
392 #define CSR_FH_INT_BIT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
393 #define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */
394 #define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */
396 #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
397 CSR_FH_INT_BIT_RX_CHNL2 | \
398 CSR_FH_INT_BIT_RX_CHNL1 | \
399 CSR_FH_INT_BIT_RX_CHNL0)
401 #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
402 CSR_FH_INT_BIT_TX_CHNL1 | \
403 CSR_FH_INT_BIT_TX_CHNL0 )
407 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
408 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
409 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
410 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
411 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
413 /* GP (general purpose) CONTROL */
414 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
415 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
416 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
417 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
419 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
421 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
422 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
423 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
427 #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
428 #define CSR_EEPROM_REG_BIT_CMD (0x00000002)
431 #define CSR_EEPROM_GP_VALID_MSK (0x00000006)
432 #define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
433 #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
436 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
437 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
438 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
439 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
442 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
443 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
444 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
446 /* GI Chicken Bits */
447 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
448 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
450 /* CSR_ANA_PLL_CFG */
451 #define CSR_ANA_PLL_CFG_SH (0x00880300)
453 #define CSR_LED_REG_TRUN_ON (0x00000078)
454 #define CSR_LED_REG_TRUN_OFF (0x00000038)
455 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
457 /* DRAM_INT_TBL_CTRL */
458 #define CSR_DRAM_INT_TBL_CTRL_EN (1<<31)
459 #define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27)
461 /*=== HBUS (Host-side Bus) ===*/
462 #define HBUS_BASE (0x400)
464 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
465 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
466 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
467 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
468 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
469 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
470 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
471 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
472 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
474 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
477 /* SCD (Scheduler) */
478 #define SCD_BASE (CSR_BASE + 0x2E00)
480 #define SCD_MODE_REG (SCD_BASE + 0x000)
481 #define SCD_ARASTAT_REG (SCD_BASE + 0x004)
482 #define SCD_TXFACT_REG (SCD_BASE + 0x010)
483 #define SCD_TXF4MF_REG (SCD_BASE + 0x014)
484 #define SCD_TXF5MF_REG (SCD_BASE + 0x020)
485 #define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
486 #define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
488 /*=== FH (data Flow Handler) ===*/
489 #define FH_BASE (0x800)
491 #define FH_CBCC_TABLE (FH_BASE+0x140)
492 #define FH_TFDB_TABLE (FH_BASE+0x180)
493 #define FH_RCSR_TABLE (FH_BASE+0x400)
494 #define FH_RSSR_TABLE (FH_BASE+0x4c0)
495 #define FH_TCSR_TABLE (FH_BASE+0x500)
496 #define FH_TSSR_TABLE (FH_BASE+0x680)
498 /* TFDB (Transmit Frame Buffer Descriptor) */
499 #define FH_TFDB(_channel, buf) \
500 (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
501 #define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
502 (FH_TFDB_TABLE + 0x50 * _channel)
503 /* CBCC _channel is [0,2] */
504 #define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
505 #define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
506 #define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
508 /* RCSR _channel is [0,2] */
509 #define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
510 #define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
511 #define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
512 #define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
513 #define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
515 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
518 #define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
519 #define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
521 #define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
522 #define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
523 #define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
524 #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
526 #define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
527 #define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
528 #define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
531 /* card static random access memory (SRAM) for processor data and instructs */
532 #define RTC_INST_LOWER_BOUND (0x000000)
533 #define RTC_DATA_LOWER_BOUND (0x800000)
538 #define ALM_FH_SRVC_CHNL (6)
540 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
541 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
543 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
545 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
547 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
549 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
551 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
553 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
555 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
556 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
558 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
559 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
561 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
563 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
565 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
566 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
568 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
570 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
572 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
573 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
575 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
577 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
578 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
580 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
581 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
583 #define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
585 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
586 ((1LU << _channel) << 24)
587 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
588 ((1LU << _channel) << 16)
590 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
591 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
592 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
593 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
594 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
596 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
598 #define TFD_QUEUE_MIN 0
599 #define TFD_QUEUE_MAX 6
600 #define TFD_QUEUE_SIZE_MAX (256)
602 /* spectrum and channel data structures */
603 #define IWL_NUM_SCAN_RATES (2)
605 #define IWL_SCAN_FLAG_24GHZ (1<<0)
606 #define IWL_SCAN_FLAG_52GHZ (1<<1)
607 #define IWL_SCAN_FLAG_ACTIVE (1<<2)
608 #define IWL_SCAN_FLAG_DIRECT (1<<3)
610 #define IWL_MAX_CMD_SIZE 1024
612 #define IWL_DEFAULT_TX_RETRY 15
613 #define IWL_MAX_TX_RETRY 16
615 /*********************************************/
618 #define NUM_TFD_CHUNKS 4
620 #define RX_QUEUE_SIZE 256
621 #define RX_QUEUE_MASK 255
622 #define RX_QUEUE_SIZE_LOG 8
624 /* QoS definitions */
626 #define CW_MIN_OFDM 15
627 #define CW_MAX_OFDM 1023
628 #define CW_MIN_CCK 31
629 #define CW_MAX_CCK 1023
631 #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
632 #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
633 #define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
634 #define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
636 #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
637 #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
638 #define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
639 #define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
641 #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
642 #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
643 #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
644 #define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
646 #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
647 #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
648 #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
649 #define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
651 #define QOS_TX0_AIFS 3
652 #define QOS_TX1_AIFS 7
653 #define QOS_TX2_AIFS 2
654 #define QOS_TX3_AIFS 2
656 #define QOS_TX0_ACM 0
657 #define QOS_TX1_ACM 0
658 #define QOS_TX2_ACM 0
659 #define QOS_TX3_ACM 0
661 #define QOS_TX0_TXOP_LIMIT_CCK 0
662 #define QOS_TX1_TXOP_LIMIT_CCK 0
663 #define QOS_TX2_TXOP_LIMIT_CCK 6016
664 #define QOS_TX3_TXOP_LIMIT_CCK 3264
666 #define QOS_TX0_TXOP_LIMIT_OFDM 0
667 #define QOS_TX1_TXOP_LIMIT_OFDM 0
668 #define QOS_TX2_TXOP_LIMIT_OFDM 3008
669 #define QOS_TX3_TXOP_LIMIT_OFDM 1504
671 #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
672 #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
673 #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
674 #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
676 #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
677 #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
678 #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
679 #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
681 #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
682 #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
683 #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
684 #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
686 #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
687 #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
688 #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
689 #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
691 #define DEF_TX0_AIFS (2)
692 #define DEF_TX1_AIFS (2)
693 #define DEF_TX2_AIFS (2)
694 #define DEF_TX3_AIFS (2)
696 #define DEF_TX0_ACM 0
697 #define DEF_TX1_ACM 0
698 #define DEF_TX2_ACM 0
699 #define DEF_TX3_ACM 0
701 #define DEF_TX0_TXOP_LIMIT_CCK 0
702 #define DEF_TX1_TXOP_LIMIT_CCK 0
703 #define DEF_TX2_TXOP_LIMIT_CCK 0
704 #define DEF_TX3_TXOP_LIMIT_CCK 0
706 #define DEF_TX0_TXOP_LIMIT_OFDM 0
707 #define DEF_TX1_TXOP_LIMIT_OFDM 0
708 #define DEF_TX2_TXOP_LIMIT_OFDM 0
709 #define DEF_TX3_TXOP_LIMIT_OFDM 0
711 #define QOS_QOS_SETS 3
712 #define QOS_PARAM_SET_ACTIVE 0
713 #define QOS_PARAM_SET_DEF_CCK 1
714 #define QOS_PARAM_SET_DEF_OFDM 2
716 #define CTRL_QOS_NO_ACK (0x0020)
717 #define DCT_FLAG_EXT_QOS_ENABLED (0x10)
719 #define U32_PAD(n) ((4-(n))&0x3)
722 * Generic queue structure
724 * Contains common data for Rx and Tx queues
726 #define TFD_CTL_COUNT_SET(n) (n<<24)
727 #define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7)
728 #define TFD_CTL_PAD_SET(n) (n<<28)
729 #define TFD_CTL_PAD_GET(ctl) (ctl>>28)
731 #define TFD_TX_CMD_SLOTS 256
732 #define TFD_CMD_SLOTS 32
734 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
735 sizeof(struct iwl_cmd_meta))
738 * RX related structures and functions
740 #define RX_FREE_BUFFERS 64
741 #define RX_LOW_WATERMARK 8
744 #define IWL_RX_BUF_SIZE (4 * 1024)
745 #define IWL_MAX_BSM_SIZE BSM_SRAM_SIZE
746 #define KDR_RTC_INST_UPPER_BOUND (0x018000)
747 #define KDR_RTC_DATA_UPPER_BOUND (0x80A000)
748 #define KDR_RTC_INST_SIZE (KDR_RTC_INST_UPPER_BOUND - RTC_INST_LOWER_BOUND)
749 #define KDR_RTC_DATA_SIZE (KDR_RTC_DATA_UPPER_BOUND - RTC_DATA_LOWER_BOUND)
751 #define IWL_MAX_INST_SIZE KDR_RTC_INST_SIZE
752 #define IWL_MAX_DATA_SIZE KDR_RTC_DATA_SIZE
754 static inline int iwl_hw_valid_rtc_data_addr(u32 addr)
756 return (addr >= RTC_DATA_LOWER_BOUND) &&
757 (addr < KDR_RTC_DATA_UPPER_BOUND);
760 /********************* START TXPOWER *****************************************/
762 HT_IE_EXT_CHANNEL_NONE = 0,
763 HT_IE_EXT_CHANNEL_ABOVE,
764 HT_IE_EXT_CHANNEL_INVALID,
765 HT_IE_EXT_CHANNEL_BELOW,
766 HT_IE_EXT_CHANNEL_MAX
770 CALIB_CH_GROUP_1 = 0,
771 CALIB_CH_GROUP_2 = 1,
772 CALIB_CH_GROUP_3 = 2,
773 CALIB_CH_GROUP_4 = 3,
774 CALIB_CH_GROUP_5 = 4,
778 /* Temperature calibration offset is 3% 0C in Kelvin */
779 #define TEMPERATURE_CALIB_KELVIN_OFFSET 8
780 #define TEMPERATURE_CALIB_A_VAL 259
782 #define IWL_TX_POWER_TEMPERATURE_MIN (263)
783 #define IWL_TX_POWER_TEMPERATURE_MAX (410)
785 #define IWL_TX_POWER_TEMPERATURE_OUT_OF_RANGE(t) \
786 (((t) < IWL_TX_POWER_TEMPERATURE_MIN) || \
787 ((t) > IWL_TX_POWER_TEMPERATURE_MAX))
789 #define IWL_TX_POWER_ILLEGAL_TEMPERATURE (300)
791 #define IWL_TX_POWER_TEMPERATURE_DIFFERENCE (2)
793 #define IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION (6)
795 #define IWL_TX_POWER_TARGET_POWER_MIN (0) /* 0 dBm = 1 milliwatt */
796 #define IWL_TX_POWER_TARGET_POWER_MAX (16) /* 16 dBm */
798 /* timeout equivalent to 3 minutes */
799 #define IWL_TX_POWER_TIMELIMIT_NOCALIB 1800000000
801 #define IWL_TX_POWER_CCK_COMPENSATION (9)
803 #define MIN_TX_GAIN_INDEX (0)
804 #define MIN_TX_GAIN_INDEX_52GHZ_EXT (-9)
805 #define MAX_TX_GAIN_INDEX_52GHZ (98)
806 #define MIN_TX_GAIN_52GHZ (98)
807 #define MAX_TX_GAIN_INDEX_24GHZ (98)
808 #define MIN_TX_GAIN_24GHZ (98)
809 #define MAX_TX_GAIN (0)
810 #define MAX_TX_GAIN_52GHZ_EXT (-9)
812 #define IWL_TX_POWER_DEFAULT_REGULATORY_24 (34)
813 #define IWL_TX_POWER_DEFAULT_REGULATORY_52 (34)
814 #define IWL_TX_POWER_REGULATORY_MIN (0)
815 #define IWL_TX_POWER_REGULATORY_MAX (34)
816 #define IWL_TX_POWER_DEFAULT_SATURATION_24 (38)
817 #define IWL_TX_POWER_DEFAULT_SATURATION_52 (38)
818 #define IWL_TX_POWER_SATURATION_MIN (20)
819 #define IWL_TX_POWER_SATURATION_MAX (50)
821 /* dv *0.4 = dt; so that 5 degrees temperature diff equals
822 * 12.5 in voltage diff */
823 #define IWL_TX_TEMPERATURE_UPDATE_LIMIT 9
825 #define IWL_INVALID_CHANNEL (0xffffffff)
826 #define IWL_TX_POWER_REGITRY_BIT (2)
828 #define MIN_IWL_TX_POWER_CALIB_DUR (100)
829 #define IWL_CCK_FROM_OFDM_POWER_DIFF (-5)
830 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (9)
832 /* Number of entries in the gain table */
833 #define POWER_GAIN_NUM_ENTRIES 78
834 #define TX_POW_MAX_SESSION_NUM 5
835 /* timeout equivalent to 3 minutes */
836 #define TX_IWL_TIMELIMIT_NOCALIB 1800000000
838 /* Kedron TX_CALIB_STATES */
839 #define IWL_TX_CALIB_STATE_SEND_TX 0x00000001
840 #define IWL_TX_CALIB_WAIT_TX_RESPONSE 0x00000002
841 #define IWL_TX_CALIB_ENABLED 0x00000004
842 #define IWL_TX_CALIB_XVT_ON 0x00000008
843 #define IWL_TX_CALIB_TEMPERATURE_CORRECT 0x00000010
844 #define IWL_TX_CALIB_WORKING_WITH_XVT 0x00000020
845 #define IWL_TX_CALIB_XVT_PERIODICAL 0x00000040
847 #define NUM_IWL_TX_CALIB_SETTINS 5 /* Number of tx correction groups */
849 #define IWL_MIN_POWER_IN_VP_TABLE 1 /* 0.5dBm multiplied by 2 */
850 #define IWL_MAX_POWER_IN_VP_TABLE 40 /* 20dBm - multiplied by 2 (because
851 * entries are for each 0.5dBm) */
852 #define IWL_STEP_IN_VP_TABLE 1 /* 0.5dB - multiplied by 2 */
853 #define IWL_NUM_POINTS_IN_VPTABLE \
854 (1 + IWL_MAX_POWER_IN_VP_TABLE - IWL_MIN_POWER_IN_VP_TABLE)
856 #define MIN_TX_GAIN_INDEX (0)
857 #define MAX_TX_GAIN_INDEX_52GHZ (98)
858 #define MIN_TX_GAIN_52GHZ (98)
859 #define MAX_TX_GAIN_INDEX_24GHZ (98)
860 #define MIN_TX_GAIN_24GHZ (98)
861 #define MAX_TX_GAIN (0)
863 /* First and last channels of all groups */
864 #define CALIB_IWL_TX_ATTEN_GR1_FCH 34
865 #define CALIB_IWL_TX_ATTEN_GR1_LCH 43
866 #define CALIB_IWL_TX_ATTEN_GR2_FCH 44
867 #define CALIB_IWL_TX_ATTEN_GR2_LCH 70
868 #define CALIB_IWL_TX_ATTEN_GR3_FCH 71
869 #define CALIB_IWL_TX_ATTEN_GR3_LCH 124
870 #define CALIB_IWL_TX_ATTEN_GR4_FCH 125
871 #define CALIB_IWL_TX_ATTEN_GR4_LCH 200
872 #define CALIB_IWL_TX_ATTEN_GR5_FCH 1
873 #define CALIB_IWL_TX_ATTEN_GR5_LCH 20
876 union iwl_tx_power_dual_stream {
879 u8 dsp_predis_atten[2];
884 /********************* END TXPOWER *****************************************/
887 #define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
888 #define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK __constant_cpu_to_le32(0x1<<22)
890 #define RXON_FLG_HT_OPERATING_MODE_POS (23)
892 #define RXON_FLG_HT_PROT_MSK __constant_cpu_to_le32(0x1<<23)
893 #define RXON_FLG_FAT_PROT_MSK __constant_cpu_to_le32(0x2<<23)
895 #define RXON_FLG_CHANNEL_MODE_POS (25)
896 #define RXON_FLG_CHANNEL_MODE_MSK __constant_cpu_to_le32(0x3<<25)
897 #define RXON_FLG_CHANNEL_MODE_PURE_40_MSK __constant_cpu_to_le32(0x1<<25)
898 #define RXON_FLG_CHANNEL_MODE_MIXED_MSK __constant_cpu_to_le32(0x2<<25)
900 #define RXON_RX_CHAIN_DRIVER_FORCE_MSK __constant_cpu_to_le16(0x1<<0)
901 #define RXON_RX_CHAIN_VALID_MSK __constant_cpu_to_le16(0x7<<1)
902 #define RXON_RX_CHAIN_VALID_POS (1)
903 #define RXON_RX_CHAIN_FORCE_SEL_MSK __constant_cpu_to_le16(0x7<<4)
904 #define RXON_RX_CHAIN_FORCE_SEL_POS (4)
905 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK __constant_cpu_to_le16(0x7<<7)
906 #define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
907 #define RXON_RX_CHAIN_CNT_MSK __constant_cpu_to_le16(0x3<<10)
908 #define RXON_RX_CHAIN_CNT_POS (10)
909 #define RXON_RX_CHAIN_MIMO_CNT_MSK __constant_cpu_to_le16(0x3<<12)
910 #define RXON_RX_CHAIN_MIMO_CNT_POS (12)
911 #define RXON_RX_CHAIN_MIMO_FORCE_MSK __constant_cpu_to_le16(0x1<<14)
912 #define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
915 #define MCS_DUP_6M_PLCP 0x20
917 /* OFDM HT rate masks */
918 /* ***************************************** */
919 #define R_MCS_6M_MSK 0x1
920 #define R_MCS_12M_MSK 0x2
921 #define R_MCS_18M_MSK 0x4
922 #define R_MCS_24M_MSK 0x8
923 #define R_MCS_36M_MSK 0x10
924 #define R_MCS_48M_MSK 0x20
925 #define R_MCS_54M_MSK 0x40
926 #define R_MCS_60M_MSK 0x80
927 #define R_MCS_12M_DUAL_MSK 0x100
928 #define R_MCS_24M_DUAL_MSK 0x200
929 #define R_MCS_36M_DUAL_MSK 0x400
930 #define R_MCS_48M_DUAL_MSK 0x800
932 #define is_legacy(tbl) (((tbl) == LQ_G) || ((tbl) == LQ_A))
933 #define is_siso(tbl) (((tbl) == LQ_SISO))
934 #define is_mimo(tbl) (((tbl) == LQ_MIMO))
935 #define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
936 #define is_a_band(tbl) (((tbl) == LQ_A))
937 #define is_g_and(tbl) (((tbl) == LQ_G))
939 /* Flow Handler Definitions */
941 /**********************/
943 /**********************/
945 #define FH_MEM_LOWER_BOUND (0x1000)
946 #define FH_MEM_UPPER_BOUND (0x1EF0)
948 #define IWL_FH_REGS_LOWER_BOUND (0x1000)
949 #define IWL_FH_REGS_UPPER_BOUND (0x2000)
951 #define IWL_FH_KW_MEM_ADDR_REG (FH_MEM_LOWER_BOUND + 0x97C)
953 /* CBBC Area - Circular buffers base address cache pointers table */
954 #define FH_MEM_CBBC_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0x9D0)
955 #define FH_MEM_CBBC_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xA10)
957 #define FH_MEM_CBBC_QUEUE(x) (FH_MEM_CBBC_LOWER_BOUND + (x) * 0x4)
960 #define FH_MEM_RSCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xBC0)
961 #define FH_MEM_RSCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
962 #define FH_MEM_RSCSR_CHNL0 (FH_MEM_RSCSR_LOWER_BOUND)
964 #define FH_RSCSR_CHNL0_STTS_WPTR_REG (FH_MEM_RSCSR_CHNL0)
965 #define FH_RSCSR_CHNL0_RBDCB_BASE_REG (FH_MEM_RSCSR_CHNL0 + 0x004)
966 #define FH_RSCSR_CHNL0_RBDCB_WPTR_REG (FH_MEM_RSCSR_CHNL0 + 0x008)
968 /* RCSR Area - Registers address map */
969 #define FH_MEM_RCSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC00)
970 #define FH_MEM_RCSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xCC0)
971 #define FH_MEM_RCSR_CHNL0 (FH_MEM_RCSR_LOWER_BOUND)
973 #define FH_MEM_RCSR_CHNL0_CONFIG_REG (FH_MEM_RCSR_CHNL0)
975 /* RSSR Area - Rx shared ctrl & status registers */
976 #define FH_MEM_RSSR_LOWER_BOUND (FH_MEM_LOWER_BOUND + 0xC40)
977 #define FH_MEM_RSSR_UPPER_BOUND (FH_MEM_LOWER_BOUND + 0xD00)
978 #define FH_MEM_RSSR_SHARED_CTRL_REG (FH_MEM_RSSR_LOWER_BOUND)
979 #define FH_MEM_RSSR_RX_STATUS_REG (FH_MEM_RSSR_LOWER_BOUND + 0x004)
980 #define FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV (FH_MEM_RSSR_LOWER_BOUND + 0x008)
983 #define IWL_FH_TCSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xD00)
984 #define IWL_FH_TCSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xE60)
986 #define IWL_FH_TCSR_CHNL_NUM (7)
987 #define IWL_FH_TCSR_CHNL_TX_CONFIG_REG(_chnl) \
988 (IWL_FH_TCSR_LOWER_BOUND + 0x20 * _chnl)
990 /* TSSR Area - Tx shared status registers */
992 #define IWL_FH_TSSR_LOWER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEA0)
993 #define IWL_FH_TSSR_UPPER_BOUND (IWL_FH_REGS_LOWER_BOUND + 0xEC0)
995 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG (IWL_FH_TSSR_LOWER_BOUND + 0x008)
996 #define IWL_FH_TSSR_TX_STATUS_REG (IWL_FH_TSSR_LOWER_BOUND + 0x010)
998 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
999 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
1001 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_64B (0x00000000)
1002 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
1003 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_256B (0x00000800)
1004 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_512B (0x00000C00)
1006 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
1007 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
1009 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
1010 #define IWL_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
1012 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) \
1013 ((1 << (_chnl)) << 24)
1014 #define IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl) \
1015 ((1 << (_chnl)) << 16)
1017 #define IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_chnl) \
1018 (IWL_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_chnl) | \
1019 IWL_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_chnl))
1021 /* TCSR: tx_config register values */
1022 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
1023 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
1024 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_ARC (0x00000002)
1026 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
1027 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
1029 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_NOINT (0x00000000)
1030 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD (0x00100000)
1031 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
1033 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
1034 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_ENDTFD (0x00400000)
1035 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_IFTFD (0x00800000)
1037 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
1038 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE_EOF (0x40000000)
1039 #define IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
1041 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_EMPTY (0x00000000)
1042 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_WAIT (0x00002000)
1043 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00000003)
1045 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
1047 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM (20)
1048 #define IWL_FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX (12)
1050 /* RCSR: channel 0 rx_config register defines */
1051 #define FH_RCSR_CHNL0_RX_CONFIG_DMA_CHNL_EN_MASK (0xC0000000) /* bits 30-31 */
1052 #define FH_RCSR_CHNL0_RX_CONFIG_RBDBC_SIZE_MASK (0x00F00000) /* bits 20-23 */
1053 #define FH_RCSR_CHNL0_RX_CONFIG_RB_SIZE_MASK (0x00030000) /* bits 16-17 */
1054 #define FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MASK (0x00008000) /* bit 15 */
1055 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_MASK (0x00001000) /* bit 12 */
1056 #define FH_RCSR_CHNL0_RX_CONFIG_RB_TIMEOUT_MASK (0x00000FF0) /* bit 4-11 */
1058 #define FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT (20)
1059 #define FH_RCSR_RX_CONFIG_RB_SIZE_BITSHIFT (16)
1061 /* RCSR: rx_config register values */
1062 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_VAL (0x00000000)
1063 #define FH_RCSR_RX_CONFIG_CHNL_EN_PAUSE_EOF_VAL (0x40000000)
1064 #define FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL (0x80000000)
1066 #define IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K (0x00000000)
1068 /* RCSR channel 0 config register values */
1069 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_NO_INT_VAL (0x00000000)
1070 #define FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL (0x00001000)
1072 /* RSCSR: defs used in normal mode */
1073 #define FH_RSCSR_CHNL0_RBDCB_WPTR_MASK (0x00000FFF) /* bits 0-11 */
1075 #define SCD_WIN_SIZE 64
1076 #define SCD_FRAME_LIMIT 64
1078 /* SRAM structures */
1079 #define SCD_CONTEXT_DATA_OFFSET 0x380
1080 #define SCD_TX_STTS_BITMAP_OFFSET 0x400
1081 #define SCD_TRANSLATE_TBL_OFFSET 0x500
1082 #define SCD_CONTEXT_QUEUE_OFFSET(x) (SCD_CONTEXT_DATA_OFFSET + ((x) * 8))
1083 #define SCD_TRANSLATE_TBL_OFFSET_QUEUE(x) \
1084 ((SCD_TRANSLATE_TBL_OFFSET + ((x) * 2)) & 0xfffffffc)
1086 #define SCD_TXFACT_REG_TXFIFO_MASK(lo, hi) \
1087 ((1<<(hi))|((1<<(hi))-(1<<(lo))))
1090 #define SCD_MODE_REG_BIT_SEARCH_MODE (1<<0)
1091 #define SCD_MODE_REG_BIT_SBYP_MODE (1<<1)
1093 #define SCD_TXFIFO_POS_TID (0)
1094 #define SCD_TXFIFO_POS_RA (4)
1095 #define SCD_QUEUE_STTS_REG_POS_ACTIVE (0)
1096 #define SCD_QUEUE_STTS_REG_POS_TXF (1)
1097 #define SCD_QUEUE_STTS_REG_POS_WSL (5)
1098 #define SCD_QUEUE_STTS_REG_POS_SCD_ACK (8)
1099 #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (10)
1100 #define SCD_QUEUE_STTS_REG_MSK (0x0007FC00)
1102 #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF)
1104 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_POS (0)
1105 #define SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK (0x0000007F)
1106 #define SCD_QUEUE_CTX_REG1_CREDIT_POS (8)
1107 #define SCD_QUEUE_CTX_REG1_CREDIT_MSK (0x00FFFF00)
1108 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_POS (24)
1109 #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT_MSK (0xFF000000)
1110 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS (16)
1111 #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK (0x007F0000)
1113 #define CSR_HW_IF_CONFIG_REG_BIT_KEDRON_R (0x00000010)
1114 #define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x00000C00)
1115 #define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
1116 #define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
1118 static inline u8 iwl_hw_get_rate(__le32 rate_n_flags)
1120 return le32_to_cpu(rate_n_flags) & 0xFF;
1122 static inline u16 iwl_hw_get_rate_n_flags(__le32 rate_n_flags)
1124 return le32_to_cpu(rate_n_flags) & 0xFFFF;
1126 static inline __le32 iwl_hw_set_rate_n_flags(u8 rate, u16 flags)
1128 return cpu_to_le32(flags|(u16)rate);
1131 struct iwl_tfd_frame_data {
1135 /* __le32 ptb1_32_35:4; */
1136 #define IWL_tb1_addr_hi_POS 0
1137 #define IWL_tb1_addr_hi_LEN 4
1138 #define IWL_tb1_addr_hi_SYM val1
1139 /* __le32 tb_len1:12; */
1140 #define IWL_tb1_len_POS 4
1141 #define IWL_tb1_len_LEN 12
1142 #define IWL_tb1_len_SYM val1
1143 /* __le32 ptb2_0_15:16; */
1144 #define IWL_tb2_addr_lo16_POS 16
1145 #define IWL_tb2_addr_lo16_LEN 16
1146 #define IWL_tb2_addr_lo16_SYM val1
1149 /* __le32 ptb2_16_35:20; */
1150 #define IWL_tb2_addr_hi20_POS 0
1151 #define IWL_tb2_addr_hi20_LEN 20
1152 #define IWL_tb2_addr_hi20_SYM val2
1153 /* __le32 tb_len2:12; */
1154 #define IWL_tb2_len_POS 20
1155 #define IWL_tb2_len_LEN 12
1156 #define IWL_tb2_len_SYM val2
1157 } __attribute__ ((packed));
1159 struct iwl_tfd_frame {
1161 /* __le32 rsvd1:24; */
1162 /* __le32 num_tbs:5; */
1163 #define IWL_num_tbs_POS 24
1164 #define IWL_num_tbs_LEN 5
1165 #define IWL_num_tbs_SYM val0
1166 /* __le32 rsvd2:1; */
1167 /* __le32 padding:2; */
1168 struct iwl_tfd_frame_data pa[10];
1170 } __attribute__ ((packed));
1172 #define IWL4965_MAX_WIN_SIZE 64
1173 #define IWL4965_QUEUE_SIZE 256
1174 #define IWL4965_NUM_FIFOS 7
1175 #define IWL_MAX_NUM_QUEUES 16
1177 struct iwl4965_queue_byte_cnt_entry {
1179 /* __le16 byte_cnt:12; */
1180 #define IWL_byte_cnt_POS 0
1181 #define IWL_byte_cnt_LEN 12
1182 #define IWL_byte_cnt_SYM val
1183 /* __le16 rsvd:4; */
1184 } __attribute__ ((packed));
1186 struct iwl4965_sched_queue_byte_cnt_tbl {
1187 struct iwl4965_queue_byte_cnt_entry tfd_offset[IWL4965_QUEUE_SIZE +
1188 IWL4965_MAX_WIN_SIZE];
1190 (IWL4965_QUEUE_SIZE + IWL4965_MAX_WIN_SIZE) *
1192 } __attribute__ ((packed));
1194 /* Base physical address of iwl_shared is provided to KDR_SCD_DRAM_BASE_ADDR
1195 * and &iwl_shared.val0 is provided to FH_RSCSR_CHNL0_STTS_WPTR_REG */
1197 struct iwl4965_sched_queue_byte_cnt_tbl
1198 queues_byte_cnt_tbls[IWL_MAX_NUM_QUEUES];
1201 /* __le32 rb_closed_stts_rb_num:12; */
1202 #define IWL_rb_closed_stts_rb_num_POS 0
1203 #define IWL_rb_closed_stts_rb_num_LEN 12
1204 #define IWL_rb_closed_stts_rb_num_SYM val0
1205 /* __le32 rsrv1:4; */
1206 /* __le32 rb_closed_stts_rx_frame_num:12; */
1207 #define IWL_rb_closed_stts_rx_frame_num_POS 16
1208 #define IWL_rb_closed_stts_rx_frame_num_LEN 12
1209 #define IWL_rb_closed_stts_rx_frame_num_SYM val0
1210 /* __le32 rsrv2:4; */
1213 /* __le32 frame_finished_stts_rb_num:12; */
1214 #define IWL_frame_finished_stts_rb_num_POS 0
1215 #define IWL_frame_finished_stts_rb_num_LEN 12
1216 #define IWL_frame_finished_stts_rb_num_SYM val1
1217 /* __le32 rsrv3:4; */
1218 /* __le32 frame_finished_stts_rx_frame_num:12; */
1219 #define IWL_frame_finished_stts_rx_frame_num_POS 16
1220 #define IWL_frame_finished_stts_rx_frame_num_LEN 12
1221 #define IWL_frame_finished_stts_rx_frame_num_SYM val1
1222 /* __le32 rsrv4:4; */
1224 __le32 padding1; /* so that allocation will be aligned to 16B */
1226 } __attribute__ ((packed));
1228 #endif /* __iwl_4965_hw_h__ */