1 /******************************************************************************
3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
7 published by the Free Software Foundation.
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 You should have received a copy of the GNU General Public License along with
15 this program; if not, write to the Free Software Foundation, Inc., 59
16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 The full GNU General Public License is included in this distribution in the
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #define WEXT_USECHANNELS 1
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/config.h>
35 #include <linux/init.h>
37 #include <linux/version.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/ethtool.h>
41 #include <linux/skbuff.h>
42 #include <linux/etherdevice.h>
43 #include <linux/delay.h>
44 #include <linux/random.h>
46 #include <linux/firmware.h>
47 #include <linux/wireless.h>
50 #include <net/ieee80211.h>
52 #define DRV_NAME "ipw2200"
54 #include <linux/workqueue.h>
57 typedef void irqreturn_t;
63 #if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9) )
67 #if ( LINUX_VERSION_CODE < KERNEL_VERSION(2,6,5) )
68 #define pci_dma_sync_single_for_cpu pci_dma_sync_single
69 #define pci_dma_sync_single_for_device pci_dma_sync_single
72 #ifndef HAVE_FREE_NETDEV
73 #define free_netdev(x) kfree(x)
76 /* Authentication and Association States */
77 enum connection_manager_assoc_states
98 #define IPW_WAIT (1<<0)
99 #define IPW_QUIET (1<<1)
100 #define IPW_ROAMING (1<<2)
102 #define IPW_POWER_MODE_CAM 0x00 //(always on)
103 #define IPW_POWER_INDEX_1 0x01
104 #define IPW_POWER_INDEX_2 0x02
105 #define IPW_POWER_INDEX_3 0x03
106 #define IPW_POWER_INDEX_4 0x04
107 #define IPW_POWER_INDEX_5 0x05
108 #define IPW_POWER_AC 0x06
109 #define IPW_POWER_BATTERY 0x07
110 #define IPW_POWER_LIMIT 0x07
111 #define IPW_POWER_MASK 0x0F
112 #define IPW_POWER_ENABLED 0x10
113 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
115 #define IPW_CMD_HOST_COMPLETE 2
116 #define IPW_CMD_POWER_DOWN 4
117 #define IPW_CMD_SYSTEM_CONFIG 6
118 #define IPW_CMD_MULTICAST_ADDRESS 7
119 #define IPW_CMD_SSID 8
120 #define IPW_CMD_ADAPTER_ADDRESS 11
121 #define IPW_CMD_PORT_TYPE 12
122 #define IPW_CMD_RTS_THRESHOLD 15
123 #define IPW_CMD_FRAG_THRESHOLD 16
124 #define IPW_CMD_POWER_MODE 17
125 #define IPW_CMD_WEP_KEY 18
126 #define IPW_CMD_TGI_TX_KEY 19
127 #define IPW_CMD_SCAN_REQUEST 20
128 #define IPW_CMD_ASSOCIATE 21
129 #define IPW_CMD_SUPPORTED_RATES 22
130 #define IPW_CMD_SCAN_ABORT 23
131 #define IPW_CMD_TX_FLUSH 24
132 #define IPW_CMD_QOS_PARAMETERS 25
133 #define IPW_CMD_SCAN_REQUEST_EXT 26
134 #define IPW_CMD_DINO_CONFIG 30
135 #define IPW_CMD_RSN_CAPABILITIES 31
136 #define IPW_CMD_RX_KEY 32
137 #define IPW_CMD_CARD_DISABLE 33
138 #define IPW_CMD_SEED_NUMBER 34
139 #define IPW_CMD_TX_POWER 35
140 #define IPW_CMD_COUNTRY_INFO 36
141 #define IPW_CMD_AIRONET_INFO 37
142 #define IPW_CMD_AP_TX_POWER 38
143 #define IPW_CMD_CCKM_INFO 39
144 #define IPW_CMD_CCX_VER_INFO 40
145 #define IPW_CMD_SET_CALIBRATION 41
146 #define IPW_CMD_SENSITIVITY_CALIB 42
147 #define IPW_CMD_RETRY_LIMIT 51
148 #define IPW_CMD_IPW_PRE_POWER_DOWN 58
149 #define IPW_CMD_VAP_BEACON_TEMPLATE 60
150 #define IPW_CMD_VAP_DTIM_PERIOD 61
151 #define IPW_CMD_EXT_SUPPORTED_RATES 62
152 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
153 #define IPW_CMD_VAP_QUIET_INTERVALS 64
154 #define IPW_CMD_VAP_CHANNEL_SWITCH 65
155 #define IPW_CMD_VAP_MANDATORY_CHANNELS 66
156 #define IPW_CMD_VAP_CELL_PWR_LIMIT 67
157 #define IPW_CMD_VAP_CF_PARAM_SET 68
158 #define IPW_CMD_VAP_SET_BEACONING_STATE 69
159 #define IPW_CMD_MEASUREMENT 80
160 #define IPW_CMD_POWER_CAPABILITY 81
161 #define IPW_CMD_SUPPORTED_CHANNELS 82
162 #define IPW_CMD_TPC_REPORT 83
163 #define IPW_CMD_WME_INFO 84
164 #define IPW_CMD_PRODUCTION_COMMAND 85
165 #define IPW_CMD_LINKSYS_EOU_INFO 90
168 #define NUM_TFD_CHUNKS 6
170 #define TX_QUEUE_SIZE 32
171 #define RX_QUEUE_SIZE 32
173 #define DINO_CMD_WEP_KEY 0x08
174 #define DINO_CMD_TX 0x0B
175 #define DCT_ANTENNA_A 0x01
176 #define DCT_ANTENNA_B 0x02
183 * TX Queue Flag Definitions
186 /* abort attempt if mgmt frame is rx'd */
187 #define DCT_FLAG_ABORT_MGMT 0x01
190 #define DCT_FLAG_CTS_REQUIRED 0x02
192 /* use short preamble */
193 #define DCT_FLAG_SHORT_PREMBL 0x04
196 #define DCT_FLAG_RTS_REQD 0x08
198 /* dont calculate duration field */
199 #define DCT_FLAG_DUR_SET 0x10
201 /* even if MAC WEP set (allows pre-encrypt) */
202 #define DCT_FLAG_NO_WEP 0x20
204 /* overwrite TSF field */
205 #define DCT_FLAG_TSF_REQD 0x40
207 /* ACK rx is expected to follow */
208 #define DCT_FLAG_ACK_REQD 0x80
210 #define DCT_FLAG_EXT_MODE_CCK 0x01
211 #define DCT_FLAG_EXT_MODE_OFDM 0x00
214 #define TX_RX_TYPE_MASK 0xFF
215 #define TX_FRAME_TYPE 0x00
216 #define TX_HOST_COMMAND_TYPE 0x01
217 #define RX_FRAME_TYPE 0x09
218 #define RX_HOST_NOTIFICATION_TYPE 0x03
219 #define RX_HOST_CMD_RESPONSE_TYPE 0x04
220 #define RX_TX_FRAME_RESPONSE_TYPE 0x05
221 #define TFD_NEED_IRQ_MASK 0x04
223 #define HOST_CMD_DINO_CONFIG 30
225 #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
226 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
227 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
228 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
229 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
230 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
231 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
232 #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
233 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
234 #define HOST_NOTIFICATION_TX_STATUS 19
235 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
236 #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
237 #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
238 #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
239 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
240 #define HOST_NOTIFICATION_NOISE_STATS 25
241 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
242 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
244 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
245 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24
246 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
247 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
249 #define MACADRR_BYTE_LEN 6
251 #define DCR_TYPE_AP 0x01
252 #define DCR_TYPE_WLAP 0x02
253 #define DCR_TYPE_MU_ESS 0x03
254 #define DCR_TYPE_MU_IBSS 0x04
255 #define DCR_TYPE_MU_PIBSS 0x05
256 #define DCR_TYPE_SNIFFER 0x06
257 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
260 * Generic queue structure
262 * Contains common data for Rx and Tx queues
265 int n_bd; /**< number of BDs in this queue */
266 int first_empty; /**< 1-st empty entry (index) */
267 int last_used; /**< last used entry (index) */
268 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
269 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
270 dma_addr_t dma_addr; /**< physical addr for BD's */
271 int low_mark; /**< low watermark, resume queue if free space more than this */
272 int high_mark; /**< high watermark, stop queue if free space less than this */
273 } __attribute__ ((packed));
278 u16 duration; // watch out for endians!
279 u8 addr1[ MACADRR_BYTE_LEN ];
280 u8 addr2[ MACADRR_BYTE_LEN ];
281 u8 addr3[ MACADRR_BYTE_LEN ];
282 u16 seq_ctrl; // more endians!
283 u8 addr4[ MACADRR_BYTE_LEN ];
285 } __attribute__ ((packed)) ;
290 u16 duration; // watch out for endians!
291 u8 addr1[ MACADRR_BYTE_LEN ];
292 u8 addr2[ MACADRR_BYTE_LEN ];
293 u8 addr3[ MACADRR_BYTE_LEN ];
294 u16 seq_ctrl; // more endians!
295 u8 addr4[ MACADRR_BYTE_LEN ];
296 } __attribute__ ((packed)) ;
301 u16 duration; // watch out for endians!
302 u8 addr1[ MACADRR_BYTE_LEN ];
303 u8 addr2[ MACADRR_BYTE_LEN ];
304 u8 addr3[ MACADRR_BYTE_LEN ];
305 u16 seq_ctrl; // more endians!
307 } __attribute__ ((packed)) ;
312 u16 duration; // watch out for endians!
313 u8 addr1[ MACADRR_BYTE_LEN ];
314 u8 addr2[ MACADRR_BYTE_LEN ];
315 u8 addr3[ MACADRR_BYTE_LEN ];
316 u16 seq_ctrl; // more endians!
317 } __attribute__ ((packed)) ;
319 // TX TFD with 32 byte MAC Header
322 struct machdr32 mchdr; // 32
323 u32 uivplaceholder[2]; // 8
324 } __attribute__ ((packed)) ;
326 // TX TFD with 30 byte MAC Header
329 struct machdr30 mchdr; // 30
331 u32 uivplaceholder[2]; // 8
332 } __attribute__ ((packed)) ;
334 // tx tfd with 26 byte mac header
337 struct machdr26 mchdr; // 26
338 u8 reserved1[2]; // 2
339 u32 uivplaceholder[2]; // 8
340 u8 reserved2[4]; // 4
341 } __attribute__ ((packed)) ;
343 // tx tfd with 24 byte mac header
346 struct machdr24 mchdr; // 24
347 u32 uivplaceholder[2]; // 8
349 } __attribute__ ((packed)) ;
352 #define DCT_WEP_KEY_FIELD_LENGTH 16
360 } __attribute__ ((packed)) ;
365 u8 station_number; /* 0 for BSS */
377 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
380 u16 next_packet_duration;
382 u16 back_off_counter; //////txop;
387 /* 802.11 MAC Header */
390 struct tx_tfd_24 tfd_24;
391 struct tx_tfd_26 tfd_26;
392 struct tx_tfd_30 tfd_30;
393 struct tx_tfd_32 tfd_32;
396 /* Payload DMA info */
398 u32 chunk_ptr[NUM_TFD_CHUNKS];
399 u16 chunk_len[NUM_TFD_CHUNKS];
400 } __attribute__ ((packed));
402 struct txrx_control_flags
408 } __attribute__ ((packed));
411 #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
415 struct txrx_control_flags control_flags;
417 struct tfd_data data;
418 struct tfd_command cmd;
419 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
421 } __attribute__ ((packed)) ;
423 typedef void destructor_func(const void*);
426 * Tx Queue for DMA. Queue consists of circular buffer of
427 * BD's and required locking structures.
429 struct clx2_tx_queue {
431 struct tfd_frame* bd;
432 struct ieee80211_txb **txb;
436 * RX related structures and functions
438 #define RX_FREE_BUFFERS 32
439 #define RX_LOW_WATERMARK 8
441 #define SUP_RATE_11A_MAX_NUM_CHANNELS (8)
442 #define SUP_RATE_11B_MAX_NUM_CHANNELS (4)
443 #define SUP_RATE_11G_MAX_NUM_CHANNELS (12)
445 // Used for passing to driver number of successes and failures per rate
446 struct rate_histogram
449 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
450 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
451 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
454 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
455 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
456 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
458 } __attribute__ ((packed));
460 /* statistics command response */
461 struct ipw_cmd_stats {
469 u16 reserved_frame_types;
474 u16 long_distance_ina_fina;
475 u16 dsp_silence_unreachable;
476 u16 accumulated_rssi;
477 u16 rx_ovfl_frame_tossed;
478 u16 rssi_silence_threshold;
479 u16 rx_ovfl_frame_supplied;
480 u16 last_rx_frame_signal;
481 u16 last_rx_frame_noise;
482 u16 rx_autodetec_no_ofdm;
483 u16 rx_autodetec_no_barker;
485 } __attribute__ ((packed));
487 struct notif_channel_result {
489 struct ipw_cmd_stats stats;
491 } __attribute__ ((packed));
493 struct notif_scan_complete {
498 } __attribute__ ((packed));
500 struct notif_frag_length {
503 } __attribute__ ((packed));
505 struct notif_beacon_state {
508 } __attribute__ ((packed));
510 struct notif_tgi_tx_key {
515 } __attribute__ ((packed));
517 struct notif_link_deterioration {
518 struct ipw_cmd_stats stats;
521 struct rate_histogram histogram;
524 } __attribute__ ((packed));
526 struct notif_association {
528 } __attribute__ ((packed));
530 struct notif_authenticate {
532 struct machdr24 addr;
534 } __attribute__ ((packed));
540 } __attribute__ ((packed));
542 struct notif_calibration {
544 } __attribute__ ((packed));
548 } __attribute__ ((packed));
550 struct ipw_rx_notification {
556 struct notif_association assoc;
557 struct notif_authenticate auth;
558 struct notif_channel_result channel_result;
559 struct notif_scan_complete scan_complete;
560 struct notif_frag_length frag_len;
561 struct notif_beacon_state beacon_state;
562 struct notif_tgi_tx_key tgi_tx_key;
563 struct notif_link_deterioration link_deterioration;
564 struct notif_calibration calibration;
565 struct notif_noise noise;
568 } __attribute__ ((packed));
570 struct ipw_rx_frame {
572 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
573 u8 received_channel; // The channel that this frame was received on.
574 // Note that for .11b this does not have to be
575 // the same as the channel that it was sent.
585 u8 control; // control bit should be on in bg
586 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
588 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
591 } __attribute__ ((packed));
593 struct ipw_rx_header {
598 } __attribute__ ((packed));
602 struct ipw_rx_header header;
604 struct ipw_rx_frame frame;
605 struct ipw_rx_notification notification;
607 } __attribute__ ((packed));
609 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
610 #define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \
611 sizeof(struct ipw_rx_frame)
613 struct ipw_rx_mem_buffer {
615 struct ipw_rx_buffer *rxb;
617 struct list_head list;
618 }; /* Not transferred over network, so not __attribute__ ((packed)) */
620 struct ipw_rx_queue {
621 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
622 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
623 u32 processed; /* Internal index to last handled Rx packet */
624 u32 read; /* Shared index to newest available Rx buffer */
625 u32 write; /* Shared index to oldest written Rx packet */
626 u32 free_count;/* Number of pre-allocated buffers in rx_free */
627 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
628 struct list_head rx_free; /* Own an SKBs */
629 struct list_head rx_used; /* No SKB allocated */
631 }; /* Not transferred over network, so not __attribute__ ((packed)) */
634 struct alive_command_responce {
637 u16 software_revision;
638 u8 device_identifier;
642 u16 clock_settle_time;
643 u16 powerup_settle_time;
645 u8 time_stamp[5]; /* month, day, year, hours, minutes */
647 } __attribute__ ((packed));
649 #define IPW_MAX_RATES 12
653 u8 rates[IPW_MAX_RATES];
654 } __attribute__ ((packed));
658 unsigned int control;
662 } __attribute__ ((packed));
664 #define CB_NUMBER_OF_ELEMENTS_SMALL 64
667 unsigned long last_cb_index;
668 unsigned long current_cb_index;
669 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
671 unsigned long p_addr;
675 struct ipw_sys_config
679 u8 answer_broadcast_ssid_probe;
680 u8 accept_all_data_frames;
681 u8 accept_non_directed_frames;
682 u8 exclude_unicast_unencrypted;
683 u8 disable_unicast_decryption;
684 u8 exclude_multicast_unencrypted;
685 u8 disable_multicast_decryption;
686 u8 antenna_diversity;
688 u8 dot11g_auto_detection;
689 u8 enable_cts_to_self;
690 u8 enable_multicast_filtering;
691 u8 bt_coexist_collision_thr;
693 u8 accept_all_mgmt_bcpr;
694 u8 accept_all_mgtm_frames;
695 u8 pass_noise_stats_to_host;
697 } __attribute__ ((packed));
699 struct ipw_multicast_addr
701 u8 num_of_multicast_addresses;
707 } __attribute__ ((packed));
716 } __attribute__ ((packed));
718 struct ipw_tgi_tx_key
726 } __attribute__ ((packed));
728 #define IPW_SCAN_CHANNELS 54
730 struct ipw_scan_request
734 u8 channels_list[IPW_SCAN_CHANNELS];
735 u8 channels_reserved[3];
736 } __attribute__ ((packed));
739 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
740 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
741 IPW_SCAN_ACTIVE_DIRECT_SCAN,
742 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
743 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
747 struct ipw_scan_request_ext
750 u8 channels_list[IPW_SCAN_CHANNELS];
751 u8 scan_type[IPW_SCAN_CHANNELS / 2];
753 u16 dwell_time[IPW_SCAN_TYPES];
754 } __attribute__ ((packed));
756 extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
759 return scan->scan_type[index / 2] & 0x0F;
761 return (scan->scan_type[index / 2] & 0xF0) >> 4;
764 extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
765 u8 index, u8 scan_type)
768 scan->scan_type[index / 2] =
769 (scan->scan_type[index / 2] & 0xF0) |
772 scan->scan_type[index / 2] =
773 (scan->scan_type[index / 2] & 0x0F) |
774 ((scan_type & 0x0F) << 4);
798 } __attribute__ ((packed));
800 struct ipw_supported_rates
806 u8 supported_rates[IPW_MAX_RATES];
807 } __attribute__ ((packed));
809 struct ipw_rts_threshold
813 } __attribute__ ((packed));
815 struct ipw_frag_threshold
819 } __attribute__ ((packed));
821 struct ipw_retry_limit
823 u8 short_retry_limit;
826 } __attribute__ ((packed));
828 struct ipw_dino_config
830 u32 dino_config_addr;
831 u16 dino_config_size;
834 } __attribute__ ((packed));
836 struct ipw_aironet_info
841 } __attribute__ ((packed));
850 u8 station_address[6];
853 } __attribute__ ((packed));
855 struct ipw_country_channel_info
860 } __attribute__ ((packed));
862 struct ipw_country_info
867 struct ipw_country_channel_info groups[7];
868 } __attribute__ ((packed));
870 struct ipw_channel_tx_power
874 } __attribute__ ((packed));
876 #define SCAN_ASSOCIATED_INTERVAL (HZ)
877 #define SCAN_INTERVAL (HZ / 10)
878 #define MAX_A_CHANNELS 37
879 #define MAX_B_CHANNELS 14
885 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
886 } __attribute__ ((packed));
888 struct ipw_qos_parameters
895 } __attribute__ ((packed));
897 struct ipw_rsn_capabilities
902 } __attribute__ ((packed));
904 struct ipw_sensitivity_calib
908 } __attribute__ ((packed));
911 * Host command structure.
913 * On input, the following fields should be filled:
917 * - param (if needed)
920 * - \a status contains status;
921 * - \a param filled with status parameters.
924 u32 cmd; /**< Host command */
925 u32 status; /**< Status */
926 u32 status_len; /**< How many 32 bit parameters in the status */
927 u32 len; /**< incoming parameters length, bytes */
929 * command parameters.
930 * There should be enough space for incoming and
931 * outcoming parameters.
932 * Incoming parameters listed 1-st, followed by outcoming params.
933 * nParams=(len+3)/4+status_len
936 } __attribute__ ((packed));
938 #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
940 #define STATUS_INT_ENABLED (1<<1)
941 #define STATUS_RF_KILL_HW (1<<2)
942 #define STATUS_RF_KILL_SW (1<<3)
943 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
945 #define STATUS_INIT (1<<5)
946 #define STATUS_AUTH (1<<6)
947 #define STATUS_ASSOCIATED (1<<7)
948 #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
950 #define STATUS_ASSOCIATING (1<<8)
951 #define STATUS_DISASSOCIATING (1<<9)
952 #define STATUS_ROAMING (1<<10)
953 #define STATUS_EXIT_PENDING (1<<11)
954 #define STATUS_DISASSOC_PENDING (1<<12)
955 #define STATUS_STATE_PENDING (1<<13)
957 #define STATUS_SCAN_PENDING (1<<20)
958 #define STATUS_SCANNING (1<<21)
959 #define STATUS_SCAN_ABORTING (1<<22)
961 #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
962 #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
963 #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
965 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
967 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
968 #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
969 #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
970 #define CFG_CUSTOM_MAC (1<<3)
971 #define CFG_PREAMBLE (1<<4)
972 #define CFG_ADHOC_PERSIST (1<<5)
973 #define CFG_ASSOCIATE (1<<6)
974 #define CFG_FIXED_RATE (1<<7)
975 #define CFG_ADHOC_CREATE (1<<8)
977 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
978 #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
980 #define MAX_STATIONS 32
981 #define IPW_INVALID_STATION (0xff)
983 struct ipw_station_entry {
984 u8 mac_addr[ETH_ALEN];
989 #define AVG_ENTRIES 8
991 s16 entries[AVG_ENTRIES];
998 /* ieee device used by generic ieee processing code */
999 struct ieee80211_device *ieee;
1000 struct ieee80211_security sec;
1005 /* basic pci-network driver stuff */
1006 struct pci_dev *pci_dev;
1007 struct net_device *net_dev;
1009 /* pci hardware address support */
1010 void __iomem *hw_base;
1011 unsigned long hw_len;
1013 struct fw_image_desc sram_desc;
1015 /* result of ucode download */
1016 struct alive_command_responce dino_alive;
1018 wait_queue_head_t wait_command_queue;
1019 wait_queue_head_t wait_state;
1021 /* Rx and Tx DMA processing queues */
1022 struct ipw_rx_queue *rxq;
1023 struct clx2_tx_queue txq_cmd;
1024 struct clx2_tx_queue txq[4];
1031 struct average average_missed_beacons;
1032 struct average average_rssi;
1033 struct average average_noise;
1035 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
1036 int rx_pend_max; /**< maximum pending buffers for one IRQ */
1037 u32 hcmd_seq; /**< sequence number for hcmd */
1038 u32 missed_beacon_threshold;
1039 u32 roaming_threshold;
1041 struct ipw_associate assoc_request;
1042 struct ieee80211_network *assoc_network;
1044 unsigned long ts_scan_abort;
1045 struct ipw_supported_rates rates;
1046 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
1047 struct ipw_rates supp; /**< software defined */
1048 struct ipw_rates extended; /**< use for corresp. IE, AP only */
1050 struct notif_link_deterioration last_link_deterioration; /** for statistics */
1051 struct ipw_cmd* hcmd; /**< host command currently executed */
1053 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
1054 u32 tsf_bcn[2]; /**< TSF from latest beacon */
1056 struct notif_calibration calib; /**< last calibration */
1058 /* ordinal interface with firmware */
1066 /* context information */
1067 u8 essid[IW_ESSID_MAX_SIZE];
1069 u8 nick[IW_ESSID_MAX_SIZE];
1072 struct ipw_sys_config sys_config;
1076 u8 mac_addr[ETH_ALEN];
1078 u8 stations[MAX_STATIONS][ETH_ALEN];
1080 u32 notif_missed_beacons;
1082 /* Statistics and counters normalized with each association */
1083 u32 last_missed_beacons;
1084 u32 last_tx_packets;
1085 u32 last_rx_packets;
1086 u32 last_tx_failures;
1090 u32 missed_adhoc_beacons;
1097 u8 eeprom[0x100]; /* 256 bytes of eeprom */
1100 struct iw_statistics wstats;
1102 struct workqueue_struct *workqueue;
1104 struct work_struct adhoc_check;
1105 struct work_struct associate;
1106 struct work_struct disassociate;
1107 struct work_struct rx_replenish;
1108 struct work_struct request_scan;
1109 struct work_struct adapter_restart;
1110 struct work_struct rf_kill;
1111 struct work_struct up;
1112 struct work_struct down;
1113 struct work_struct gather_stats;
1114 struct work_struct abort_scan;
1115 struct work_struct roam;
1116 struct work_struct scan_check;
1118 struct tasklet_struct irq_tasklet;
1121 #define IPW_2200BG 1
1122 #define IPW_2915ABG 2
1125 #define IPW_DEFAULT_TX_POWER 0x14
1134 /* Used to pass the current INTA value from ISR to Tasklet */
1137 /* debugging info */
1146 #ifdef CONFIG_IPW_DEBUG
1147 #define IPW_DEBUG(level, fmt, args...) \
1148 do { if (ipw_debug_level & (level)) \
1149 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1150 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1152 #define IPW_DEBUG(level, fmt, args...) do {} while (0)
1153 #endif /* CONFIG_IPW_DEBUG */
1156 * To use the debug system;
1158 * If you are defining a new debug classification, simply add it to the #define
1159 * list here in the form of:
1161 * #define IPW_DL_xxxx VALUE
1163 * shifting value to the left one bit from the previous entry. xxxx should be
1164 * the name of the classification (for example, WEP)
1166 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1167 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1168 * to send output to that classification.
1170 * To add your debug level to the list of levels seen when you perform
1172 * % cat /proc/net/ipw/debug_level
1174 * you simply need to add your entry to the ipw_debug_levels array.
1176 * If you do not see debug_level in /proc/net/ipw then you do not have
1177 * CONFIG_IPW_DEBUG defined in your kernel configuration
1181 #define IPW_DL_ERROR (1<<0)
1182 #define IPW_DL_WARNING (1<<1)
1183 #define IPW_DL_INFO (1<<2)
1184 #define IPW_DL_WX (1<<3)
1185 #define IPW_DL_HOST_COMMAND (1<<5)
1186 #define IPW_DL_STATE (1<<6)
1188 #define IPW_DL_NOTIF (1<<10)
1189 #define IPW_DL_SCAN (1<<11)
1190 #define IPW_DL_ASSOC (1<<12)
1191 #define IPW_DL_DROP (1<<13)
1192 #define IPW_DL_IOCTL (1<<14)
1194 #define IPW_DL_MANAGE (1<<15)
1195 #define IPW_DL_FW (1<<16)
1196 #define IPW_DL_RF_KILL (1<<17)
1197 #define IPW_DL_FW_ERRORS (1<<18)
1200 #define IPW_DL_ORD (1<<20)
1202 #define IPW_DL_FRAG (1<<21)
1203 #define IPW_DL_WEP (1<<22)
1204 #define IPW_DL_TX (1<<23)
1205 #define IPW_DL_RX (1<<24)
1206 #define IPW_DL_ISR (1<<25)
1207 #define IPW_DL_FW_INFO (1<<26)
1208 #define IPW_DL_IO (1<<27)
1209 #define IPW_DL_TRACE (1<<28)
1211 #define IPW_DL_STATS (1<<29)
1214 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1215 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1216 #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1218 #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1219 #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1220 #define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a)
1221 #define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a)
1222 #define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a)
1223 #define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
1224 #define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
1225 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1226 #define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
1227 #define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1228 #define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
1229 #define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a)
1230 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1231 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1232 #define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a)
1233 #define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a)
1234 #define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a)
1235 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1236 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1237 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1238 #define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
1240 #include <linux/ctype.h>
1243 * Register bit definitions
1246 /* Dino control registers bits */
1248 #define DINO_ENABLE_SYSTEM 0x80
1249 #define DINO_ENABLE_CS 0x40
1250 #define DINO_RXFIFO_DATA 0x01
1251 #define DINO_CONTROL_REG 0x00200000
1253 #define CX2_INTA_RW 0x00000008
1254 #define CX2_INTA_MASK_R 0x0000000C
1255 #define CX2_INDIRECT_ADDR 0x00000010
1256 #define CX2_INDIRECT_DATA 0x00000014
1257 #define CX2_AUTOINC_ADDR 0x00000018
1258 #define CX2_AUTOINC_DATA 0x0000001C
1259 #define CX2_RESET_REG 0x00000020
1260 #define CX2_GP_CNTRL_RW 0x00000024
1262 #define CX2_READ_INT_REGISTER 0xFF4
1264 #define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004
1266 #define CX2_REGISTER_DOMAIN1_END 0x00001000
1267 #define CX2_SRAM_READ_INT_REGISTER 0x00000ff4
1269 #define CX2_SHARED_LOWER_BOUND 0x00000200
1270 #define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1272 #define CX2_NIC_SRAM_LOWER_BOUND 0x00000000
1273 #define CX2_NIC_SRAM_UPPER_BOUND 0x00030000
1275 #define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1276 #define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1277 #define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1280 * RESET Register Bit Indexes
1282 #define CBD_RESET_REG_PRINCETON_RESET 0x00000001 /* Bit 0 (LSB) */
1283 #define CX2_RESET_REG_SW_RESET 0x00000080 /* Bit 7 */
1284 #define CX2_RESET_REG_MASTER_DISABLED 0x00000100 /* Bit 8 */
1285 #define CX2_RESET_REG_STOP_MASTER 0x00000200 /* Bit 9 */
1286 #define CX2_ARC_KESHET_CONFIG 0x08000000 /* Bit 27 */
1287 #define CX2_START_STANDBY 0x00000004 /* Bit 2 */
1289 #define CX2_CSR_CIS_UPPER_BOUND 0x00000200
1290 #define CX2_DOMAIN_0_END 0x1000
1291 #define CLX_MEM_BAR_SIZE 0x1000
1293 #define CX2_BASEBAND_CONTROL_STATUS 0X00200000
1294 #define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004
1295 #define CX2_BASEBAND_RX_FIFO_READ 0X00200004
1296 #define CX2_BASEBAND_CONTROL_STORE 0X00200010
1298 #define CX2_INTERNAL_CMD_EVENT 0X00300004
1299 #define CX2_BASEBAND_POWER_DOWN 0x00000001
1301 #define CX2_MEM_HALT_AND_RESET 0x003000e0
1303 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1304 #define CX2_BIT_HALT_RESET_ON 0x80000000
1305 #define CX2_BIT_HALT_RESET_OFF 0x00000000
1307 #define CB_LAST_VALID 0x20000000
1308 #define CB_INT_ENABLED 0x40000000
1309 #define CB_VALID 0x80000000
1310 #define CB_SRC_LE 0x08000000
1311 #define CB_DEST_LE 0x04000000
1312 #define CB_SRC_AUTOINC 0x00800000
1313 #define CB_SRC_IO_GATED 0x00400000
1314 #define CB_DEST_AUTOINC 0x00080000
1315 #define CB_SRC_SIZE_LONG 0x00200000
1316 #define CB_DEST_SIZE_LONG 0x00020000
1321 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1322 #define DMA_CB_STOP_AND_ABORT 0x00000C00
1323 #define DMA_CB_START 0x00000100
1326 #define CX2_SHARED_SRAM_SIZE 0x00030000
1327 #define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000
1328 #define CB_MAX_LENGTH 0x1FFF
1330 #define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1331 #define CX2_EEPROM_IMAGE_SIZE 0x100
1335 #define CX2_DMA_I_CURRENT_CB 0x003000D0
1336 #define CX2_DMA_O_CURRENT_CB 0x003000D4
1337 #define CX2_DMA_I_DMA_CONTROL 0x003000A4
1338 #define CX2_DMA_I_CB_BASE 0x003000A0
1340 #define CX2_TX_CMD_QUEUE_BD_BASE (0x00000200)
1341 #define CX2_TX_CMD_QUEUE_BD_SIZE (0x00000204)
1342 #define CX2_TX_QUEUE_0_BD_BASE (0x00000208)
1343 #define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C)
1344 #define CX2_TX_QUEUE_1_BD_BASE (0x00000210)
1345 #define CX2_TX_QUEUE_1_BD_SIZE (0x00000214)
1346 #define CX2_TX_QUEUE_2_BD_BASE (0x00000218)
1347 #define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C)
1348 #define CX2_TX_QUEUE_3_BD_BASE (0x00000220)
1349 #define CX2_TX_QUEUE_3_BD_SIZE (0x00000224)
1350 #define CX2_RX_BD_BASE (0x00000240)
1351 #define CX2_RX_BD_SIZE (0x00000244)
1352 #define CX2_RFDS_TABLE_LOWER (0x00000500)
1354 #define CX2_TX_CMD_QUEUE_READ_INDEX (0x00000280)
1355 #define CX2_TX_QUEUE_0_READ_INDEX (0x00000284)
1356 #define CX2_TX_QUEUE_1_READ_INDEX (0x00000288)
1357 #define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C)
1358 #define CX2_TX_QUEUE_3_READ_INDEX (0x00000290)
1359 #define CX2_RX_READ_INDEX (0x000002A0)
1361 #define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1362 #define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1363 #define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1364 #define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1365 #define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1366 #define CX2_RX_WRITE_INDEX (0x00000FA0)
1369 * EEPROM Related Definitions
1372 #define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814)
1373 #define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818)
1374 #define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C)
1375 #define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820)
1376 #define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0)
1378 #define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C)
1379 #define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C)
1380 #define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C)
1381 #define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10)
1382 #define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14)
1383 #define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18)
1388 #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1390 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1391 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1393 /* EEPROM access by BYTE */
1394 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1395 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1396 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1397 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1398 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1399 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1400 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1401 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1402 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1403 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1405 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
1406 #define EEPROM_NIC_TYPE_STANDARD 0
1407 #define EEPROM_NIC_TYPE_DELL 1
1408 #define EEPROM_NIC_TYPE_FUJITSU 2
1409 #define EEPROM_NIC_TYPE_IBM 3
1410 #define EEPROM_NIC_TYPE_HP 4
1412 #define FW_MEM_REG_LOWER_BOUND 0x00300000
1413 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1415 #define EEPROM_BIT_SK (1<<0)
1416 #define EEPROM_BIT_CS (1<<1)
1417 #define EEPROM_BIT_DI (1<<2)
1418 #define EEPROM_BIT_DO (1<<4)
1420 #define EEPROM_CMD_READ 0x2
1422 /* Interrupts masks */
1423 #define CX2_INTA_NONE 0x00000000
1425 #define CX2_INTA_BIT_RX_TRANSFER 0x00000002
1426 #define CX2_INTA_BIT_STATUS_CHANGE 0x00000010
1427 #define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1430 #define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800
1431 #define CX2_INTA_BIT_TX_QUEUE_1 0x00001000
1432 #define CX2_INTA_BIT_TX_QUEUE_2 0x00002000
1433 #define CX2_INTA_BIT_TX_QUEUE_3 0x00004000
1434 #define CX2_INTA_BIT_TX_QUEUE_4 0x00008000
1436 #define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1438 #define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1439 #define CX2_INTA_BIT_POWER_DOWN 0x00200000
1441 #define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1442 #define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1443 #define CX2_INTA_BIT_RF_KILL_DONE 0x04000000
1444 #define CX2_INTA_BIT_FATAL_ERROR 0x40000000
1445 #define CX2_INTA_BIT_PARITY_ERROR 0x80000000
1447 /* Interrupts enabled at init time. */
1448 #define CX2_INTA_MASK_ALL \
1449 (CX2_INTA_BIT_TX_QUEUE_1 | \
1450 CX2_INTA_BIT_TX_QUEUE_2 | \
1451 CX2_INTA_BIT_TX_QUEUE_3 | \
1452 CX2_INTA_BIT_TX_QUEUE_4 | \
1453 CX2_INTA_BIT_TX_CMD_QUEUE | \
1454 CX2_INTA_BIT_RX_TRANSFER | \
1455 CX2_INTA_BIT_FATAL_ERROR | \
1456 CX2_INTA_BIT_PARITY_ERROR | \
1457 CX2_INTA_BIT_STATUS_CHANGE | \
1458 CX2_INTA_BIT_FW_INITIALIZATION_DONE | \
1459 CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1460 CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1461 CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1462 CX2_INTA_BIT_POWER_DOWN | \
1463 CX2_INTA_BIT_RF_KILL_DONE )
1465 #define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410)
1466 #define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414)
1468 /* FW event log definitions */
1469 #define EVENT_ELEM_SIZE (3 * sizeof(u32))
1470 #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1472 /* FW error log definitions */
1473 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1474 #define ERROR_START_OFFSET (1 * sizeof(u32))
1477 IPW_FW_ERROR_OK = 0,
1479 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1480 IPW_FW_ERROR_MEMORY_OVERFLOW,
1481 IPW_FW_ERROR_BAD_PARAM,
1482 IPW_FW_ERROR_BAD_CHECKSUM,
1483 IPW_FW_ERROR_NMI_INTERRUPT,
1484 IPW_FW_ERROR_BAD_DATABASE,
1485 IPW_FW_ERROR_ALLOC_FAIL,
1486 IPW_FW_ERROR_DMA_UNDERRUN,
1487 IPW_FW_ERROR_DMA_STATUS,
1488 IPW_FW_ERROR_DINOSTATUS_ERROR,
1489 IPW_FW_ERROR_EEPROMSTATUS_ERROR,
1490 IPW_FW_ERROR_SYSASSERT,
1491 IPW_FW_ERROR_FATAL_ERROR
1495 #define AUTH_SHARED_KEY 1
1496 #define AUTH_IGNORE 3
1498 #define HC_ASSOCIATE 0
1499 #define HC_REASSOCIATE 1
1500 #define HC_DISASSOCIATE 2
1501 #define HC_IBSS_START 3
1502 #define HC_IBSS_RECONF 4
1503 #define HC_DISASSOC_QUIET 5
1505 #define IPW_RATE_CAPABILITIES 1
1506 #define IPW_RATE_CONNECT 0
1510 * Rate values and masks
1512 #define IPW_TX_RATE_1MB 0x0A
1513 #define IPW_TX_RATE_2MB 0x14
1514 #define IPW_TX_RATE_5MB 0x37
1515 #define IPW_TX_RATE_6MB 0x0D
1516 #define IPW_TX_RATE_9MB 0x0F
1517 #define IPW_TX_RATE_11MB 0x6E
1518 #define IPW_TX_RATE_12MB 0x05
1519 #define IPW_TX_RATE_18MB 0x07
1520 #define IPW_TX_RATE_24MB 0x09
1521 #define IPW_TX_RATE_36MB 0x0B
1522 #define IPW_TX_RATE_48MB 0x01
1523 #define IPW_TX_RATE_54MB 0x03
1525 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1526 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1528 #define IPW_ORD_TABLE_0_MASK 0x0000F000
1529 #define IPW_ORD_TABLE_1_MASK 0x0000F100
1530 #define IPW_ORD_TABLE_2_MASK 0x0000F200
1531 #define IPW_ORD_TABLE_3_MASK 0x0000F300
1532 #define IPW_ORD_TABLE_4_MASK 0x0000F400
1533 #define IPW_ORD_TABLE_5_MASK 0x0000F500
1534 #define IPW_ORD_TABLE_6_MASK 0x0000F600
1535 #define IPW_ORD_TABLE_7_MASK 0x0000F700
1538 * Table 0 Entries (all entries are 32 bits)
1541 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1542 IPW_ORD_STAT_FRAG_TRESHOLD,
1543 IPW_ORD_STAT_RTS_THRESHOLD,
1544 IPW_ORD_STAT_TX_HOST_REQUESTS,
1545 IPW_ORD_STAT_TX_HOST_COMPLETE,
1546 IPW_ORD_STAT_TX_DIR_DATA,
1547 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1548 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1549 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1550 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1559 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1560 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1561 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1562 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1563 IPW_ORD_STAT_TX_DIR_DATA_G_9,
1564 IPW_ORD_STAT_TX_DIR_DATA_G_11,
1565 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1566 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1567 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1568 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1569 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1570 IPW_ORD_STAT_TX_DIR_DATA_G_54,
1571 IPW_ORD_STAT_TX_NON_DIR_DATA,
1572 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1573 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1574 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1575 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1584 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1585 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1586 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1587 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1588 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1589 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1590 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1591 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1592 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1593 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1594 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1595 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1596 IPW_ORD_STAT_TX_RETRY,
1597 IPW_ORD_STAT_TX_FAILURE,
1598 IPW_ORD_STAT_RX_ERR_CRC,
1599 IPW_ORD_STAT_RX_ERR_ICV,
1600 IPW_ORD_STAT_RX_NO_BUFFER,
1601 IPW_ORD_STAT_FULL_SCANS,
1602 IPW_ORD_STAT_PARTIAL_SCANS,
1603 IPW_ORD_STAT_TGH_ABORTED_SCANS,
1604 IPW_ORD_STAT_TX_TOTAL_BYTES,
1605 IPW_ORD_STAT_CURR_RSSI_RAW,
1606 IPW_ORD_STAT_RX_BEACON,
1607 IPW_ORD_STAT_MISSED_BEACONS,
1608 IPW_ORD_TABLE_0_LAST
1611 #define IPW_RSSI_TO_DBM 112
1616 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1622 * FW_VERSION: 16 byte string
1623 * FW_DATE: 16 byte string (only 14 bytes used)
1624 * UCODE_VERSION: 4 byte version code
1625 * UCODE_DATE: 5 bytes code code
1626 * ADDAPTER_MAC: 6 byte MAC address
1630 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1631 IPW_ORD_STAT_FW_DATE,
1632 IPW_ORD_STAT_UCODE_VERSION,
1633 IPW_ORD_STAT_UCODE_DATE,
1634 IPW_ORD_STAT_ADAPTER_MAC,
1636 IPW_ORD_TABLE_2_LAST
1641 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1642 IPW_ORD_STAT_TX_PACKET_FAILURE,
1643 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1644 IPW_ORD_STAT_TX_PACKET_ABORTED,
1645 IPW_ORD_TABLE_3_LAST
1650 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1655 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1656 IPW_ORD_STAT_AP_ASSNS,
1658 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1659 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1660 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1661 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1662 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1663 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1664 IPW_ORD_STAT_LINK_UP,
1665 IPW_ORD_STAT_LINK_DOWN,
1666 IPW_ORD_ANTENNA_DIVERSITY,
1668 IPW_ORD_TABLE_5_LAST
1673 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1676 IPW_ORD_TABLE_6_LAST
1681 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1682 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1683 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1684 IPW_ORD_STAT_CURR_RSSI_DBM,
1685 IPW_ORD_TABLE_7_LAST
1688 #define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500)
1689 #define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180)
1690 #define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184)
1691 #define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188)
1692 #define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C)
1694 struct ipw_fixed_rate {
1697 } __attribute__ ((packed));
1699 #define CX2_INDIRECT_ADDR_MASK (~0x3ul)
1705 u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
1706 } __attribute__ ((packed));
1708 #define CFG_BT_COEXISTENCE_MIN 0x00
1709 #define CFG_BT_COEXISTENCE_DEFER 0x02
1710 #define CFG_BT_COEXISTENCE_KILL 0x04
1711 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08
1712 #define CFG_BT_COEXISTENCE_OOB 0x10
1713 #define CFG_BT_COEXISTENCE_MAX 0xFF
1714 #define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM*/
1716 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0
1717 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1
1718 #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1720 #define CFG_SYS_ANTENNA_BOTH 0x000
1721 #define CFG_SYS_ANTENNA_A 0x001
1722 #define CFG_SYS_ANTENNA_B 0x003
1725 * The definitions below were lifted off the ipw2100 driver, which only
1726 * supports 'b' mode, so I'm sure these are not exactly correct.
1728 * Somebody fix these!!
1730 #define REG_MIN_CHANNEL 0
1731 #define REG_MAX_CHANNEL 14
1733 #define REG_CHANNEL_MASK 0x00003FFF
1734 #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
1736 static const long ipw_frequencies[] = {
1737 2412, 2417, 2422, 2427,
1738 2432, 2437, 2442, 2447,
1739 2452, 2457, 2462, 2467,
1743 #define FREQ_COUNT ARRAY_SIZE(ipw_frequencies)
1745 #define IPW_MAX_CONFIG_RETRIES 10
1747 static inline u32 frame_hdr_len(struct ieee80211_hdr *hdr)
1752 retval = sizeof(struct ieee80211_hdr);
1753 fc = le16_to_cpu(hdr->frame_ctl);
1756 * Function ToDS FromDS
1762 * Only WDS frames use Address4 among them. --YZ
1764 if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS))
1770 #endif /* __ipw2200_h__ */