1 /******************************************************************************
3 Copyright(c) 2003 - 2004 Intel Corporation. All rights reserved.
5 This program is free software; you can redistribute it and/or modify it
6 under the terms of version 2 of the GNU General Public License as
7 published by the Free Software Foundation.
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 You should have received a copy of the GNU General Public License along with
15 this program; if not, write to the Free Software Foundation, Inc., 59
16 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 The full GNU General Public License is included in this distribution in the
22 James P. Ketrenos <ipw2100-admin@linux.intel.com>
23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25 ******************************************************************************/
30 #define WEXT_USECHANNELS 1
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/config.h>
35 #include <linux/init.h>
37 #include <linux/version.h>
38 #include <linux/pci.h>
39 #include <linux/netdevice.h>
40 #include <linux/ethtool.h>
41 #include <linux/skbuff.h>
42 #include <linux/etherdevice.h>
43 #include <linux/delay.h>
44 #include <linux/random.h>
45 #include <linux/dma-mapping.h>
47 #include <linux/firmware.h>
48 #include <linux/wireless.h>
49 #include <linux/dma-mapping.h>
52 #include <net/ieee80211.h>
54 #define DRV_NAME "ipw2200"
56 #include <linux/workqueue.h>
58 /* Authentication and Association States */
59 enum connection_manager_assoc_states {
76 #define IPW_WAIT (1<<0)
77 #define IPW_QUIET (1<<1)
78 #define IPW_ROAMING (1<<2)
80 #define IPW_POWER_MODE_CAM 0x00 //(always on)
81 #define IPW_POWER_INDEX_1 0x01
82 #define IPW_POWER_INDEX_2 0x02
83 #define IPW_POWER_INDEX_3 0x03
84 #define IPW_POWER_INDEX_4 0x04
85 #define IPW_POWER_INDEX_5 0x05
86 #define IPW_POWER_AC 0x06
87 #define IPW_POWER_BATTERY 0x07
88 #define IPW_POWER_LIMIT 0x07
89 #define IPW_POWER_MASK 0x0F
90 #define IPW_POWER_ENABLED 0x10
91 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
93 #define IPW_CMD_HOST_COMPLETE 2
94 #define IPW_CMD_POWER_DOWN 4
95 #define IPW_CMD_SYSTEM_CONFIG 6
96 #define IPW_CMD_MULTICAST_ADDRESS 7
97 #define IPW_CMD_SSID 8
98 #define IPW_CMD_ADAPTER_ADDRESS 11
99 #define IPW_CMD_PORT_TYPE 12
100 #define IPW_CMD_RTS_THRESHOLD 15
101 #define IPW_CMD_FRAG_THRESHOLD 16
102 #define IPW_CMD_POWER_MODE 17
103 #define IPW_CMD_WEP_KEY 18
104 #define IPW_CMD_TGI_TX_KEY 19
105 #define IPW_CMD_SCAN_REQUEST 20
106 #define IPW_CMD_ASSOCIATE 21
107 #define IPW_CMD_SUPPORTED_RATES 22
108 #define IPW_CMD_SCAN_ABORT 23
109 #define IPW_CMD_TX_FLUSH 24
110 #define IPW_CMD_QOS_PARAMETERS 25
111 #define IPW_CMD_SCAN_REQUEST_EXT 26
112 #define IPW_CMD_DINO_CONFIG 30
113 #define IPW_CMD_RSN_CAPABILITIES 31
114 #define IPW_CMD_RX_KEY 32
115 #define IPW_CMD_CARD_DISABLE 33
116 #define IPW_CMD_SEED_NUMBER 34
117 #define IPW_CMD_TX_POWER 35
118 #define IPW_CMD_COUNTRY_INFO 36
119 #define IPW_CMD_AIRONET_INFO 37
120 #define IPW_CMD_AP_TX_POWER 38
121 #define IPW_CMD_CCKM_INFO 39
122 #define IPW_CMD_CCX_VER_INFO 40
123 #define IPW_CMD_SET_CALIBRATION 41
124 #define IPW_CMD_SENSITIVITY_CALIB 42
125 #define IPW_CMD_RETRY_LIMIT 51
126 #define IPW_CMD_IPW_PRE_POWER_DOWN 58
127 #define IPW_CMD_VAP_BEACON_TEMPLATE 60
128 #define IPW_CMD_VAP_DTIM_PERIOD 61
129 #define IPW_CMD_EXT_SUPPORTED_RATES 62
130 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
131 #define IPW_CMD_VAP_QUIET_INTERVALS 64
132 #define IPW_CMD_VAP_CHANNEL_SWITCH 65
133 #define IPW_CMD_VAP_MANDATORY_CHANNELS 66
134 #define IPW_CMD_VAP_CELL_PWR_LIMIT 67
135 #define IPW_CMD_VAP_CF_PARAM_SET 68
136 #define IPW_CMD_VAP_SET_BEACONING_STATE 69
137 #define IPW_CMD_MEASUREMENT 80
138 #define IPW_CMD_POWER_CAPABILITY 81
139 #define IPW_CMD_SUPPORTED_CHANNELS 82
140 #define IPW_CMD_TPC_REPORT 83
141 #define IPW_CMD_WME_INFO 84
142 #define IPW_CMD_PRODUCTION_COMMAND 85
143 #define IPW_CMD_LINKSYS_EOU_INFO 90
146 #define NUM_TFD_CHUNKS 6
148 #define TX_QUEUE_SIZE 32
149 #define RX_QUEUE_SIZE 32
151 #define DINO_CMD_WEP_KEY 0x08
152 #define DINO_CMD_TX 0x0B
153 #define DCT_ANTENNA_A 0x01
154 #define DCT_ANTENNA_B 0x02
161 * TX Queue Flag Definitions
164 /* abort attempt if mgmt frame is rx'd */
165 #define DCT_FLAG_ABORT_MGMT 0x01
168 #define DCT_FLAG_CTS_REQUIRED 0x02
170 /* use short preamble */
171 #define DCT_FLAG_LONG_PREAMBLE 0x00
172 #define DCT_FLAG_SHORT_PREAMBLE 0x04
175 #define DCT_FLAG_RTS_REQD 0x08
177 /* dont calculate duration field */
178 #define DCT_FLAG_DUR_SET 0x10
180 /* even if MAC WEP set (allows pre-encrypt) */
181 #define DCT_FLAG_NO_WEP 0x20
183 /* overwrite TSF field */
184 #define DCT_FLAG_TSF_REQD 0x40
186 /* ACK rx is expected to follow */
187 #define DCT_FLAG_ACK_REQD 0x80
189 #define DCT_FLAG_EXT_MODE_CCK 0x01
190 #define DCT_FLAG_EXT_MODE_OFDM 0x00
192 #define TX_RX_TYPE_MASK 0xFF
193 #define TX_FRAME_TYPE 0x00
194 #define TX_HOST_COMMAND_TYPE 0x01
195 #define RX_FRAME_TYPE 0x09
196 #define RX_HOST_NOTIFICATION_TYPE 0x03
197 #define RX_HOST_CMD_RESPONSE_TYPE 0x04
198 #define RX_TX_FRAME_RESPONSE_TYPE 0x05
199 #define TFD_NEED_IRQ_MASK 0x04
201 #define HOST_CMD_DINO_CONFIG 30
203 #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
204 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
205 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
206 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
207 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
208 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
209 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
210 #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
211 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
212 #define HOST_NOTIFICATION_TX_STATUS 19
213 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
214 #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
215 #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
216 #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
217 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
218 #define HOST_NOTIFICATION_NOISE_STATS 25
219 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
220 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
222 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
223 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 24
224 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
225 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
227 #define MACADRR_BYTE_LEN 6
229 #define DCR_TYPE_AP 0x01
230 #define DCR_TYPE_WLAP 0x02
231 #define DCR_TYPE_MU_ESS 0x03
232 #define DCR_TYPE_MU_IBSS 0x04
233 #define DCR_TYPE_MU_PIBSS 0x05
234 #define DCR_TYPE_SNIFFER 0x06
235 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
238 * Generic queue structure
240 * Contains common data for Rx and Tx queues
243 int n_bd; /**< number of BDs in this queue */
244 int first_empty; /**< 1-st empty entry (index) */
245 int last_used; /**< last used entry (index) */
246 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
247 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
248 dma_addr_t dma_addr; /**< physical addr for BD's */
249 int low_mark; /**< low watermark, resume queue if free space more than this */
250 int high_mark; /**< high watermark, stop queue if free space less than this */
251 } __attribute__ ((packed));
255 u16 duration; // watch out for endians!
256 u8 addr1[MACADRR_BYTE_LEN];
257 u8 addr2[MACADRR_BYTE_LEN];
258 u8 addr3[MACADRR_BYTE_LEN];
259 u16 seq_ctrl; // more endians!
260 u8 addr4[MACADRR_BYTE_LEN];
262 } __attribute__ ((packed));
266 u16 duration; // watch out for endians!
267 u8 addr1[MACADRR_BYTE_LEN];
268 u8 addr2[MACADRR_BYTE_LEN];
269 u8 addr3[MACADRR_BYTE_LEN];
270 u16 seq_ctrl; // more endians!
271 u8 addr4[MACADRR_BYTE_LEN];
272 } __attribute__ ((packed));
276 u16 duration; // watch out for endians!
277 u8 addr1[MACADRR_BYTE_LEN];
278 u8 addr2[MACADRR_BYTE_LEN];
279 u8 addr3[MACADRR_BYTE_LEN];
280 u16 seq_ctrl; // more endians!
282 } __attribute__ ((packed));
286 u16 duration; // watch out for endians!
287 u8 addr1[MACADRR_BYTE_LEN];
288 u8 addr2[MACADRR_BYTE_LEN];
289 u8 addr3[MACADRR_BYTE_LEN];
290 u16 seq_ctrl; // more endians!
291 } __attribute__ ((packed));
293 // TX TFD with 32 byte MAC Header
295 struct machdr32 mchdr; // 32
296 u32 uivplaceholder[2]; // 8
297 } __attribute__ ((packed));
299 // TX TFD with 30 byte MAC Header
301 struct machdr30 mchdr; // 30
303 u32 uivplaceholder[2]; // 8
304 } __attribute__ ((packed));
306 // tx tfd with 26 byte mac header
308 struct machdr26 mchdr; // 26
309 u8 reserved1[2]; // 2
310 u32 uivplaceholder[2]; // 8
311 u8 reserved2[4]; // 4
312 } __attribute__ ((packed));
314 // tx tfd with 24 byte mac header
316 struct machdr24 mchdr; // 24
317 u32 uivplaceholder[2]; // 8
319 } __attribute__ ((packed));
321 #define DCT_WEP_KEY_FIELD_LENGTH 16
328 } __attribute__ ((packed));
333 u8 station_number; /* 0 for BSS */
345 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
348 u16 next_packet_duration;
350 u16 back_off_counter; //////txop;
355 /* 802.11 MAC Header */
357 struct tx_tfd_24 tfd_24;
358 struct tx_tfd_26 tfd_26;
359 struct tx_tfd_30 tfd_30;
360 struct tx_tfd_32 tfd_32;
363 /* Payload DMA info */
365 u32 chunk_ptr[NUM_TFD_CHUNKS];
366 u16 chunk_len[NUM_TFD_CHUNKS];
367 } __attribute__ ((packed));
369 struct txrx_control_flags {
374 } __attribute__ ((packed));
377 #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
380 struct txrx_control_flags control_flags;
382 struct tfd_data data;
383 struct tfd_command cmd;
384 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
386 } __attribute__ ((packed));
388 typedef void destructor_func(const void *);
391 * Tx Queue for DMA. Queue consists of circular buffer of
392 * BD's and required locking structures.
394 struct clx2_tx_queue {
396 struct tfd_frame *bd;
397 struct ieee80211_txb **txb;
401 * RX related structures and functions
403 #define RX_FREE_BUFFERS 32
404 #define RX_LOW_WATERMARK 8
406 #define SUP_RATE_11A_MAX_NUM_CHANNELS (8)
407 #define SUP_RATE_11B_MAX_NUM_CHANNELS (4)
408 #define SUP_RATE_11G_MAX_NUM_CHANNELS (12)
410 // Used for passing to driver number of successes and failures per rate
411 struct rate_histogram {
413 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
414 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
415 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
418 u32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
419 u32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
420 u32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
422 } __attribute__ ((packed));
424 /* statistics command response */
425 struct ipw_cmd_stats {
433 u16 reserved_frame_types;
438 u16 long_distance_ina_fina;
439 u16 dsp_silence_unreachable;
440 u16 accumulated_rssi;
441 u16 rx_ovfl_frame_tossed;
442 u16 rssi_silence_threshold;
443 u16 rx_ovfl_frame_supplied;
444 u16 last_rx_frame_signal;
445 u16 last_rx_frame_noise;
446 u16 rx_autodetec_no_ofdm;
447 u16 rx_autodetec_no_barker;
449 } __attribute__ ((packed));
451 struct notif_channel_result {
453 struct ipw_cmd_stats stats;
455 } __attribute__ ((packed));
457 struct notif_scan_complete {
462 } __attribute__ ((packed));
464 struct notif_frag_length {
467 } __attribute__ ((packed));
469 struct notif_beacon_state {
472 } __attribute__ ((packed));
474 struct notif_tgi_tx_key {
479 } __attribute__ ((packed));
481 struct notif_link_deterioration {
482 struct ipw_cmd_stats stats;
485 struct rate_histogram histogram;
488 } __attribute__ ((packed));
490 struct notif_association {
492 } __attribute__ ((packed));
494 struct notif_authenticate {
496 struct machdr24 addr;
498 } __attribute__ ((packed));
500 struct notif_calibration {
502 } __attribute__ ((packed));
506 } __attribute__ ((packed));
508 struct ipw_rx_notification {
514 struct notif_association assoc;
515 struct notif_authenticate auth;
516 struct notif_channel_result channel_result;
517 struct notif_scan_complete scan_complete;
518 struct notif_frag_length frag_len;
519 struct notif_beacon_state beacon_state;
520 struct notif_tgi_tx_key tgi_tx_key;
521 struct notif_link_deterioration link_deterioration;
522 struct notif_calibration calibration;
523 struct notif_noise noise;
526 } __attribute__ ((packed));
528 struct ipw_rx_frame {
530 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
531 u8 received_channel; // The channel that this frame was received on.
532 // Note that for .11b this does not have to be
533 // the same as the channel that it was sent.
543 u8 control; // control bit should be on in bg
544 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
546 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
549 } __attribute__ ((packed));
551 struct ipw_rx_header {
556 } __attribute__ ((packed));
558 struct ipw_rx_packet {
559 struct ipw_rx_header header;
561 struct ipw_rx_frame frame;
562 struct ipw_rx_notification notification;
564 } __attribute__ ((packed));
566 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
567 #define IPW_RX_FRAME_SIZE sizeof(struct ipw_rx_header) + \
568 sizeof(struct ipw_rx_frame)
570 struct ipw_rx_mem_buffer {
572 struct ipw_rx_buffer *rxb;
574 struct list_head list;
575 }; /* Not transferred over network, so not __attribute__ ((packed)) */
577 struct ipw_rx_queue {
578 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
579 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
580 u32 processed; /* Internal index to last handled Rx packet */
581 u32 read; /* Shared index to newest available Rx buffer */
582 u32 write; /* Shared index to oldest written Rx packet */
583 u32 free_count; /* Number of pre-allocated buffers in rx_free */
584 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
585 struct list_head rx_free; /* Own an SKBs */
586 struct list_head rx_used; /* No SKB allocated */
588 }; /* Not transferred over network, so not __attribute__ ((packed)) */
590 struct alive_command_responce {
593 u16 software_revision;
594 u8 device_identifier;
598 u16 clock_settle_time;
599 u16 powerup_settle_time;
601 u8 time_stamp[5]; /* month, day, year, hours, minutes */
603 } __attribute__ ((packed));
605 #define IPW_MAX_RATES 12
609 u8 rates[IPW_MAX_RATES];
610 } __attribute__ ((packed));
612 struct command_block {
613 unsigned int control;
617 } __attribute__ ((packed));
619 #define CB_NUMBER_OF_ELEMENTS_SMALL 64
620 struct fw_image_desc {
621 unsigned long last_cb_index;
622 unsigned long current_cb_index;
623 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
625 unsigned long p_addr;
629 struct ipw_sys_config {
632 u8 answer_broadcast_ssid_probe;
633 u8 accept_all_data_frames;
634 u8 accept_non_directed_frames;
635 u8 exclude_unicast_unencrypted;
636 u8 disable_unicast_decryption;
637 u8 exclude_multicast_unencrypted;
638 u8 disable_multicast_decryption;
639 u8 antenna_diversity;
641 u8 dot11g_auto_detection;
642 u8 enable_cts_to_self;
643 u8 enable_multicast_filtering;
644 u8 bt_coexist_collision_thr;
646 u8 accept_all_mgmt_bcpr;
647 u8 accept_all_mgtm_frames;
648 u8 pass_noise_stats_to_host;
650 } __attribute__ ((packed));
652 struct ipw_multicast_addr {
653 u8 num_of_multicast_addresses;
659 } __attribute__ ((packed));
667 } __attribute__ ((packed));
669 struct ipw_tgi_tx_key {
676 } __attribute__ ((packed));
678 #define IPW_SCAN_CHANNELS 54
680 struct ipw_scan_request {
683 u8 channels_list[IPW_SCAN_CHANNELS];
684 u8 channels_reserved[3];
685 } __attribute__ ((packed));
688 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
689 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
690 IPW_SCAN_ACTIVE_DIRECT_SCAN,
691 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
692 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
696 struct ipw_scan_request_ext {
698 u8 channels_list[IPW_SCAN_CHANNELS];
699 u8 scan_type[IPW_SCAN_CHANNELS / 2];
701 u16 dwell_time[IPW_SCAN_TYPES];
702 } __attribute__ ((packed));
704 extern inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
707 return scan->scan_type[index / 2] & 0x0F;
709 return (scan->scan_type[index / 2] & 0xF0) >> 4;
712 extern inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
713 u8 index, u8 scan_type)
716 scan->scan_type[index / 2] =
717 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
719 scan->scan_type[index / 2] =
720 (scan->scan_type[index / 2] & 0x0F) |
721 ((scan_type & 0x0F) << 4);
724 struct ipw_associate {
726 u8 auth_type:4, auth_key:4;
743 } __attribute__ ((packed));
745 struct ipw_supported_rates {
750 u8 supported_rates[IPW_MAX_RATES];
751 } __attribute__ ((packed));
753 struct ipw_rts_threshold {
756 } __attribute__ ((packed));
758 struct ipw_frag_threshold {
761 } __attribute__ ((packed));
763 struct ipw_retry_limit {
764 u8 short_retry_limit;
767 } __attribute__ ((packed));
769 struct ipw_dino_config {
770 u32 dino_config_addr;
771 u16 dino_config_size;
774 } __attribute__ ((packed));
776 struct ipw_aironet_info {
780 } __attribute__ ((packed));
788 u8 station_address[6];
791 } __attribute__ ((packed));
793 struct ipw_country_channel_info {
797 } __attribute__ ((packed));
799 struct ipw_country_info {
803 struct ipw_country_channel_info groups[7];
804 } __attribute__ ((packed));
806 struct ipw_channel_tx_power {
809 } __attribute__ ((packed));
811 #define SCAN_ASSOCIATED_INTERVAL (HZ)
812 #define SCAN_INTERVAL (HZ / 10)
813 #define MAX_A_CHANNELS 37
814 #define MAX_B_CHANNELS 14
816 struct ipw_tx_power {
819 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
820 } __attribute__ ((packed));
822 struct ipw_qos_parameters {
828 } __attribute__ ((packed));
830 struct ipw_rsn_capabilities {
834 } __attribute__ ((packed));
836 struct ipw_sensitivity_calib {
839 } __attribute__ ((packed));
842 * Host command structure.
844 * On input, the following fields should be filled:
848 * - param (if needed)
851 * - \a status contains status;
852 * - \a param filled with status parameters.
855 u32 cmd; /**< Host command */
856 u32 status;/**< Status */
858 /**< How many 32 bit parameters in the status */
859 u32 len; /**< incoming parameters length, bytes */
861 * command parameters.
862 * There should be enough space for incoming and
863 * outcoming parameters.
864 * Incoming parameters listed 1-st, followed by outcoming params.
865 * nParams=(len+3)/4+status_len
868 } __attribute__ ((packed));
870 #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
872 #define STATUS_INT_ENABLED (1<<1)
873 #define STATUS_RF_KILL_HW (1<<2)
874 #define STATUS_RF_KILL_SW (1<<3)
875 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
877 #define STATUS_INIT (1<<5)
878 #define STATUS_AUTH (1<<6)
879 #define STATUS_ASSOCIATED (1<<7)
880 #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
882 #define STATUS_ASSOCIATING (1<<8)
883 #define STATUS_DISASSOCIATING (1<<9)
884 #define STATUS_ROAMING (1<<10)
885 #define STATUS_EXIT_PENDING (1<<11)
886 #define STATUS_DISASSOC_PENDING (1<<12)
887 #define STATUS_STATE_PENDING (1<<13)
889 #define STATUS_SCAN_PENDING (1<<20)
890 #define STATUS_SCANNING (1<<21)
891 #define STATUS_SCAN_ABORTING (1<<22)
893 #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
894 #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
895 #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
897 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
899 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
900 #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
901 #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
902 #define CFG_CUSTOM_MAC (1<<3)
903 #define CFG_PREAMBLE_LONG (1<<4)
904 #define CFG_ADHOC_PERSIST (1<<5)
905 #define CFG_ASSOCIATE (1<<6)
906 #define CFG_FIXED_RATE (1<<7)
907 #define CFG_ADHOC_CREATE (1<<8)
909 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
910 #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
912 #define MAX_STATIONS 32
913 #define IPW_INVALID_STATION (0xff)
915 struct ipw_station_entry {
916 u8 mac_addr[ETH_ALEN];
921 #define AVG_ENTRIES 8
923 s16 entries[AVG_ENTRIES];
930 /* ieee device used by generic ieee processing code */
931 struct ieee80211_device *ieee;
932 struct ieee80211_security sec;
937 /* basic pci-network driver stuff */
938 struct pci_dev *pci_dev;
939 struct net_device *net_dev;
941 /* pci hardware address support */
942 void __iomem *hw_base;
943 unsigned long hw_len;
945 struct fw_image_desc sram_desc;
947 /* result of ucode download */
948 struct alive_command_responce dino_alive;
950 wait_queue_head_t wait_command_queue;
951 wait_queue_head_t wait_state;
953 /* Rx and Tx DMA processing queues */
954 struct ipw_rx_queue *rxq;
955 struct clx2_tx_queue txq_cmd;
956 struct clx2_tx_queue txq[4];
963 struct average average_missed_beacons;
964 struct average average_rssi;
965 struct average average_noise;
967 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
968 int rx_pend_max; /**< maximum pending buffers for one IRQ */
969 u32 hcmd_seq; /**< sequence number for hcmd */
970 u32 missed_beacon_threshold;
971 u32 roaming_threshold;
973 struct ipw_associate assoc_request;
974 struct ieee80211_network *assoc_network;
976 unsigned long ts_scan_abort;
977 struct ipw_supported_rates rates;
978 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
979 struct ipw_rates supp; /**< software defined */
980 struct ipw_rates extended; /**< use for corresp. IE, AP only */
982 struct notif_link_deterioration last_link_deterioration; /** for statistics */
983 struct ipw_cmd *hcmd; /**< host command currently executed */
985 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
986 u32 tsf_bcn[2]; /**< TSF from latest beacon */
988 struct notif_calibration calib; /**< last calibration */
990 /* ordinal interface with firmware */
998 /* context information */
999 u8 essid[IW_ESSID_MAX_SIZE];
1001 u8 nick[IW_ESSID_MAX_SIZE];
1004 struct ipw_sys_config sys_config;
1008 u8 mac_addr[ETH_ALEN];
1010 u8 stations[MAX_STATIONS][ETH_ALEN];
1012 u32 notif_missed_beacons;
1014 /* Statistics and counters normalized with each association */
1015 u32 last_missed_beacons;
1016 u32 last_tx_packets;
1017 u32 last_rx_packets;
1018 u32 last_tx_failures;
1022 u32 missed_adhoc_beacons;
1029 u8 eeprom[0x100]; /* 256 bytes of eeprom */
1032 struct iw_statistics wstats;
1034 struct workqueue_struct *workqueue;
1036 struct work_struct adhoc_check;
1037 struct work_struct associate;
1038 struct work_struct disassociate;
1039 struct work_struct rx_replenish;
1040 struct work_struct request_scan;
1041 struct work_struct adapter_restart;
1042 struct work_struct rf_kill;
1043 struct work_struct up;
1044 struct work_struct down;
1045 struct work_struct gather_stats;
1046 struct work_struct abort_scan;
1047 struct work_struct roam;
1048 struct work_struct scan_check;
1050 struct tasklet_struct irq_tasklet;
1052 #define IPW_2200BG 1
1053 #define IPW_2915ABG 2
1056 #define IPW_DEFAULT_TX_POWER 0x14
1065 /* Used to pass the current INTA value from ISR to Tasklet */
1068 /* debugging info */
1076 #ifdef CONFIG_IPW_DEBUG
1077 #define IPW_DEBUG(level, fmt, args...) \
1078 do { if (ipw_debug_level & (level)) \
1079 printk(KERN_DEBUG DRV_NAME": %c %s " fmt, \
1080 in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
1082 #define IPW_DEBUG(level, fmt, args...) do {} while (0)
1083 #endif /* CONFIG_IPW_DEBUG */
1086 * To use the debug system;
1088 * If you are defining a new debug classification, simply add it to the #define
1089 * list here in the form of:
1091 * #define IPW_DL_xxxx VALUE
1093 * shifting value to the left one bit from the previous entry. xxxx should be
1094 * the name of the classification (for example, WEP)
1096 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1097 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1098 * to send output to that classification.
1100 * To add your debug level to the list of levels seen when you perform
1102 * % cat /proc/net/ipw/debug_level
1104 * you simply need to add your entry to the ipw_debug_levels array.
1106 * If you do not see debug_level in /proc/net/ipw then you do not have
1107 * CONFIG_IPW_DEBUG defined in your kernel configuration
1111 #define IPW_DL_ERROR (1<<0)
1112 #define IPW_DL_WARNING (1<<1)
1113 #define IPW_DL_INFO (1<<2)
1114 #define IPW_DL_WX (1<<3)
1115 #define IPW_DL_HOST_COMMAND (1<<5)
1116 #define IPW_DL_STATE (1<<6)
1118 #define IPW_DL_NOTIF (1<<10)
1119 #define IPW_DL_SCAN (1<<11)
1120 #define IPW_DL_ASSOC (1<<12)
1121 #define IPW_DL_DROP (1<<13)
1122 #define IPW_DL_IOCTL (1<<14)
1124 #define IPW_DL_MANAGE (1<<15)
1125 #define IPW_DL_FW (1<<16)
1126 #define IPW_DL_RF_KILL (1<<17)
1127 #define IPW_DL_FW_ERRORS (1<<18)
1129 #define IPW_DL_ORD (1<<20)
1131 #define IPW_DL_FRAG (1<<21)
1132 #define IPW_DL_WEP (1<<22)
1133 #define IPW_DL_TX (1<<23)
1134 #define IPW_DL_RX (1<<24)
1135 #define IPW_DL_ISR (1<<25)
1136 #define IPW_DL_FW_INFO (1<<26)
1137 #define IPW_DL_IO (1<<27)
1138 #define IPW_DL_TRACE (1<<28)
1140 #define IPW_DL_STATS (1<<29)
1142 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1143 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1144 #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1146 #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1147 #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1148 #define IPW_DEBUG_STATUS(f, a...) IPW_DEBUG(IPW_DL_STATUS, f, ## a)
1149 #define IPW_DEBUG_TRACE(f, a...) IPW_DEBUG(IPW_DL_TRACE, f, ## a)
1150 #define IPW_DEBUG_RX(f, a...) IPW_DEBUG(IPW_DL_RX, f, ## a)
1151 #define IPW_DEBUG_TX(f, a...) IPW_DEBUG(IPW_DL_TX, f, ## a)
1152 #define IPW_DEBUG_ISR(f, a...) IPW_DEBUG(IPW_DL_ISR, f, ## a)
1153 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1154 #define IPW_DEBUG_WEP(f, a...) IPW_DEBUG(IPW_DL_WEP, f, ## a)
1155 #define IPW_DEBUG_HC(f, a...) IPW_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1156 #define IPW_DEBUG_FRAG(f, a...) IPW_DEBUG(IPW_DL_FRAG, f, ## a)
1157 #define IPW_DEBUG_FW(f, a...) IPW_DEBUG(IPW_DL_FW, f, ## a)
1158 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1159 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1160 #define IPW_DEBUG_IO(f, a...) IPW_DEBUG(IPW_DL_IO, f, ## a)
1161 #define IPW_DEBUG_ORD(f, a...) IPW_DEBUG(IPW_DL_ORD, f, ## a)
1162 #define IPW_DEBUG_FW_INFO(f, a...) IPW_DEBUG(IPW_DL_FW_INFO, f, ## a)
1163 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1164 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1165 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1166 #define IPW_DEBUG_STATS(f, a...) IPW_DEBUG(IPW_DL_STATS, f, ## a)
1168 #include <linux/ctype.h>
1171 * Register bit definitions
1174 /* Dino control registers bits */
1176 #define DINO_ENABLE_SYSTEM 0x80
1177 #define DINO_ENABLE_CS 0x40
1178 #define DINO_RXFIFO_DATA 0x01
1179 #define DINO_CONTROL_REG 0x00200000
1181 #define CX2_INTA_RW 0x00000008
1182 #define CX2_INTA_MASK_R 0x0000000C
1183 #define CX2_INDIRECT_ADDR 0x00000010
1184 #define CX2_INDIRECT_DATA 0x00000014
1185 #define CX2_AUTOINC_ADDR 0x00000018
1186 #define CX2_AUTOINC_DATA 0x0000001C
1187 #define CX2_RESET_REG 0x00000020
1188 #define CX2_GP_CNTRL_RW 0x00000024
1190 #define CX2_READ_INT_REGISTER 0xFF4
1192 #define CX2_GP_CNTRL_BIT_INIT_DONE 0x00000004
1194 #define CX2_REGISTER_DOMAIN1_END 0x00001000
1195 #define CX2_SRAM_READ_INT_REGISTER 0x00000ff4
1197 #define CX2_SHARED_LOWER_BOUND 0x00000200
1198 #define CX2_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1200 #define CX2_NIC_SRAM_LOWER_BOUND 0x00000000
1201 #define CX2_NIC_SRAM_UPPER_BOUND 0x00030000
1203 #define CX2_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1204 #define CX2_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1205 #define CX2_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1208 * RESET Register Bit Indexes
1210 #define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1211 #define CX2_START_STANDBY (1<<2)
1212 #define CX2_ACTIVITY_LED (1<<4)
1213 #define CX2_ASSOCIATED_LED (1<<5)
1214 #define CX2_OFDM_LED (1<<6)
1215 #define CX2_RESET_REG_SW_RESET (1<<7)
1216 #define CX2_RESET_REG_MASTER_DISABLED (1<<8)
1217 #define CX2_RESET_REG_STOP_MASTER (1<<9)
1218 #define CX2_GATE_ODMA (1<<25)
1219 #define CX2_GATE_IDMA (1<<26)
1220 #define CX2_ARC_KESHET_CONFIG (1<<27)
1221 #define CX2_GATE_ADMA (1<<29)
1223 #define CX2_CSR_CIS_UPPER_BOUND 0x00000200
1224 #define CX2_DOMAIN_0_END 0x1000
1225 #define CLX_MEM_BAR_SIZE 0x1000
1227 #define CX2_BASEBAND_CONTROL_STATUS 0X00200000
1228 #define CX2_BASEBAND_TX_FIFO_WRITE 0X00200004
1229 #define CX2_BASEBAND_RX_FIFO_READ 0X00200004
1230 #define CX2_BASEBAND_CONTROL_STORE 0X00200010
1232 #define CX2_INTERNAL_CMD_EVENT 0X00300004
1233 #define CX2_BASEBAND_POWER_DOWN 0x00000001
1235 #define CX2_MEM_HALT_AND_RESET 0x003000e0
1237 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1238 #define CX2_BIT_HALT_RESET_ON 0x80000000
1239 #define CX2_BIT_HALT_RESET_OFF 0x00000000
1241 #define CB_LAST_VALID 0x20000000
1242 #define CB_INT_ENABLED 0x40000000
1243 #define CB_VALID 0x80000000
1244 #define CB_SRC_LE 0x08000000
1245 #define CB_DEST_LE 0x04000000
1246 #define CB_SRC_AUTOINC 0x00800000
1247 #define CB_SRC_IO_GATED 0x00400000
1248 #define CB_DEST_AUTOINC 0x00080000
1249 #define CB_SRC_SIZE_LONG 0x00200000
1250 #define CB_DEST_SIZE_LONG 0x00020000
1254 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1255 #define DMA_CB_STOP_AND_ABORT 0x00000C00
1256 #define DMA_CB_START 0x00000100
1258 #define CX2_SHARED_SRAM_SIZE 0x00030000
1259 #define CX2_SHARED_SRAM_DMA_CONTROL 0x00027000
1260 #define CB_MAX_LENGTH 0x1FFF
1262 #define CX2_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1263 #define CX2_EEPROM_IMAGE_SIZE 0x100
1266 #define CX2_DMA_I_CURRENT_CB 0x003000D0
1267 #define CX2_DMA_O_CURRENT_CB 0x003000D4
1268 #define CX2_DMA_I_DMA_CONTROL 0x003000A4
1269 #define CX2_DMA_I_CB_BASE 0x003000A0
1271 #define CX2_TX_CMD_QUEUE_BD_BASE (0x00000200)
1272 #define CX2_TX_CMD_QUEUE_BD_SIZE (0x00000204)
1273 #define CX2_TX_QUEUE_0_BD_BASE (0x00000208)
1274 #define CX2_TX_QUEUE_0_BD_SIZE (0x0000020C)
1275 #define CX2_TX_QUEUE_1_BD_BASE (0x00000210)
1276 #define CX2_TX_QUEUE_1_BD_SIZE (0x00000214)
1277 #define CX2_TX_QUEUE_2_BD_BASE (0x00000218)
1278 #define CX2_TX_QUEUE_2_BD_SIZE (0x0000021C)
1279 #define CX2_TX_QUEUE_3_BD_BASE (0x00000220)
1280 #define CX2_TX_QUEUE_3_BD_SIZE (0x00000224)
1281 #define CX2_RX_BD_BASE (0x00000240)
1282 #define CX2_RX_BD_SIZE (0x00000244)
1283 #define CX2_RFDS_TABLE_LOWER (0x00000500)
1285 #define CX2_TX_CMD_QUEUE_READ_INDEX (0x00000280)
1286 #define CX2_TX_QUEUE_0_READ_INDEX (0x00000284)
1287 #define CX2_TX_QUEUE_1_READ_INDEX (0x00000288)
1288 #define CX2_TX_QUEUE_2_READ_INDEX (0x0000028C)
1289 #define CX2_TX_QUEUE_3_READ_INDEX (0x00000290)
1290 #define CX2_RX_READ_INDEX (0x000002A0)
1292 #define CX2_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1293 #define CX2_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1294 #define CX2_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1295 #define CX2_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1296 #define CX2_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1297 #define CX2_RX_WRITE_INDEX (0x00000FA0)
1300 * EEPROM Related Definitions
1303 #define IPW_EEPROM_DATA_SRAM_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x814)
1304 #define IPW_EEPROM_DATA_SRAM_SIZE (CX2_SHARED_LOWER_BOUND + 0x818)
1305 #define IPW_EEPROM_LOAD_DISABLE (CX2_SHARED_LOWER_BOUND + 0x81C)
1306 #define IPW_EEPROM_DATA (CX2_SHARED_LOWER_BOUND + 0x820)
1307 #define IPW_EEPROM_UPPER_ADDRESS (CX2_SHARED_LOWER_BOUND + 0x9E0)
1309 #define IPW_STATION_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0xA0C)
1310 #define IPW_STATION_TABLE_UPPER (CX2_SHARED_LOWER_BOUND + 0xB0C)
1311 #define IPW_REQUEST_ATIM (CX2_SHARED_LOWER_BOUND + 0xB0C)
1312 #define IPW_ATIM_SENT (CX2_SHARED_LOWER_BOUND + 0xB10)
1313 #define IPW_WHO_IS_AWAKE (CX2_SHARED_LOWER_BOUND + 0xB14)
1314 #define IPW_DURING_ATIM_WINDOW (CX2_SHARED_LOWER_BOUND + 0xB18)
1318 #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1320 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1321 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1323 /* EEPROM access by BYTE */
1324 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1325 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1326 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1327 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1328 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1329 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1330 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1331 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1332 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1333 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1335 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset*/
1336 #define EEPROM_NIC_TYPE_STANDARD 0
1337 #define EEPROM_NIC_TYPE_DELL 1
1338 #define EEPROM_NIC_TYPE_FUJITSU 2
1339 #define EEPROM_NIC_TYPE_IBM 3
1340 #define EEPROM_NIC_TYPE_HP 4
1342 #define FW_MEM_REG_LOWER_BOUND 0x00300000
1343 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1345 #define EEPROM_BIT_SK (1<<0)
1346 #define EEPROM_BIT_CS (1<<1)
1347 #define EEPROM_BIT_DI (1<<2)
1348 #define EEPROM_BIT_DO (1<<4)
1350 #define EEPROM_CMD_READ 0x2
1352 /* Interrupts masks */
1353 #define CX2_INTA_NONE 0x00000000
1355 #define CX2_INTA_BIT_RX_TRANSFER 0x00000002
1356 #define CX2_INTA_BIT_STATUS_CHANGE 0x00000010
1357 #define CX2_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1360 #define CX2_INTA_BIT_TX_CMD_QUEUE 0x00000800
1361 #define CX2_INTA_BIT_TX_QUEUE_1 0x00001000
1362 #define CX2_INTA_BIT_TX_QUEUE_2 0x00002000
1363 #define CX2_INTA_BIT_TX_QUEUE_3 0x00004000
1364 #define CX2_INTA_BIT_TX_QUEUE_4 0x00008000
1366 #define CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1368 #define CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1369 #define CX2_INTA_BIT_POWER_DOWN 0x00200000
1371 #define CX2_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1372 #define CX2_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1373 #define CX2_INTA_BIT_RF_KILL_DONE 0x04000000
1374 #define CX2_INTA_BIT_FATAL_ERROR 0x40000000
1375 #define CX2_INTA_BIT_PARITY_ERROR 0x80000000
1377 /* Interrupts enabled at init time. */
1378 #define CX2_INTA_MASK_ALL \
1379 (CX2_INTA_BIT_TX_QUEUE_1 | \
1380 CX2_INTA_BIT_TX_QUEUE_2 | \
1381 CX2_INTA_BIT_TX_QUEUE_3 | \
1382 CX2_INTA_BIT_TX_QUEUE_4 | \
1383 CX2_INTA_BIT_TX_CMD_QUEUE | \
1384 CX2_INTA_BIT_RX_TRANSFER | \
1385 CX2_INTA_BIT_FATAL_ERROR | \
1386 CX2_INTA_BIT_PARITY_ERROR | \
1387 CX2_INTA_BIT_STATUS_CHANGE | \
1388 CX2_INTA_BIT_FW_INITIALIZATION_DONE | \
1389 CX2_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1390 CX2_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1391 CX2_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1392 CX2_INTA_BIT_POWER_DOWN | \
1393 CX2_INTA_BIT_RF_KILL_DONE )
1395 #define IPWSTATUS_ERROR_LOG (CX2_SHARED_LOWER_BOUND + 0x410)
1396 #define IPW_EVENT_LOG (CX2_SHARED_LOWER_BOUND + 0x414)
1398 /* FW event log definitions */
1399 #define EVENT_ELEM_SIZE (3 * sizeof(u32))
1400 #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1402 /* FW error log definitions */
1403 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1404 #define ERROR_START_OFFSET (1 * sizeof(u32))
1407 IPW_FW_ERROR_OK = 0,
1409 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1410 IPW_FW_ERROR_MEMORY_OVERFLOW,
1411 IPW_FW_ERROR_BAD_PARAM,
1412 IPW_FW_ERROR_BAD_CHECKSUM,
1413 IPW_FW_ERROR_NMI_INTERRUPT,
1414 IPW_FW_ERROR_BAD_DATABASE,
1415 IPW_FW_ERROR_ALLOC_FAIL,
1416 IPW_FW_ERROR_DMA_UNDERRUN,
1417 IPW_FW_ERROR_DMA_STATUS,
1418 IPW_FW_ERROR_DINOSTATUS_ERROR,
1419 IPW_FW_ERROR_EEPROMSTATUS_ERROR,
1420 IPW_FW_ERROR_SYSASSERT,
1421 IPW_FW_ERROR_FATAL_ERROR
1425 #define AUTH_SHARED_KEY 1
1426 #define AUTH_IGNORE 3
1428 #define HC_ASSOCIATE 0
1429 #define HC_REASSOCIATE 1
1430 #define HC_DISASSOCIATE 2
1431 #define HC_IBSS_START 3
1432 #define HC_IBSS_RECONF 4
1433 #define HC_DISASSOC_QUIET 5
1435 #define IPW_RATE_CAPABILITIES 1
1436 #define IPW_RATE_CONNECT 0
1439 * Rate values and masks
1441 #define IPW_TX_RATE_1MB 0x0A
1442 #define IPW_TX_RATE_2MB 0x14
1443 #define IPW_TX_RATE_5MB 0x37
1444 #define IPW_TX_RATE_6MB 0x0D
1445 #define IPW_TX_RATE_9MB 0x0F
1446 #define IPW_TX_RATE_11MB 0x6E
1447 #define IPW_TX_RATE_12MB 0x05
1448 #define IPW_TX_RATE_18MB 0x07
1449 #define IPW_TX_RATE_24MB 0x09
1450 #define IPW_TX_RATE_36MB 0x0B
1451 #define IPW_TX_RATE_48MB 0x01
1452 #define IPW_TX_RATE_54MB 0x03
1454 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1455 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1457 #define IPW_ORD_TABLE_0_MASK 0x0000F000
1458 #define IPW_ORD_TABLE_1_MASK 0x0000F100
1459 #define IPW_ORD_TABLE_2_MASK 0x0000F200
1460 #define IPW_ORD_TABLE_3_MASK 0x0000F300
1461 #define IPW_ORD_TABLE_4_MASK 0x0000F400
1462 #define IPW_ORD_TABLE_5_MASK 0x0000F500
1463 #define IPW_ORD_TABLE_6_MASK 0x0000F600
1464 #define IPW_ORD_TABLE_7_MASK 0x0000F700
1467 * Table 0 Entries (all entries are 32 bits)
1470 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1471 IPW_ORD_STAT_FRAG_TRESHOLD,
1472 IPW_ORD_STAT_RTS_THRESHOLD,
1473 IPW_ORD_STAT_TX_HOST_REQUESTS,
1474 IPW_ORD_STAT_TX_HOST_COMPLETE,
1475 IPW_ORD_STAT_TX_DIR_DATA,
1476 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1477 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1478 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1479 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1482 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1483 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1484 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1485 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1486 IPW_ORD_STAT_TX_DIR_DATA_G_9,
1487 IPW_ORD_STAT_TX_DIR_DATA_G_11,
1488 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1489 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1490 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1491 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1492 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1493 IPW_ORD_STAT_TX_DIR_DATA_G_54,
1494 IPW_ORD_STAT_TX_NON_DIR_DATA,
1495 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1496 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1497 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1498 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1501 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1502 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1503 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1504 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1505 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1506 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1507 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1508 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1509 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1510 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1511 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1512 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1513 IPW_ORD_STAT_TX_RETRY,
1514 IPW_ORD_STAT_TX_FAILURE,
1515 IPW_ORD_STAT_RX_ERR_CRC,
1516 IPW_ORD_STAT_RX_ERR_ICV,
1517 IPW_ORD_STAT_RX_NO_BUFFER,
1518 IPW_ORD_STAT_FULL_SCANS,
1519 IPW_ORD_STAT_PARTIAL_SCANS,
1520 IPW_ORD_STAT_TGH_ABORTED_SCANS,
1521 IPW_ORD_STAT_TX_TOTAL_BYTES,
1522 IPW_ORD_STAT_CURR_RSSI_RAW,
1523 IPW_ORD_STAT_RX_BEACON,
1524 IPW_ORD_STAT_MISSED_BEACONS,
1525 IPW_ORD_TABLE_0_LAST
1528 #define IPW_RSSI_TO_DBM 112
1533 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1539 * FW_VERSION: 16 byte string
1540 * FW_DATE: 16 byte string (only 14 bytes used)
1541 * UCODE_VERSION: 4 byte version code
1542 * UCODE_DATE: 5 bytes code code
1543 * ADDAPTER_MAC: 6 byte MAC address
1547 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1548 IPW_ORD_STAT_FW_DATE,
1549 IPW_ORD_STAT_UCODE_VERSION,
1550 IPW_ORD_STAT_UCODE_DATE,
1551 IPW_ORD_STAT_ADAPTER_MAC,
1553 IPW_ORD_TABLE_2_LAST
1558 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1559 IPW_ORD_STAT_TX_PACKET_FAILURE,
1560 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1561 IPW_ORD_STAT_TX_PACKET_ABORTED,
1562 IPW_ORD_TABLE_3_LAST
1567 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1572 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1573 IPW_ORD_STAT_AP_ASSNS,
1575 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1576 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1577 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1578 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1579 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1580 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1581 IPW_ORD_STAT_LINK_UP,
1582 IPW_ORD_STAT_LINK_DOWN,
1583 IPW_ORD_ANTENNA_DIVERSITY,
1585 IPW_ORD_TABLE_5_LAST
1590 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1593 IPW_ORD_TABLE_6_LAST
1598 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1599 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1600 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1601 IPW_ORD_STAT_CURR_RSSI_DBM,
1602 IPW_ORD_TABLE_7_LAST
1605 #define IPW_ORDINALS_TABLE_LOWER (CX2_SHARED_LOWER_BOUND + 0x500)
1606 #define IPW_ORDINALS_TABLE_0 (CX2_SHARED_LOWER_BOUND + 0x180)
1607 #define IPW_ORDINALS_TABLE_1 (CX2_SHARED_LOWER_BOUND + 0x184)
1608 #define IPW_ORDINALS_TABLE_2 (CX2_SHARED_LOWER_BOUND + 0x188)
1609 #define IPW_MEM_FIXED_OVERRIDE (CX2_SHARED_LOWER_BOUND + 0x41C)
1611 struct ipw_fixed_rate {
1614 } __attribute__ ((packed));
1616 #define CX2_INDIRECT_ADDR_MASK (~0x3ul)
1622 u32 param[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
1623 } __attribute__ ((packed));
1625 #define CFG_BT_COEXISTENCE_MIN 0x00
1626 #define CFG_BT_COEXISTENCE_DEFER 0x02
1627 #define CFG_BT_COEXISTENCE_KILL 0x04
1628 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08
1629 #define CFG_BT_COEXISTENCE_OOB 0x10
1630 #define CFG_BT_COEXISTENCE_MAX 0xFF
1631 #define CFG_BT_COEXISTENCE_DEF 0x80 /* read Bt from EEPROM */
1633 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x0
1634 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x1
1635 #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1637 #define CFG_SYS_ANTENNA_BOTH 0x000
1638 #define CFG_SYS_ANTENNA_A 0x001
1639 #define CFG_SYS_ANTENNA_B 0x003
1642 * The definitions below were lifted off the ipw2100 driver, which only
1643 * supports 'b' mode, so I'm sure these are not exactly correct.
1645 * Somebody fix these!!
1647 #define REG_MIN_CHANNEL 0
1648 #define REG_MAX_CHANNEL 14
1650 #define REG_CHANNEL_MASK 0x00003FFF
1651 #define IPW_IBSS_11B_DEFAULT_MASK 0x87ff
1653 static const long ipw_frequencies[] = {
1654 2412, 2417, 2422, 2427,
1655 2432, 2437, 2442, 2447,
1656 2452, 2457, 2462, 2467,
1660 #define FREQ_COUNT ARRAY_SIZE(ipw_frequencies)
1662 #define IPW_MAX_CONFIG_RETRIES 10
1664 static inline u32 frame_hdr_len(struct ieee80211_hdr_4addr *hdr)
1669 retval = sizeof(struct ieee80211_hdr_3addr);
1670 fc = le16_to_cpu(hdr->frame_ctl);
1673 * Function ToDS FromDS
1679 * Only WDS frames use Address4 among them. --YZ
1681 if (!(fc & IEEE80211_FCTL_TODS) || !(fc & IEEE80211_FCTL_FROMDS))
1687 #endif /* __ipw2200_h__ */