3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
34 #include "bcm43xx_main.h"
35 #include "bcm43xx_phy.h"
36 #include "bcm43xx_radio.h"
37 #include "bcm43xx_ilt.h"
40 /* Table for bcm43xx_radio_calibrationvalue() */
41 static const u16 rcc_table[16] = {
42 0x0002, 0x0003, 0x0001, 0x000F,
43 0x0006, 0x0007, 0x0005, 0x000F,
44 0x000A, 0x000B, 0x0009, 0x000F,
45 0x000E, 0x000F, 0x000D, 0x000F,
48 /* Reverse the bits of a 4bit value.
49 * Example: 1101 is flipped 1011
51 static u16 flip_4bit(u16 value)
55 assert((value & ~0x000F) == 0x0000);
57 flipped |= (value & 0x0001) << 3;
58 flipped |= (value & 0x0002) << 1;
59 flipped |= (value & 0x0004) >> 1;
60 flipped |= (value & 0x0008) >> 3;
65 /* Get the freq, as it has to be written to the device. */
67 u16 channel2freq_bg(u8 channel)
69 /* Frequencies are given as frequencies_bg[index] + 2.4GHz
70 * Starting with channel 1
72 static const u16 frequencies_bg[14] = {
79 assert(channel >= 1 && channel <= 14);
81 return frequencies_bg[channel - 1];
84 /* Get the freq, as it has to be written to the device. */
86 u16 channel2freq_a(u8 channel)
88 assert(channel <= 200);
90 return (5000 + 5 * channel);
93 void bcm43xx_radio_lock(struct bcm43xx_private *bcm)
97 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
98 status |= BCM43xx_SBF_RADIOREG_LOCK;
99 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
104 void bcm43xx_radio_unlock(struct bcm43xx_private *bcm)
108 bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER); /* dummy read */
109 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
110 status &= ~BCM43xx_SBF_RADIOREG_LOCK;
111 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
115 u16 bcm43xx_radio_read16(struct bcm43xx_private *bcm, u16 offset)
117 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
118 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
121 case BCM43xx_PHYTYPE_A:
124 case BCM43xx_PHYTYPE_B:
125 if (radio->version == 0x2053) {
128 else if (offset < 0x80)
130 } else if (radio->version == 0x2050) {
135 case BCM43xx_PHYTYPE_G:
140 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, offset);
141 return bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
144 void bcm43xx_radio_write16(struct bcm43xx_private *bcm, u16 offset, u16 val)
146 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, offset);
148 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW, val);
151 static void bcm43xx_set_all_gains(struct bcm43xx_private *bcm,
152 s16 first, s16 second, s16 third)
154 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
156 u16 start = 0x08, end = 0x18;
166 for (i = 0; i < 4; i++)
167 bcm43xx_ilt_write(bcm, offset + i, first);
169 for (i = start; i < end; i++)
170 bcm43xx_ilt_write(bcm, offset + i, second);
173 tmp = ((u16)third << 14) | ((u16)third << 6);
174 bcm43xx_phy_write(bcm, 0x04A0,
175 (bcm43xx_phy_read(bcm, 0x04A0) & 0xBFBF) | tmp);
176 bcm43xx_phy_write(bcm, 0x04A1,
177 (bcm43xx_phy_read(bcm, 0x04A1) & 0xBFBF) | tmp);
178 bcm43xx_phy_write(bcm, 0x04A2,
179 (bcm43xx_phy_read(bcm, 0x04A2) & 0xBFBF) | tmp);
181 bcm43xx_dummy_transmission(bcm);
184 static void bcm43xx_set_original_gains(struct bcm43xx_private *bcm)
186 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
189 u16 start = 0x0008, end = 0x0018;
197 for (i = 0; i < 4; i++) {
199 tmp |= (i & 0x0001) << 1;
200 tmp |= (i & 0x0002) >> 1;
202 bcm43xx_ilt_write(bcm, offset + i, tmp);
205 for (i = start; i < end; i++)
206 bcm43xx_ilt_write(bcm, offset + i, i - start);
208 bcm43xx_phy_write(bcm, 0x04A0,
209 (bcm43xx_phy_read(bcm, 0x04A0) & 0xBFBF) | 0x4040);
210 bcm43xx_phy_write(bcm, 0x04A1,
211 (bcm43xx_phy_read(bcm, 0x04A1) & 0xBFBF) | 0x4040);
212 bcm43xx_phy_write(bcm, 0x04A2,
213 (bcm43xx_phy_read(bcm, 0x04A2) & 0xBFBF) | 0x4000);
214 bcm43xx_dummy_transmission(bcm);
217 /* Synthetic PU workaround */
218 static void bcm43xx_synth_pu_workaround(struct bcm43xx_private *bcm, u8 channel)
220 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
222 if (radio->version != 0x2050 || radio->revision >= 6) {
223 /* We do not need the workaround. */
228 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL,
229 channel2freq_bg(channel + 4));
231 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL,
235 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL,
236 channel2freq_bg(channel));
239 u8 bcm43xx_radio_aci_detect(struct bcm43xx_private *bcm, u8 channel)
241 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
243 u16 saved, rssi, temp;
246 saved = bcm43xx_phy_read(bcm, 0x0403);
247 bcm43xx_radio_selectchannel(bcm, channel, 0);
248 bcm43xx_phy_write(bcm, 0x0403, (saved & 0xFFF8) | 5);
249 if (radio->aci_hw_rssi)
250 rssi = bcm43xx_phy_read(bcm, 0x048A) & 0x3F;
253 /* clamp temp to signed 5bit */
256 for (i = 0;i < 100; i++) {
257 temp = (bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x3F;
265 bcm43xx_phy_write(bcm, 0x0403, saved);
270 u8 bcm43xx_radio_aci_scan(struct bcm43xx_private *bcm)
272 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
273 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
275 unsigned int channel = radio->channel;
276 unsigned int i, j, start, end;
277 unsigned long phylock_flags;
279 if (!((phy->type == BCM43xx_PHYTYPE_G) && (phy->rev > 0)))
282 bcm43xx_phy_lock(bcm, phylock_flags);
283 bcm43xx_radio_lock(bcm);
284 bcm43xx_phy_write(bcm, 0x0802,
285 bcm43xx_phy_read(bcm, 0x0802) & 0xFFFC);
286 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
287 bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & 0x7FFF);
288 bcm43xx_set_all_gains(bcm, 3, 8, 1);
290 start = (channel - 5 > 0) ? channel - 5 : 1;
291 end = (channel + 5 < 14) ? channel + 5 : 13;
293 for (i = start; i <= end; i++) {
294 if (abs(channel - i) > 2)
295 ret[i-1] = bcm43xx_radio_aci_detect(bcm, i);
297 bcm43xx_radio_selectchannel(bcm, channel, 0);
298 bcm43xx_phy_write(bcm, 0x0802,
299 (bcm43xx_phy_read(bcm, 0x0802) & 0xFFFC) | 0x0003);
300 bcm43xx_phy_write(bcm, 0x0403,
301 bcm43xx_phy_read(bcm, 0x0403) & 0xFFF8);
302 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
303 bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) | 0x8000);
304 bcm43xx_set_original_gains(bcm);
305 for (i = 0; i < 13; i++) {
308 end = (i + 5 < 13) ? i + 5 : 13;
309 for (j = i; j < end; j++)
312 bcm43xx_radio_unlock(bcm);
313 bcm43xx_phy_unlock(bcm, phylock_flags);
315 return ret[channel - 1];
318 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
319 void bcm43xx_nrssi_hw_write(struct bcm43xx_private *bcm, u16 offset, s16 val)
321 bcm43xx_phy_write(bcm, BCM43xx_PHY_NRSSILT_CTRL, offset);
323 bcm43xx_phy_write(bcm, BCM43xx_PHY_NRSSILT_DATA, (u16)val);
326 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
327 s16 bcm43xx_nrssi_hw_read(struct bcm43xx_private *bcm, u16 offset)
331 bcm43xx_phy_write(bcm, BCM43xx_PHY_NRSSILT_CTRL, offset);
332 val = bcm43xx_phy_read(bcm, BCM43xx_PHY_NRSSILT_DATA);
337 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
338 void bcm43xx_nrssi_hw_update(struct bcm43xx_private *bcm, u16 val)
343 for (i = 0; i < 64; i++) {
344 tmp = bcm43xx_nrssi_hw_read(bcm, i);
346 tmp = limit_value(tmp, -32, 31);
347 bcm43xx_nrssi_hw_write(bcm, i, tmp);
351 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
352 void bcm43xx_nrssi_mem_update(struct bcm43xx_private *bcm)
354 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
358 delta = 0x1F - radio->nrssi[0];
359 for (i = 0; i < 64; i++) {
360 tmp = (i - delta) * radio->nrssislope;
363 tmp = limit_value(tmp, 0, 0x3F);
364 radio->nrssi_lt[i] = tmp;
368 static void bcm43xx_calc_nrssi_offset(struct bcm43xx_private *bcm)
370 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
371 u16 backup[20] = { 0 };
376 backup[0] = bcm43xx_phy_read(bcm, 0x0001);
377 backup[1] = bcm43xx_phy_read(bcm, 0x0811);
378 backup[2] = bcm43xx_phy_read(bcm, 0x0812);
379 backup[3] = bcm43xx_phy_read(bcm, 0x0814);
380 backup[4] = bcm43xx_phy_read(bcm, 0x0815);
381 backup[5] = bcm43xx_phy_read(bcm, 0x005A);
382 backup[6] = bcm43xx_phy_read(bcm, 0x0059);
383 backup[7] = bcm43xx_phy_read(bcm, 0x0058);
384 backup[8] = bcm43xx_phy_read(bcm, 0x000A);
385 backup[9] = bcm43xx_phy_read(bcm, 0x0003);
386 backup[10] = bcm43xx_radio_read16(bcm, 0x007A);
387 backup[11] = bcm43xx_radio_read16(bcm, 0x0043);
389 bcm43xx_phy_write(bcm, 0x0429,
390 bcm43xx_phy_read(bcm, 0x0429) & 0x7FFF);
391 bcm43xx_phy_write(bcm, 0x0001,
392 (bcm43xx_phy_read(bcm, 0x0001) & 0x3FFF) | 0x4000);
393 bcm43xx_phy_write(bcm, 0x0811,
394 bcm43xx_phy_read(bcm, 0x0811) | 0x000C);
395 bcm43xx_phy_write(bcm, 0x0812,
396 (bcm43xx_phy_read(bcm, 0x0812) & 0xFFF3) | 0x0004);
397 bcm43xx_phy_write(bcm, 0x0802,
398 bcm43xx_phy_read(bcm, 0x0802) & ~(0x1 | 0x2));
400 backup[12] = bcm43xx_phy_read(bcm, 0x002E);
401 backup[13] = bcm43xx_phy_read(bcm, 0x002F);
402 backup[14] = bcm43xx_phy_read(bcm, 0x080F);
403 backup[15] = bcm43xx_phy_read(bcm, 0x0810);
404 backup[16] = bcm43xx_phy_read(bcm, 0x0801);
405 backup[17] = bcm43xx_phy_read(bcm, 0x0060);
406 backup[18] = bcm43xx_phy_read(bcm, 0x0014);
407 backup[19] = bcm43xx_phy_read(bcm, 0x0478);
409 bcm43xx_phy_write(bcm, 0x002E, 0);
410 bcm43xx_phy_write(bcm, 0x002F, 0);
411 bcm43xx_phy_write(bcm, 0x080F, 0);
412 bcm43xx_phy_write(bcm, 0x0810, 0);
413 bcm43xx_phy_write(bcm, 0x0478,
414 bcm43xx_phy_read(bcm, 0x0478) | 0x0100);
415 bcm43xx_phy_write(bcm, 0x0801,
416 bcm43xx_phy_read(bcm, 0x0801) | 0x0040);
417 bcm43xx_phy_write(bcm, 0x0060,
418 bcm43xx_phy_read(bcm, 0x0060) | 0x0040);
419 bcm43xx_phy_write(bcm, 0x0014,
420 bcm43xx_phy_read(bcm, 0x0014) | 0x0200);
422 bcm43xx_radio_write16(bcm, 0x007A,
423 bcm43xx_radio_read16(bcm, 0x007A) | 0x0070);
424 bcm43xx_radio_write16(bcm, 0x007A,
425 bcm43xx_radio_read16(bcm, 0x007A) | 0x0080);
428 v47F = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
432 for (i = 7; i >= 4; i--) {
433 bcm43xx_radio_write16(bcm, 0x007B, i);
435 v47F = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
438 if (v47F < 31 && saved == 0xFFFF)
444 bcm43xx_radio_write16(bcm, 0x007A,
445 bcm43xx_radio_read16(bcm, 0x007A) & 0x007F);
446 bcm43xx_phy_write(bcm, 0x0814,
447 bcm43xx_phy_read(bcm, 0x0814) | 0x0001);
448 bcm43xx_phy_write(bcm, 0x0815,
449 bcm43xx_phy_read(bcm, 0x0815) & 0xFFFE);
450 bcm43xx_phy_write(bcm, 0x0811,
451 bcm43xx_phy_read(bcm, 0x0811) | 0x000C);
452 bcm43xx_phy_write(bcm, 0x0812,
453 bcm43xx_phy_read(bcm, 0x0812) | 0x000C);
454 bcm43xx_phy_write(bcm, 0x0811,
455 bcm43xx_phy_read(bcm, 0x0811) | 0x0030);
456 bcm43xx_phy_write(bcm, 0x0812,
457 bcm43xx_phy_read(bcm, 0x0812) | 0x0030);
458 bcm43xx_phy_write(bcm, 0x005A, 0x0480);
459 bcm43xx_phy_write(bcm, 0x0059, 0x0810);
460 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
462 bcm43xx_phy_write(bcm, 0x0003, 0x0122);
464 bcm43xx_phy_write(bcm, 0x000A,
465 bcm43xx_phy_read(bcm, 0x000A)
468 bcm43xx_phy_write(bcm, 0x0814,
469 bcm43xx_phy_read(bcm, 0x0814) | 0x0004);
470 bcm43xx_phy_write(bcm, 0x0815,
471 bcm43xx_phy_read(bcm, 0x0815) & 0xFFFB);
472 bcm43xx_phy_write(bcm, 0x0003,
473 (bcm43xx_phy_read(bcm, 0x0003) & 0xFF9F)
475 bcm43xx_radio_write16(bcm, 0x007A,
476 bcm43xx_radio_read16(bcm, 0x007A) | 0x000F);
477 bcm43xx_set_all_gains(bcm, 3, 0, 1);
478 bcm43xx_radio_write16(bcm, 0x0043,
479 (bcm43xx_radio_read16(bcm, 0x0043)
482 v47F = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
486 for (i = 0; i < 4; i++) {
487 bcm43xx_radio_write16(bcm, 0x007B, i);
489 v47F = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
492 if (v47F > -31 && saved == 0xFFFF)
500 bcm43xx_radio_write16(bcm, 0x007B, saved);
503 bcm43xx_phy_write(bcm, 0x002E, backup[12]);
504 bcm43xx_phy_write(bcm, 0x002F, backup[13]);
505 bcm43xx_phy_write(bcm, 0x080F, backup[14]);
506 bcm43xx_phy_write(bcm, 0x0810, backup[15]);
508 bcm43xx_phy_write(bcm, 0x0814, backup[3]);
509 bcm43xx_phy_write(bcm, 0x0815, backup[4]);
510 bcm43xx_phy_write(bcm, 0x005A, backup[5]);
511 bcm43xx_phy_write(bcm, 0x0059, backup[6]);
512 bcm43xx_phy_write(bcm, 0x0058, backup[7]);
513 bcm43xx_phy_write(bcm, 0x000A, backup[8]);
514 bcm43xx_phy_write(bcm, 0x0003, backup[9]);
515 bcm43xx_radio_write16(bcm, 0x0043, backup[11]);
516 bcm43xx_radio_write16(bcm, 0x007A, backup[10]);
517 bcm43xx_phy_write(bcm, 0x0802,
518 bcm43xx_phy_read(bcm, 0x0802) | 0x1 | 0x2);
519 bcm43xx_phy_write(bcm, 0x0429,
520 bcm43xx_phy_read(bcm, 0x0429) | 0x8000);
521 bcm43xx_set_original_gains(bcm);
523 bcm43xx_phy_write(bcm, 0x0801, backup[16]);
524 bcm43xx_phy_write(bcm, 0x0060, backup[17]);
525 bcm43xx_phy_write(bcm, 0x0014, backup[18]);
526 bcm43xx_phy_write(bcm, 0x0478, backup[19]);
528 bcm43xx_phy_write(bcm, 0x0001, backup[0]);
529 bcm43xx_phy_write(bcm, 0x0812, backup[2]);
530 bcm43xx_phy_write(bcm, 0x0811, backup[1]);
533 void bcm43xx_calc_nrssi_slope(struct bcm43xx_private *bcm)
535 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
536 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
537 u16 backup[18] = { 0 };
542 case BCM43xx_PHYTYPE_B:
543 backup[0] = bcm43xx_radio_read16(bcm, 0x007A);
544 backup[1] = bcm43xx_radio_read16(bcm, 0x0052);
545 backup[2] = bcm43xx_radio_read16(bcm, 0x0043);
546 backup[3] = bcm43xx_phy_read(bcm, 0x0030);
547 backup[4] = bcm43xx_phy_read(bcm, 0x0026);
548 backup[5] = bcm43xx_phy_read(bcm, 0x0015);
549 backup[6] = bcm43xx_phy_read(bcm, 0x002A);
550 backup[7] = bcm43xx_phy_read(bcm, 0x0020);
551 backup[8] = bcm43xx_phy_read(bcm, 0x005A);
552 backup[9] = bcm43xx_phy_read(bcm, 0x0059);
553 backup[10] = bcm43xx_phy_read(bcm, 0x0058);
554 backup[11] = bcm43xx_read16(bcm, 0x03E2);
555 backup[12] = bcm43xx_read16(bcm, 0x03E6);
556 backup[13] = bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT);
558 tmp = bcm43xx_radio_read16(bcm, 0x007A);
559 tmp &= (phy->rev >= 5) ? 0x007F : 0x000F;
560 bcm43xx_radio_write16(bcm, 0x007A, tmp);
561 bcm43xx_phy_write(bcm, 0x0030, 0x00FF);
562 bcm43xx_write16(bcm, 0x03EC, 0x7F7F);
563 bcm43xx_phy_write(bcm, 0x0026, 0x0000);
564 bcm43xx_phy_write(bcm, 0x0015,
565 bcm43xx_phy_read(bcm, 0x0015) | 0x0020);
566 bcm43xx_phy_write(bcm, 0x002A, 0x08A3);
567 bcm43xx_radio_write16(bcm, 0x007A,
568 bcm43xx_radio_read16(bcm, 0x007A) | 0x0080);
570 nrssi0 = (s16)bcm43xx_phy_read(bcm, 0x0027);
571 bcm43xx_radio_write16(bcm, 0x007A,
572 bcm43xx_radio_read16(bcm, 0x007A) & 0x007F);
574 bcm43xx_write16(bcm, 0x03E6, 0x0040);
575 } else if (phy->rev == 0) {
576 bcm43xx_write16(bcm, 0x03E6, 0x0122);
578 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
579 bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT) & 0x2000);
581 bcm43xx_phy_write(bcm, 0x0020, 0x3F3F);
582 bcm43xx_phy_write(bcm, 0x0015, 0xF330);
583 bcm43xx_radio_write16(bcm, 0x005A, 0x0060);
584 bcm43xx_radio_write16(bcm, 0x0043,
585 bcm43xx_radio_read16(bcm, 0x0043) & 0x00F0);
586 bcm43xx_phy_write(bcm, 0x005A, 0x0480);
587 bcm43xx_phy_write(bcm, 0x0059, 0x0810);
588 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
591 nrssi1 = (s16)bcm43xx_phy_read(bcm, 0x0027);
592 bcm43xx_phy_write(bcm, 0x0030, backup[3]);
593 bcm43xx_radio_write16(bcm, 0x007A, backup[0]);
594 bcm43xx_write16(bcm, 0x03E2, backup[11]);
595 bcm43xx_phy_write(bcm, 0x0026, backup[4]);
596 bcm43xx_phy_write(bcm, 0x0015, backup[5]);
597 bcm43xx_phy_write(bcm, 0x002A, backup[6]);
598 bcm43xx_synth_pu_workaround(bcm, radio->channel);
600 bcm43xx_write16(bcm, 0x03F4, backup[13]);
602 bcm43xx_phy_write(bcm, 0x0020, backup[7]);
603 bcm43xx_phy_write(bcm, 0x005A, backup[8]);
604 bcm43xx_phy_write(bcm, 0x0059, backup[9]);
605 bcm43xx_phy_write(bcm, 0x0058, backup[10]);
606 bcm43xx_radio_write16(bcm, 0x0052, backup[1]);
607 bcm43xx_radio_write16(bcm, 0x0043, backup[2]);
609 if (nrssi0 == nrssi1)
610 radio->nrssislope = 0x00010000;
612 radio->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
615 radio->nrssi[0] = nrssi0;
616 radio->nrssi[1] = nrssi1;
619 case BCM43xx_PHYTYPE_G:
620 if (radio->revision >= 9)
622 if (radio->revision == 8)
623 bcm43xx_calc_nrssi_offset(bcm);
625 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
626 bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & 0x7FFF);
627 bcm43xx_phy_write(bcm, 0x0802,
628 bcm43xx_phy_read(bcm, 0x0802) & 0xFFFC);
629 backup[7] = bcm43xx_read16(bcm, 0x03E2);
630 bcm43xx_write16(bcm, 0x03E2,
631 bcm43xx_read16(bcm, 0x03E2) | 0x8000);
632 backup[0] = bcm43xx_radio_read16(bcm, 0x007A);
633 backup[1] = bcm43xx_radio_read16(bcm, 0x0052);
634 backup[2] = bcm43xx_radio_read16(bcm, 0x0043);
635 backup[3] = bcm43xx_phy_read(bcm, 0x0015);
636 backup[4] = bcm43xx_phy_read(bcm, 0x005A);
637 backup[5] = bcm43xx_phy_read(bcm, 0x0059);
638 backup[6] = bcm43xx_phy_read(bcm, 0x0058);
639 backup[8] = bcm43xx_read16(bcm, 0x03E6);
640 backup[9] = bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT);
642 backup[10] = bcm43xx_phy_read(bcm, 0x002E);
643 backup[11] = bcm43xx_phy_read(bcm, 0x002F);
644 backup[12] = bcm43xx_phy_read(bcm, 0x080F);
645 backup[13] = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_LO_CONTROL);
646 backup[14] = bcm43xx_phy_read(bcm, 0x0801);
647 backup[15] = bcm43xx_phy_read(bcm, 0x0060);
648 backup[16] = bcm43xx_phy_read(bcm, 0x0014);
649 backup[17] = bcm43xx_phy_read(bcm, 0x0478);
650 bcm43xx_phy_write(bcm, 0x002E, 0);
651 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_LO_CONTROL, 0);
653 case 4: case 6: case 7:
654 bcm43xx_phy_write(bcm, 0x0478,
655 bcm43xx_phy_read(bcm, 0x0478)
657 bcm43xx_phy_write(bcm, 0x0801,
658 bcm43xx_phy_read(bcm, 0x0801)
662 bcm43xx_phy_write(bcm, 0x0801,
663 bcm43xx_phy_read(bcm, 0x0801)
667 bcm43xx_phy_write(bcm, 0x0060,
668 bcm43xx_phy_read(bcm, 0x0060)
670 bcm43xx_phy_write(bcm, 0x0014,
671 bcm43xx_phy_read(bcm, 0x0014)
674 bcm43xx_radio_write16(bcm, 0x007A,
675 bcm43xx_radio_read16(bcm, 0x007A) | 0x0070);
676 bcm43xx_set_all_gains(bcm, 0, 8, 0);
677 bcm43xx_radio_write16(bcm, 0x007A,
678 bcm43xx_radio_read16(bcm, 0x007A) & 0x00F7);
680 bcm43xx_phy_write(bcm, 0x0811,
681 (bcm43xx_phy_read(bcm, 0x0811) & 0xFFCF) | 0x0030);
682 bcm43xx_phy_write(bcm, 0x0812,
683 (bcm43xx_phy_read(bcm, 0x0812) & 0xFFCF) | 0x0010);
685 bcm43xx_radio_write16(bcm, 0x007A,
686 bcm43xx_radio_read16(bcm, 0x007A) | 0x0080);
689 nrssi0 = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
690 if (nrssi0 >= 0x0020)
693 bcm43xx_radio_write16(bcm, 0x007A,
694 bcm43xx_radio_read16(bcm, 0x007A) & 0x007F);
696 bcm43xx_phy_write(bcm, 0x0003,
697 (bcm43xx_phy_read(bcm, 0x0003)
701 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
702 bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT)
704 bcm43xx_radio_write16(bcm, 0x007A,
705 bcm43xx_radio_read16(bcm, 0x007A) | 0x000F);
706 bcm43xx_phy_write(bcm, 0x0015, 0xF330);
708 bcm43xx_phy_write(bcm, 0x0812,
709 (bcm43xx_phy_read(bcm, 0x0812) & 0xFFCF) | 0x0020);
710 bcm43xx_phy_write(bcm, 0x0811,
711 (bcm43xx_phy_read(bcm, 0x0811) & 0xFFCF) | 0x0020);
714 bcm43xx_set_all_gains(bcm, 3, 0, 1);
715 if (radio->revision == 8) {
716 bcm43xx_radio_write16(bcm, 0x0043, 0x001F);
718 tmp = bcm43xx_radio_read16(bcm, 0x0052) & 0xFF0F;
719 bcm43xx_radio_write16(bcm, 0x0052, tmp | 0x0060);
720 tmp = bcm43xx_radio_read16(bcm, 0x0043) & 0xFFF0;
721 bcm43xx_radio_write16(bcm, 0x0043, tmp | 0x0009);
723 bcm43xx_phy_write(bcm, 0x005A, 0x0480);
724 bcm43xx_phy_write(bcm, 0x0059, 0x0810);
725 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
727 nrssi1 = (s16)((bcm43xx_phy_read(bcm, 0x047F) >> 8) & 0x003F);
728 if (nrssi1 >= 0x0020)
730 if (nrssi0 == nrssi1)
731 radio->nrssislope = 0x00010000;
733 radio->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
735 radio->nrssi[0] = nrssi1;
736 radio->nrssi[1] = nrssi0;
739 bcm43xx_phy_write(bcm, 0x002E, backup[10]);
740 bcm43xx_phy_write(bcm, 0x002F, backup[11]);
741 bcm43xx_phy_write(bcm, 0x080F, backup[12]);
742 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_LO_CONTROL, backup[13]);
745 bcm43xx_phy_write(bcm, 0x0812,
746 bcm43xx_phy_read(bcm, 0x0812) & 0xFFCF);
747 bcm43xx_phy_write(bcm, 0x0811,
748 bcm43xx_phy_read(bcm, 0x0811) & 0xFFCF);
751 bcm43xx_radio_write16(bcm, 0x007A, backup[0]);
752 bcm43xx_radio_write16(bcm, 0x0052, backup[1]);
753 bcm43xx_radio_write16(bcm, 0x0043, backup[2]);
754 bcm43xx_write16(bcm, 0x03E2, backup[7]);
755 bcm43xx_write16(bcm, 0x03E6, backup[8]);
756 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, backup[9]);
757 bcm43xx_phy_write(bcm, 0x0015, backup[3]);
758 bcm43xx_phy_write(bcm, 0x005A, backup[4]);
759 bcm43xx_phy_write(bcm, 0x0059, backup[5]);
760 bcm43xx_phy_write(bcm, 0x0058, backup[6]);
761 bcm43xx_synth_pu_workaround(bcm, radio->channel);
762 bcm43xx_phy_write(bcm, 0x0802,
763 bcm43xx_phy_read(bcm, 0x0802) | (0x0001 | 0x0002));
764 bcm43xx_set_original_gains(bcm);
765 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
766 bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) | 0x8000);
768 bcm43xx_phy_write(bcm, 0x0801, backup[14]);
769 bcm43xx_phy_write(bcm, 0x0060, backup[15]);
770 bcm43xx_phy_write(bcm, 0x0014, backup[16]);
771 bcm43xx_phy_write(bcm, 0x0478, backup[17]);
773 bcm43xx_nrssi_mem_update(bcm);
774 bcm43xx_calc_nrssi_threshold(bcm);
781 void bcm43xx_calc_nrssi_threshold(struct bcm43xx_private *bcm)
783 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
784 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
792 case BCM43xx_PHYTYPE_B: {
797 if (radio->version != 0x2050)
799 if (!(bcm->sprom.boardflags & BCM43xx_BFL_RSSI))
802 tmp = radio->revision;
803 if ((radio->manufact == 0x175 && tmp == 5) ||
804 (radio->manufact == 0x17F && (tmp == 3 || tmp == 4)))
807 if (radiotype == 1) {
808 threshold = radio->nrssi[1] - 5;
810 threshold = 40 * radio->nrssi[0];
811 threshold += 33 * (radio->nrssi[1] - radio->nrssi[0]);
815 threshold = limit_value(threshold, 0, 0x3E);
816 bcm43xx_phy_read(bcm, 0x0020); /* dummy read */
817 bcm43xx_phy_write(bcm, 0x0020, (((u16)threshold) << 8) | 0x001C);
819 if (radiotype == 1) {
820 bcm43xx_phy_write(bcm, 0x0087, 0x0E0D);
821 bcm43xx_phy_write(bcm, 0x0086, 0x0C0B);
822 bcm43xx_phy_write(bcm, 0x0085, 0x0A09);
823 bcm43xx_phy_write(bcm, 0x0084, 0x0808);
824 bcm43xx_phy_write(bcm, 0x0083, 0x0808);
825 bcm43xx_phy_write(bcm, 0x0082, 0x0604);
826 bcm43xx_phy_write(bcm, 0x0081, 0x0302);
827 bcm43xx_phy_write(bcm, 0x0080, 0x0100);
831 case BCM43xx_PHYTYPE_G:
832 if (!phy->connected ||
833 !(bcm->sprom.boardflags & BCM43xx_BFL_RSSI)) {
834 tmp16 = bcm43xx_nrssi_hw_read(bcm, 0x20);
838 bcm43xx_phy_write(bcm, 0x048A,
839 (bcm43xx_phy_read(bcm, 0x048A)
842 bcm43xx_phy_write(bcm, 0x048A,
843 (bcm43xx_phy_read(bcm, 0x048A)
847 tmp = radio->interfmode;
848 if (tmp == BCM43xx_RADIO_INTERFMODE_NONWLAN) {
851 } else if (tmp == BCM43xx_RADIO_INTERFMODE_NONE &&
852 !radio->aci_enable) {
860 a *= radio->nrssi[1] - radio->nrssi[0];
861 a += radio->nrssi[0] * 0x40;
864 b *= radio->nrssi[1] - radio->nrssi[0];
865 b += radio->nrssi[0] * 0x40;
868 a = limit_value(a, -31, 31);
869 b = limit_value(b, -31, 31);
871 tmp_u16 = bcm43xx_phy_read(bcm, 0x048A) & 0xF000;
872 tmp_u16 |= ((u32)a & 0x003F);
873 tmp_u16 |= (((u32)b & 0x003F) << 6);
874 bcm43xx_phy_write(bcm, 0x048A, tmp_u16);
882 /* Stack implementation to save/restore values from the
883 * interference mitigation code.
884 * It is save to restore values in random order.
886 static void _stack_save(u32 *_stackptr, size_t *stackidx,
887 u8 id, u16 offset, u16 value)
889 u32 *stackptr = &(_stackptr[*stackidx]);
891 assert((offset & 0xF000) == 0x0000);
892 assert((id & 0xF0) == 0x00);
894 *stackptr |= ((u32)id) << 12;
895 *stackptr |= ((u32)value) << 16;
897 assert(*stackidx < BCM43xx_INTERFSTACK_SIZE);
900 static u16 _stack_restore(u32 *stackptr,
905 assert((offset & 0xF000) == 0x0000);
906 assert((id & 0xF0) == 0x00);
907 for (i = 0; i < BCM43xx_INTERFSTACK_SIZE; i++, stackptr++) {
908 if ((*stackptr & 0x00000FFF) != offset)
910 if (((*stackptr & 0x0000F000) >> 12) != id)
912 return ((*stackptr & 0xFFFF0000) >> 16);
919 #define phy_stacksave(offset) \
921 _stack_save(stack, &stackidx, 0x1, (offset), \
922 bcm43xx_phy_read(bcm, (offset))); \
924 #define phy_stackrestore(offset) \
926 bcm43xx_phy_write(bcm, (offset), \
927 _stack_restore(stack, 0x1, \
930 #define radio_stacksave(offset) \
932 _stack_save(stack, &stackidx, 0x2, (offset), \
933 bcm43xx_radio_read16(bcm, (offset))); \
935 #define radio_stackrestore(offset) \
937 bcm43xx_radio_write16(bcm, (offset), \
938 _stack_restore(stack, 0x2, \
941 #define ilt_stacksave(offset) \
943 _stack_save(stack, &stackidx, 0x3, (offset), \
944 bcm43xx_ilt_read(bcm, (offset))); \
946 #define ilt_stackrestore(offset) \
948 bcm43xx_ilt_write(bcm, (offset), \
949 _stack_restore(stack, 0x3, \
954 bcm43xx_radio_interference_mitigation_enable(struct bcm43xx_private *bcm,
957 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
958 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
962 u32 *stack = radio->interfstack;
965 case BCM43xx_RADIO_INTERFMODE_NONWLAN:
967 bcm43xx_phy_write(bcm, 0x042B,
968 bcm43xx_phy_read(bcm, 0x042B) | 0x0800);
969 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
970 bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & ~0x4000);
973 radio_stacksave(0x0078);
974 tmp = (bcm43xx_radio_read16(bcm, 0x0078) & 0x001E);
975 flipped = flip_4bit(tmp);
976 if (flipped < 10 && flipped >= 8)
978 else if (flipped >= 10)
980 flipped = flip_4bit(flipped);
981 flipped = (flipped << 1) | 0x0020;
982 bcm43xx_radio_write16(bcm, 0x0078, flipped);
984 bcm43xx_calc_nrssi_threshold(bcm);
986 phy_stacksave(0x0406);
987 bcm43xx_phy_write(bcm, 0x0406, 0x7E28);
989 bcm43xx_phy_write(bcm, 0x042B,
990 bcm43xx_phy_read(bcm, 0x042B) | 0x0800);
991 bcm43xx_phy_write(bcm, BCM43xx_PHY_RADIO_BITFIELD,
992 bcm43xx_phy_read(bcm, BCM43xx_PHY_RADIO_BITFIELD) | 0x1000);
994 phy_stacksave(0x04A0);
995 bcm43xx_phy_write(bcm, 0x04A0,
996 (bcm43xx_phy_read(bcm, 0x04A0) & 0xC0C0) | 0x0008);
997 phy_stacksave(0x04A1);
998 bcm43xx_phy_write(bcm, 0x04A1,
999 (bcm43xx_phy_read(bcm, 0x04A1) & 0xC0C0) | 0x0605);
1000 phy_stacksave(0x04A2);
1001 bcm43xx_phy_write(bcm, 0x04A2,
1002 (bcm43xx_phy_read(bcm, 0x04A2) & 0xC0C0) | 0x0204);
1003 phy_stacksave(0x04A8);
1004 bcm43xx_phy_write(bcm, 0x04A8,
1005 (bcm43xx_phy_read(bcm, 0x04A8) & 0xC0C0) | 0x0803);
1006 phy_stacksave(0x04AB);
1007 bcm43xx_phy_write(bcm, 0x04AB,
1008 (bcm43xx_phy_read(bcm, 0x04AB) & 0xC0C0) | 0x0605);
1010 phy_stacksave(0x04A7);
1011 bcm43xx_phy_write(bcm, 0x04A7, 0x0002);
1012 phy_stacksave(0x04A3);
1013 bcm43xx_phy_write(bcm, 0x04A3, 0x287A);
1014 phy_stacksave(0x04A9);
1015 bcm43xx_phy_write(bcm, 0x04A9, 0x2027);
1016 phy_stacksave(0x0493);
1017 bcm43xx_phy_write(bcm, 0x0493, 0x32F5);
1018 phy_stacksave(0x04AA);
1019 bcm43xx_phy_write(bcm, 0x04AA, 0x2027);
1020 phy_stacksave(0x04AC);
1021 bcm43xx_phy_write(bcm, 0x04AC, 0x32F5);
1023 case BCM43xx_RADIO_INTERFMODE_MANUALWLAN:
1024 if (bcm43xx_phy_read(bcm, 0x0033) & 0x0800)
1027 radio->aci_enable = 1;
1029 phy_stacksave(BCM43xx_PHY_RADIO_BITFIELD);
1030 phy_stacksave(BCM43xx_PHY_G_CRS);
1032 phy_stacksave(0x0406);
1034 phy_stacksave(0x04C0);
1035 phy_stacksave(0x04C1);
1037 phy_stacksave(0x0033);
1038 phy_stacksave(0x04A7);
1039 phy_stacksave(0x04A3);
1040 phy_stacksave(0x04A9);
1041 phy_stacksave(0x04AA);
1042 phy_stacksave(0x04AC);
1043 phy_stacksave(0x0493);
1044 phy_stacksave(0x04A1);
1045 phy_stacksave(0x04A0);
1046 phy_stacksave(0x04A2);
1047 phy_stacksave(0x048A);
1048 phy_stacksave(0x04A8);
1049 phy_stacksave(0x04AB);
1050 if (phy->rev == 2) {
1051 phy_stacksave(0x04AD);
1052 phy_stacksave(0x04AE);
1053 } else if (phy->rev >= 3) {
1054 phy_stacksave(0x04AD);
1055 phy_stacksave(0x0415);
1056 phy_stacksave(0x0416);
1057 phy_stacksave(0x0417);
1058 ilt_stacksave(0x1A00 + 0x2);
1059 ilt_stacksave(0x1A00 + 0x3);
1061 phy_stacksave(0x042B);
1062 phy_stacksave(0x048C);
1064 bcm43xx_phy_write(bcm, BCM43xx_PHY_RADIO_BITFIELD,
1065 bcm43xx_phy_read(bcm, BCM43xx_PHY_RADIO_BITFIELD)
1067 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
1068 (bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS)
1069 & 0xFFFC) | 0x0002);
1071 bcm43xx_phy_write(bcm, 0x0033, 0x0800);
1072 bcm43xx_phy_write(bcm, 0x04A3, 0x2027);
1073 bcm43xx_phy_write(bcm, 0x04A9, 0x1CA8);
1074 bcm43xx_phy_write(bcm, 0x0493, 0x287A);
1075 bcm43xx_phy_write(bcm, 0x04AA, 0x1CA8);
1076 bcm43xx_phy_write(bcm, 0x04AC, 0x287A);
1078 bcm43xx_phy_write(bcm, 0x04A0,
1079 (bcm43xx_phy_read(bcm, 0x04A0)
1080 & 0xFFC0) | 0x001A);
1081 bcm43xx_phy_write(bcm, 0x04A7, 0x000D);
1084 bcm43xx_phy_write(bcm, 0x0406, 0xFF0D);
1085 } else if (phy->rev == 2) {
1086 bcm43xx_phy_write(bcm, 0x04C0, 0xFFFF);
1087 bcm43xx_phy_write(bcm, 0x04C1, 0x00A9);
1089 bcm43xx_phy_write(bcm, 0x04C0, 0x00C1);
1090 bcm43xx_phy_write(bcm, 0x04C1, 0x0059);
1093 bcm43xx_phy_write(bcm, 0x04A1,
1094 (bcm43xx_phy_read(bcm, 0x04A1)
1095 & 0xC0FF) | 0x1800);
1096 bcm43xx_phy_write(bcm, 0x04A1,
1097 (bcm43xx_phy_read(bcm, 0x04A1)
1098 & 0xFFC0) | 0x0015);
1099 bcm43xx_phy_write(bcm, 0x04A8,
1100 (bcm43xx_phy_read(bcm, 0x04A8)
1101 & 0xCFFF) | 0x1000);
1102 bcm43xx_phy_write(bcm, 0x04A8,
1103 (bcm43xx_phy_read(bcm, 0x04A8)
1104 & 0xF0FF) | 0x0A00);
1105 bcm43xx_phy_write(bcm, 0x04AB,
1106 (bcm43xx_phy_read(bcm, 0x04AB)
1107 & 0xCFFF) | 0x1000);
1108 bcm43xx_phy_write(bcm, 0x04AB,
1109 (bcm43xx_phy_read(bcm, 0x04AB)
1110 & 0xF0FF) | 0x0800);
1111 bcm43xx_phy_write(bcm, 0x04AB,
1112 (bcm43xx_phy_read(bcm, 0x04AB)
1113 & 0xFFCF) | 0x0010);
1114 bcm43xx_phy_write(bcm, 0x04AB,
1115 (bcm43xx_phy_read(bcm, 0x04AB)
1116 & 0xFFF0) | 0x0005);
1117 bcm43xx_phy_write(bcm, 0x04A8,
1118 (bcm43xx_phy_read(bcm, 0x04A8)
1119 & 0xFFCF) | 0x0010);
1120 bcm43xx_phy_write(bcm, 0x04A8,
1121 (bcm43xx_phy_read(bcm, 0x04A8)
1122 & 0xFFF0) | 0x0006);
1123 bcm43xx_phy_write(bcm, 0x04A2,
1124 (bcm43xx_phy_read(bcm, 0x04A2)
1125 & 0xF0FF) | 0x0800);
1126 bcm43xx_phy_write(bcm, 0x04A0,
1127 (bcm43xx_phy_read(bcm, 0x04A0)
1128 & 0xF0FF) | 0x0500);
1129 bcm43xx_phy_write(bcm, 0x04A2,
1130 (bcm43xx_phy_read(bcm, 0x04A2)
1131 & 0xFFF0) | 0x000B);
1133 if (phy->rev >= 3) {
1134 bcm43xx_phy_write(bcm, 0x048A,
1135 bcm43xx_phy_read(bcm, 0x048A)
1137 bcm43xx_phy_write(bcm, 0x0415,
1138 (bcm43xx_phy_read(bcm, 0x0415)
1139 & 0x8000) | 0x36D8);
1140 bcm43xx_phy_write(bcm, 0x0416,
1141 (bcm43xx_phy_read(bcm, 0x0416)
1142 & 0x8000) | 0x36D8);
1143 bcm43xx_phy_write(bcm, 0x0417,
1144 (bcm43xx_phy_read(bcm, 0x0417)
1145 & 0xFE00) | 0x016D);
1147 bcm43xx_phy_write(bcm, 0x048A,
1148 bcm43xx_phy_read(bcm, 0x048A)
1150 bcm43xx_phy_write(bcm, 0x048A,
1151 (bcm43xx_phy_read(bcm, 0x048A)
1152 & 0x9FFF) | 0x2000);
1153 tmp32 = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
1154 BCM43xx_UCODEFLAGS_OFFSET);
1155 if (!(tmp32 & 0x800)) {
1157 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
1158 BCM43xx_UCODEFLAGS_OFFSET,
1162 if (phy->rev >= 2) {
1163 bcm43xx_phy_write(bcm, 0x042B,
1164 bcm43xx_phy_read(bcm, 0x042B)
1167 bcm43xx_phy_write(bcm, 0x048C,
1168 (bcm43xx_phy_read(bcm, 0x048C)
1169 & 0xF0FF) | 0x0200);
1170 if (phy->rev == 2) {
1171 bcm43xx_phy_write(bcm, 0x04AE,
1172 (bcm43xx_phy_read(bcm, 0x04AE)
1173 & 0xFF00) | 0x007F);
1174 bcm43xx_phy_write(bcm, 0x04AD,
1175 (bcm43xx_phy_read(bcm, 0x04AD)
1176 & 0x00FF) | 0x1300);
1177 } else if (phy->rev >= 6) {
1178 bcm43xx_ilt_write(bcm, 0x1A00 + 0x3, 0x007F);
1179 bcm43xx_ilt_write(bcm, 0x1A00 + 0x2, 0x007F);
1180 bcm43xx_phy_write(bcm, 0x04AD,
1181 bcm43xx_phy_read(bcm, 0x04AD)
1184 bcm43xx_calc_nrssi_slope(bcm);
1192 bcm43xx_radio_interference_mitigation_disable(struct bcm43xx_private *bcm,
1195 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1196 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1198 u32 *stack = radio->interfstack;
1201 case BCM43xx_RADIO_INTERFMODE_NONWLAN:
1202 if (phy->rev != 1) {
1203 bcm43xx_phy_write(bcm, 0x042B,
1204 bcm43xx_phy_read(bcm, 0x042B) & ~0x0800);
1205 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
1206 bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) | 0x4000);
1209 phy_stackrestore(0x0078);
1210 bcm43xx_calc_nrssi_threshold(bcm);
1211 phy_stackrestore(0x0406);
1212 bcm43xx_phy_write(bcm, 0x042B,
1213 bcm43xx_phy_read(bcm, 0x042B) & ~0x0800);
1214 if (!bcm->bad_frames_preempt) {
1215 bcm43xx_phy_write(bcm, BCM43xx_PHY_RADIO_BITFIELD,
1216 bcm43xx_phy_read(bcm, BCM43xx_PHY_RADIO_BITFIELD)
1219 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
1220 bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) | 0x4000);
1221 phy_stackrestore(0x04A0);
1222 phy_stackrestore(0x04A1);
1223 phy_stackrestore(0x04A2);
1224 phy_stackrestore(0x04A8);
1225 phy_stackrestore(0x04AB);
1226 phy_stackrestore(0x04A7);
1227 phy_stackrestore(0x04A3);
1228 phy_stackrestore(0x04A9);
1229 phy_stackrestore(0x0493);
1230 phy_stackrestore(0x04AA);
1231 phy_stackrestore(0x04AC);
1233 case BCM43xx_RADIO_INTERFMODE_MANUALWLAN:
1234 if (!(bcm43xx_phy_read(bcm, 0x0033) & 0x0800))
1237 radio->aci_enable = 0;
1239 phy_stackrestore(BCM43xx_PHY_RADIO_BITFIELD);
1240 phy_stackrestore(BCM43xx_PHY_G_CRS);
1241 phy_stackrestore(0x0033);
1242 phy_stackrestore(0x04A3);
1243 phy_stackrestore(0x04A9);
1244 phy_stackrestore(0x0493);
1245 phy_stackrestore(0x04AA);
1246 phy_stackrestore(0x04AC);
1247 phy_stackrestore(0x04A0);
1248 phy_stackrestore(0x04A7);
1249 if (phy->rev >= 2) {
1250 phy_stackrestore(0x04C0);
1251 phy_stackrestore(0x04C1);
1253 phy_stackrestore(0x0406);
1254 phy_stackrestore(0x04A1);
1255 phy_stackrestore(0x04AB);
1256 phy_stackrestore(0x04A8);
1257 if (phy->rev == 2) {
1258 phy_stackrestore(0x04AD);
1259 phy_stackrestore(0x04AE);
1260 } else if (phy->rev >= 3) {
1261 phy_stackrestore(0x04AD);
1262 phy_stackrestore(0x0415);
1263 phy_stackrestore(0x0416);
1264 phy_stackrestore(0x0417);
1265 ilt_stackrestore(0x1A00 + 0x2);
1266 ilt_stackrestore(0x1A00 + 0x3);
1268 phy_stackrestore(0x04A2);
1269 phy_stackrestore(0x04A8);
1270 phy_stackrestore(0x042B);
1271 phy_stackrestore(0x048C);
1272 tmp32 = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
1273 BCM43xx_UCODEFLAGS_OFFSET);
1274 if (tmp32 & 0x800) {
1276 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
1277 BCM43xx_UCODEFLAGS_OFFSET,
1280 bcm43xx_calc_nrssi_slope(bcm);
1287 #undef phy_stacksave
1288 #undef phy_stackrestore
1289 #undef radio_stacksave
1290 #undef radio_stackrestore
1291 #undef ilt_stacksave
1292 #undef ilt_stackrestore
1294 int bcm43xx_radio_set_interference_mitigation(struct bcm43xx_private *bcm,
1297 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1298 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1301 if ((phy->type != BCM43xx_PHYTYPE_G) ||
1306 radio->aci_wlan_automatic = 0;
1308 case BCM43xx_RADIO_INTERFMODE_AUTOWLAN:
1309 radio->aci_wlan_automatic = 1;
1310 if (radio->aci_enable)
1311 mode = BCM43xx_RADIO_INTERFMODE_MANUALWLAN;
1313 mode = BCM43xx_RADIO_INTERFMODE_NONE;
1315 case BCM43xx_RADIO_INTERFMODE_NONE:
1316 case BCM43xx_RADIO_INTERFMODE_NONWLAN:
1317 case BCM43xx_RADIO_INTERFMODE_MANUALWLAN:
1323 currentmode = radio->interfmode;
1324 if (currentmode == mode)
1326 if (currentmode != BCM43xx_RADIO_INTERFMODE_NONE)
1327 bcm43xx_radio_interference_mitigation_disable(bcm, currentmode);
1329 if (mode == BCM43xx_RADIO_INTERFMODE_NONE) {
1330 radio->aci_enable = 0;
1331 radio->aci_hw_rssi = 0;
1333 bcm43xx_radio_interference_mitigation_enable(bcm, mode);
1334 radio->interfmode = mode;
1339 u16 bcm43xx_radio_calibrationvalue(struct bcm43xx_private *bcm)
1341 u16 reg, index, ret;
1343 reg = bcm43xx_radio_read16(bcm, 0x0060);
1344 index = (reg & 0x001E) >> 1;
1345 ret = rcc_table[index] << 1;
1346 ret |= (reg & 0x0001);
1352 u16 bcm43xx_radio_init2050(struct bcm43xx_private *bcm)
1354 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1355 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1356 u16 backup[19] = { 0 };
1359 u32 tmp1 = 0, tmp2 = 0;
1361 backup[0] = bcm43xx_radio_read16(bcm, 0x0043);
1362 backup[14] = bcm43xx_radio_read16(bcm, 0x0051);
1363 backup[15] = bcm43xx_radio_read16(bcm, 0x0052);
1364 backup[1] = bcm43xx_phy_read(bcm, 0x0015);
1365 backup[16] = bcm43xx_phy_read(bcm, 0x005A);
1366 backup[17] = bcm43xx_phy_read(bcm, 0x0059);
1367 backup[18] = bcm43xx_phy_read(bcm, 0x0058);
1368 if (phy->type == BCM43xx_PHYTYPE_B) {
1369 backup[2] = bcm43xx_phy_read(bcm, 0x0030);
1370 backup[3] = bcm43xx_read16(bcm, 0x03EC);
1371 bcm43xx_phy_write(bcm, 0x0030, 0x00FF);
1372 bcm43xx_write16(bcm, 0x03EC, 0x3F3F);
1374 if (phy->connected) {
1375 backup[4] = bcm43xx_phy_read(bcm, 0x0811);
1376 backup[5] = bcm43xx_phy_read(bcm, 0x0812);
1377 backup[6] = bcm43xx_phy_read(bcm, 0x0814);
1378 backup[7] = bcm43xx_phy_read(bcm, 0x0815);
1379 backup[8] = bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS);
1380 backup[9] = bcm43xx_phy_read(bcm, 0x0802);
1381 bcm43xx_phy_write(bcm, 0x0814,
1382 (bcm43xx_phy_read(bcm, 0x0814) | 0x0003));
1383 bcm43xx_phy_write(bcm, 0x0815,
1384 (bcm43xx_phy_read(bcm, 0x0815) & 0xFFFC));
1385 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS,
1386 (bcm43xx_phy_read(bcm, BCM43xx_PHY_G_CRS) & 0x7FFF));
1387 bcm43xx_phy_write(bcm, 0x0802,
1388 (bcm43xx_phy_read(bcm, 0x0802) & 0xFFFC));
1389 bcm43xx_phy_write(bcm, 0x0811, 0x01B3);
1390 bcm43xx_phy_write(bcm, 0x0812, 0x0FB2);
1392 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_RADIO,
1393 (bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_RADIO) | 0x8000));
1395 backup[10] = bcm43xx_phy_read(bcm, 0x0035);
1396 bcm43xx_phy_write(bcm, 0x0035,
1397 (bcm43xx_phy_read(bcm, 0x0035) & 0xFF7F));
1398 backup[11] = bcm43xx_read16(bcm, 0x03E6);
1399 backup[12] = bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT);
1402 if (phy->version == 0) {
1403 bcm43xx_write16(bcm, 0x03E6, 0x0122);
1405 if (phy->version >= 2)
1406 bcm43xx_write16(bcm, 0x03E6, 0x0040);
1407 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
1408 (bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT) | 0x2000));
1411 ret = bcm43xx_radio_calibrationvalue(bcm);
1413 if (phy->type == BCM43xx_PHYTYPE_B)
1414 bcm43xx_radio_write16(bcm, 0x0078, 0x0003);
1416 bcm43xx_phy_write(bcm, 0x0015, 0xBFAF);
1417 bcm43xx_phy_write(bcm, 0x002B, 0x1403);
1419 bcm43xx_phy_write(bcm, 0x0812, 0x00B2);
1420 bcm43xx_phy_write(bcm, 0x0015, 0xBFA0);
1421 bcm43xx_radio_write16(bcm, 0x0051,
1422 (bcm43xx_radio_read16(bcm, 0x0051) | 0x0004));
1423 bcm43xx_radio_write16(bcm, 0x0052, 0x0000);
1424 bcm43xx_radio_write16(bcm, 0x0043,
1425 bcm43xx_radio_read16(bcm, 0x0043) | 0x0009);
1426 bcm43xx_phy_write(bcm, 0x0058, 0x0000);
1428 for (i = 0; i < 16; i++) {
1429 bcm43xx_phy_write(bcm, 0x005A, 0x0480);
1430 bcm43xx_phy_write(bcm, 0x0059, 0xC810);
1431 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
1433 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1434 bcm43xx_phy_write(bcm, 0x0015, 0xAFB0);
1437 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1438 bcm43xx_phy_write(bcm, 0x0015, 0xEFB0);
1441 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1442 bcm43xx_phy_write(bcm, 0x0015, 0xFFF0);
1444 tmp1 += bcm43xx_phy_read(bcm, 0x002D);
1445 bcm43xx_phy_write(bcm, 0x0058, 0x0000);
1447 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1448 bcm43xx_phy_write(bcm, 0x0015, 0xAFB0);
1454 bcm43xx_phy_write(bcm, 0x0058, 0x0000);
1456 for (i = 0; i < 16; i++) {
1457 bcm43xx_radio_write16(bcm, 0x0078, (flip_4bit(i) << 1) | 0x0020);
1458 backup[13] = bcm43xx_radio_read16(bcm, 0x0078);
1460 for (j = 0; j < 16; j++) {
1461 bcm43xx_phy_write(bcm, 0x005A, 0x0D80);
1462 bcm43xx_phy_write(bcm, 0x0059, 0xC810);
1463 bcm43xx_phy_write(bcm, 0x0058, 0x000D);
1465 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1466 bcm43xx_phy_write(bcm, 0x0015, 0xAFB0);
1469 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1470 bcm43xx_phy_write(bcm, 0x0015, 0xEFB0);
1473 bcm43xx_phy_write(bcm, 0x0812, 0x30B3); /* 0x30B3 is not a typo */
1474 bcm43xx_phy_write(bcm, 0x0015, 0xFFF0);
1476 tmp2 += bcm43xx_phy_read(bcm, 0x002D);
1477 bcm43xx_phy_write(bcm, 0x0058, 0x0000);
1479 bcm43xx_phy_write(bcm, 0x0812, 0x30B2);
1480 bcm43xx_phy_write(bcm, 0x0015, 0xAFB0);
1488 /* Restore the registers */
1489 bcm43xx_phy_write(bcm, 0x0015, backup[1]);
1490 bcm43xx_radio_write16(bcm, 0x0051, backup[14]);
1491 bcm43xx_radio_write16(bcm, 0x0052, backup[15]);
1492 bcm43xx_radio_write16(bcm, 0x0043, backup[0]);
1493 bcm43xx_phy_write(bcm, 0x005A, backup[16]);
1494 bcm43xx_phy_write(bcm, 0x0059, backup[17]);
1495 bcm43xx_phy_write(bcm, 0x0058, backup[18]);
1496 bcm43xx_write16(bcm, 0x03E6, backup[11]);
1497 if (phy->version != 0)
1498 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT, backup[12]);
1499 bcm43xx_phy_write(bcm, 0x0035, backup[10]);
1500 bcm43xx_radio_selectchannel(bcm, radio->channel, 1);
1501 if (phy->type == BCM43xx_PHYTYPE_B) {
1502 bcm43xx_phy_write(bcm, 0x0030, backup[2]);
1503 bcm43xx_write16(bcm, 0x03EC, backup[3]);
1505 bcm43xx_write16(bcm, BCM43xx_MMIO_PHY_RADIO,
1506 (bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_RADIO) & 0x7FFF));
1507 if (phy->connected) {
1508 bcm43xx_phy_write(bcm, 0x0811, backup[4]);
1509 bcm43xx_phy_write(bcm, 0x0812, backup[5]);
1510 bcm43xx_phy_write(bcm, 0x0814, backup[6]);
1511 bcm43xx_phy_write(bcm, 0x0815, backup[7]);
1512 bcm43xx_phy_write(bcm, BCM43xx_PHY_G_CRS, backup[8]);
1513 bcm43xx_phy_write(bcm, 0x0802, backup[9]);
1522 void bcm43xx_radio_init2060(struct bcm43xx_private *bcm)
1526 bcm43xx_radio_write16(bcm, 0x0004, 0x00C0);
1527 bcm43xx_radio_write16(bcm, 0x0005, 0x0008);
1528 bcm43xx_radio_write16(bcm, 0x0009, 0x0040);
1529 bcm43xx_radio_write16(bcm, 0x0005, 0x00AA);
1530 bcm43xx_radio_write16(bcm, 0x0032, 0x008F);
1531 bcm43xx_radio_write16(bcm, 0x0006, 0x008F);
1532 bcm43xx_radio_write16(bcm, 0x0034, 0x008F);
1533 bcm43xx_radio_write16(bcm, 0x002C, 0x0007);
1534 bcm43xx_radio_write16(bcm, 0x0082, 0x0080);
1535 bcm43xx_radio_write16(bcm, 0x0080, 0x0000);
1536 bcm43xx_radio_write16(bcm, 0x003F, 0x00DA);
1537 bcm43xx_radio_write16(bcm, 0x0005, bcm43xx_radio_read16(bcm, 0x0005) & ~0x0008);
1538 bcm43xx_radio_write16(bcm, 0x0081, bcm43xx_radio_read16(bcm, 0x0081) & ~0x0010);
1539 bcm43xx_radio_write16(bcm, 0x0081, bcm43xx_radio_read16(bcm, 0x0081) & ~0x0020);
1540 bcm43xx_radio_write16(bcm, 0x0081, bcm43xx_radio_read16(bcm, 0x0081) & ~0x0020);
1543 bcm43xx_radio_write16(bcm, 0x0081, (bcm43xx_radio_read16(bcm, 0x0081) & ~0x0020) | 0x0010);
1546 bcm43xx_radio_write16(bcm, 0x0005, (bcm43xx_radio_read16(bcm, 0x0005) & ~0x0008) | 0x0008);
1547 bcm43xx_radio_write16(bcm, 0x0085, bcm43xx_radio_read16(bcm, 0x0085) & ~0x0010);
1548 bcm43xx_radio_write16(bcm, 0x0005, bcm43xx_radio_read16(bcm, 0x0005) & ~0x0008);
1549 bcm43xx_radio_write16(bcm, 0x0081, bcm43xx_radio_read16(bcm, 0x0081) & ~0x0040);
1550 bcm43xx_radio_write16(bcm, 0x0081, (bcm43xx_radio_read16(bcm, 0x0081) & ~0x0040) | 0x0040);
1551 bcm43xx_radio_write16(bcm, 0x0005, (bcm43xx_radio_read16(bcm, 0x0081) & ~0x0008) | 0x0008);
1552 bcm43xx_phy_write(bcm, 0x0063, 0xDDC6);
1553 bcm43xx_phy_write(bcm, 0x0069, 0x07BE);
1554 bcm43xx_phy_write(bcm, 0x006A, 0x0000);
1556 err = bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_A, 0);
1562 u16 freq_r3A_value(u16 frequency)
1566 if (frequency < 5091)
1568 else if (frequency < 5321)
1570 else if (frequency < 5806)
1578 void bcm43xx_radio_set_tx_iq(struct bcm43xx_private *bcm)
1580 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
1581 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
1582 u16 tmp = bcm43xx_radio_read16(bcm, 0x001E);
1585 for (i = 0; i < 5; i++) {
1586 for (j = 0; j < 5; j++) {
1587 if (tmp == (data_high[i] << 4 | data_low[j])) {
1588 bcm43xx_phy_write(bcm, 0x0069, (i - j) << 8 | 0x00C0);
1595 int bcm43xx_radio_selectchannel(struct bcm43xx_private *bcm,
1597 int synthetic_pu_workaround)
1599 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1603 if ((radio->manufact == 0x17F) &&
1604 (radio->version == 0x2060) &&
1605 (radio->revision == 1)) {
1608 freq = channel2freq_a(channel);
1610 r8 = bcm43xx_radio_read16(bcm, 0x0008);
1611 bcm43xx_write16(bcm, 0x03F0, freq);
1612 bcm43xx_radio_write16(bcm, 0x0008, r8);
1614 TODO();//TODO: write max channel TX power? to Radio 0x2D
1615 tmp = bcm43xx_radio_read16(bcm, 0x002E);
1617 TODO();//TODO: OR tmp with the Power out estimation for this channel?
1618 bcm43xx_radio_write16(bcm, 0x002E, tmp);
1620 if (freq >= 4920 && freq <= 5500) {
1622 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
1623 * = (freq * 0.025862069
1625 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
1627 bcm43xx_radio_write16(bcm, 0x0007, (r8 << 4) | r8);
1628 bcm43xx_radio_write16(bcm, 0x0020, (r8 << 4) | r8);
1629 bcm43xx_radio_write16(bcm, 0x0021, (r8 << 4) | r8);
1630 bcm43xx_radio_write16(bcm, 0x0022,
1631 (bcm43xx_radio_read16(bcm, 0x0022)
1632 & 0x000F) | (r8 << 4));
1633 bcm43xx_radio_write16(bcm, 0x002A, (r8 << 4));
1634 bcm43xx_radio_write16(bcm, 0x002B, (r8 << 4));
1635 bcm43xx_radio_write16(bcm, 0x0008,
1636 (bcm43xx_radio_read16(bcm, 0x0008)
1637 & 0x00F0) | (r8 << 4));
1638 bcm43xx_radio_write16(bcm, 0x0029,
1639 (bcm43xx_radio_read16(bcm, 0x0029)
1640 & 0xFF0F) | 0x00B0);
1641 bcm43xx_radio_write16(bcm, 0x0035, 0x00AA);
1642 bcm43xx_radio_write16(bcm, 0x0036, 0x0085);
1643 bcm43xx_radio_write16(bcm, 0x003A,
1644 (bcm43xx_radio_read16(bcm, 0x003A)
1645 & 0xFF20) | freq_r3A_value(freq));
1646 bcm43xx_radio_write16(bcm, 0x003D,
1647 bcm43xx_radio_read16(bcm, 0x003D) & 0x00FF);
1648 bcm43xx_radio_write16(bcm, 0x0081,
1649 (bcm43xx_radio_read16(bcm, 0x0081)
1650 & 0xFF7F) | 0x0080);
1651 bcm43xx_radio_write16(bcm, 0x0035,
1652 bcm43xx_radio_read16(bcm, 0x0035) & 0xFFEF);
1653 bcm43xx_radio_write16(bcm, 0x0035,
1654 (bcm43xx_radio_read16(bcm, 0x0035)
1655 & 0xFFEF) | 0x0010);
1656 bcm43xx_radio_set_tx_iq(bcm);
1657 TODO(); //TODO: TSSI2dbm workaround
1658 bcm43xx_phy_xmitpower(bcm);//FIXME correct?
1660 if ((channel < 1) || (channel > 14))
1663 if (synthetic_pu_workaround)
1664 bcm43xx_synth_pu_workaround(bcm, channel);
1666 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL,
1667 channel2freq_bg(channel));
1669 if (channel == 14) {
1670 if (bcm->sprom.locale == BCM43xx_LOCALE_JAPAN) {
1671 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
1672 BCM43xx_UCODEFLAGS_OFFSET,
1673 bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
1674 BCM43xx_UCODEFLAGS_OFFSET)
1677 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
1678 BCM43xx_UCODEFLAGS_OFFSET,
1679 bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
1680 BCM43xx_UCODEFLAGS_OFFSET)
1683 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
1684 bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT)
1687 bcm43xx_write16(bcm, BCM43xx_MMIO_CHANNEL_EXT,
1688 bcm43xx_read16(bcm, BCM43xx_MMIO_CHANNEL_EXT)
1693 radio->channel = channel;
1694 //XXX: Using the longer of 2 timeouts (8000 vs 2000 usecs). Specs states
1695 // that 2000 usecs might suffice.
1701 void bcm43xx_radio_set_txantenna(struct bcm43xx_private *bcm, u32 val)
1706 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0022) & 0xFCFF;
1707 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0022, tmp | val);
1708 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x03A8) & 0xFCFF;
1709 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x03A8, tmp | val);
1710 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x0054) & 0xFCFF;
1711 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0054, tmp | val);
1714 /* http://bcm-specs.sipsolutions.net/TX_Gain_Base_Band */
1715 static u16 bcm43xx_get_txgain_base_band(u16 txpower)
1719 assert(txpower <= 63);
1723 else if (txpower >= 49)
1725 else if (txpower >= 44)
1733 /* http://bcm-specs.sipsolutions.net/TX_Gain_Radio_Frequency_Power_Amplifier */
1734 static u16 bcm43xx_get_txgain_freq_power_amp(u16 txpower)
1738 assert(txpower <= 63);
1742 else if (txpower >= 25)
1744 else if (txpower >= 20)
1746 else if (txpower >= 12)
1754 /* http://bcm-specs.sipsolutions.net/TX_Gain_Digital_Analog_Converter */
1755 static u16 bcm43xx_get_txgain_dac(u16 txpower)
1759 assert(txpower <= 63);
1763 else if (txpower >= 49)
1765 else if (txpower >= 44)
1767 else if (txpower >= 32)
1769 else if (txpower >= 25)
1771 else if (txpower >= 20)
1773 else if (txpower >= 12)
1781 void bcm43xx_radio_set_txpower_a(struct bcm43xx_private *bcm, u16 txpower)
1783 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1784 u16 pamp, base, dac, ilt;
1786 txpower = limit_value(txpower, 0, 63);
1788 pamp = bcm43xx_get_txgain_freq_power_amp(txpower);
1791 bcm43xx_phy_write(bcm, 0x0019, pamp);
1793 base = bcm43xx_get_txgain_base_band(txpower);
1795 bcm43xx_phy_write(bcm, 0x0017, base | 0x0020);
1797 ilt = bcm43xx_ilt_read(bcm, 0x3001);
1800 dac = bcm43xx_get_txgain_dac(txpower);
1804 bcm43xx_ilt_write(bcm, 0x3001, dac);
1806 radio->txpwr_offset = txpower;
1809 //TODO: FuncPlaceholder (Adjust BB loft cancel)
1812 void bcm43xx_radio_set_txpower_bg(struct bcm43xx_private *bcm,
1813 u16 baseband_attenuation, u16 radio_attenuation,
1816 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1817 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1819 if (baseband_attenuation == 0xFFFF)
1820 baseband_attenuation = radio->baseband_atten;
1821 if (radio_attenuation == 0xFFFF)
1822 radio_attenuation = radio->radio_atten;
1823 if (txpower == 0xFFFF)
1824 txpower = radio->txctl1;
1825 radio->baseband_atten = baseband_attenuation;
1826 radio->radio_atten = radio_attenuation;
1827 radio->txctl1 = txpower;
1829 assert(/*baseband_attenuation >= 0 &&*/ baseband_attenuation <= 11);
1830 if (radio->revision < 6)
1831 assert(/*radio_attenuation >= 0 &&*/ radio_attenuation <= 9);
1833 assert(/* radio_attenuation >= 0 &&*/ radio_attenuation <= 31);
1834 assert(/*txpower >= 0 &&*/ txpower <= 7);
1836 bcm43xx_phy_set_baseband_attenuation(bcm, baseband_attenuation);
1837 bcm43xx_radio_write16(bcm, 0x0043, radio_attenuation);
1838 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0064, radio_attenuation);
1839 if (radio->version == 0x2050) {
1840 bcm43xx_radio_write16(bcm, 0x0052,
1841 (bcm43xx_radio_read16(bcm, 0x0052) & ~0x0070)
1842 | ((txpower << 4) & 0x0070));
1844 //FIXME: The spec is very weird and unclear here.
1845 if (phy->type == BCM43xx_PHYTYPE_G)
1846 bcm43xx_phy_lo_adjust(bcm, 0);
1849 u16 bcm43xx_default_baseband_attenuation(struct bcm43xx_private *bcm)
1851 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1853 if (radio->version == 0x2050 && radio->revision < 6)
1858 u16 bcm43xx_default_radio_attenuation(struct bcm43xx_private *bcm)
1860 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1861 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1864 if (phy->type == BCM43xx_PHYTYPE_A)
1867 switch (radio->version) {
1869 switch (radio->revision) {
1876 switch (radio->revision) {
1881 if (phy->type == BCM43xx_PHYTYPE_G) {
1882 if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1883 bcm->board_type == 0x421 &&
1884 bcm->board_revision >= 30)
1886 else if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1887 bcm->board_type == 0x416)
1892 if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1893 bcm->board_type == 0x421 &&
1894 bcm->board_revision >= 30)
1901 if (phy->type == BCM43xx_PHYTYPE_G) {
1902 if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1903 bcm->board_type == 0x421 &&
1904 bcm->board_revision >= 30)
1906 else if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1907 bcm->board_type == 0x416)
1909 else if (bcm->chip_id == 0x4320)
1935 if (bcm->board_vendor == PCI_VENDOR_ID_BROADCOM &&
1936 bcm->board_type == 0x421) {
1937 if (bcm->board_revision < 0x43)
1939 else if (bcm->board_revision < 0x51)
1948 u16 bcm43xx_default_txctl1(struct bcm43xx_private *bcm)
1950 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1952 if (radio->version != 0x2050)
1954 if (radio->revision == 1)
1956 if (radio->revision < 6)
1958 if (radio->revision == 8)
1963 void bcm43xx_radio_turn_on(struct bcm43xx_private *bcm)
1965 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1966 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1972 switch (phy->type) {
1973 case BCM43xx_PHYTYPE_A:
1974 bcm43xx_radio_write16(bcm, 0x0004, 0x00C0);
1975 bcm43xx_radio_write16(bcm, 0x0005, 0x0008);
1976 bcm43xx_phy_write(bcm, 0x0010, bcm43xx_phy_read(bcm, 0x0010) & 0xFFF7);
1977 bcm43xx_phy_write(bcm, 0x0011, bcm43xx_phy_read(bcm, 0x0011) & 0xFFF7);
1978 bcm43xx_radio_init2060(bcm);
1980 case BCM43xx_PHYTYPE_B:
1981 case BCM43xx_PHYTYPE_G:
1982 bcm43xx_phy_write(bcm, 0x0015, 0x8000);
1983 bcm43xx_phy_write(bcm, 0x0015, 0xCC00);
1984 bcm43xx_phy_write(bcm, 0x0015, (phy->connected ? 0x00C0 : 0x0000));
1985 err = bcm43xx_radio_selectchannel(bcm, BCM43xx_RADIO_DEFAULT_CHANNEL_BG, 1);
1992 dprintk(KERN_INFO PFX "Radio turned on\n");
1995 void bcm43xx_radio_turn_off(struct bcm43xx_private *bcm)
1997 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1998 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2000 if (phy->type == BCM43xx_PHYTYPE_A) {
2001 bcm43xx_radio_write16(bcm, 0x0004, 0x00FF);
2002 bcm43xx_radio_write16(bcm, 0x0005, 0x00FB);
2003 bcm43xx_phy_write(bcm, 0x0010, bcm43xx_phy_read(bcm, 0x0010) | 0x0008);
2004 bcm43xx_phy_write(bcm, 0x0011, bcm43xx_phy_read(bcm, 0x0011) | 0x0008);
2006 if (phy->type == BCM43xx_PHYTYPE_G && bcm->current_core->rev >= 5) {
2007 bcm43xx_phy_write(bcm, 0x0811, bcm43xx_phy_read(bcm, 0x0811) | 0x008C);
2008 bcm43xx_phy_write(bcm, 0x0812, bcm43xx_phy_read(bcm, 0x0812) & 0xFF73);
2010 bcm43xx_phy_write(bcm, 0x0015, 0xAA00);
2012 dprintk(KERN_INFO PFX "Radio turned off\n");
2015 void bcm43xx_radio_clear_tssi(struct bcm43xx_private *bcm)
2017 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2019 switch (phy->type) {
2020 case BCM43xx_PHYTYPE_A:
2021 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0068, 0x7F7F);
2022 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x006a, 0x7F7F);
2024 case BCM43xx_PHYTYPE_B:
2025 case BCM43xx_PHYTYPE_G:
2026 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0058, 0x7F7F);
2027 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x005a, 0x7F7F);
2028 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0070, 0x7F7F);
2029 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0072, 0x7F7F);