3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
6 Stefano Brivio <st3@riseup.net>
7 Michael Buesch <mbuesch@freenet.de>
8 Danny van Dyk <kugelfang@gentoo.org>
9 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <net/iw_handler.h>
45 #include "bcm43xx_main.h"
46 #include "bcm43xx_debugfs.h"
47 #include "bcm43xx_radio.h"
48 #include "bcm43xx_phy.h"
49 #include "bcm43xx_dma.h"
50 #include "bcm43xx_pio.h"
51 #include "bcm43xx_power.h"
52 #include "bcm43xx_wx.h"
53 #include "bcm43xx_ethtool.h"
54 #include "bcm43xx_xmit.h"
55 #include "bcm43xx_sysfs.h"
58 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
59 MODULE_AUTHOR("Martin Langer");
60 MODULE_AUTHOR("Stefano Brivio");
61 MODULE_AUTHOR("Michael Buesch");
62 MODULE_LICENSE("GPL");
64 #ifdef CONFIG_BCM947XX
65 extern char *nvram_get(char *name);
68 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
69 static int modparam_pio;
70 module_param_named(pio, modparam_pio, int, 0444);
71 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
72 #elif defined(CONFIG_BCM43XX_DMA)
73 # define modparam_pio 0
74 #elif defined(CONFIG_BCM43XX_PIO)
75 # define modparam_pio 1
78 static int modparam_bad_frames_preempt;
79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
80 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames Preemption");
82 static int modparam_short_retry = BCM43xx_DEFAULT_SHORT_RETRY_LIMIT;
83 module_param_named(short_retry, modparam_short_retry, int, 0444);
84 MODULE_PARM_DESC(short_retry, "Short-Retry-Limit (0 - 15)");
86 static int modparam_long_retry = BCM43xx_DEFAULT_LONG_RETRY_LIMIT;
87 module_param_named(long_retry, modparam_long_retry, int, 0444);
88 MODULE_PARM_DESC(long_retry, "Long-Retry-Limit (0 - 15)");
90 static int modparam_locale = -1;
91 module_param_named(locale, modparam_locale, int, 0444);
92 MODULE_PARM_DESC(country, "Select LocaleCode 0-11 (For travelers)");
94 static int modparam_noleds;
95 module_param_named(noleds, modparam_noleds, int, 0444);
96 MODULE_PARM_DESC(noleds, "Turn off all LED activity");
98 #ifdef CONFIG_BCM43XX_DEBUG
99 static char modparam_fwpostfix[64];
100 module_param_string(fwpostfix, modparam_fwpostfix, 64, 0444);
101 MODULE_PARM_DESC(fwpostfix, "Postfix for .fw files. Useful for debugging.");
103 # define modparam_fwpostfix ""
104 #endif /* CONFIG_BCM43XX_DEBUG*/
107 /* If you want to debug with just a single device, enable this,
108 * where the string is the pci device ID (as given by the kernel's
109 * pci_name function) of the device to be used.
111 //#define DEBUG_SINGLE_DEVICE_ONLY "0001:11:00.0"
113 /* If you want to enable printing of each MMIO access, enable this. */
114 //#define DEBUG_ENABLE_MMIO_PRINT
116 /* If you want to enable printing of MMIO access within
117 * ucode/pcm upload, initvals write, enable this.
119 //#define DEBUG_ENABLE_UCODE_MMIO_PRINT
121 /* If you want to enable printing of PCI Config Space access, enable this */
122 //#define DEBUG_ENABLE_PCILOG
125 /* Detailed list maintained at:
126 * http://openfacts.berlios.de/index-en.phtml?title=Bcm43xxDevices
128 static struct pci_device_id bcm43xx_pci_tbl[] = {
129 /* Broadcom 4303 802.11b */
130 { PCI_VENDOR_ID_BROADCOM, 0x4301, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
131 /* Broadcom 4307 802.11b */
132 { PCI_VENDOR_ID_BROADCOM, 0x4307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
133 /* Broadcom 4318 802.11b/g */
134 { PCI_VENDOR_ID_BROADCOM, 0x4318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
135 /* Broadcom 4319 802.11a/b/g */
136 { PCI_VENDOR_ID_BROADCOM, 0x4319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
137 /* Broadcom 4306 802.11b/g */
138 { PCI_VENDOR_ID_BROADCOM, 0x4320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
139 /* Broadcom 4306 802.11a */
140 // { PCI_VENDOR_ID_BROADCOM, 0x4321, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
141 /* Broadcom 4309 802.11a/b/g */
142 { PCI_VENDOR_ID_BROADCOM, 0x4324, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
143 /* Broadcom 43XG 802.11b/g */
144 { PCI_VENDOR_ID_BROADCOM, 0x4325, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
145 #ifdef CONFIG_BCM947XX
146 /* SB bus on BCM947xx */
147 { PCI_VENDOR_ID_BROADCOM, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
151 MODULE_DEVICE_TABLE(pci, bcm43xx_pci_tbl);
153 static void bcm43xx_ram_write(struct bcm43xx_private *bcm, u16 offset, u32 val)
157 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
158 if (!(status & BCM43xx_SBF_XFER_REG_BYTESWAP))
161 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_CONTROL, offset);
163 bcm43xx_write32(bcm, BCM43xx_MMIO_RAM_DATA, val);
167 void bcm43xx_shm_control_word(struct bcm43xx_private *bcm,
168 u16 routing, u16 offset)
172 /* "offset" is the WORD offset. */
177 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_CONTROL, control);
180 u32 bcm43xx_shm_read32(struct bcm43xx_private *bcm,
181 u16 routing, u16 offset)
185 if (routing == BCM43xx_SHM_SHARED) {
186 if (offset & 0x0003) {
187 /* Unaligned access */
188 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
189 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
191 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
192 ret |= bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
198 bcm43xx_shm_control_word(bcm, routing, offset);
199 ret = bcm43xx_read32(bcm, BCM43xx_MMIO_SHM_DATA);
204 u16 bcm43xx_shm_read16(struct bcm43xx_private *bcm,
205 u16 routing, u16 offset)
209 if (routing == BCM43xx_SHM_SHARED) {
210 if (offset & 0x0003) {
211 /* Unaligned access */
212 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
213 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED);
219 bcm43xx_shm_control_word(bcm, routing, offset);
220 ret = bcm43xx_read16(bcm, BCM43xx_MMIO_SHM_DATA);
225 void bcm43xx_shm_write32(struct bcm43xx_private *bcm,
226 u16 routing, u16 offset,
229 if (routing == BCM43xx_SHM_SHARED) {
230 if (offset & 0x0003) {
231 /* Unaligned access */
232 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
234 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
235 (value >> 16) & 0xffff);
237 bcm43xx_shm_control_word(bcm, routing, (offset >> 2) + 1);
239 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA,
245 bcm43xx_shm_control_word(bcm, routing, offset);
247 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, value);
250 void bcm43xx_shm_write16(struct bcm43xx_private *bcm,
251 u16 routing, u16 offset,
254 if (routing == BCM43xx_SHM_SHARED) {
255 if (offset & 0x0003) {
256 /* Unaligned access */
257 bcm43xx_shm_control_word(bcm, routing, offset >> 2);
259 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA_UNALIGNED,
265 bcm43xx_shm_control_word(bcm, routing, offset);
267 bcm43xx_write16(bcm, BCM43xx_MMIO_SHM_DATA, value);
270 void bcm43xx_tsf_read(struct bcm43xx_private *bcm, u64 *tsf)
272 /* We need to be careful. As we read the TSF from multiple
273 * registers, we should take care of register overflows.
274 * In theory, the whole tsf read process should be atomic.
275 * We try to be atomic here, by restaring the read process,
276 * if any of the high registers changed (overflew).
278 if (bcm->current_core->rev >= 3) {
279 u32 low, high, high2;
282 high = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
283 low = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW);
284 high2 = bcm43xx_read32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH);
285 } while (unlikely(high != high2));
293 u16 test1, test2, test3;
296 v3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
297 v2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
298 v1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
299 v0 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_0);
301 test3 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_3);
302 test2 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_2);
303 test1 = bcm43xx_read16(bcm, BCM43xx_MMIO_TSF_1);
304 } while (v3 != test3 || v2 != test2 || v1 != test1);
318 void bcm43xx_tsf_write(struct bcm43xx_private *bcm, u64 tsf)
322 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
323 status |= BCM43xx_SBF_TIME_UPDATE;
324 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
327 /* Be careful with the in-progress timer.
328 * First zero out the low register, so we have a full
329 * register-overflow duration to complete the operation.
331 if (bcm->current_core->rev >= 3) {
332 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
333 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
335 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, 0);
337 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_HIGH, hi);
339 bcm43xx_write32(bcm, BCM43xx_MMIO_REV3PLUS_TSF_LOW, lo);
341 u16 v0 = (tsf & 0x000000000000FFFFULL);
342 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
343 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
344 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
346 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, 0);
348 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_3, v3);
350 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_2, v2);
352 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_1, v1);
354 bcm43xx_write16(bcm, BCM43xx_MMIO_TSF_0, v0);
357 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
358 status &= ~BCM43xx_SBF_TIME_UPDATE;
359 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
363 void bcm43xx_macfilter_set(struct bcm43xx_private *bcm,
370 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_CONTROL, offset);
374 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
377 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
380 bcm43xx_write16(bcm, BCM43xx_MMIO_MACFILTER_DATA, data);
383 static void bcm43xx_macfilter_clear(struct bcm43xx_private *bcm,
386 const u8 zero_addr[ETH_ALEN] = { 0 };
388 bcm43xx_macfilter_set(bcm, offset, zero_addr);
391 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_private *bcm)
393 const u8 *mac = (const u8 *)(bcm->net_dev->dev_addr);
394 const u8 *bssid = (const u8 *)(bcm->ieee->bssid);
395 u8 mac_bssid[ETH_ALEN * 2];
398 memcpy(mac_bssid, mac, ETH_ALEN);
399 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
401 /* Write our MAC address and BSSID to template ram */
402 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
403 bcm43xx_ram_write(bcm, 0x20 + i, *((u32 *)(mac_bssid + i)));
404 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
405 bcm43xx_ram_write(bcm, 0x78 + i, *((u32 *)(mac_bssid + i)));
406 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32))
407 bcm43xx_ram_write(bcm, 0x478 + i, *((u32 *)(mac_bssid + i)));
410 //FIXME: Well, we should probably call them from somewhere.
412 static void bcm43xx_set_slot_time(struct bcm43xx_private *bcm, u16 slot_time)
414 /* slot_time is in usec. */
415 if (bcm43xx_current_phy(bcm)->type != BCM43xx_PHYTYPE_G)
417 bcm43xx_write16(bcm, 0x684, 510 + slot_time);
418 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0010, slot_time);
421 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_private *bcm)
423 bcm43xx_set_slot_time(bcm, 9);
426 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_private *bcm)
428 bcm43xx_set_slot_time(bcm, 20);
432 /* FIXME: To get the MAC-filter working, we need to implement the
433 * following functions (and rename them :)
436 static void bcm43xx_disassociate(struct bcm43xx_private *bcm)
438 bcm43xx_mac_suspend(bcm);
439 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
441 bcm43xx_ram_write(bcm, 0x0026, 0x0000);
442 bcm43xx_ram_write(bcm, 0x0028, 0x0000);
443 bcm43xx_ram_write(bcm, 0x007E, 0x0000);
444 bcm43xx_ram_write(bcm, 0x0080, 0x0000);
445 bcm43xx_ram_write(bcm, 0x047E, 0x0000);
446 bcm43xx_ram_write(bcm, 0x0480, 0x0000);
448 if (bcm->current_core->rev < 3) {
449 bcm43xx_write16(bcm, 0x0610, 0x8000);
450 bcm43xx_write16(bcm, 0x060E, 0x0000);
452 bcm43xx_write32(bcm, 0x0188, 0x80000000);
454 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
456 if (bcm43xx_current_phy(bcm)->type == BCM43xx_PHYTYPE_G &&
457 ieee80211_is_ofdm_rate(bcm->softmac->txrates.default_rate))
458 bcm43xx_short_slot_timing_enable(bcm);
460 bcm43xx_mac_enable(bcm);
463 static void bcm43xx_associate(struct bcm43xx_private *bcm,
466 memcpy(bcm->ieee->bssid, mac, ETH_ALEN);
468 bcm43xx_mac_suspend(bcm);
469 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_ASSOC, mac);
470 bcm43xx_write_mac_bssid_templates(bcm);
471 bcm43xx_mac_enable(bcm);
475 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
476 * Returns the _previously_ enabled IRQ mask.
478 static inline u32 bcm43xx_interrupt_enable(struct bcm43xx_private *bcm, u32 mask)
482 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
483 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask | mask);
488 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
489 * Returns the _previously_ enabled IRQ mask.
491 static inline u32 bcm43xx_interrupt_disable(struct bcm43xx_private *bcm, u32 mask)
495 old_mask = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
496 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
501 /* Synchronize IRQ top- and bottom-half.
502 * IRQs must be masked before calling this.
503 * This must not be called with the irq_lock held.
505 static void bcm43xx_synchronize_irq(struct bcm43xx_private *bcm)
507 synchronize_irq(bcm->irq);
508 tasklet_disable(&bcm->isr_tasklet);
511 /* Make sure we don't receive more data from the device. */
512 static int bcm43xx_disable_interrupts_sync(struct bcm43xx_private *bcm)
516 spin_lock_irqsave(&bcm->irq_lock, flags);
517 if (unlikely(bcm43xx_status(bcm) != BCM43xx_STAT_INITIALIZED)) {
518 spin_unlock_irqrestore(&bcm->irq_lock, flags);
521 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
522 spin_unlock_irqrestore(&bcm->irq_lock, flags);
523 bcm43xx_synchronize_irq(bcm);
528 static int bcm43xx_read_radioinfo(struct bcm43xx_private *bcm)
530 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
531 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
537 if (bcm->chip_id == 0x4317) {
538 if (bcm->chip_rev == 0x00)
539 radio_id = 0x3205017F;
540 else if (bcm->chip_rev == 0x01)
541 radio_id = 0x4205017F;
543 radio_id = 0x5205017F;
545 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
546 radio_id = bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_HIGH);
548 bcm43xx_write16(bcm, BCM43xx_MMIO_RADIO_CONTROL, BCM43xx_RADIOCTL_ID);
549 radio_id |= bcm43xx_read16(bcm, BCM43xx_MMIO_RADIO_DATA_LOW);
552 manufact = (radio_id & 0x00000FFF);
553 version = (radio_id & 0x0FFFF000) >> 12;
554 revision = (radio_id & 0xF0000000) >> 28;
556 dprintk(KERN_INFO PFX "Detected Radio: ID: %x (Manuf: %x Ver: %x Rev: %x)\n",
557 radio_id, manufact, version, revision);
560 case BCM43xx_PHYTYPE_A:
561 if ((version != 0x2060) || (revision != 1) || (manufact != 0x17f))
562 goto err_unsupported_radio;
564 case BCM43xx_PHYTYPE_B:
565 if ((version & 0xFFF0) != 0x2050)
566 goto err_unsupported_radio;
568 case BCM43xx_PHYTYPE_G:
569 if (version != 0x2050)
570 goto err_unsupported_radio;
574 radio->manufact = manufact;
575 radio->version = version;
576 radio->revision = revision;
578 if (phy->type == BCM43xx_PHYTYPE_A)
579 radio->txpower_desired = bcm->sprom.maxpower_aphy;
581 radio->txpower_desired = bcm->sprom.maxpower_bgphy;
585 err_unsupported_radio:
586 printk(KERN_ERR PFX "Unsupported Radio connected to the PHY!\n");
590 static const char * bcm43xx_locale_iso(u8 locale)
592 /* ISO 3166-1 country codes.
593 * Note that there aren't ISO 3166-1 codes for
594 * all or locales. (Not all locales are countries)
597 case BCM43xx_LOCALE_WORLD:
598 case BCM43xx_LOCALE_ALL:
600 case BCM43xx_LOCALE_THAILAND:
602 case BCM43xx_LOCALE_ISRAEL:
604 case BCM43xx_LOCALE_JORDAN:
606 case BCM43xx_LOCALE_CHINA:
608 case BCM43xx_LOCALE_JAPAN:
609 case BCM43xx_LOCALE_JAPAN_HIGH:
611 case BCM43xx_LOCALE_USA_CANADA_ANZ:
612 case BCM43xx_LOCALE_USA_LOW:
614 case BCM43xx_LOCALE_EUROPE:
616 case BCM43xx_LOCALE_NONE:
623 static const char * bcm43xx_locale_string(u8 locale)
626 case BCM43xx_LOCALE_WORLD:
628 case BCM43xx_LOCALE_THAILAND:
630 case BCM43xx_LOCALE_ISRAEL:
632 case BCM43xx_LOCALE_JORDAN:
634 case BCM43xx_LOCALE_CHINA:
636 case BCM43xx_LOCALE_JAPAN:
638 case BCM43xx_LOCALE_USA_CANADA_ANZ:
639 return "USA/Canada/ANZ";
640 case BCM43xx_LOCALE_EUROPE:
642 case BCM43xx_LOCALE_USA_LOW:
644 case BCM43xx_LOCALE_JAPAN_HIGH:
646 case BCM43xx_LOCALE_ALL:
648 case BCM43xx_LOCALE_NONE:
655 static inline u8 bcm43xx_crc8(u8 crc, u8 data)
657 static const u8 t[] = {
658 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
659 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
660 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
661 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
662 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
663 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
664 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
665 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
666 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
667 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
668 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
669 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
670 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
671 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
672 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
673 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
674 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
675 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
676 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
677 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
678 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
679 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
680 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
681 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
682 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
683 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
684 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
685 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
686 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
687 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
688 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
689 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F,
691 return t[crc ^ data];
694 static u8 bcm43xx_sprom_crc(const u16 *sprom)
699 for (word = 0; word < BCM43xx_SPROM_SIZE - 1; word++) {
700 crc = bcm43xx_crc8(crc, sprom[word] & 0x00FF);
701 crc = bcm43xx_crc8(crc, (sprom[word] & 0xFF00) >> 8);
703 crc = bcm43xx_crc8(crc, sprom[BCM43xx_SPROM_VERSION] & 0x00FF);
709 int bcm43xx_sprom_read(struct bcm43xx_private *bcm, u16 *sprom)
712 u8 crc, expected_crc;
714 for (i = 0; i < BCM43xx_SPROM_SIZE; i++)
715 sprom[i] = bcm43xx_read16(bcm, BCM43xx_SPROM_BASE + (i * 2));
717 crc = bcm43xx_sprom_crc(sprom);
718 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
719 if (crc != expected_crc) {
720 printk(KERN_WARNING PFX "WARNING: Invalid SPROM checksum "
721 "(0x%02X, expected: 0x%02X)\n",
729 int bcm43xx_sprom_write(struct bcm43xx_private *bcm, const u16 *sprom)
732 u8 crc, expected_crc;
735 /* CRC-8 validation of the input data. */
736 crc = bcm43xx_sprom_crc(sprom);
737 expected_crc = (sprom[BCM43xx_SPROM_VERSION] & 0xFF00) >> 8;
738 if (crc != expected_crc) {
739 printk(KERN_ERR PFX "SPROM input data: Invalid CRC\n");
743 printk(KERN_INFO PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
744 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_SPROMCTL, &spromctl);
747 spromctl |= 0x10; /* SPROM WRITE enable. */
748 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
751 /* We must burn lots of CPU cycles here, but that does not
752 * really matter as one does not write the SPROM every other minute...
754 printk(KERN_INFO PFX "[ 0%%");
756 for (i = 0; i < BCM43xx_SPROM_SIZE; i++) {
765 bcm43xx_write16(bcm, BCM43xx_SPROM_BASE + (i * 2), sprom[i]);
769 spromctl &= ~0x10; /* SPROM WRITE enable. */
770 bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_SPROMCTL, spromctl);
775 printk(KERN_INFO PFX "SPROM written.\n");
776 bcm43xx_controller_restart(bcm, "SPROM update");
780 printk(KERN_ERR PFX "Could not access SPROM control register.\n");
784 static int bcm43xx_sprom_extract(struct bcm43xx_private *bcm)
788 #ifdef CONFIG_BCM947XX
792 sprom = kzalloc(BCM43xx_SPROM_SIZE * sizeof(u16),
795 printk(KERN_ERR PFX "sprom_extract OOM\n");
798 #ifdef CONFIG_BCM947XX
799 sprom[BCM43xx_SPROM_BOARDFLAGS2] = atoi(nvram_get("boardflags2"));
800 sprom[BCM43xx_SPROM_BOARDFLAGS] = atoi(nvram_get("boardflags"));
802 if ((c = nvram_get("il0macaddr")) != NULL)
803 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_IL0MACADDR]));
805 if ((c = nvram_get("et1macaddr")) != NULL)
806 e_aton(c, (char *) &(sprom[BCM43xx_SPROM_ET1MACADDR]));
808 sprom[BCM43xx_SPROM_PA0B0] = atoi(nvram_get("pa0b0"));
809 sprom[BCM43xx_SPROM_PA0B1] = atoi(nvram_get("pa0b1"));
810 sprom[BCM43xx_SPROM_PA0B2] = atoi(nvram_get("pa0b2"));
812 sprom[BCM43xx_SPROM_PA1B0] = atoi(nvram_get("pa1b0"));
813 sprom[BCM43xx_SPROM_PA1B1] = atoi(nvram_get("pa1b1"));
814 sprom[BCM43xx_SPROM_PA1B2] = atoi(nvram_get("pa1b2"));
816 sprom[BCM43xx_SPROM_BOARDREV] = atoi(nvram_get("boardrev"));
818 bcm43xx_sprom_read(bcm, sprom);
822 value = sprom[BCM43xx_SPROM_BOARDFLAGS2];
823 bcm->sprom.boardflags2 = value;
826 value = sprom[BCM43xx_SPROM_IL0MACADDR + 0];
827 *(((u16 *)bcm->sprom.il0macaddr) + 0) = cpu_to_be16(value);
828 value = sprom[BCM43xx_SPROM_IL0MACADDR + 1];
829 *(((u16 *)bcm->sprom.il0macaddr) + 1) = cpu_to_be16(value);
830 value = sprom[BCM43xx_SPROM_IL0MACADDR + 2];
831 *(((u16 *)bcm->sprom.il0macaddr) + 2) = cpu_to_be16(value);
834 value = sprom[BCM43xx_SPROM_ET0MACADDR + 0];
835 *(((u16 *)bcm->sprom.et0macaddr) + 0) = cpu_to_be16(value);
836 value = sprom[BCM43xx_SPROM_ET0MACADDR + 1];
837 *(((u16 *)bcm->sprom.et0macaddr) + 1) = cpu_to_be16(value);
838 value = sprom[BCM43xx_SPROM_ET0MACADDR + 2];
839 *(((u16 *)bcm->sprom.et0macaddr) + 2) = cpu_to_be16(value);
842 value = sprom[BCM43xx_SPROM_ET1MACADDR + 0];
843 *(((u16 *)bcm->sprom.et1macaddr) + 0) = cpu_to_be16(value);
844 value = sprom[BCM43xx_SPROM_ET1MACADDR + 1];
845 *(((u16 *)bcm->sprom.et1macaddr) + 1) = cpu_to_be16(value);
846 value = sprom[BCM43xx_SPROM_ET1MACADDR + 2];
847 *(((u16 *)bcm->sprom.et1macaddr) + 2) = cpu_to_be16(value);
849 /* ethernet phy settings */
850 value = sprom[BCM43xx_SPROM_ETHPHY];
851 bcm->sprom.et0phyaddr = (value & 0x001F);
852 bcm->sprom.et1phyaddr = (value & 0x03E0) >> 5;
853 bcm->sprom.et0mdcport = (value & (1 << 14)) >> 14;
854 bcm->sprom.et1mdcport = (value & (1 << 15)) >> 15;
856 /* boardrev, antennas, locale */
857 value = sprom[BCM43xx_SPROM_BOARDREV];
858 bcm->sprom.boardrev = (value & 0x00FF);
859 bcm->sprom.locale = (value & 0x0F00) >> 8;
860 bcm->sprom.antennas_aphy = (value & 0x3000) >> 12;
861 bcm->sprom.antennas_bgphy = (value & 0xC000) >> 14;
862 if (modparam_locale != -1) {
863 if (modparam_locale >= 0 && modparam_locale <= 11) {
864 bcm->sprom.locale = modparam_locale;
865 printk(KERN_WARNING PFX "Operating with modified "
866 "LocaleCode %u (%s)\n",
868 bcm43xx_locale_string(bcm->sprom.locale));
870 printk(KERN_WARNING PFX "Module parameter \"locale\" "
871 "invalid value. (0 - 11)\n");
876 value = sprom[BCM43xx_SPROM_PA0B0];
877 bcm->sprom.pa0b0 = value;
878 value = sprom[BCM43xx_SPROM_PA0B1];
879 bcm->sprom.pa0b1 = value;
880 value = sprom[BCM43xx_SPROM_PA0B2];
881 bcm->sprom.pa0b2 = value;
884 value = sprom[BCM43xx_SPROM_WL0GPIO0];
887 bcm->sprom.wl0gpio0 = value & 0x00FF;
888 bcm->sprom.wl0gpio1 = (value & 0xFF00) >> 8;
889 value = sprom[BCM43xx_SPROM_WL0GPIO2];
892 bcm->sprom.wl0gpio2 = value & 0x00FF;
893 bcm->sprom.wl0gpio3 = (value & 0xFF00) >> 8;
896 value = sprom[BCM43xx_SPROM_MAXPWR];
897 bcm->sprom.maxpower_aphy = (value & 0xFF00) >> 8;
898 bcm->sprom.maxpower_bgphy = value & 0x00FF;
901 value = sprom[BCM43xx_SPROM_PA1B0];
902 bcm->sprom.pa1b0 = value;
903 value = sprom[BCM43xx_SPROM_PA1B1];
904 bcm->sprom.pa1b1 = value;
905 value = sprom[BCM43xx_SPROM_PA1B2];
906 bcm->sprom.pa1b2 = value;
908 /* idle tssi target */
909 value = sprom[BCM43xx_SPROM_IDL_TSSI_TGT];
910 bcm->sprom.idle_tssi_tgt_aphy = value & 0x00FF;
911 bcm->sprom.idle_tssi_tgt_bgphy = (value & 0xFF00) >> 8;
914 value = sprom[BCM43xx_SPROM_BOARDFLAGS];
917 bcm->sprom.boardflags = value;
918 /* boardflags workarounds */
919 if (bcm->board_vendor == PCI_VENDOR_ID_DELL &&
920 bcm->chip_id == 0x4301 &&
921 bcm->board_revision == 0x74)
922 bcm->sprom.boardflags |= BCM43xx_BFL_BTCOEXIST;
923 if (bcm->board_vendor == PCI_VENDOR_ID_APPLE &&
924 bcm->board_type == 0x4E &&
925 bcm->board_revision > 0x40)
926 bcm->sprom.boardflags |= BCM43xx_BFL_PACTRL;
929 value = sprom[BCM43xx_SPROM_ANTENNA_GAIN];
930 if (value == 0x0000 || value == 0xFFFF)
932 /* convert values to Q5.2 */
933 bcm->sprom.antennagain_aphy = ((value & 0xFF00) >> 8) * 4;
934 bcm->sprom.antennagain_bgphy = (value & 0x00FF) * 4;
941 static int bcm43xx_geo_init(struct bcm43xx_private *bcm)
943 struct ieee80211_geo *geo;
944 struct ieee80211_channel *chan;
945 int have_a = 0, have_bg = 0;
948 struct bcm43xx_phyinfo *phy;
949 const char *iso_country;
951 geo = kzalloc(sizeof(*geo), GFP_KERNEL);
955 for (i = 0; i < bcm->nr_80211_available; i++) {
956 phy = &(bcm->core_80211_ext[i].phy);
958 case BCM43xx_PHYTYPE_B:
959 case BCM43xx_PHYTYPE_G:
962 case BCM43xx_PHYTYPE_A:
969 iso_country = bcm43xx_locale_iso(bcm->sprom.locale);
972 for (i = 0, channel = IEEE80211_52GHZ_MIN_CHANNEL;
973 channel <= IEEE80211_52GHZ_MAX_CHANNEL; channel++) {
975 chan->freq = bcm43xx_channel_to_freq_a(channel);
976 chan->channel = channel;
981 for (i = 0, channel = IEEE80211_24GHZ_MIN_CHANNEL;
982 channel <= IEEE80211_24GHZ_MAX_CHANNEL; channel++) {
983 chan = &geo->bg[i++];
984 chan->freq = bcm43xx_channel_to_freq_bg(channel);
985 chan->channel = channel;
987 geo->bg_channels = i;
989 memcpy(geo->name, iso_country, 2);
990 if (0 /*TODO: Outdoor use only */)
992 else if (0 /*TODO: Indoor use only */)
998 ieee80211_set_geo(bcm->ieee, geo);
1004 /* DummyTransmission function, as documented on
1005 * http://bcm-specs.sipsolutions.net/DummyTransmission
1007 void bcm43xx_dummy_transmission(struct bcm43xx_private *bcm)
1009 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1010 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1011 unsigned int i, max_loop;
1021 switch (phy->type) {
1022 case BCM43xx_PHYTYPE_A:
1024 buffer[0] = 0xCC010200;
1026 case BCM43xx_PHYTYPE_B:
1027 case BCM43xx_PHYTYPE_G:
1029 buffer[0] = 0x6E840B00;
1036 for (i = 0; i < 5; i++)
1037 bcm43xx_ram_write(bcm, i * 4, buffer[i]);
1039 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
1041 bcm43xx_write16(bcm, 0x0568, 0x0000);
1042 bcm43xx_write16(bcm, 0x07C0, 0x0000);
1043 bcm43xx_write16(bcm, 0x050C, ((phy->type == BCM43xx_PHYTYPE_A) ? 1 : 0));
1044 bcm43xx_write16(bcm, 0x0508, 0x0000);
1045 bcm43xx_write16(bcm, 0x050A, 0x0000);
1046 bcm43xx_write16(bcm, 0x054C, 0x0000);
1047 bcm43xx_write16(bcm, 0x056A, 0x0014);
1048 bcm43xx_write16(bcm, 0x0568, 0x0826);
1049 bcm43xx_write16(bcm, 0x0500, 0x0000);
1050 bcm43xx_write16(bcm, 0x0502, 0x0030);
1052 if (radio->version == 0x2050 && radio->revision <= 0x5)
1053 bcm43xx_radio_write16(bcm, 0x0051, 0x0017);
1054 for (i = 0x00; i < max_loop; i++) {
1055 value = bcm43xx_read16(bcm, 0x050E);
1060 for (i = 0x00; i < 0x0A; i++) {
1061 value = bcm43xx_read16(bcm, 0x050E);
1066 for (i = 0x00; i < 0x0A; i++) {
1067 value = bcm43xx_read16(bcm, 0x0690);
1068 if (!(value & 0x0100))
1072 if (radio->version == 0x2050 && radio->revision <= 0x5)
1073 bcm43xx_radio_write16(bcm, 0x0051, 0x0037);
1076 static void key_write(struct bcm43xx_private *bcm,
1077 u8 index, u8 algorithm, const u16 *key)
1079 unsigned int i, basic_wep = 0;
1083 /* Write associated key information */
1084 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x100 + (index * 2),
1085 ((index << 4) | (algorithm & 0x0F)));
1087 /* The first 4 WEP keys need extra love */
1088 if (((algorithm == BCM43xx_SEC_ALGO_WEP) ||
1089 (algorithm == BCM43xx_SEC_ALGO_WEP104)) && (index < 4))
1092 /* Write key payload, 8 little endian words */
1093 offset = bcm->security_offset + (index * BCM43xx_SEC_KEYSIZE);
1094 for (i = 0; i < (BCM43xx_SEC_KEYSIZE / sizeof(u16)); i++) {
1095 value = cpu_to_le16(key[i]);
1096 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1097 offset + (i * 2), value);
1102 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1103 offset + (i * 2) + 4 * BCM43xx_SEC_KEYSIZE,
1108 static void keymac_write(struct bcm43xx_private *bcm,
1109 u8 index, const u32 *addr)
1111 /* for keys 0-3 there is no associated mac address */
1116 if (bcm->current_core->rev >= 5) {
1117 bcm43xx_shm_write32(bcm,
1120 cpu_to_be32(*addr));
1121 bcm43xx_shm_write16(bcm,
1124 cpu_to_be16(*((u16 *)(addr + 1))));
1127 TODO(); /* Put them in the macaddress filter */
1130 /* Put them BCM43xx_SHM_SHARED, stating index 0x0120.
1131 Keep in mind to update the count of keymacs in 0x003E as well! */
1136 static int bcm43xx_key_write(struct bcm43xx_private *bcm,
1137 u8 index, u8 algorithm,
1138 const u8 *_key, int key_len,
1141 u8 key[BCM43xx_SEC_KEYSIZE] = { 0 };
1143 if (index >= ARRAY_SIZE(bcm->key))
1145 if (key_len > ARRAY_SIZE(key))
1147 if (algorithm < 1 || algorithm > 5)
1150 memcpy(key, _key, key_len);
1151 key_write(bcm, index, algorithm, (const u16 *)key);
1152 keymac_write(bcm, index, (const u32 *)mac_addr);
1154 bcm->key[index].algorithm = algorithm;
1159 static void bcm43xx_clear_keys(struct bcm43xx_private *bcm)
1161 static const u32 zero_mac[2] = { 0 };
1162 unsigned int i,j, nr_keys = 54;
1165 if (bcm->current_core->rev < 5)
1167 assert(nr_keys <= ARRAY_SIZE(bcm->key));
1169 for (i = 0; i < nr_keys; i++) {
1170 bcm->key[i].enabled = 0;
1171 /* returns for i < 4 immediately */
1172 keymac_write(bcm, i, zero_mac);
1173 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1174 0x100 + (i * 2), 0x0000);
1175 for (j = 0; j < 8; j++) {
1176 offset = bcm->security_offset + (j * 4) + (i * BCM43xx_SEC_KEYSIZE);
1177 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED,
1181 dprintk(KERN_INFO PFX "Keys cleared\n");
1184 /* Lowlevel core-switch function. This is only to be used in
1185 * bcm43xx_switch_core() and bcm43xx_probe_cores()
1187 static int _switch_core(struct bcm43xx_private *bcm, int core)
1195 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1196 (core * 0x1000) + 0x18000000);
1199 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ACTIVE_CORE,
1203 current_core = (current_core - 0x18000000) / 0x1000;
1204 if (current_core == core)
1207 if (unlikely(attempts++ > BCM43xx_SWITCH_CORE_MAX_RETRIES))
1211 #ifdef CONFIG_BCM947XX
1212 if (bcm->pci_dev->bus->number == 0)
1213 bcm->current_core_offset = 0x1000 * core;
1215 bcm->current_core_offset = 0;
1220 printk(KERN_ERR PFX "Failed to switch to core %d\n", core);
1224 int bcm43xx_switch_core(struct bcm43xx_private *bcm, struct bcm43xx_coreinfo *new_core)
1228 if (unlikely(!new_core))
1230 if (!new_core->available)
1232 if (bcm->current_core == new_core)
1234 err = _switch_core(bcm, new_core->index);
1238 bcm->current_core = new_core;
1243 static int bcm43xx_core_enabled(struct bcm43xx_private *bcm)
1247 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1248 value &= BCM43xx_SBTMSTATELOW_CLOCK | BCM43xx_SBTMSTATELOW_RESET
1249 | BCM43xx_SBTMSTATELOW_REJECT;
1251 return (value == BCM43xx_SBTMSTATELOW_CLOCK);
1254 /* disable current core */
1255 static int bcm43xx_core_disable(struct bcm43xx_private *bcm, u32 core_flags)
1261 /* fetch sbtmstatelow from core information registers */
1262 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1264 /* core is already in reset */
1265 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_RESET)
1268 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_CLOCK) {
1269 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1270 BCM43xx_SBTMSTATELOW_REJECT;
1271 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1273 for (i = 0; i < 1000; i++) {
1274 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1275 if (sbtmstatelow & BCM43xx_SBTMSTATELOW_REJECT) {
1282 printk(KERN_ERR PFX "Error: core_disable() REJECT timeout!\n");
1286 for (i = 0; i < 1000; i++) {
1287 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1288 if (!(sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_BUSY)) {
1295 printk(KERN_ERR PFX "Error: core_disable() BUSY timeout!\n");
1299 sbtmstatelow = BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1300 BCM43xx_SBTMSTATELOW_REJECT |
1301 BCM43xx_SBTMSTATELOW_RESET |
1302 BCM43xx_SBTMSTATELOW_CLOCK |
1304 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1308 sbtmstatelow = BCM43xx_SBTMSTATELOW_RESET |
1309 BCM43xx_SBTMSTATELOW_REJECT |
1311 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1314 bcm->current_core->enabled = 0;
1319 /* enable (reset) current core */
1320 static int bcm43xx_core_enable(struct bcm43xx_private *bcm, u32 core_flags)
1327 err = bcm43xx_core_disable(bcm, core_flags);
1331 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1332 BCM43xx_SBTMSTATELOW_RESET |
1333 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1335 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1338 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
1339 if (sbtmstatehigh & BCM43xx_SBTMSTATEHIGH_SERROR) {
1340 sbtmstatehigh = 0x00000000;
1341 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATEHIGH, sbtmstatehigh);
1344 sbimstate = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMSTATE);
1345 if (sbimstate & (BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT)) {
1346 sbimstate &= ~(BCM43xx_SBIMSTATE_IB_ERROR | BCM43xx_SBIMSTATE_TIMEOUT);
1347 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMSTATE, sbimstate);
1350 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK |
1351 BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK |
1353 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1356 sbtmstatelow = BCM43xx_SBTMSTATELOW_CLOCK | core_flags;
1357 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1360 bcm->current_core->enabled = 1;
1366 /* http://bcm-specs.sipsolutions.net/80211CoreReset */
1367 void bcm43xx_wireless_core_reset(struct bcm43xx_private *bcm, int connect_phy)
1369 u32 flags = 0x00040000;
1371 if ((bcm43xx_core_enabled(bcm)) &&
1372 !bcm43xx_using_pio(bcm)) {
1373 //FIXME: Do we _really_ want #ifndef CONFIG_BCM947XX here?
1375 #ifndef CONFIG_BCM947XX
1376 /* reset all used DMA controllers. */
1377 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1378 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA2_BASE);
1379 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA3_BASE);
1380 bcm43xx_dmacontroller_tx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1381 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA1_BASE);
1382 if (bcm->current_core->rev < 5)
1383 bcm43xx_dmacontroller_rx_reset(bcm, BCM43xx_MMIO_DMA4_BASE);
1387 if (bcm43xx_status(bcm) == BCM43xx_STAT_SHUTTINGDOWN) {
1388 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1389 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1390 & ~(BCM43xx_SBF_MAC_ENABLED | 0x00000002));
1393 flags |= 0x20000000;
1394 bcm43xx_phy_connect(bcm, connect_phy);
1395 bcm43xx_core_enable(bcm, flags);
1396 bcm43xx_write16(bcm, 0x03E6, 0x0000);
1397 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
1398 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
1403 static void bcm43xx_wireless_core_disable(struct bcm43xx_private *bcm)
1405 bcm43xx_radio_turn_off(bcm);
1406 bcm43xx_write16(bcm, 0x03E6, 0x00F4);
1407 bcm43xx_core_disable(bcm, 0);
1410 /* Mark the current 80211 core inactive. */
1411 static void bcm43xx_wireless_core_mark_inactive(struct bcm43xx_private *bcm)
1415 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1416 bcm43xx_radio_turn_off(bcm);
1417 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1418 sbtmstatelow &= 0xDFF5FFFF;
1419 sbtmstatelow |= 0x000A0000;
1420 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1422 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
1423 sbtmstatelow &= 0xFFF5FFFF;
1424 sbtmstatelow |= 0x00080000;
1425 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
1429 static void handle_irq_transmit_status(struct bcm43xx_private *bcm)
1433 struct bcm43xx_xmitstatus stat;
1436 v0 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_0);
1439 v1 = bcm43xx_read32(bcm, BCM43xx_MMIO_XMITSTAT_1);
1441 stat.cookie = (v0 >> 16) & 0x0000FFFF;
1442 tmp = (u16)((v0 & 0xFFF0) | ((v0 & 0xF) >> 1));
1443 stat.flags = tmp & 0xFF;
1444 stat.cnt1 = (tmp & 0x0F00) >> 8;
1445 stat.cnt2 = (tmp & 0xF000) >> 12;
1446 stat.seq = (u16)(v1 & 0xFFFF);
1447 stat.unknown = (u16)((v1 >> 16) & 0xFF);
1449 bcm43xx_debugfs_log_txstat(bcm, &stat);
1451 if (stat.flags & BCM43xx_TXSTAT_FLAG_IGNORE)
1453 if (!(stat.flags & BCM43xx_TXSTAT_FLAG_ACK)) {
1454 //TODO: packet was not acked (was lost)
1456 //TODO: There are more (unknown) flags to test. see bcm43xx_main.h
1458 if (bcm43xx_using_pio(bcm))
1459 bcm43xx_pio_handle_xmitstatus(bcm, &stat);
1461 bcm43xx_dma_handle_xmitstatus(bcm, &stat);
1465 static void bcm43xx_generate_noise_sample(struct bcm43xx_private *bcm)
1467 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x408, 0x7F7F);
1468 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x40A, 0x7F7F);
1469 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1470 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD) | (1 << 4));
1471 assert(bcm->noisecalc.core_at_start == bcm->current_core);
1472 assert(bcm->noisecalc.channel_at_start == bcm43xx_current_radio(bcm)->channel);
1475 static void bcm43xx_calculate_link_quality(struct bcm43xx_private *bcm)
1477 /* Top half of Link Quality calculation. */
1479 if (bcm->noisecalc.calculation_running)
1481 bcm->noisecalc.core_at_start = bcm->current_core;
1482 bcm->noisecalc.channel_at_start = bcm43xx_current_radio(bcm)->channel;
1483 bcm->noisecalc.calculation_running = 1;
1484 bcm->noisecalc.nr_samples = 0;
1486 bcm43xx_generate_noise_sample(bcm);
1489 static void handle_irq_noise(struct bcm43xx_private *bcm)
1491 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
1497 /* Bottom half of Link Quality calculation. */
1499 assert(bcm->noisecalc.calculation_running);
1500 if (bcm->noisecalc.core_at_start != bcm->current_core ||
1501 bcm->noisecalc.channel_at_start != radio->channel)
1502 goto drop_calculation;
1503 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x408);
1504 noise[0] = (tmp & 0x00FF);
1505 noise[1] = (tmp & 0xFF00) >> 8;
1506 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40A);
1507 noise[2] = (tmp & 0x00FF);
1508 noise[3] = (tmp & 0xFF00) >> 8;
1509 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1510 noise[2] == 0x7F || noise[3] == 0x7F)
1513 /* Get the noise samples. */
1514 assert(bcm->noisecalc.nr_samples < 8);
1515 i = bcm->noisecalc.nr_samples;
1516 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1517 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1518 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1519 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(radio->nrssi_lt) - 1);
1520 bcm->noisecalc.samples[i][0] = radio->nrssi_lt[noise[0]];
1521 bcm->noisecalc.samples[i][1] = radio->nrssi_lt[noise[1]];
1522 bcm->noisecalc.samples[i][2] = radio->nrssi_lt[noise[2]];
1523 bcm->noisecalc.samples[i][3] = radio->nrssi_lt[noise[3]];
1524 bcm->noisecalc.nr_samples++;
1525 if (bcm->noisecalc.nr_samples == 8) {
1526 /* Calculate the Link Quality by the noise samples. */
1528 for (i = 0; i < 8; i++) {
1529 for (j = 0; j < 4; j++)
1530 average += bcm->noisecalc.samples[i][j];
1537 tmp = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, 0x40C);
1538 tmp = (tmp / 128) & 0x1F;
1548 /* FIXME: This is wrong, but people want fancy stats. well... */
1549 bcm->stats.noise = average;
1551 bcm->stats.link_quality = 0;
1552 else if (average > -75)
1553 bcm->stats.link_quality = 1;
1554 else if (average > -85)
1555 bcm->stats.link_quality = 2;
1557 bcm->stats.link_quality = 3;
1558 // dprintk(KERN_INFO PFX "Link Quality: %u (avg was %d)\n", bcm->stats.link_quality, average);
1560 bcm->noisecalc.calculation_running = 0;
1564 bcm43xx_generate_noise_sample(bcm);
1567 static void handle_irq_ps(struct bcm43xx_private *bcm)
1569 if (bcm->ieee->iw_mode == IW_MODE_MASTER) {
1572 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1573 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
1575 if (bcm->ieee->iw_mode == IW_MODE_ADHOC)
1576 bcm->reg124_set_0x4 = 1;
1577 //FIXME else set to false?
1580 static void handle_irq_reg124(struct bcm43xx_private *bcm)
1582 if (!bcm->reg124_set_0x4)
1584 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD,
1585 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD)
1587 //FIXME: reset reg124_set_0x4 to false?
1590 static void handle_irq_pmq(struct bcm43xx_private *bcm)
1597 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_PS_STATUS);
1598 if (!(tmp & 0x00000008))
1601 /* 16bit write is odd, but correct. */
1602 bcm43xx_write16(bcm, BCM43xx_MMIO_PS_STATUS, 0x0002);
1605 static void bcm43xx_generate_beacon_template(struct bcm43xx_private *bcm,
1606 u16 ram_offset, u16 shm_size_offset)
1612 //FIXME: assumption: The chip sets the timestamp
1614 bcm43xx_ram_write(bcm, ram_offset++, value);
1615 bcm43xx_ram_write(bcm, ram_offset++, value);
1618 /* Beacon Interval / Capability Information */
1619 value = 0x0000;//FIXME: Which interval?
1620 value |= (1 << 0) << 16; /* ESS */
1621 value |= (1 << 2) << 16; /* CF Pollable */ //FIXME?
1622 value |= (1 << 3) << 16; /* CF Poll Request */ //FIXME?
1623 if (!bcm->ieee->open_wep)
1624 value |= (1 << 4) << 16; /* Privacy */
1625 bcm43xx_ram_write(bcm, ram_offset++, value);
1631 /* FH Parameter Set */
1634 /* DS Parameter Set */
1637 /* CF Parameter Set */
1643 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, shm_size_offset, size);
1646 static void handle_irq_beacon(struct bcm43xx_private *bcm)
1650 bcm->irq_savedstate &= ~BCM43xx_IRQ_BEACON;
1651 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD);
1653 if ((status & 0x1) && (status & 0x2)) {
1654 /* ACK beacon IRQ. */
1655 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON,
1656 BCM43xx_IRQ_BEACON);
1657 bcm->irq_savedstate |= BCM43xx_IRQ_BEACON;
1660 if (!(status & 0x1)) {
1661 bcm43xx_generate_beacon_template(bcm, 0x68, 0x18);
1663 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1665 if (!(status & 0x2)) {
1666 bcm43xx_generate_beacon_template(bcm, 0x468, 0x1A);
1668 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS2_BITFIELD, status);
1672 /* Interrupt handler bottom-half */
1673 static void bcm43xx_interrupt_tasklet(struct bcm43xx_private *bcm)
1677 u32 merged_dma_reason = 0;
1678 int i, activity = 0;
1679 unsigned long flags;
1681 #ifdef CONFIG_BCM43XX_DEBUG
1682 u32 _handled = 0x00000000;
1683 # define bcmirq_handled(irq) do { _handled |= (irq); } while (0)
1685 # define bcmirq_handled(irq) do { /* nothing */ } while (0)
1686 #endif /* CONFIG_BCM43XX_DEBUG*/
1688 spin_lock_irqsave(&bcm->irq_lock, flags);
1689 reason = bcm->irq_reason;
1690 for (i = 5; i >= 0; i--) {
1691 dma_reason[i] = bcm->dma_reason[i];
1692 merged_dma_reason |= dma_reason[i];
1695 if (unlikely(reason & BCM43xx_IRQ_XMIT_ERROR)) {
1696 /* TX error. We get this when Template Ram is written in wrong endianess
1697 * in dummy_tx(). We also get this if something is wrong with the TX header
1698 * on DMA or PIO queues.
1699 * Maybe we get this in other error conditions, too.
1701 printkl(KERN_ERR PFX "FATAL ERROR: BCM43xx_IRQ_XMIT_ERROR\n");
1702 bcmirq_handled(BCM43xx_IRQ_XMIT_ERROR);
1704 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_FATALMASK)) {
1705 printkl(KERN_ERR PFX "FATAL ERROR: Fatal DMA error: "
1706 "0x%08X, 0x%08X, 0x%08X, "
1707 "0x%08X, 0x%08X, 0x%08X\n",
1708 dma_reason[0], dma_reason[1],
1709 dma_reason[2], dma_reason[3],
1710 dma_reason[4], dma_reason[5]);
1711 bcm43xx_controller_restart(bcm, "DMA error");
1713 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1716 if (unlikely(merged_dma_reason & BCM43xx_DMAIRQ_NONFATALMASK)) {
1717 printkl(KERN_ERR PFX "DMA error: "
1718 "0x%08X, 0x%08X, 0x%08X, "
1719 "0x%08X, 0x%08X, 0x%08X\n",
1720 dma_reason[0], dma_reason[1],
1721 dma_reason[2], dma_reason[3],
1722 dma_reason[4], dma_reason[5]);
1725 if (reason & BCM43xx_IRQ_PS) {
1727 bcmirq_handled(BCM43xx_IRQ_PS);
1730 if (reason & BCM43xx_IRQ_REG124) {
1731 handle_irq_reg124(bcm);
1732 bcmirq_handled(BCM43xx_IRQ_REG124);
1735 if (reason & BCM43xx_IRQ_BEACON) {
1736 if (bcm->ieee->iw_mode == IW_MODE_MASTER)
1737 handle_irq_beacon(bcm);
1738 bcmirq_handled(BCM43xx_IRQ_BEACON);
1741 if (reason & BCM43xx_IRQ_PMQ) {
1742 handle_irq_pmq(bcm);
1743 bcmirq_handled(BCM43xx_IRQ_PMQ);
1746 if (reason & BCM43xx_IRQ_SCAN) {
1748 //bcmirq_handled(BCM43xx_IRQ_SCAN);
1751 if (reason & BCM43xx_IRQ_NOISE) {
1752 handle_irq_noise(bcm);
1753 bcmirq_handled(BCM43xx_IRQ_NOISE);
1756 /* Check the DMA reason registers for received data. */
1757 if (dma_reason[0] & BCM43xx_DMAIRQ_RX_DONE) {
1758 if (bcm43xx_using_pio(bcm))
1759 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue0);
1761 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring0);
1762 /* We intentionally don't set "activity" to 1, here. */
1764 assert(!(dma_reason[1] & BCM43xx_DMAIRQ_RX_DONE));
1765 assert(!(dma_reason[2] & BCM43xx_DMAIRQ_RX_DONE));
1766 if (dma_reason[3] & BCM43xx_DMAIRQ_RX_DONE) {
1767 if (bcm43xx_using_pio(bcm))
1768 bcm43xx_pio_rx(bcm43xx_current_pio(bcm)->queue3);
1770 bcm43xx_dma_rx(bcm43xx_current_dma(bcm)->rx_ring3);
1773 assert(!(dma_reason[4] & BCM43xx_DMAIRQ_RX_DONE));
1774 assert(!(dma_reason[5] & BCM43xx_DMAIRQ_RX_DONE));
1775 bcmirq_handled(BCM43xx_IRQ_RX);
1777 if (reason & BCM43xx_IRQ_XMIT_STATUS) {
1778 handle_irq_transmit_status(bcm);
1780 //TODO: In AP mode, this also causes sending of powersave responses.
1781 bcmirq_handled(BCM43xx_IRQ_XMIT_STATUS);
1784 /* IRQ_PIO_WORKAROUND is handled in the top-half. */
1785 bcmirq_handled(BCM43xx_IRQ_PIO_WORKAROUND);
1786 #ifdef CONFIG_BCM43XX_DEBUG
1787 if (unlikely(reason & ~_handled)) {
1788 printkl(KERN_WARNING PFX
1789 "Unhandled IRQ! Reason: 0x%08x, Unhandled: 0x%08x, "
1790 "DMA: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1791 reason, (reason & ~_handled),
1792 dma_reason[0], dma_reason[1],
1793 dma_reason[2], dma_reason[3]);
1796 #undef bcmirq_handled
1798 if (!modparam_noleds)
1799 bcm43xx_leds_update(bcm, activity);
1800 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
1802 spin_unlock_irqrestore(&bcm->irq_lock, flags);
1805 static void pio_irq_workaround(struct bcm43xx_private *bcm,
1806 u16 base, int queueidx)
1810 rxctl = bcm43xx_read16(bcm, base + BCM43xx_PIO_RXCTL);
1811 if (rxctl & BCM43xx_PIO_RXCTL_DATAAVAILABLE)
1812 bcm->dma_reason[queueidx] |= BCM43xx_DMAIRQ_RX_DONE;
1814 bcm->dma_reason[queueidx] &= ~BCM43xx_DMAIRQ_RX_DONE;
1817 static void bcm43xx_interrupt_ack(struct bcm43xx_private *bcm, u32 reason)
1819 if (bcm43xx_using_pio(bcm) &&
1820 (bcm->current_core->rev < 3) &&
1821 (!(reason & BCM43xx_IRQ_PIO_WORKAROUND))) {
1822 /* Apply a PIO specific workaround to the dma_reasons */
1823 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO1_BASE, 0);
1824 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO2_BASE, 1);
1825 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO3_BASE, 2);
1826 pio_irq_workaround(bcm, BCM43xx_MMIO_PIO4_BASE, 3);
1829 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, reason);
1831 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_REASON,
1832 bcm->dma_reason[0]);
1833 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_REASON,
1834 bcm->dma_reason[1]);
1835 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_REASON,
1836 bcm->dma_reason[2]);
1837 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_REASON,
1838 bcm->dma_reason[3]);
1839 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_REASON,
1840 bcm->dma_reason[4]);
1841 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_REASON,
1842 bcm->dma_reason[5]);
1845 /* Interrupt handler top-half */
1846 static irqreturn_t bcm43xx_interrupt_handler(int irq, void *dev_id, struct pt_regs *regs)
1848 irqreturn_t ret = IRQ_HANDLED;
1849 struct bcm43xx_private *bcm = dev_id;
1855 spin_lock(&bcm->irq_lock);
1857 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
1858 assert(bcm->current_core->id == BCM43xx_COREID_80211);
1860 reason = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
1861 if (reason == 0xffffffff) {
1862 /* irq not for us (shared irq) */
1866 reason &= bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_MASK);
1870 bcm->dma_reason[0] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA0_REASON)
1872 bcm->dma_reason[1] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA1_REASON)
1874 bcm->dma_reason[2] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA2_REASON)
1876 bcm->dma_reason[3] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA3_REASON)
1878 bcm->dma_reason[4] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA4_REASON)
1880 bcm->dma_reason[5] = bcm43xx_read32(bcm, BCM43xx_MMIO_DMA5_REASON)
1883 bcm43xx_interrupt_ack(bcm, reason);
1885 /* disable all IRQs. They are enabled again in the bottom half. */
1886 bcm->irq_savedstate = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
1887 /* save the reason code and call our bottom half. */
1888 bcm->irq_reason = reason;
1889 tasklet_schedule(&bcm->isr_tasklet);
1893 spin_unlock(&bcm->irq_lock);
1898 static void bcm43xx_release_firmware(struct bcm43xx_private *bcm, int force)
1900 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1902 if (bcm->firmware_norelease && !force)
1903 return; /* Suspending or controller reset. */
1904 release_firmware(phy->ucode);
1906 release_firmware(phy->pcm);
1908 release_firmware(phy->initvals0);
1909 phy->initvals0 = NULL;
1910 release_firmware(phy->initvals1);
1911 phy->initvals1 = NULL;
1914 static int bcm43xx_request_firmware(struct bcm43xx_private *bcm)
1916 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
1917 u8 rev = bcm->current_core->rev;
1920 char buf[22 + sizeof(modparam_fwpostfix) - 1] = { 0 };
1923 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_microcode%d%s.fw",
1924 (rev >= 5 ? 5 : rev),
1925 modparam_fwpostfix);
1926 err = request_firmware(&phy->ucode, buf, &bcm->pci_dev->dev);
1929 "Error: Microcode \"%s\" not available or load failed.\n",
1936 snprintf(buf, ARRAY_SIZE(buf),
1937 "bcm43xx_pcm%d%s.fw",
1939 modparam_fwpostfix);
1940 err = request_firmware(&phy->pcm, buf, &bcm->pci_dev->dev);
1943 "Error: PCM \"%s\" not available or load failed.\n",
1949 if (!phy->initvals0) {
1950 if (rev == 2 || rev == 4) {
1951 switch (phy->type) {
1952 case BCM43xx_PHYTYPE_A:
1955 case BCM43xx_PHYTYPE_B:
1956 case BCM43xx_PHYTYPE_G:
1963 } else if (rev >= 5) {
1964 switch (phy->type) {
1965 case BCM43xx_PHYTYPE_A:
1968 case BCM43xx_PHYTYPE_B:
1969 case BCM43xx_PHYTYPE_G:
1977 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
1978 nr, modparam_fwpostfix);
1980 err = request_firmware(&phy->initvals0, buf, &bcm->pci_dev->dev);
1983 "Error: InitVals \"%s\" not available or load failed.\n",
1987 if (phy->initvals0->size % sizeof(struct bcm43xx_initval)) {
1988 printk(KERN_ERR PFX "InitVals fileformat error.\n");
1993 if (!phy->initvals1) {
1997 switch (phy->type) {
1998 case BCM43xx_PHYTYPE_A:
1999 sbtmstatehigh = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATEHIGH);
2000 if (sbtmstatehigh & 0x00010000)
2005 case BCM43xx_PHYTYPE_B:
2006 case BCM43xx_PHYTYPE_G:
2012 snprintf(buf, ARRAY_SIZE(buf), "bcm43xx_initval%02d%s.fw",
2013 nr, modparam_fwpostfix);
2015 err = request_firmware(&phy->initvals1, buf, &bcm->pci_dev->dev);
2018 "Error: InitVals \"%s\" not available or load failed.\n",
2022 if (phy->initvals1->size % sizeof(struct bcm43xx_initval)) {
2023 printk(KERN_ERR PFX "InitVals fileformat error.\n");
2032 bcm43xx_release_firmware(bcm, 1);
2035 printk(KERN_ERR PFX "Error: No InitVals available!\n");
2040 static void bcm43xx_upload_microcode(struct bcm43xx_private *bcm)
2042 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2044 unsigned int i, len;
2046 /* Upload Microcode. */
2047 data = (u32 *)(phy->ucode->data);
2048 len = phy->ucode->size / sizeof(u32);
2049 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_UCODE, 0x0000);
2050 for (i = 0; i < len; i++) {
2051 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2052 be32_to_cpu(data[i]));
2056 /* Upload PCM data. */
2057 data = (u32 *)(phy->pcm->data);
2058 len = phy->pcm->size / sizeof(u32);
2059 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01ea);
2060 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA, 0x00004000);
2061 bcm43xx_shm_control_word(bcm, BCM43xx_SHM_PCM, 0x01eb);
2062 for (i = 0; i < len; i++) {
2063 bcm43xx_write32(bcm, BCM43xx_MMIO_SHM_DATA,
2064 be32_to_cpu(data[i]));
2069 static int bcm43xx_write_initvals(struct bcm43xx_private *bcm,
2070 const struct bcm43xx_initval *data,
2071 const unsigned int len)
2077 for (i = 0; i < len; i++) {
2078 offset = be16_to_cpu(data[i].offset);
2079 size = be16_to_cpu(data[i].size);
2080 value = be32_to_cpu(data[i].value);
2082 if (unlikely(offset >= 0x1000))
2085 if (unlikely(value & 0xFFFF0000))
2087 bcm43xx_write16(bcm, offset, (u16)value);
2088 } else if (size == 4) {
2089 bcm43xx_write32(bcm, offset, value);
2097 printk(KERN_ERR PFX "InitVals (bcm43xx_initvalXX.fw) file-format error. "
2098 "Please fix your bcm43xx firmware files.\n");
2102 static int bcm43xx_upload_initvals(struct bcm43xx_private *bcm)
2104 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2107 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals0->data,
2108 phy->initvals0->size / sizeof(struct bcm43xx_initval));
2111 if (phy->initvals1) {
2112 err = bcm43xx_write_initvals(bcm, (struct bcm43xx_initval *)phy->initvals1->data,
2113 phy->initvals1->size / sizeof(struct bcm43xx_initval));
2121 #ifdef CONFIG_BCM947XX
2122 static struct pci_device_id bcm43xx_47xx_ids[] = {
2123 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
2128 static int bcm43xx_initialize_irq(struct bcm43xx_private *bcm)
2132 bcm->irq = bcm->pci_dev->irq;
2133 #ifdef CONFIG_BCM947XX
2134 if (bcm->pci_dev->bus->number == 0) {
2136 struct pci_device_id *id;
2137 for (id = bcm43xx_47xx_ids; id->vendor; id++) {
2138 d = pci_get_device(id->vendor, id->device, NULL);
2147 err = request_irq(bcm->irq, bcm43xx_interrupt_handler,
2148 IRQF_SHARED, KBUILD_MODNAME, bcm);
2150 printk(KERN_ERR PFX "Cannot register IRQ%d\n", bcm->irq);
2155 /* Switch to the core used to write the GPIO register.
2156 * This is either the ChipCommon, or the PCI core.
2158 static int switch_to_gpio_core(struct bcm43xx_private *bcm)
2162 /* Where to find the GPIO register depends on the chipset.
2163 * If it has a ChipCommon, its register at offset 0x6c is the GPIO
2164 * control register. Otherwise the register at offset 0x6c in the
2165 * PCI core is the GPIO control register.
2167 err = bcm43xx_switch_core(bcm, &bcm->core_chipcommon);
2168 if (err == -ENODEV) {
2169 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2170 if (unlikely(err == -ENODEV)) {
2171 printk(KERN_ERR PFX "gpio error: "
2172 "Neither ChipCommon nor PCI core available!\n");
2179 /* Initialize the GPIOs
2180 * http://bcm-specs.sipsolutions.net/GPIO
2182 static int bcm43xx_gpio_init(struct bcm43xx_private *bcm)
2184 struct bcm43xx_coreinfo *old_core;
2188 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2189 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2192 bcm43xx_leds_switch_all(bcm, 0);
2193 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2194 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK) | 0x000F);
2198 if (bcm->chip_id == 0x4301) {
2202 if (0 /* FIXME: conditional unknown */) {
2203 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2204 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2209 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL) {
2210 bcm43xx_write16(bcm, BCM43xx_MMIO_GPIO_MASK,
2211 bcm43xx_read16(bcm, BCM43xx_MMIO_GPIO_MASK)
2216 if (bcm->current_core->rev >= 2)
2217 mask |= 0x0010; /* FIXME: This is redundant. */
2219 old_core = bcm->current_core;
2220 err = switch_to_gpio_core(bcm);
2223 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL,
2224 (bcm43xx_read32(bcm, BCM43xx_GPIO_CONTROL) & mask) | set);
2225 err = bcm43xx_switch_core(bcm, old_core);
2230 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2231 static int bcm43xx_gpio_cleanup(struct bcm43xx_private *bcm)
2233 struct bcm43xx_coreinfo *old_core;
2236 old_core = bcm->current_core;
2237 err = switch_to_gpio_core(bcm);
2240 bcm43xx_write32(bcm, BCM43xx_GPIO_CONTROL, 0x00000000);
2241 err = bcm43xx_switch_core(bcm, old_core);
2247 /* http://bcm-specs.sipsolutions.net/EnableMac */
2248 void bcm43xx_mac_enable(struct bcm43xx_private *bcm)
2250 bcm->mac_suspended--;
2251 assert(bcm->mac_suspended >= 0);
2252 if (bcm->mac_suspended == 0) {
2253 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2254 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2255 | BCM43xx_SBF_MAC_ENABLED);
2256 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, BCM43xx_IRQ_READY);
2257 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD); /* dummy read */
2258 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2259 bcm43xx_power_saving_ctl_bits(bcm, -1, -1);
2263 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2264 void bcm43xx_mac_suspend(struct bcm43xx_private *bcm)
2269 assert(bcm->mac_suspended >= 0);
2270 if (bcm->mac_suspended == 0) {
2271 bcm43xx_power_saving_ctl_bits(bcm, -1, 1);
2272 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2273 bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD)
2274 & ~BCM43xx_SBF_MAC_ENABLED);
2275 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2276 for (i = 10000; i; i--) {
2277 tmp = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2278 if (tmp & BCM43xx_IRQ_READY)
2282 printkl(KERN_ERR PFX "MAC suspend failed\n");
2285 bcm->mac_suspended++;
2288 void bcm43xx_set_iwmode(struct bcm43xx_private *bcm,
2291 unsigned long flags;
2292 struct net_device *net_dev = bcm->net_dev;
2296 spin_lock_irqsave(&bcm->ieee->lock, flags);
2297 bcm->ieee->iw_mode = iw_mode;
2298 spin_unlock_irqrestore(&bcm->ieee->lock, flags);
2299 if (iw_mode == IW_MODE_MONITOR)
2300 net_dev->type = ARPHRD_IEEE80211;
2302 net_dev->type = ARPHRD_ETHER;
2304 status = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2305 /* Reset status to infrastructured mode */
2306 status &= ~(BCM43xx_SBF_MODE_AP | BCM43xx_SBF_MODE_MONITOR);
2307 status &= ~BCM43xx_SBF_MODE_PROMISC;
2308 status |= BCM43xx_SBF_MODE_NOTADHOC;
2310 /* FIXME: Always enable promisc mode, until we get the MAC filters working correctly. */
2311 status |= BCM43xx_SBF_MODE_PROMISC;
2314 case IW_MODE_MONITOR:
2315 status |= BCM43xx_SBF_MODE_MONITOR;
2316 status |= BCM43xx_SBF_MODE_PROMISC;
2319 status &= ~BCM43xx_SBF_MODE_NOTADHOC;
2321 case IW_MODE_MASTER:
2322 status |= BCM43xx_SBF_MODE_AP;
2324 case IW_MODE_SECOND:
2325 case IW_MODE_REPEAT:
2329 /* nothing to be done here... */
2332 dprintk(KERN_ERR PFX "Unknown mode in set_iwmode: %d\n", iw_mode);
2334 if (net_dev->flags & IFF_PROMISC)
2335 status |= BCM43xx_SBF_MODE_PROMISC;
2336 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, status);
2339 if (iw_mode != IW_MODE_ADHOC && iw_mode != IW_MODE_MASTER) {
2340 if (bcm->chip_id == 0x4306 && bcm->chip_rev == 3)
2345 bcm43xx_write16(bcm, 0x0612, value);
2348 /* This is the opposite of bcm43xx_chip_init() */
2349 static void bcm43xx_chip_cleanup(struct bcm43xx_private *bcm)
2351 bcm43xx_radio_turn_off(bcm);
2352 if (!modparam_noleds)
2353 bcm43xx_leds_exit(bcm);
2354 bcm43xx_gpio_cleanup(bcm);
2355 bcm43xx_release_firmware(bcm, 0);
2358 /* Initialize the chip
2359 * http://bcm-specs.sipsolutions.net/ChipInit
2361 static int bcm43xx_chip_init(struct bcm43xx_private *bcm)
2363 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2364 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2370 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD,
2371 BCM43xx_SBF_CORE_READY
2374 err = bcm43xx_request_firmware(bcm);
2377 bcm43xx_upload_microcode(bcm);
2379 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0xFFFFFFFF);
2380 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, 0x00020402);
2383 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2384 if (value32 == BCM43xx_IRQ_READY)
2387 if (i >= BCM43xx_IRQWAIT_MAX_RETRIES) {
2388 printk(KERN_ERR PFX "IRQ_READY timeout\n");
2390 goto err_release_fw;
2394 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
2396 err = bcm43xx_gpio_init(bcm);
2398 goto err_release_fw;
2400 err = bcm43xx_upload_initvals(bcm);
2402 goto err_gpio_cleanup;
2403 bcm43xx_radio_turn_on(bcm);
2405 bcm43xx_write16(bcm, 0x03E6, 0x0000);
2406 err = bcm43xx_phy_init(bcm);
2410 /* Select initial Interference Mitigation. */
2411 tmp = radio->interfmode;
2412 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2413 bcm43xx_radio_set_interference_mitigation(bcm, tmp);
2415 bcm43xx_phy_set_antenna_diversity(bcm);
2416 bcm43xx_radio_set_txantenna(bcm, BCM43xx_RADIO_TXANTENNA_DEFAULT);
2417 if (phy->type == BCM43xx_PHYTYPE_B) {
2418 value16 = bcm43xx_read16(bcm, 0x005E);
2420 bcm43xx_write16(bcm, 0x005E, value16);
2422 bcm43xx_write32(bcm, 0x0100, 0x01000000);
2423 if (bcm->current_core->rev < 5)
2424 bcm43xx_write32(bcm, 0x010C, 0x01000000);
2426 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2427 value32 &= ~ BCM43xx_SBF_MODE_NOTADHOC;
2428 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2429 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2430 value32 |= BCM43xx_SBF_MODE_NOTADHOC;
2431 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2433 value32 = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2434 value32 |= 0x100000;
2435 bcm43xx_write32(bcm, BCM43xx_MMIO_STATUS_BITFIELD, value32);
2437 if (bcm43xx_using_pio(bcm)) {
2438 bcm43xx_write32(bcm, 0x0210, 0x00000100);
2439 bcm43xx_write32(bcm, 0x0230, 0x00000100);
2440 bcm43xx_write32(bcm, 0x0250, 0x00000100);
2441 bcm43xx_write32(bcm, 0x0270, 0x00000100);
2442 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0034, 0x0000);
2445 /* Probe Response Timeout value */
2446 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2447 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0074, 0x0000);
2449 /* Initially set the wireless operation mode. */
2450 bcm43xx_set_iwmode(bcm, bcm->ieee->iw_mode);
2452 if (bcm->current_core->rev < 3) {
2453 bcm43xx_write16(bcm, 0x060E, 0x0000);
2454 bcm43xx_write16(bcm, 0x0610, 0x8000);
2455 bcm43xx_write16(bcm, 0x0604, 0x0000);
2456 bcm43xx_write16(bcm, 0x0606, 0x0200);
2458 bcm43xx_write32(bcm, 0x0188, 0x80000000);
2459 bcm43xx_write32(bcm, 0x018C, 0x02000000);
2461 bcm43xx_write32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON, 0x00004000);
2462 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2463 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2464 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2465 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2466 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2467 bcm43xx_write32(bcm, BCM43xx_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2469 value32 = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
2470 value32 |= 0x00100000;
2471 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, value32);
2473 bcm43xx_write16(bcm, BCM43xx_MMIO_POWERUP_DELAY, bcm43xx_pctl_powerup_delay(bcm));
2476 dprintk(KERN_INFO PFX "Chip initialized\n");
2481 bcm43xx_radio_turn_off(bcm);
2483 bcm43xx_gpio_cleanup(bcm);
2485 bcm43xx_release_firmware(bcm, 1);
2489 /* Validate chip access
2490 * http://bcm-specs.sipsolutions.net/ValidateChipAccess */
2491 static int bcm43xx_validate_chip(struct bcm43xx_private *bcm)
2496 shm_backup = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000);
2497 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0xAA5555AA);
2498 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0xAA5555AA)
2500 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, 0x55AAAA55);
2501 if (bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, 0x0000) != 0x55AAAA55)
2503 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED, 0x0000, shm_backup);
2505 value = bcm43xx_read32(bcm, BCM43xx_MMIO_STATUS_BITFIELD);
2506 if ((value | 0x80000000) != 0x80000400)
2509 value = bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON);
2510 if (value != 0x00000000)
2515 printk(KERN_ERR PFX "Failed to validate the chipaccess\n");
2519 static void bcm43xx_init_struct_phyinfo(struct bcm43xx_phyinfo *phy)
2521 /* Initialize a "phyinfo" structure. The structure is already
2523 * This is called on insmod time to initialize members.
2525 phy->savedpctlreg = 0xFFFF;
2526 spin_lock_init(&phy->lock);
2529 static void bcm43xx_init_struct_radioinfo(struct bcm43xx_radioinfo *radio)
2531 /* Initialize a "radioinfo" structure. The structure is already
2533 * This is called on insmod time to initialize members.
2535 radio->interfmode = BCM43xx_RADIO_INTERFMODE_NONE;
2536 radio->channel = 0xFF;
2537 radio->initial_channel = 0xFF;
2540 static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2544 u32 core_vendor, core_id, core_rev;
2545 u32 sb_id_hi, chip_id_32 = 0;
2546 u16 pci_device, chip_id_16;
2549 memset(&bcm->core_chipcommon, 0, sizeof(struct bcm43xx_coreinfo));
2550 memset(&bcm->core_pci, 0, sizeof(struct bcm43xx_coreinfo));
2551 memset(&bcm->core_80211, 0, sizeof(struct bcm43xx_coreinfo)
2552 * BCM43xx_MAX_80211_CORES);
2553 memset(&bcm->core_80211_ext, 0, sizeof(struct bcm43xx_coreinfo_80211)
2554 * BCM43xx_MAX_80211_CORES);
2555 bcm->nr_80211_available = 0;
2556 bcm->current_core = NULL;
2557 bcm->active_80211_core = NULL;
2560 err = _switch_core(bcm, 0);
2564 /* fetch sb_id_hi from core information registers */
2565 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2567 core_id = (sb_id_hi & 0xFFF0) >> 4;
2568 core_rev = (sb_id_hi & 0xF);
2569 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2571 /* if present, chipcommon is always core 0; read the chipid from it */
2572 if (core_id == BCM43xx_COREID_CHIPCOMMON) {
2573 chip_id_32 = bcm43xx_read32(bcm, 0);
2574 chip_id_16 = chip_id_32 & 0xFFFF;
2575 bcm->core_chipcommon.available = 1;
2576 bcm->core_chipcommon.id = core_id;
2577 bcm->core_chipcommon.rev = core_rev;
2578 bcm->core_chipcommon.index = 0;
2579 /* While we are at it, also read the capabilities. */
2580 bcm->chipcommon_capabilities = bcm43xx_read32(bcm, BCM43xx_CHIPCOMMON_CAPABILITIES);
2582 /* without a chipCommon, use a hard coded table. */
2583 pci_device = bcm->pci_dev->device;
2584 if (pci_device == 0x4301)
2585 chip_id_16 = 0x4301;
2586 else if ((pci_device >= 0x4305) && (pci_device <= 0x4307))
2587 chip_id_16 = 0x4307;
2588 else if ((pci_device >= 0x4402) && (pci_device <= 0x4403))
2589 chip_id_16 = 0x4402;
2590 else if ((pci_device >= 0x4610) && (pci_device <= 0x4615))
2591 chip_id_16 = 0x4610;
2592 else if ((pci_device >= 0x4710) && (pci_device <= 0x4715))
2593 chip_id_16 = 0x4710;
2594 #ifdef CONFIG_BCM947XX
2595 else if ((pci_device >= 0x4320) && (pci_device <= 0x4325))
2596 chip_id_16 = 0x4309;
2599 printk(KERN_ERR PFX "Could not determine Chip ID\n");
2604 /* ChipCommon with Core Rev >=4 encodes number of cores,
2605 * otherwise consult hardcoded table */
2606 if ((core_id == BCM43xx_COREID_CHIPCOMMON) && (core_rev >= 4)) {
2607 core_count = (chip_id_32 & 0x0F000000) >> 24;
2609 switch (chip_id_16) {
2632 /* SOL if we get here */
2638 bcm->chip_id = chip_id_16;
2639 bcm->chip_rev = (chip_id_32 & 0x000F0000) >> 16;
2640 bcm->chip_package = (chip_id_32 & 0x00F00000) >> 20;
2642 dprintk(KERN_INFO PFX "Chip ID 0x%x, rev 0x%x\n",
2643 bcm->chip_id, bcm->chip_rev);
2644 dprintk(KERN_INFO PFX "Number of cores: %d\n", core_count);
2645 if (bcm->core_chipcommon.available) {
2646 dprintk(KERN_INFO PFX "Core 0: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2647 core_id, core_rev, core_vendor,
2648 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled");
2651 if (bcm->core_chipcommon.available)
2655 for ( ; current_core < core_count; current_core++) {
2656 struct bcm43xx_coreinfo *core;
2657 struct bcm43xx_coreinfo_80211 *ext_80211;
2659 err = _switch_core(bcm, current_core);
2662 /* Gather information */
2663 /* fetch sb_id_hi from core information registers */
2664 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2666 /* extract core_id, core_rev, core_vendor */
2667 core_id = (sb_id_hi & 0xFFF0) >> 4;
2668 core_rev = (sb_id_hi & 0xF);
2669 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2671 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x, %s\n",
2672 current_core, core_id, core_rev, core_vendor,
2673 bcm43xx_core_enabled(bcm) ? "enabled" : "disabled" );
2677 case BCM43xx_COREID_PCI:
2678 core = &bcm->core_pci;
2679 if (core->available) {
2680 printk(KERN_WARNING PFX "Multiple PCI cores found.\n");
2684 case BCM43xx_COREID_80211:
2685 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
2686 core = &(bcm->core_80211[i]);
2687 ext_80211 = &(bcm->core_80211_ext[i]);
2688 if (!core->available)
2693 printk(KERN_WARNING PFX "More than %d cores of type 802.11 found.\n",
2694 BCM43xx_MAX_80211_CORES);
2698 /* More than one 80211 core is only supported
2700 * There are chips with two 80211 cores, but with
2701 * dangling pins on the second core. Be careful
2702 * and ignore these cores here.
2704 if (bcm->pci_dev->device != 0x4324) {
2705 dprintk(KERN_INFO PFX "Ignoring additional 802.11 core.\n");
2718 printk(KERN_ERR PFX "Error: Unsupported 80211 core revision %u\n",
2723 bcm->nr_80211_available++;
2724 core->priv = ext_80211;
2725 bcm43xx_init_struct_phyinfo(&ext_80211->phy);
2726 bcm43xx_init_struct_radioinfo(&ext_80211->radio);
2728 case BCM43xx_COREID_CHIPCOMMON:
2729 printk(KERN_WARNING PFX "Multiple CHIPCOMMON cores found.\n");
2733 core->available = 1;
2735 core->rev = core_rev;
2736 core->index = current_core;
2740 if (!bcm->core_80211[0].available) {
2741 printk(KERN_ERR PFX "Error: No 80211 core found!\n");
2746 err = bcm43xx_switch_core(bcm, &bcm->core_80211[0]);
2753 static void bcm43xx_gen_bssid(struct bcm43xx_private *bcm)
2755 const u8 *mac = (const u8*)(bcm->net_dev->dev_addr);
2756 u8 *bssid = bcm->ieee->bssid;
2758 switch (bcm->ieee->iw_mode) {
2760 random_ether_addr(bssid);
2762 case IW_MODE_MASTER:
2764 case IW_MODE_REPEAT:
2765 case IW_MODE_SECOND:
2766 case IW_MODE_MONITOR:
2767 memcpy(bssid, mac, ETH_ALEN);
2774 static void bcm43xx_rate_memory_write(struct bcm43xx_private *bcm,
2782 offset += (bcm43xx_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2786 offset += (bcm43xx_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2788 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, offset + 0x20,
2789 bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED, offset));
2792 static void bcm43xx_rate_memory_init(struct bcm43xx_private *bcm)
2794 switch (bcm43xx_current_phy(bcm)->type) {
2795 case BCM43xx_PHYTYPE_A:
2796 case BCM43xx_PHYTYPE_G:
2797 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_6MB, 1);
2798 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_12MB, 1);
2799 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_18MB, 1);
2800 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_24MB, 1);
2801 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_36MB, 1);
2802 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_48MB, 1);
2803 bcm43xx_rate_memory_write(bcm, IEEE80211_OFDM_RATE_54MB, 1);
2804 case BCM43xx_PHYTYPE_B:
2805 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_1MB, 0);
2806 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_2MB, 0);
2807 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_5MB, 0);
2808 bcm43xx_rate_memory_write(bcm, IEEE80211_CCK_RATE_11MB, 0);
2815 static void bcm43xx_wireless_core_cleanup(struct bcm43xx_private *bcm)
2817 bcm43xx_chip_cleanup(bcm);
2818 bcm43xx_pio_free(bcm);
2819 bcm43xx_dma_free(bcm);
2821 bcm->current_core->initialized = 0;
2824 /* http://bcm-specs.sipsolutions.net/80211Init */
2825 static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2828 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
2829 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
2835 if (bcm->chip_rev < 5) {
2836 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2837 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2838 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2839 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2840 sbimconfiglow |= 0x32;
2841 else if (bcm->bustype == BCM43xx_BUSTYPE_SB)
2842 sbimconfiglow |= 0x53;
2845 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2848 bcm43xx_phy_calibrate(bcm);
2849 err = bcm43xx_chip_init(bcm);
2853 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0016, bcm->current_core->rev);
2854 ucodeflags = bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED, BCM43xx_UCODEFLAGS_OFFSET);
2856 if (0 /*FIXME: which condition has to be used here? */)
2857 ucodeflags |= 0x00000010;
2859 /* HW decryption needs to be set now */
2860 ucodeflags |= 0x40000000;
2862 if (phy->type == BCM43xx_PHYTYPE_G) {
2863 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2865 ucodeflags |= BCM43xx_UCODEFLAG_UNKGPHY;
2866 if (bcm->sprom.boardflags & BCM43xx_BFL_PACTRL)
2867 ucodeflags |= BCM43xx_UCODEFLAG_UNKPACTRL;
2868 } else if (phy->type == BCM43xx_PHYTYPE_B) {
2869 ucodeflags |= BCM43xx_UCODEFLAG_UNKBGPHY;
2870 if (phy->rev >= 2 && radio->version == 0x2050)
2871 ucodeflags &= ~BCM43xx_UCODEFLAG_UNKGPHY;
2874 if (ucodeflags != bcm43xx_shm_read32(bcm, BCM43xx_SHM_SHARED,
2875 BCM43xx_UCODEFLAGS_OFFSET)) {
2876 bcm43xx_shm_write32(bcm, BCM43xx_SHM_SHARED,
2877 BCM43xx_UCODEFLAGS_OFFSET, ucodeflags);
2880 /* Short/Long Retry Limit.
2881 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
2882 * the chip-internal counter.
2884 limit = limit_value(modparam_short_retry, 0, 0xF);
2885 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0006, limit);
2886 limit = limit_value(modparam_long_retry, 0, 0xF);
2887 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0007, limit);
2889 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0044, 3);
2890 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0046, 2);
2892 bcm43xx_rate_memory_init(bcm);
2894 /* Minimum Contention Window */
2895 if (phy->type == BCM43xx_PHYTYPE_B)
2896 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000001f);
2898 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0003, 0x0000000f);
2899 /* Maximum Contention Window */
2900 bcm43xx_shm_write32(bcm, BCM43xx_SHM_WIRELESS, 0x0004, 0x000003ff);
2902 bcm43xx_gen_bssid(bcm);
2903 bcm43xx_write_mac_bssid_templates(bcm);
2905 if (bcm->current_core->rev >= 5)
2906 bcm43xx_write16(bcm, 0x043C, 0x000C);
2908 if (active_wlcore) {
2909 if (bcm43xx_using_pio(bcm))
2910 err = bcm43xx_pio_init(bcm);
2912 err = bcm43xx_dma_init(bcm);
2914 goto err_chip_cleanup;
2916 bcm43xx_write16(bcm, 0x0612, 0x0050);
2917 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0416, 0x0050);
2918 bcm43xx_shm_write16(bcm, BCM43xx_SHM_SHARED, 0x0414, 0x01F4);
2920 if (active_wlcore) {
2921 if (radio->initial_channel != 0xFF)
2922 bcm43xx_radio_selectchannel(bcm, radio->initial_channel, 0);
2925 /* Don't enable MAC/IRQ here, as it will race with the IRQ handler.
2926 * We enable it later.
2928 bcm->current_core->initialized = 1;
2933 bcm43xx_chip_cleanup(bcm);
2937 static int bcm43xx_chipset_attach(struct bcm43xx_private *bcm)
2942 err = bcm43xx_pctl_set_crystal(bcm, 1);
2945 bcm43xx_pci_read_config16(bcm, PCI_STATUS, &pci_status);
2946 bcm43xx_pci_write_config16(bcm, PCI_STATUS, pci_status & ~PCI_STATUS_SIG_TARGET_ABORT);
2952 static void bcm43xx_chipset_detach(struct bcm43xx_private *bcm)
2954 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
2955 bcm43xx_pctl_set_crystal(bcm, 0);
2958 static void bcm43xx_pcicore_broadcast_value(struct bcm43xx_private *bcm,
2962 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_ADDR, address);
2963 bcm43xx_write32(bcm, BCM43xx_PCICORE_BCAST_DATA, data);
2966 static int bcm43xx_pcicore_commit_settings(struct bcm43xx_private *bcm)
2969 struct bcm43xx_coreinfo *old_core;
2971 old_core = bcm->current_core;
2972 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
2976 bcm43xx_pcicore_broadcast_value(bcm, 0xfd8, 0x00000000);
2978 bcm43xx_switch_core(bcm, old_core);
2984 /* Make an I/O Core usable. "core_mask" is the bitmask of the cores to enable.
2985 * To enable core 0, pass a core_mask of 1<<0
2987 static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
2990 u32 backplane_flag_nr;
2992 struct bcm43xx_coreinfo *old_core;
2995 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBTPSFLAG);
2996 backplane_flag_nr = value & BCM43xx_BACKPLANE_FLAG_NR_MASK;
2998 old_core = bcm->current_core;
2999 err = bcm43xx_switch_core(bcm, &bcm->core_pci);
3003 if (bcm->core_pci.rev < 6) {
3004 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3005 value |= (1 << backplane_flag_nr);
3006 bcm43xx_write32(bcm, BCM43xx_CIR_SBINTVEC, value);
3008 err = bcm43xx_pci_read_config32(bcm, BCM43xx_PCICFG_ICR, &value);
3010 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3011 goto out_switch_back;
3013 value |= core_mask << 8;
3014 err = bcm43xx_pci_write_config32(bcm, BCM43xx_PCICFG_ICR, value);
3016 printk(KERN_ERR PFX "Error: ICR setup failure!\n");
3017 goto out_switch_back;
3021 value = bcm43xx_read32(bcm, BCM43xx_PCICORE_SBTOPCI2);
3022 value |= BCM43xx_SBTOPCI2_PREFETCH | BCM43xx_SBTOPCI2_BURST;
3023 bcm43xx_write32(bcm, BCM43xx_PCICORE_SBTOPCI2, value);
3025 if (bcm->core_pci.rev < 5) {
3026 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
3027 value |= (2 << BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT)
3028 & BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
3029 value |= (3 << BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT)
3030 & BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
3031 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, value);
3032 err = bcm43xx_pcicore_commit_settings(bcm);
3037 err = bcm43xx_switch_core(bcm, old_core);
3042 static void bcm43xx_periodic_every120sec(struct bcm43xx_private *bcm)
3044 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3046 if (phy->type != BCM43xx_PHYTYPE_G || phy->rev < 2)
3049 bcm43xx_mac_suspend(bcm);
3050 bcm43xx_phy_lo_g_measure(bcm);
3051 bcm43xx_mac_enable(bcm);
3054 static void bcm43xx_periodic_every60sec(struct bcm43xx_private *bcm)
3056 bcm43xx_phy_lo_mark_all_unused(bcm);
3057 if (bcm->sprom.boardflags & BCM43xx_BFL_RSSI) {
3058 bcm43xx_mac_suspend(bcm);
3059 bcm43xx_calc_nrssi_slope(bcm);
3060 bcm43xx_mac_enable(bcm);
3064 static void bcm43xx_periodic_every30sec(struct bcm43xx_private *bcm)
3066 /* Update device statistics. */
3067 bcm43xx_calculate_link_quality(bcm);
3070 static void bcm43xx_periodic_every15sec(struct bcm43xx_private *bcm)
3072 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3073 struct bcm43xx_radioinfo *radio = bcm43xx_current_radio(bcm);
3075 if (phy->type == BCM43xx_PHYTYPE_G) {
3076 //TODO: update_aci_moving_average
3077 if (radio->aci_enable && radio->aci_wlan_automatic) {
3078 bcm43xx_mac_suspend(bcm);
3079 if (!radio->aci_enable && 1 /*TODO: not scanning? */) {
3080 if (0 /*TODO: bunch of conditions*/) {
3081 bcm43xx_radio_set_interference_mitigation(bcm,
3082 BCM43xx_RADIO_INTERFMODE_MANUALWLAN);
3084 } else if (1/*TODO*/) {
3086 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(bcm))) {
3087 bcm43xx_radio_set_interference_mitigation(bcm,
3088 BCM43xx_RADIO_INTERFMODE_NONE);
3092 bcm43xx_mac_enable(bcm);
3093 } else if (radio->interfmode == BCM43xx_RADIO_INTERFMODE_NONWLAN &&
3095 //TODO: implement rev1 workaround
3098 bcm43xx_phy_xmitpower(bcm); //FIXME: unless scanning?
3099 //TODO for APHY (temperature?)
3102 static void do_periodic_work(struct bcm43xx_private *bcm)
3106 state = bcm->periodic_state;
3108 bcm43xx_periodic_every120sec(bcm);
3110 bcm43xx_periodic_every60sec(bcm);
3112 bcm43xx_periodic_every30sec(bcm);
3114 bcm43xx_periodic_every15sec(bcm);
3115 bcm->periodic_state = state + 1;
3117 schedule_delayed_work(&bcm->periodic_work, HZ * 15);
3120 /* Estimate a "Badness" value based on the periodic work
3121 * state-machine state. "Badness" is worse (bigger), if the
3122 * periodic work will take longer.
3124 static int estimate_periodic_work_badness(unsigned int state)
3128 if (state % 8 == 0) /* every 120 sec */
3130 if (state % 4 == 0) /* every 60 sec */
3132 if (state % 2 == 0) /* every 30 sec */
3134 if (state % 1 == 0) /* every 15 sec */
3137 #define BADNESS_LIMIT 4
3141 static void bcm43xx_periodic_work_handler(void *d)
3143 struct bcm43xx_private *bcm = d;
3144 unsigned long flags;
3148 badness = estimate_periodic_work_badness(bcm->periodic_state);
3149 if (badness > BADNESS_LIMIT) {
3150 /* Periodic work will take a long time, so we want it to
3153 netif_stop_queue(bcm->net_dev);
3155 spin_lock_irqsave(&bcm->irq_lock, flags);
3156 bcm43xx_mac_suspend(bcm);
3157 if (bcm43xx_using_pio(bcm))
3158 bcm43xx_pio_freeze_txqueues(bcm);
3159 savedirqs = bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3160 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3161 mutex_lock(&bcm->mutex);
3162 bcm43xx_synchronize_irq(bcm);
3164 /* Periodic work should take short time, so we want low
3167 mutex_lock(&bcm->mutex);
3168 spin_lock_irqsave(&bcm->irq_lock, flags);
3171 do_periodic_work(bcm);
3173 if (badness > BADNESS_LIMIT) {
3174 spin_lock_irqsave(&bcm->irq_lock, flags);
3175 if (likely(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED)) {
3176 tasklet_enable(&bcm->isr_tasklet);
3177 bcm43xx_interrupt_enable(bcm, savedirqs);
3178 if (bcm43xx_using_pio(bcm))
3179 bcm43xx_pio_thaw_txqueues(bcm);
3180 bcm43xx_mac_enable(bcm);
3182 netif_wake_queue(bcm->net_dev);
3185 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3186 mutex_unlock(&bcm->mutex);
3189 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_private *bcm)
3191 cancel_rearming_delayed_work(&bcm->periodic_work);
3194 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_private *bcm)
3196 struct work_struct *work = &(bcm->periodic_work);
3198 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
3199 INIT_WORK(work, bcm43xx_periodic_work_handler, bcm);
3200 schedule_work(work);
3203 static void bcm43xx_security_init(struct bcm43xx_private *bcm)
3205 bcm->security_offset = bcm43xx_shm_read16(bcm, BCM43xx_SHM_SHARED,
3207 bcm43xx_clear_keys(bcm);
3210 static int bcm43xx_rng_read(struct hwrng *rng, u32 *data)
3212 struct bcm43xx_private *bcm = (struct bcm43xx_private *)rng->priv;
3213 unsigned long flags;
3215 spin_lock_irqsave(&(bcm)->irq_lock, flags);
3216 *data = bcm43xx_read16(bcm, BCM43xx_MMIO_RNG);
3217 spin_unlock_irqrestore(&(bcm)->irq_lock, flags);
3219 return (sizeof(u16));
3222 static void bcm43xx_rng_exit(struct bcm43xx_private *bcm)
3224 hwrng_unregister(&bcm->rng);
3227 static int bcm43xx_rng_init(struct bcm43xx_private *bcm)
3231 snprintf(bcm->rng_name, ARRAY_SIZE(bcm->rng_name),
3232 "%s_%s", KBUILD_MODNAME, bcm->net_dev->name);
3233 bcm->rng.name = bcm->rng_name;
3234 bcm->rng.data_read = bcm43xx_rng_read;
3235 bcm->rng.priv = (unsigned long)bcm;
3236 err = hwrng_register(&bcm->rng);
3238 printk(KERN_ERR PFX "RNG init failed (%d)\n", err);
3243 static int bcm43xx_shutdown_all_wireless_cores(struct bcm43xx_private *bcm)
3247 struct bcm43xx_coreinfo *core;
3249 bcm43xx_set_status(bcm, BCM43xx_STAT_SHUTTINGDOWN);
3250 for (i = 0; i < bcm->nr_80211_available; i++) {
3251 core = &(bcm->core_80211[i]);
3252 assert(core->available);
3253 if (!core->initialized)
3255 err = bcm43xx_switch_core(bcm, core);
3257 dprintk(KERN_ERR PFX "shutdown_all_wireless_cores "
3258 "switch_core failed (%d)\n", err);
3262 bcm43xx_interrupt_disable(bcm, BCM43xx_IRQ_ALL);
3263 bcm43xx_read32(bcm, BCM43xx_MMIO_GEN_IRQ_REASON); /* dummy read */
3264 bcm43xx_wireless_core_cleanup(bcm);
3265 if (core == bcm->active_80211_core)
3266 bcm->active_80211_core = NULL;
3268 free_irq(bcm->irq, bcm);
3269 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3274 /* This is the opposite of bcm43xx_init_board() */
3275 static void bcm43xx_free_board(struct bcm43xx_private *bcm)
3277 bcm43xx_sysfs_unregister(bcm);
3278 bcm43xx_periodic_tasks_delete(bcm);
3280 mutex_lock(&(bcm)->mutex);
3281 bcm43xx_shutdown_all_wireless_cores(bcm);
3282 bcm43xx_pctl_set_crystal(bcm, 0);
3283 mutex_unlock(&(bcm)->mutex);
3286 static void prepare_phydata_for_init(struct bcm43xx_phyinfo *phy)
3288 phy->antenna_diversity = 0xFFFF;
3289 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3290 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3293 phy->calibrated = 0;
3296 if (phy->_lo_pairs) {
3297 memset(phy->_lo_pairs, 0,
3298 sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT);
3300 memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3303 static void prepare_radiodata_for_init(struct bcm43xx_private *bcm,
3304 struct bcm43xx_radioinfo *radio)
3308 /* Set default attenuation values. */
3309 radio->baseband_atten = bcm43xx_default_baseband_attenuation(bcm);
3310 radio->radio_atten = bcm43xx_default_radio_attenuation(bcm);
3311 radio->txctl1 = bcm43xx_default_txctl1(bcm);
3312 radio->txctl2 = 0xFFFF;
3313 radio->txpwr_offset = 0;
3316 radio->nrssislope = 0;
3317 for (i = 0; i < ARRAY_SIZE(radio->nrssi); i++)
3318 radio->nrssi[i] = -1000;
3319 for (i = 0; i < ARRAY_SIZE(radio->nrssi_lt); i++)
3320 radio->nrssi_lt[i] = i;
3322 radio->lofcal = 0xFFFF;
3323 radio->initval = 0xFFFF;
3325 radio->aci_enable = 0;
3326 radio->aci_wlan_automatic = 0;
3327 radio->aci_hw_rssi = 0;
3330 static void prepare_priv_for_init(struct bcm43xx_private *bcm)
3333 struct bcm43xx_coreinfo *core;
3334 struct bcm43xx_coreinfo_80211 *wlext;
3336 assert(!bcm->active_80211_core);
3338 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3341 bcm->was_initialized = 0;
3342 bcm->reg124_set_0x4 = 0;
3345 memset(&bcm->stats, 0, sizeof(bcm->stats));
3347 /* Wireless core data */
3348 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3349 core = &(bcm->core_80211[i]);
3352 if (!core->available)
3354 assert(wlext == &(bcm->core_80211_ext[i]));
3356 prepare_phydata_for_init(&wlext->phy);
3357 prepare_radiodata_for_init(bcm, &wlext->radio);
3360 /* IRQ related flags */
3361 bcm->irq_reason = 0;
3362 memset(bcm->dma_reason, 0, sizeof(bcm->dma_reason));
3363 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3365 /* Noise calculation context */
3366 memset(&bcm->noisecalc, 0, sizeof(bcm->noisecalc));
3368 /* Periodic work context */
3369 bcm->periodic_state = 0;
3372 static int wireless_core_up(struct bcm43xx_private *bcm,
3377 if (!bcm43xx_core_enabled(bcm))
3378 bcm43xx_wireless_core_reset(bcm, 1);
3380 bcm43xx_wireless_core_mark_inactive(bcm);
3381 err = bcm43xx_wireless_core_init(bcm, active_wlcore);
3385 bcm43xx_radio_turn_off(bcm);
3390 /* Select and enable the "to be used" wireless core.
3391 * Locking: bcm->mutex must be aquired before calling this.
3392 * bcm->irq_lock must not be aquired.
3394 int bcm43xx_select_wireless_core(struct bcm43xx_private *bcm,
3398 struct bcm43xx_coreinfo *active_core = NULL;
3399 struct bcm43xx_coreinfo_80211 *active_wlext = NULL;
3400 struct bcm43xx_coreinfo *core;
3401 struct bcm43xx_coreinfo_80211 *wlext;
3402 int adjust_active_sbtmstatelow = 0;
3407 /* If no phytype is requested, select the first core. */
3408 assert(bcm->core_80211[0].available);
3409 wlext = bcm->core_80211[0].priv;
3410 phytype = wlext->phy.type;
3412 /* Find the requested core. */
3413 for (i = 0; i < bcm->nr_80211_available; i++) {
3414 core = &(bcm->core_80211[i]);
3416 if (wlext->phy.type == phytype) {
3418 active_wlext = wlext;
3423 return -ESRCH; /* No such PHYTYPE on this board. */
3425 if (bcm->active_80211_core) {
3426 /* We already selected a wl core in the past.
3427 * So first clean up everything.
3429 dprintk(KERN_INFO PFX "select_wireless_core: cleanup\n");
3430 ieee80211softmac_stop(bcm->net_dev);
3431 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3432 err = bcm43xx_disable_interrupts_sync(bcm);
3434 tasklet_enable(&bcm->isr_tasklet);
3435 err = bcm43xx_shutdown_all_wireless_cores(bcm);
3438 /* Ok, everything down, continue to re-initialize. */
3439 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZING);
3442 /* Reset all data structures. */
3443 prepare_priv_for_init(bcm);
3445 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_FAST);
3449 /* Mark all unused cores "inactive". */
3450 for (i = 0; i < bcm->nr_80211_available; i++) {
3451 core = &(bcm->core_80211[i]);
3454 if (core == active_core)
3456 err = bcm43xx_switch_core(bcm, core);
3458 dprintk(KERN_ERR PFX "Could not switch to inactive "
3459 "802.11 core (%d)\n", err);
3462 err = wireless_core_up(bcm, 0);
3464 dprintk(KERN_ERR PFX "core_up for inactive 802.11 core "
3465 "failed (%d)\n", err);
3468 adjust_active_sbtmstatelow = 1;
3471 /* Now initialize the active 802.11 core. */
3472 err = bcm43xx_switch_core(bcm, active_core);
3474 dprintk(KERN_ERR PFX "Could not switch to active "
3475 "802.11 core (%d)\n", err);
3478 if (adjust_active_sbtmstatelow &&
3479 active_wlext->phy.type == BCM43xx_PHYTYPE_G) {
3482 sbtmstatelow = bcm43xx_read32(bcm, BCM43xx_CIR_SBTMSTATELOW);
3483 sbtmstatelow |= 0x20000000;
3484 bcm43xx_write32(bcm, BCM43xx_CIR_SBTMSTATELOW, sbtmstatelow);
3486 err = wireless_core_up(bcm, 1);
3488 dprintk(KERN_ERR PFX "core_up for active 802.11 core "
3489 "failed (%d)\n", err);
3492 err = bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_DYNAMIC);
3495 bcm->active_80211_core = active_core;
3497 bcm43xx_macfilter_clear(bcm, BCM43xx_MACFILTER_ASSOC);
3498 bcm43xx_macfilter_set(bcm, BCM43xx_MACFILTER_SELF, (u8 *)(bcm->net_dev->dev_addr));
3499 bcm43xx_security_init(bcm);
3500 ieee80211softmac_start(bcm->net_dev);
3502 /* Let's go! Be careful after enabling the IRQs.
3503 * Don't switch cores, for example.
3505 bcm43xx_mac_enable(bcm);
3506 bcm43xx_set_status(bcm, BCM43xx_STAT_INITIALIZED);
3507 err = bcm43xx_initialize_irq(bcm);
3510 bcm43xx_interrupt_enable(bcm, bcm->irq_savedstate);
3512 dprintk(KERN_INFO PFX "Selected 802.11 core (phytype %d)\n",
3513 active_wlext->phy.type);
3518 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3519 bcm43xx_pctl_set_clock(bcm, BCM43xx_PCTL_CLK_SLOW);
3523 static int bcm43xx_init_board(struct bcm43xx_private *bcm)
3527 mutex_lock(&(bcm)->mutex);
3529 tasklet_enable(&bcm->isr_tasklet);
3530 err = bcm43xx_pctl_set_crystal(bcm, 1);
3533 err = bcm43xx_pctl_init(bcm);
3535 goto err_crystal_off;
3536 err = bcm43xx_select_wireless_core(bcm, -1);
3538 goto err_crystal_off;
3540 bcm43xx_periodic_tasks_setup(bcm);
3541 err = bcm43xx_sysfs_register(bcm);
3543 goto err_wlshutdown;
3545 /*FIXME: This should be handled by softmac instead. */
3546 schedule_work(&bcm->softmac->associnfo.work);
3549 mutex_unlock(&(bcm)->mutex);
3554 bcm43xx_shutdown_all_wireless_cores(bcm);
3556 bcm43xx_pctl_set_crystal(bcm, 0);
3558 tasklet_disable(&bcm->isr_tasklet);
3562 static void bcm43xx_detach_board(struct bcm43xx_private *bcm)
3564 struct pci_dev *pci_dev = bcm->pci_dev;
3567 bcm43xx_chipset_detach(bcm);
3568 /* Do _not_ access the chip, after it is detached. */
3569 pci_iounmap(pci_dev, bcm->mmio_addr);
3570 pci_release_regions(pci_dev);
3571 pci_disable_device(pci_dev);
3573 /* Free allocated structures/fields */
3574 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3575 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3576 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3577 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3581 static int bcm43xx_read_phyinfo(struct bcm43xx_private *bcm)
3583 struct bcm43xx_phyinfo *phy = bcm43xx_current_phy(bcm);
3591 value = bcm43xx_read16(bcm, BCM43xx_MMIO_PHY_VER);
3593 phy_version = (value & 0xF000) >> 12;
3594 phy_type = (value & 0x0F00) >> 8;
3595 phy_rev = (value & 0x000F);
3597 dprintk(KERN_INFO PFX "Detected PHY: Version: %x, Type %x, Revision %x\n",
3598 phy_version, phy_type, phy_rev);
3601 case BCM43xx_PHYTYPE_A:
3604 /*FIXME: We need to switch the ieee->modulation, etc.. flags,
3605 * if we switch 80211 cores after init is done.
3606 * As we do not implement on the fly switching between
3607 * wireless cores, I will leave this as a future task.
3609 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION;
3610 bcm->ieee->mode = IEEE_A;
3611 bcm->ieee->freq_band = IEEE80211_52GHZ_BAND |
3612 IEEE80211_24GHZ_BAND;
3614 case BCM43xx_PHYTYPE_B:
3615 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6 && phy_rev != 7)
3617 bcm->ieee->modulation = IEEE80211_CCK_MODULATION;
3618 bcm->ieee->mode = IEEE_B;
3619 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3621 case BCM43xx_PHYTYPE_G:
3624 bcm->ieee->modulation = IEEE80211_OFDM_MODULATION |
3625 IEEE80211_CCK_MODULATION;
3626 bcm->ieee->mode = IEEE_G;
3627 bcm->ieee->freq_band = IEEE80211_24GHZ_BAND;
3630 printk(KERN_ERR PFX "Error: Unknown PHY Type %x\n",
3635 printk(KERN_WARNING PFX "Invalid PHY Revision %x\n",
3639 phy->version = phy_version;
3640 phy->type = phy_type;
3642 if ((phy_type == BCM43xx_PHYTYPE_B) || (phy_type == BCM43xx_PHYTYPE_G)) {
3643 p = kzalloc(sizeof(struct bcm43xx_lopair) * BCM43xx_LO_COUNT,
3653 static int bcm43xx_attach_board(struct bcm43xx_private *bcm)
3655 struct pci_dev *pci_dev = bcm->pci_dev;
3656 struct net_device *net_dev = bcm->net_dev;
3661 err = pci_enable_device(pci_dev);
3663 printk(KERN_ERR PFX "pci_enable_device() failed\n");
3666 err = pci_request_regions(pci_dev, KBUILD_MODNAME);
3668 printk(KERN_ERR PFX "pci_request_regions() failed\n");
3669 goto err_pci_disable;
3671 /* enable PCI bus-mastering */
3672 pci_set_master(pci_dev);
3673 bcm->mmio_addr = pci_iomap(pci_dev, 0, ~0UL);
3674 if (!bcm->mmio_addr) {
3675 printk(KERN_ERR PFX "pci_iomap() failed\n");
3677 goto err_pci_release;
3679 net_dev->base_addr = (unsigned long)bcm->mmio_addr;
3681 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_VENDOR_ID,
3682 &bcm->board_vendor);
3683 bcm43xx_pci_read_config16(bcm, PCI_SUBSYSTEM_ID,
3685 bcm43xx_pci_read_config16(bcm, PCI_REVISION_ID,
3686 &bcm->board_revision);
3688 err = bcm43xx_chipset_attach(bcm);
3691 err = bcm43xx_pctl_init(bcm);
3693 goto err_chipset_detach;
3694 err = bcm43xx_probe_cores(bcm);
3696 goto err_chipset_detach;
3698 /* Attach all IO cores to the backplane. */
3700 for (i = 0; i < bcm->nr_80211_available; i++)
3701 coremask |= (1 << bcm->core_80211[i].index);
3702 //FIXME: Also attach some non80211 cores?
3703 err = bcm43xx_setup_backplane_pci_connection(bcm, coremask);
3705 printk(KERN_ERR PFX "Backplane->PCI connection failed!\n");
3706 goto err_chipset_detach;
3709 err = bcm43xx_sprom_extract(bcm);
3711 goto err_chipset_detach;
3712 err = bcm43xx_leds_init(bcm);
3714 goto err_chipset_detach;
3716 for (i = 0; i < bcm->nr_80211_available; i++) {
3717 err = bcm43xx_switch_core(bcm, &bcm->core_80211[i]);
3718 assert(err != -ENODEV);
3720 goto err_80211_unwind;
3722 /* Enable the selected wireless core.
3723 * Connect PHY only on the first core.
3725 bcm43xx_wireless_core_reset(bcm, (i == 0));
3727 err = bcm43xx_read_phyinfo(bcm);
3728 if (err && (i == 0))
3729 goto err_80211_unwind;
3731 err = bcm43xx_read_radioinfo(bcm);
3732 if (err && (i == 0))
3733 goto err_80211_unwind;
3735 err = bcm43xx_validate_chip(bcm);
3736 if (err && (i == 0))
3737 goto err_80211_unwind;
3739 bcm43xx_radio_turn_off(bcm);
3740 err = bcm43xx_phy_init_tssi2dbm_table(bcm);
3742 goto err_80211_unwind;
3743 bcm43xx_wireless_core_disable(bcm);
3745 err = bcm43xx_geo_init(bcm);
3747 goto err_80211_unwind;
3748 bcm43xx_pctl_set_crystal(bcm, 0);
3750 /* Set the MAC address in the networking subsystem */
3751 if (is_valid_ether_addr(bcm->sprom.et1macaddr))
3752 memcpy(bcm->net_dev->dev_addr, bcm->sprom.et1macaddr, 6);
3754 memcpy(bcm->net_dev->dev_addr, bcm->sprom.il0macaddr, 6);
3756 snprintf(bcm->nick, IW_ESSID_MAX_SIZE,
3757 "Broadcom %04X", bcm->chip_id);
3764 for (i = 0; i < BCM43xx_MAX_80211_CORES; i++) {
3765 kfree(bcm->core_80211_ext[i].phy._lo_pairs);
3766 if (bcm->core_80211_ext[i].phy.dyn_tssi_tbl)
3767 kfree(bcm->core_80211_ext[i].phy.tssi2dbm);
3770 bcm43xx_chipset_detach(bcm);
3772 pci_iounmap(pci_dev, bcm->mmio_addr);
3774 pci_release_regions(pci_dev);
3776 pci_disable_device(pci_dev);
3780 /* Do the Hardware IO operations to send the txb */
3781 static inline int bcm43xx_tx(struct bcm43xx_private *bcm,
3782 struct ieee80211_txb *txb)
3786 if (bcm43xx_using_pio(bcm))
3787 err = bcm43xx_pio_tx(bcm, txb);
3789 err = bcm43xx_dma_tx(bcm, txb);
3790 bcm->net_dev->trans_start = jiffies;
3795 static void bcm43xx_ieee80211_set_chan(struct net_device *net_dev,
3798 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3799 struct bcm43xx_radioinfo *radio;
3800 unsigned long flags;
3802 mutex_lock(&bcm->mutex);
3803 spin_lock_irqsave(&bcm->irq_lock, flags);
3804 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
3805 bcm43xx_mac_suspend(bcm);
3806 bcm43xx_radio_selectchannel(bcm, channel, 0);
3807 bcm43xx_mac_enable(bcm);
3809 radio = bcm43xx_current_radio(bcm);
3810 radio->initial_channel = channel;
3812 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3813 mutex_unlock(&bcm->mutex);
3816 /* set_security() callback in struct ieee80211_device */
3817 static void bcm43xx_ieee80211_set_security(struct net_device *net_dev,
3818 struct ieee80211_security *sec)
3820 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3821 struct ieee80211_security *secinfo = &bcm->ieee->sec;
3822 unsigned long flags;
3825 dprintk(KERN_INFO PFX "set security called");
3827 mutex_lock(&bcm->mutex);
3828 spin_lock_irqsave(&bcm->irq_lock, flags);
3830 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++)
3831 if (sec->flags & (1<<keyidx)) {
3832 secinfo->encode_alg[keyidx] = sec->encode_alg[keyidx];
3833 secinfo->key_sizes[keyidx] = sec->key_sizes[keyidx];
3834 memcpy(secinfo->keys[keyidx], sec->keys[keyidx], SCM_KEY_LEN);
3837 if (sec->flags & SEC_ACTIVE_KEY) {
3838 secinfo->active_key = sec->active_key;
3839 dprintk(", .active_key = %d", sec->active_key);
3841 if (sec->flags & SEC_UNICAST_GROUP) {
3842 secinfo->unicast_uses_group = sec->unicast_uses_group;
3843 dprintk(", .unicast_uses_group = %d", sec->unicast_uses_group);
3845 if (sec->flags & SEC_LEVEL) {
3846 secinfo->level = sec->level;
3847 dprintk(", .level = %d", sec->level);
3849 if (sec->flags & SEC_ENABLED) {
3850 secinfo->enabled = sec->enabled;
3851 dprintk(", .enabled = %d", sec->enabled);
3853 if (sec->flags & SEC_ENCRYPT) {
3854 secinfo->encrypt = sec->encrypt;
3855 dprintk(", .encrypt = %d", sec->encrypt);
3857 if (sec->flags & SEC_AUTH_MODE) {
3858 secinfo->auth_mode = sec->auth_mode;
3859 dprintk(", .auth_mode = %d", sec->auth_mode);
3862 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED &&
3863 !bcm->ieee->host_encrypt) {
3864 if (secinfo->enabled) {
3865 /* upload WEP keys to hardware */
3866 char null_address[6] = { 0 };
3868 for (keyidx = 0; keyidx<WEP_KEYS; keyidx++) {
3869 if (!(sec->flags & (1<<keyidx)))
3871 switch (sec->encode_alg[keyidx]) {
3872 case SEC_ALG_NONE: algorithm = BCM43xx_SEC_ALGO_NONE; break;
3874 algorithm = BCM43xx_SEC_ALGO_WEP;
3875 if (secinfo->key_sizes[keyidx] == 13)
3876 algorithm = BCM43xx_SEC_ALGO_WEP104;
3880 algorithm = BCM43xx_SEC_ALGO_TKIP;
3884 algorithm = BCM43xx_SEC_ALGO_AES;
3890 bcm43xx_key_write(bcm, keyidx, algorithm, sec->keys[keyidx], secinfo->key_sizes[keyidx], &null_address[0]);
3891 bcm->key[keyidx].enabled = 1;
3892 bcm->key[keyidx].algorithm = algorithm;
3895 bcm43xx_clear_keys(bcm);
3897 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3898 mutex_unlock(&bcm->mutex);
3901 /* hard_start_xmit() callback in struct ieee80211_device */
3902 static int bcm43xx_ieee80211_hard_start_xmit(struct ieee80211_txb *txb,
3903 struct net_device *net_dev,
3906 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3908 unsigned long flags;
3910 spin_lock_irqsave(&bcm->irq_lock, flags);
3911 if (likely(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED))
3912 err = bcm43xx_tx(bcm, txb);
3913 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3918 static struct net_device_stats * bcm43xx_net_get_stats(struct net_device *net_dev)
3920 return &(bcm43xx_priv(net_dev)->ieee->stats);
3923 static void bcm43xx_net_tx_timeout(struct net_device *net_dev)
3925 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3926 unsigned long flags;
3928 spin_lock_irqsave(&bcm->irq_lock, flags);
3929 bcm43xx_controller_restart(bcm, "TX timeout");
3930 spin_unlock_irqrestore(&bcm->irq_lock, flags);
3933 #ifdef CONFIG_NET_POLL_CONTROLLER
3934 static void bcm43xx_net_poll_controller(struct net_device *net_dev)
3936 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3937 unsigned long flags;
3939 local_irq_save(flags);
3940 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED)
3941 bcm43xx_interrupt_handler(bcm->irq, bcm, NULL);
3942 local_irq_restore(flags);
3944 #endif /* CONFIG_NET_POLL_CONTROLLER */
3946 static int bcm43xx_net_open(struct net_device *net_dev)
3948 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3950 return bcm43xx_init_board(bcm);
3953 static int bcm43xx_net_stop(struct net_device *net_dev)
3955 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
3958 ieee80211softmac_stop(net_dev);
3959 err = bcm43xx_disable_interrupts_sync(bcm);
3961 bcm43xx_free_board(bcm);
3966 static int bcm43xx_init_private(struct bcm43xx_private *bcm,
3967 struct net_device *net_dev,
3968 struct pci_dev *pci_dev)
3972 bcm43xx_set_status(bcm, BCM43xx_STAT_UNINIT);
3973 bcm->ieee = netdev_priv(net_dev);
3974 bcm->softmac = ieee80211_priv(net_dev);
3975 bcm->softmac->set_channel = bcm43xx_ieee80211_set_chan;
3977 bcm->irq_savedstate = BCM43xx_IRQ_INITIAL;
3978 bcm->mac_suspended = 1;
3979 bcm->pci_dev = pci_dev;
3980 bcm->net_dev = net_dev;
3981 bcm->bad_frames_preempt = modparam_bad_frames_preempt;
3982 spin_lock_init(&bcm->irq_lock);
3983 spin_lock_init(&bcm->leds_lock);
3984 mutex_init(&bcm->mutex);
3985 tasklet_init(&bcm->isr_tasklet,
3986 (void (*)(unsigned long))bcm43xx_interrupt_tasklet,
3987 (unsigned long)bcm);
3988 tasklet_disable_nosync(&bcm->isr_tasklet);
3990 bcm->__using_pio = 1;
3992 err = pci_set_dma_mask(pci_dev, DMA_30BIT_MASK);
3993 err |= pci_set_consistent_dma_mask(pci_dev, DMA_30BIT_MASK);
3995 #ifdef CONFIG_BCM43XX_PIO
3996 printk(KERN_WARNING PFX "DMA not supported. Falling back to PIO.\n");
3997 bcm->__using_pio = 1;
3999 printk(KERN_ERR PFX "FATAL: DMA not supported and PIO not configured. "
4000 "Recompile the driver with PIO support, please.\n");
4002 #endif /* CONFIG_BCM43XX_PIO */
4005 bcm->rts_threshold = BCM43xx_DEFAULT_RTS_THRESHOLD;
4007 /* default to sw encryption for now */
4008 bcm->ieee->host_build_iv = 0;
4009 bcm->ieee->host_encrypt = 1;
4010 bcm->ieee->host_decrypt = 1;
4012 bcm->ieee->iw_mode = BCM43xx_INITIAL_IWMODE;
4013 bcm->ieee->tx_headroom = sizeof(struct bcm43xx_txhdr);
4014 bcm->ieee->set_security = bcm43xx_ieee80211_set_security;
4015 bcm->ieee->hard_start_xmit = bcm43xx_ieee80211_hard_start_xmit;
4020 static int __devinit bcm43xx_init_one(struct pci_dev *pdev,
4021 const struct pci_device_id *ent)
4023 struct net_device *net_dev;
4024 struct bcm43xx_private *bcm;
4027 #ifdef CONFIG_BCM947XX
4028 if ((pdev->bus->number == 0) && (pdev->device != 0x0800))
4032 #ifdef DEBUG_SINGLE_DEVICE_ONLY
4033 if (strcmp(pci_name(pdev), DEBUG_SINGLE_DEVICE_ONLY))
4037 net_dev = alloc_ieee80211softmac(sizeof(*bcm));
4040 "could not allocate ieee80211 device %s\n",
4045 /* initialize the net_device struct */
4046 SET_MODULE_OWNER(net_dev);
4047 SET_NETDEV_DEV(net_dev, &pdev->dev);
4049 net_dev->open = bcm43xx_net_open;
4050 net_dev->stop = bcm43xx_net_stop;
4051 net_dev->get_stats = bcm43xx_net_get_stats;
4052 net_dev->tx_timeout = bcm43xx_net_tx_timeout;
4053 #ifdef CONFIG_NET_POLL_CONTROLLER
4054 net_dev->poll_controller = bcm43xx_net_poll_controller;
4056 net_dev->wireless_handlers = &bcm43xx_wx_handlers_def;
4057 net_dev->irq = pdev->irq;
4058 SET_ETHTOOL_OPS(net_dev, &bcm43xx_ethtool_ops);
4060 /* initialize the bcm43xx_private struct */
4061 bcm = bcm43xx_priv(net_dev);
4062 memset(bcm, 0, sizeof(*bcm));
4063 err = bcm43xx_init_private(bcm, net_dev, pdev);
4065 goto err_free_netdev;
4067 pci_set_drvdata(pdev, net_dev);
4069 err = bcm43xx_attach_board(bcm);
4071 goto err_free_netdev;
4073 err = register_netdev(net_dev);
4075 printk(KERN_ERR PFX "Cannot register net device, "
4078 goto err_detach_board;
4081 bcm43xx_debugfs_add_device(bcm);
4088 bcm43xx_detach_board(bcm);
4090 free_ieee80211softmac(net_dev);
4094 static void __devexit bcm43xx_remove_one(struct pci_dev *pdev)
4096 struct net_device *net_dev = pci_get_drvdata(pdev);
4097 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4099 bcm43xx_debugfs_remove_device(bcm);
4100 unregister_netdev(net_dev);
4101 bcm43xx_detach_board(bcm);
4102 free_ieee80211softmac(net_dev);
4105 /* Hard-reset the chip. Do not call this directly.
4106 * Use bcm43xx_controller_restart()
4108 static void bcm43xx_chip_reset(void *_bcm)
4110 struct bcm43xx_private *bcm = _bcm;
4111 struct bcm43xx_phyinfo *phy;
4114 mutex_lock(&(bcm)->mutex);
4115 phy = bcm43xx_current_phy(bcm);
4116 err = bcm43xx_select_wireless_core(bcm, phy->type);
4117 mutex_unlock(&(bcm)->mutex);
4119 printk(KERN_ERR PFX "Controller restart%s\n",
4120 (err == 0) ? "ed" : " failed");
4123 /* Hard-reset the chip.
4124 * This can be called from interrupt or process context.
4126 void bcm43xx_controller_restart(struct bcm43xx_private *bcm, const char *reason)
4128 assert(bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED);
4129 bcm43xx_set_status(bcm, BCM43xx_STAT_RESTARTING);
4130 printk(KERN_ERR PFX "Controller RESET (%s) ...\n", reason);
4131 INIT_WORK(&bcm->restart_work, bcm43xx_chip_reset, bcm);
4132 schedule_work(&bcm->restart_work);
4137 static int bcm43xx_suspend(struct pci_dev *pdev, pm_message_t state)
4139 struct net_device *net_dev = pci_get_drvdata(pdev);
4140 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4143 dprintk(KERN_INFO PFX "Suspending...\n");
4145 netif_device_detach(net_dev);
4146 bcm->was_initialized = 0;
4147 if (bcm43xx_status(bcm) == BCM43xx_STAT_INITIALIZED) {
4148 bcm->was_initialized = 1;
4149 ieee80211softmac_stop(net_dev);
4150 err = bcm43xx_disable_interrupts_sync(bcm);
4151 if (unlikely(err)) {
4152 dprintk(KERN_ERR PFX "Suspend failed.\n");
4155 bcm->firmware_norelease = 1;
4156 bcm43xx_free_board(bcm);
4157 bcm->firmware_norelease = 0;
4159 bcm43xx_chipset_detach(bcm);
4161 pci_save_state(pdev);
4162 pci_disable_device(pdev);
4163 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4165 dprintk(KERN_INFO PFX "Device suspended.\n");
4170 static int bcm43xx_resume(struct pci_dev *pdev)
4172 struct net_device *net_dev = pci_get_drvdata(pdev);
4173 struct bcm43xx_private *bcm = bcm43xx_priv(net_dev);
4176 dprintk(KERN_INFO PFX "Resuming...\n");
4178 pci_set_power_state(pdev, 0);
4179 pci_enable_device(pdev);
4180 pci_restore_state(pdev);
4182 bcm43xx_chipset_attach(bcm);
4183 if (bcm->was_initialized)
4184 err = bcm43xx_init_board(bcm);
4186 printk(KERN_ERR PFX "Resume failed!\n");
4189 netif_device_attach(net_dev);
4191 dprintk(KERN_INFO PFX "Device resumed.\n");
4196 #endif /* CONFIG_PM */
4198 static struct pci_driver bcm43xx_pci_driver = {
4199 .name = KBUILD_MODNAME,
4200 .id_table = bcm43xx_pci_tbl,
4201 .probe = bcm43xx_init_one,
4202 .remove = __devexit_p(bcm43xx_remove_one),
4204 .suspend = bcm43xx_suspend,
4205 .resume = bcm43xx_resume,
4206 #endif /* CONFIG_PM */
4209 static int __init bcm43xx_init(void)
4211 printk(KERN_INFO KBUILD_MODNAME " driver\n");
4212 bcm43xx_debugfs_init();
4213 return pci_register_driver(&bcm43xx_pci_driver);
4216 static void __exit bcm43xx_exit(void)
4218 pci_unregister_driver(&bcm43xx_pci_driver);
4219 bcm43xx_debugfs_exit();
4222 module_init(bcm43xx_init)
4223 module_exit(bcm43xx_exit)