4 #include <linux/version.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
10 #include <net/ieee80211.h>
11 #include <net/ieee80211softmac.h>
12 #include <asm/atomic.h>
16 #include "bcm43xx_debugfs.h"
17 #include "bcm43xx_leds.h"
20 #define PFX KBUILD_MODNAME ": "
22 #define BCM43xx_SWITCH_CORE_MAX_RETRIES 50
23 #define BCM43xx_IRQWAIT_MAX_RETRIES 50
25 #define BCM43xx_IO_SIZE 8192
27 /* Active Core PCI Configuration Register. */
28 #define BCM43xx_PCICFG_ACTIVE_CORE 0x80
29 /* SPROM control register. */
30 #define BCM43xx_PCICFG_SPROMCTL 0x88
31 /* Interrupt Control PCI Configuration Register. (Only on PCI cores with rev >= 6) */
32 #define BCM43xx_PCICFG_ICR 0x94
35 #define BCM43xx_MMIO_DMA1_REASON 0x20
36 #define BCM43xx_MMIO_DMA1_IRQ_MASK 0x24
37 #define BCM43xx_MMIO_DMA2_REASON 0x28
38 #define BCM43xx_MMIO_DMA2_IRQ_MASK 0x2C
39 #define BCM43xx_MMIO_DMA3_REASON 0x30
40 #define BCM43xx_MMIO_DMA3_IRQ_MASK 0x34
41 #define BCM43xx_MMIO_DMA4_REASON 0x38
42 #define BCM43xx_MMIO_DMA4_IRQ_MASK 0x3C
43 #define BCM43xx_MMIO_STATUS_BITFIELD 0x120
44 #define BCM43xx_MMIO_STATUS2_BITFIELD 0x124
45 #define BCM43xx_MMIO_GEN_IRQ_REASON 0x128
46 #define BCM43xx_MMIO_GEN_IRQ_MASK 0x12C
47 #define BCM43xx_MMIO_RAM_CONTROL 0x130
48 #define BCM43xx_MMIO_RAM_DATA 0x134
49 #define BCM43xx_MMIO_PS_STATUS 0x140
50 #define BCM43xx_MMIO_RADIO_HWENABLED_HI 0x158
51 #define BCM43xx_MMIO_SHM_CONTROL 0x160
52 #define BCM43xx_MMIO_SHM_DATA 0x164
53 #define BCM43xx_MMIO_SHM_DATA_UNALIGNED 0x166
54 #define BCM43xx_MMIO_XMITSTAT_0 0x170
55 #define BCM43xx_MMIO_XMITSTAT_1 0x174
56 #define BCM43xx_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
57 #define BCM43xx_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
58 #define BCM43xx_MMIO_DMA1_BASE 0x200
59 #define BCM43xx_MMIO_DMA2_BASE 0x220
60 #define BCM43xx_MMIO_DMA3_BASE 0x240
61 #define BCM43xx_MMIO_DMA4_BASE 0x260
62 #define BCM43xx_MMIO_PIO1_BASE 0x300
63 #define BCM43xx_MMIO_PIO2_BASE 0x310
64 #define BCM43xx_MMIO_PIO3_BASE 0x320
65 #define BCM43xx_MMIO_PIO4_BASE 0x330
66 #define BCM43xx_MMIO_PHY_VER 0x3E0
67 #define BCM43xx_MMIO_PHY_RADIO 0x3E2
68 #define BCM43xx_MMIO_ANTENNA 0x3E8
69 #define BCM43xx_MMIO_CHANNEL 0x3F0
70 #define BCM43xx_MMIO_CHANNEL_EXT 0x3F4
71 #define BCM43xx_MMIO_RADIO_CONTROL 0x3F6
72 #define BCM43xx_MMIO_RADIO_DATA_HIGH 0x3F8
73 #define BCM43xx_MMIO_RADIO_DATA_LOW 0x3FA
74 #define BCM43xx_MMIO_PHY_CONTROL 0x3FC
75 #define BCM43xx_MMIO_PHY_DATA 0x3FE
76 #define BCM43xx_MMIO_MACFILTER_CONTROL 0x420
77 #define BCM43xx_MMIO_MACFILTER_DATA 0x422
78 #define BCM43xx_MMIO_RADIO_HWENABLED_LO 0x49A
79 #define BCM43xx_MMIO_GPIO_CONTROL 0x49C
80 #define BCM43xx_MMIO_GPIO_MASK 0x49E
81 #define BCM43xx_MMIO_TSF_0 0x632 /* core rev < 3 only */
82 #define BCM43xx_MMIO_TSF_1 0x634 /* core rev < 3 only */
83 #define BCM43xx_MMIO_TSF_2 0x636 /* core rev < 3 only */
84 #define BCM43xx_MMIO_TSF_3 0x638 /* core rev < 3 only */
85 #define BCM43xx_MMIO_POWERUP_DELAY 0x6A8
88 #define BCM43xx_SPROM_BASE 0x1000
89 #define BCM43xx_SPROM_BOARDFLAGS2 0x1c
90 #define BCM43xx_SPROM_IL0MACADDR 0x24
91 #define BCM43xx_SPROM_ET0MACADDR 0x27
92 #define BCM43xx_SPROM_ET1MACADDR 0x2a
93 #define BCM43xx_SPROM_ETHPHY 0x2d
94 #define BCM43xx_SPROM_BOARDREV 0x2e
95 #define BCM43xx_SPROM_PA0B0 0x2f
96 #define BCM43xx_SPROM_PA0B1 0x30
97 #define BCM43xx_SPROM_PA0B2 0x31
98 #define BCM43xx_SPROM_WL0GPIO0 0x32
99 #define BCM43xx_SPROM_WL0GPIO2 0x33
100 #define BCM43xx_SPROM_MAXPWR 0x34
101 #define BCM43xx_SPROM_PA1B0 0x35
102 #define BCM43xx_SPROM_PA1B1 0x36
103 #define BCM43xx_SPROM_PA1B2 0x37
104 #define BCM43xx_SPROM_IDL_TSSI_TGT 0x38
105 #define BCM43xx_SPROM_BOARDFLAGS 0x39
106 #define BCM43xx_SPROM_ANTENNA_GAIN 0x3a
107 #define BCM43xx_SPROM_VERSION 0x3f
109 /* BCM43xx_SPROM_BOARDFLAGS values */
110 #define BCM43xx_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
111 #define BCM43xx_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
112 #define BCM43xx_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
113 #define BCM43xx_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
114 #define BCM43xx_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
115 #define BCM43xx_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
116 #define BCM43xx_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
117 #define BCM43xx_BFL_ENETADM 0x0080 /* has ADMtek switch */
118 #define BCM43xx_BFL_ENETVLAN 0x0100 /* can do vlan */
119 #define BCM43xx_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
120 #define BCM43xx_BFL_NOPCI 0x0400 /* leaves PCI floating */
121 #define BCM43xx_BFL_FEM 0x0800 /* supports the Front End Module */
122 #define BCM43xx_BFL_EXTLNA 0x1000 /* has an external LNA */
123 #define BCM43xx_BFL_HGPA 0x2000 /* had high gain PA */
124 #define BCM43xx_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
125 #define BCM43xx_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
127 /* GPIO register offset, in both ChipCommon and PCI core. */
128 #define BCM43xx_GPIO_CONTROL 0x6c
131 #define BCM43xx_SHM_SHARED 0x0001
132 #define BCM43xx_SHM_WIRELESS 0x0002
133 #define BCM43xx_SHM_PCM 0x0003
134 #define BCM43xx_SHM_HWMAC 0x0004
135 #define BCM43xx_SHM_UCODE 0x0300
137 /* MacFilter offsets. */
138 #define BCM43xx_MACFILTER_SELF 0x0000
139 #define BCM43xx_MACFILTER_ASSOC 0x0003
141 /* Chipcommon registers. */
142 #define BCM43xx_CHIPCOMMON_CAPABILITIES 0x04
143 #define BCM43xx_CHIPCOMMON_PLLONDELAY 0xB0
144 #define BCM43xx_CHIPCOMMON_FREFSELDELAY 0xB4
145 #define BCM43xx_CHIPCOMMON_SLOWCLKCTL 0xB8
146 #define BCM43xx_CHIPCOMMON_SYSCLKCTL 0xC0
148 /* PCI core specific registers. */
149 #define BCM43xx_PCICORE_BCAST_ADDR 0x50
150 #define BCM43xx_PCICORE_BCAST_DATA 0x54
151 #define BCM43xx_PCICORE_SBTOPCI2 0x108
153 /* SBTOPCI2 values. */
154 #define BCM43xx_SBTOPCI2_PREFETCH 0x4
155 #define BCM43xx_SBTOPCI2_BURST 0x8
157 /* Chipcommon capabilities. */
158 #define BCM43xx_CAPABILITIES_PCTL 0x00040000
159 #define BCM43xx_CAPABILITIES_PLLMASK 0x00030000
160 #define BCM43xx_CAPABILITIES_PLLSHIFT 16
161 #define BCM43xx_CAPABILITIES_FLASHMASK 0x00000700
162 #define BCM43xx_CAPABILITIES_FLASHSHIFT 8
163 #define BCM43xx_CAPABILITIES_EXTBUSPRESENT 0x00000040
164 #define BCM43xx_CAPABILITIES_UARTGPIO 0x00000020
165 #define BCM43xx_CAPABILITIES_UARTCLOCKMASK 0x00000018
166 #define BCM43xx_CAPABILITIES_UARTCLOCKSHIFT 3
167 #define BCM43xx_CAPABILITIES_MIPSBIGENDIAN 0x00000004
168 #define BCM43xx_CAPABILITIES_NRUARTSMASK 0x00000003
171 #define BCM43xx_PCTL_IN 0xB0
172 #define BCM43xx_PCTL_OUT 0xB4
173 #define BCM43xx_PCTL_OUTENABLE 0xB8
174 #define BCM43xx_PCTL_XTAL_POWERUP 0x40
175 #define BCM43xx_PCTL_PLL_POWERDOWN 0x80
177 /* PowerControl Clock Modes */
178 #define BCM43xx_PCTL_CLK_FAST 0x00
179 #define BCM43xx_PCTL_CLK_SLOW 0x01
180 #define BCM43xx_PCTL_CLK_DYNAMIC 0x02
182 #define BCM43xx_PCTL_FORCE_SLOW 0x0800
183 #define BCM43xx_PCTL_FORCE_PLL 0x1000
184 #define BCM43xx_PCTL_DYN_XTAL 0x2000
187 #define BCM43xx_COREID_CHIPCOMMON 0x800
188 #define BCM43xx_COREID_ILINE20 0x801
189 #define BCM43xx_COREID_SDRAM 0x803
190 #define BCM43xx_COREID_PCI 0x804
191 #define BCM43xx_COREID_MIPS 0x805
192 #define BCM43xx_COREID_ETHERNET 0x806
193 #define BCM43xx_COREID_V90 0x807
194 #define BCM43xx_COREID_USB11_HOSTDEV 0x80a
195 #define BCM43xx_COREID_IPSEC 0x80b
196 #define BCM43xx_COREID_PCMCIA 0x80d
197 #define BCM43xx_COREID_EXT_IF 0x80f
198 #define BCM43xx_COREID_80211 0x812
199 #define BCM43xx_COREID_MIPS_3302 0x816
200 #define BCM43xx_COREID_USB11_HOST 0x817
201 #define BCM43xx_COREID_USB11_DEV 0x818
202 #define BCM43xx_COREID_USB20_HOST 0x819
203 #define BCM43xx_COREID_USB20_DEV 0x81a
204 #define BCM43xx_COREID_SDIO_HOST 0x81b
206 /* Core Information Registers */
207 #define BCM43xx_CIR_BASE 0xf00
208 #define BCM43xx_CIR_SBTPSFLAG (BCM43xx_CIR_BASE + 0x18)
209 #define BCM43xx_CIR_SBIMSTATE (BCM43xx_CIR_BASE + 0x90)
210 #define BCM43xx_CIR_SBINTVEC (BCM43xx_CIR_BASE + 0x94)
211 #define BCM43xx_CIR_SBTMSTATELOW (BCM43xx_CIR_BASE + 0x98)
212 #define BCM43xx_CIR_SBTMSTATEHIGH (BCM43xx_CIR_BASE + 0x9c)
213 #define BCM43xx_CIR_SBIMCONFIGLOW (BCM43xx_CIR_BASE + 0xa8)
214 #define BCM43xx_CIR_SB_ID_HI (BCM43xx_CIR_BASE + 0xfc)
216 /* Mask to get the Backplane Flag Number from SBTPSFLAG. */
217 #define BCM43xx_BACKPLANE_FLAG_NR_MASK 0x3f
219 /* SBIMCONFIGLOW values/masks. */
220 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK 0x00000007
221 #define BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_SHIFT 0
222 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK 0x00000070
223 #define BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_SHIFT 4
224 #define BCM43xx_SBIMCONFIGLOW_CONNID_MASK 0x00ff0000
225 #define BCM43xx_SBIMCONFIGLOW_CONNID_SHIFT 16
227 /* sbtmstatelow state flags */
228 #define BCM43xx_SBTMSTATELOW_RESET 0x01
229 #define BCM43xx_SBTMSTATELOW_REJECT 0x02
230 #define BCM43xx_SBTMSTATELOW_CLOCK 0x10000
231 #define BCM43xx_SBTMSTATELOW_FORCE_GATE_CLOCK 0x20000
233 /* sbtmstatehigh state flags */
234 #define BCM43xx_SBTMSTATEHIGH_SERROR 0x1
235 #define BCM43xx_SBTMSTATEHIGH_BUSY 0x4
237 /* sbimstate flags */
238 #define BCM43xx_SBIMSTATE_IB_ERROR 0x20000
239 #define BCM43xx_SBIMSTATE_TIMEOUT 0x40000
242 #define BCM43xx_PHYTYPE_A 0x00
243 #define BCM43xx_PHYTYPE_B 0x01
244 #define BCM43xx_PHYTYPE_G 0x02
247 #define BCM43xx_PHY_ILT_A_CTRL 0x0072
248 #define BCM43xx_PHY_ILT_A_DATA1 0x0073
249 #define BCM43xx_PHY_ILT_A_DATA2 0x0074
250 #define BCM43xx_PHY_G_LO_CONTROL 0x0810
251 #define BCM43xx_PHY_ILT_G_CTRL 0x0472
252 #define BCM43xx_PHY_ILT_G_DATA1 0x0473
253 #define BCM43xx_PHY_ILT_G_DATA2 0x0474
254 #define BCM43xx_PHY_A_PCTL 0x007B
255 #define BCM43xx_PHY_G_PCTL 0x0029
256 #define BCM43xx_PHY_A_CRS 0x0029
257 #define BCM43xx_PHY_RADIO_BITFIELD 0x0401
258 #define BCM43xx_PHY_G_CRS 0x0429
259 #define BCM43xx_PHY_NRSSILT_CTRL 0x0803
260 #define BCM43xx_PHY_NRSSILT_DATA 0x0804
263 #define BCM43xx_RADIOCTL_ID 0x01
266 #define BCM43xx_SBF_MAC_ENABLED 0x00000001
267 #define BCM43xx_SBF_2 0x00000002 /*FIXME: fix name*/
268 #define BCM43xx_SBF_CORE_READY 0x00000004
269 #define BCM43xx_SBF_400 0x00000400 /*FIXME: fix name*/
270 #define BCM43xx_SBF_4000 0x00004000 /*FIXME: fix name*/
271 #define BCM43xx_SBF_8000 0x00008000 /*FIXME: fix name*/
272 #define BCM43xx_SBF_XFER_REG_BYTESWAP 0x00010000
273 #define BCM43xx_SBF_MODE_NOTADHOC 0x00020000
274 #define BCM43xx_SBF_MODE_AP 0x00040000
275 #define BCM43xx_SBF_RADIOREG_LOCK 0x00080000
276 #define BCM43xx_SBF_MODE_MONITOR 0x00400000
277 #define BCM43xx_SBF_MODE_PROMISC 0x01000000
278 #define BCM43xx_SBF_PS1 0x02000000
279 #define BCM43xx_SBF_PS2 0x04000000
280 #define BCM43xx_SBF_NO_SSID_BCAST 0x08000000
281 #define BCM43xx_SBF_TIME_UPDATE 0x10000000
282 #define BCM43xx_SBF_80000000 0x80000000 /*FIXME: fix name*/
284 /* MicrocodeFlagsBitfield (addr + lo-word values?)*/
285 #define BCM43xx_UCODEFLAGS_OFFSET 0x005E
287 #define BCM43xx_UCODEFLAG_AUTODIV 0x0001
288 #define BCM43xx_UCODEFLAG_UNKBGPHY 0x0002
289 #define BCM43xx_UCODEFLAG_UNKBPHY 0x0004
290 #define BCM43xx_UCODEFLAG_UNKGPHY 0x0020
291 #define BCM43xx_UCODEFLAG_UNKPACTRL 0x0040
292 #define BCM43xx_UCODEFLAG_JAPAN 0x0080
294 /* Generic-Interrupt reasons. */
295 #define BCM43xx_IRQ_READY (1 << 0)
296 #define BCM43xx_IRQ_BEACON (1 << 1)
297 #define BCM43xx_IRQ_PS (1 << 2)
298 #define BCM43xx_IRQ_REG124 (1 << 5)
299 #define BCM43xx_IRQ_PMQ (1 << 6)
300 #define BCM43xx_IRQ_PIO_WORKAROUND (1 << 8)
301 #define BCM43xx_IRQ_XMIT_ERROR (1 << 11)
302 #define BCM43xx_IRQ_RX (1 << 15)
303 #define BCM43xx_IRQ_SCAN (1 << 16)
304 #define BCM43xx_IRQ_NOISE (1 << 18)
305 #define BCM43xx_IRQ_XMIT_STATUS (1 << 29)
307 #define BCM43xx_IRQ_ALL 0xffffffff
308 #define BCM43xx_IRQ_INITIAL (BCM43xx_IRQ_PS | \
309 BCM43xx_IRQ_REG124 | \
311 BCM43xx_IRQ_XMIT_ERROR | \
314 BCM43xx_IRQ_NOISE | \
315 BCM43xx_IRQ_XMIT_STATUS)
318 /* Initial default iw_mode */
319 #define BCM43xx_INITIAL_IWMODE IW_MODE_INFRA
322 #define BCM43xx_BUSTYPE_PCI 0
323 /* Bus type Silicone Backplane Bus. */
324 #define BCM43xx_BUSTYPE_SB 1
325 /* Bus type PCMCIA. */
326 #define BCM43xx_BUSTYPE_PCMCIA 2
328 /* Threshold values. */
329 #define BCM43xx_MIN_RTS_THRESHOLD 1U
330 #define BCM43xx_MAX_RTS_THRESHOLD 2304U
331 #define BCM43xx_DEFAULT_RTS_THRESHOLD BCM43xx_MAX_RTS_THRESHOLD
333 #define BCM43xx_DEFAULT_SHORT_RETRY_LIMIT 7
334 #define BCM43xx_DEFAULT_LONG_RETRY_LIMIT 4
336 /* Max size of a security key */
337 #define BCM43xx_SEC_KEYSIZE 16
338 /* Security algorithms. */
340 BCM43xx_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
341 BCM43xx_SEC_ALGO_WEP,
342 BCM43xx_SEC_ALGO_UNKNOWN,
343 BCM43xx_SEC_ALGO_AES,
344 BCM43xx_SEC_ALGO_WEP104,
345 BCM43xx_SEC_ALGO_TKIP,
351 #ifdef CONFIG_BCM43XX_DEBUG
352 #define assert(expr) \
354 if (unlikely(!(expr))) { \
355 printk(KERN_ERR PFX "ASSERTION FAILED (%s) at: %s:%d:%s()\n", \
356 #expr, __FILE__, __LINE__, __FUNCTION__); \
360 #define assert(expr) do { /* nothing */ } while (0)
363 /* rate limited printk(). */
367 #define printkl(f, x...) do { if (printk_ratelimit()) printk(f ,##x); } while (0)
368 /* rate limited printk() for debugging */
372 #ifdef CONFIG_BCM43XX_DEBUG
373 # define dprintkl printkl
375 # define dprintkl(f, x...) do { /* nothing */ } while (0)
378 /* Helper macro for if branches.
379 * An if branch marked with this macro is only taken in DEBUG mode.
381 * if (DEBUG_ONLY(foo == bar)) {
384 * In DEBUG mode, the branch will be taken if (foo == bar).
385 * In non-DEBUG mode, the branch will never be taken.
390 #ifdef CONFIG_BCM43XX_DEBUG
391 # define DEBUG_ONLY(x) (x)
393 # define DEBUG_ONLY(x) 0
396 /* debugging printk() */
400 #ifdef CONFIG_BCM43XX_DEBUG
401 # define dprintk(f, x...) do { printk(f ,##x); } while (0)
403 # define dprintk(f, x...) do { /* nothing */ } while (0)
409 struct bcm43xx_dmaring;
410 struct bcm43xx_pioqueue;
412 struct bcm43xx_initval {
416 } __attribute__((__packed__));
418 /* Values for bcm430x_sprominfo.locale */
420 BCM43xx_LOCALE_WORLD = 0,
421 BCM43xx_LOCALE_THAILAND,
422 BCM43xx_LOCALE_ISRAEL,
423 BCM43xx_LOCALE_JORDAN,
424 BCM43xx_LOCALE_CHINA,
425 BCM43xx_LOCALE_JAPAN,
426 BCM43xx_LOCALE_USA_CANADA_ANZ,
427 BCM43xx_LOCALE_EUROPE,
428 BCM43xx_LOCALE_USA_LOW,
429 BCM43xx_LOCALE_JAPAN_HIGH,
434 #define BCM43xx_SPROM_SIZE 64 /* in 16-bit words. */
435 struct bcm43xx_sprominfo {
460 u8 idle_tssi_tgt_aphy;
461 u8 idle_tssi_tgt_bgphy;
463 u16 antennagain_aphy;
464 u16 antennagain_bgphy;
467 /* Value pair to measure the LocalOscillator. */
468 struct bcm43xx_lopair {
473 #define BCM43xx_LO_COUNT (14*4)
475 struct bcm43xx_phyinfo {
480 u16 antenna_diversity;
486 is_locked:1, /* used in bcm43xx_phy_{un}lock() */
487 dyn_tssi_tbl:1; /* used in bcm43xx_phy_init_tssi2dbm_table() */
488 /* LO Measurement Data.
489 * Use bcm43xx_get_lopair() to get a value.
491 struct bcm43xx_lopair *_lo_pairs;
493 /* TSSI to dBm table in use */
495 /* idle TSSI value */
498 /* Values from bcm43xx_calc_loopback_gain() */
499 u16 loopback_gain[2];
501 /* PHY lock for core.rev < 3
502 * This lock is only used by bcm43xx_phy_{un}lock()
508 struct bcm43xx_radioinfo {
513 /* Desired TX power in dBm Q5.2 */
515 /* TX Power control values. */
530 /* Current Interference Mitigation mode */
532 /* Stack of saved values from the Interference Mitigation code.
533 * Each value in the stack is layed out as follows:
535 * bit 12-15: register ID
537 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
539 #define BCM43xx_INTERFSTACK_SIZE 26
540 u32 interfstack[BCM43xx_INTERFSTACK_SIZE];
542 /* Saved values from the NRSSI Slope calculation */
545 /* In memory nrssi lookup table. */
548 /* current channel */
557 /* ACI (adjacent channel interference) flags. */
559 aci_wlan_automatic:1,
563 /* Data structures for DMA transmission, per 80211 core. */
565 struct bcm43xx_dmaring *tx_ring0;
566 struct bcm43xx_dmaring *tx_ring1;
567 struct bcm43xx_dmaring *tx_ring2;
568 struct bcm43xx_dmaring *tx_ring3;
569 struct bcm43xx_dmaring *rx_ring0;
570 struct bcm43xx_dmaring *rx_ring1; /* only available on core.rev < 5 */
573 /* Data structures for PIO transmission, per 80211 core. */
575 struct bcm43xx_pioqueue *queue0;
576 struct bcm43xx_pioqueue *queue1;
577 struct bcm43xx_pioqueue *queue2;
578 struct bcm43xx_pioqueue *queue3;
581 #define BCM43xx_MAX_80211_CORES 2
583 #ifdef CONFIG_BCM947XX
584 #define core_offset(bcm) (bcm)->current_core_offset
586 #define core_offset(bcm) 0
589 /* Generic information about a core. */
590 struct bcm43xx_coreinfo {
594 /** core_id ID number */
596 /** core_rev revision number */
598 /** Index number for _switch_core() */
602 /* Additional information for each 80211 core. */
603 struct bcm43xx_coreinfo_80211 {
605 struct bcm43xx_phyinfo phy;
607 struct bcm43xx_radioinfo radio;
610 struct bcm43xx_dma dma;
612 struct bcm43xx_pio pio;
616 /* Context information for a noise calculation (Link Quality). */
617 struct bcm43xx_noise_calculation {
618 struct bcm43xx_coreinfo *core_at_start;
620 u8 calculation_running:1;
625 struct bcm43xx_stats {
628 struct iw_statistics wstats;
629 /* Store the last TX/RX times here for updating the leds. */
630 unsigned long last_tx;
631 unsigned long last_rx;
639 struct bcm43xx_private {
640 struct ieee80211_device *ieee;
641 struct ieee80211softmac_device *softmac;
643 struct net_device *net_dev;
644 struct pci_dev *pci_dev;
647 void __iomem *mmio_addr;
648 unsigned int mmio_len;
650 /* Do not use the lock directly. Use the bcm43xx_lock* helper
651 * functions, to be MMIO-safe. */
654 /* Driver status flags. */
655 u32 initialized:1, /* init_board() succeed */
656 was_initialized:1, /* for PCI suspend/resume. */
657 shutting_down:1, /* free_board() in progress */
658 __using_pio:1, /* Internal, use bcm43xx_using_pio(). */
659 bad_frames_preempt:1, /* Use "Bad Frames Preemption" (default off) */
660 reg124_set_0x4:1, /* Some variable to keep track of IRQ stuff. */
661 powersaving:1, /* TRUE if we are in PowerSaving mode. FALSE otherwise. */
662 short_preamble:1, /* TRUE, if short preamble is enabled. */
663 firmware_norelease:1; /* Do not release the firmware. Used on suspend. */
665 struct bcm43xx_stats stats;
667 /* Bus type we are connected to.
668 * This is currently always BCM43xx_BUSTYPE_PCI
680 struct bcm43xx_sprominfo sprom;
681 #define BCM43xx_NR_LEDS 4
682 struct bcm43xx_led leds[BCM43xx_NR_LEDS];
684 /* The currently active core. */
685 struct bcm43xx_coreinfo *current_core;
686 #ifdef CONFIG_BCM947XX
687 /** current core memory offset */
688 u32 current_core_offset;
690 struct bcm43xx_coreinfo *active_80211_core;
691 /* coreinfo structs for all possible cores follow.
692 * Note that a core might not exist.
693 * So check the coreinfo flags before using it.
695 struct bcm43xx_coreinfo core_chipcommon;
696 struct bcm43xx_coreinfo core_pci;
697 struct bcm43xx_coreinfo core_80211[ BCM43xx_MAX_80211_CORES ];
698 /* Additional information, specific to the 80211 cores. */
699 struct bcm43xx_coreinfo_80211 core_80211_ext[ BCM43xx_MAX_80211_CORES ];
700 /* Index of the current 80211 core. If current_core is not
701 * an 80211 core, this is -1.
703 int current_80211_core_idx;
704 /* Number of available 80211 cores. */
705 int nr_80211_available;
707 u32 chipcommon_capabilities;
709 /* Reason code of the last interrupt. */
712 /* saved irq enable/disable state bitfield. */
714 /* Link Quality calculation context. */
715 struct bcm43xx_noise_calculation noisecalc;
717 /* Threshold values. */
718 //TODO: The RTS thr has to be _used_. Currently, it is only set via WX.
721 /* Interrupt Service Routine tasklet (bottom-half) */
722 struct tasklet_struct isr_tasklet;
725 struct timer_list periodic_tasks;
726 unsigned int periodic_state;
728 struct work_struct restart_work;
730 /* Informational stuff. */
731 char nick[IW_ESSID_MAX_SIZE + 1];
733 /* encryption/decryption */
735 struct bcm43xx_key key[54];
739 const struct firmware *ucode;
740 const struct firmware *pcm;
741 const struct firmware *initvals0;
742 const struct firmware *initvals1;
744 /* Debugging stuff follows. */
745 #ifdef CONFIG_BCM43XX_DEBUG
746 struct bcm43xx_dfsentry *dfsentry;
750 /* bcm43xx_(un)lock() protect struct bcm43xx_private.
751 * Note that _NO_ MMIO writes are allowed. If you want to
752 * write to the device through MMIO in the critical section, use
753 * the *_mmio lock functions.
754 * MMIO read-access is allowed, though.
756 #define bcm43xx_lock(bcm, flags) spin_lock_irqsave(&(bcm)->_lock, flags)
757 #define bcm43xx_unlock(bcm, flags) spin_unlock_irqrestore(&(bcm)->_lock, flags)
758 /* bcm43xx_(un)lock_mmio() protect struct bcm43xx_private and MMIO.
759 * MMIO write-access to the device is allowed.
760 * All MMIO writes are flushed on unlock, so it is guaranteed to not
761 * interfere with other threads writing MMIO registers.
763 #define bcm43xx_lock_mmio(bcm, flags) bcm43xx_lock(bcm, flags)
764 #define bcm43xx_unlock_mmio(bcm, flags) do { mmiowb(); bcm43xx_unlock(bcm, flags); } while (0)
767 struct bcm43xx_private * bcm43xx_priv(struct net_device *dev)
769 return ieee80211softmac_priv(dev);
775 struct bcm43xx_private * dev_to_bcm(struct device *dev)
777 struct net_device *net_dev;
778 struct bcm43xx_private *bcm;
780 net_dev = dev_get_drvdata(dev);
781 bcm = bcm43xx_priv(net_dev);
787 /* Helper function, which returns a boolean.
788 * TRUE, if PIO is used; FALSE, if DMA is used.
790 #if defined(CONFIG_BCM43XX_DMA) && defined(CONFIG_BCM43XX_PIO)
792 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
794 return bcm->__using_pio;
796 #elif defined(CONFIG_BCM43XX_DMA)
798 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
802 #elif defined(CONFIG_BCM43XX_PIO)
804 int bcm43xx_using_pio(struct bcm43xx_private *bcm)
809 # error "Using neither DMA nor PIO? Confused..."
812 /* Helper functions to access data structures private to the 80211 cores.
813 * Note that we _must_ have an 80211 core mapped when calling
814 * any of these functions.
817 struct bcm43xx_pio * bcm43xx_current_pio(struct bcm43xx_private *bcm)
819 assert(bcm43xx_using_pio(bcm));
820 assert(bcm->current_80211_core_idx >= 0);
821 assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
822 return &(bcm->core_80211_ext[bcm->current_80211_core_idx].pio);
825 struct bcm43xx_dma * bcm43xx_current_dma(struct bcm43xx_private *bcm)
827 assert(!bcm43xx_using_pio(bcm));
828 assert(bcm->current_80211_core_idx >= 0);
829 assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
830 return &(bcm->core_80211_ext[bcm->current_80211_core_idx].dma);
833 struct bcm43xx_phyinfo * bcm43xx_current_phy(struct bcm43xx_private *bcm)
835 assert(bcm->current_80211_core_idx >= 0);
836 assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
837 return &(bcm->core_80211_ext[bcm->current_80211_core_idx].phy);
840 struct bcm43xx_radioinfo * bcm43xx_current_radio(struct bcm43xx_private *bcm)
842 assert(bcm->current_80211_core_idx >= 0);
843 assert(bcm->current_80211_core_idx < BCM43xx_MAX_80211_CORES);
844 return &(bcm->core_80211_ext[bcm->current_80211_core_idx].radio);
847 /* Are we running in init_board() context? */
849 int bcm43xx_is_initializing(struct bcm43xx_private *bcm)
851 if (bcm->initialized)
853 if (bcm->shutting_down)
859 struct bcm43xx_lopair * bcm43xx_get_lopair(struct bcm43xx_phyinfo *phy,
860 u16 radio_attenuation,
861 u16 baseband_attenuation)
863 return phy->_lo_pairs + (radio_attenuation + 14 * (baseband_attenuation / 2));
868 u16 bcm43xx_read16(struct bcm43xx_private *bcm, u16 offset)
870 return ioread16(bcm->mmio_addr + core_offset(bcm) + offset);
874 void bcm43xx_write16(struct bcm43xx_private *bcm, u16 offset, u16 value)
876 iowrite16(value, bcm->mmio_addr + core_offset(bcm) + offset);
880 u32 bcm43xx_read32(struct bcm43xx_private *bcm, u16 offset)
882 return ioread32(bcm->mmio_addr + core_offset(bcm) + offset);
886 void bcm43xx_write32(struct bcm43xx_private *bcm, u16 offset, u32 value)
888 iowrite32(value, bcm->mmio_addr + core_offset(bcm) + offset);
892 int bcm43xx_pci_read_config16(struct bcm43xx_private *bcm, int offset, u16 *value)
894 return pci_read_config_word(bcm->pci_dev, offset, value);
898 int bcm43xx_pci_read_config32(struct bcm43xx_private *bcm, int offset, u32 *value)
900 return pci_read_config_dword(bcm->pci_dev, offset, value);
904 int bcm43xx_pci_write_config16(struct bcm43xx_private *bcm, int offset, u16 value)
906 return pci_write_config_word(bcm->pci_dev, offset, value);
910 int bcm43xx_pci_write_config32(struct bcm43xx_private *bcm, int offset, u32 value)
912 return pci_write_config_dword(bcm->pci_dev, offset, value);
915 /** Limit a value between two limits */
919 #define limit_value(value, min, max) \
921 typeof(value) __value = (value); \
922 typeof(value) __min = (min); \
923 typeof(value) __max = (max); \
924 if (__value < __min) \
926 else if (__value > __max) \
931 /** Helpers to print MAC addresses. */
932 #define BCM43xx_MACFMT "%02x:%02x:%02x:%02x:%02x:%02x"
933 #define BCM43xx_MACARG(x) ((u8*)(x))[0], ((u8*)(x))[1], \
934 ((u8*)(x))[2], ((u8*)(x))[3], \
935 ((u8*)(x))[4], ((u8*)(x))[5]
937 #endif /* BCM43xx_H_ */