4 #include <linux/types.h>
9 /*** PHY Registers ***/
12 #define B43_PHYROUTE_OFDM_GPHY 0x400
13 #define B43_PHYROUTE_EXT_GPHY 0x800
16 #define B43_PHY_BASE(reg) (reg)
17 /* OFDM (A) registers of a G-PHY */
18 #define B43_PHY_OFDM(reg) ((reg) | B43_PHYROUTE_OFDM_GPHY)
19 /* Extended G-PHY registers */
20 #define B43_PHY_EXTG(reg) ((reg) | B43_PHYROUTE_EXT_GPHY)
22 /* OFDM (A) PHY Registers */
23 #define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
24 #define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */
25 #define B43_PHY_BBANDCFG_RXANT 0x180 /* RX Antenna selection */
26 #define B43_PHY_BBANDCFG_RXANT_SHIFT 7
27 #define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
28 #define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 */
29 #define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
30 #define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
31 #define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
32 #define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
33 #define B43_PHY_CRS0_EN 0x4000
34 #define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30)
35 #define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */
36 #define B43_PHY_ANTDWELL_AUTODIV1 0x0100 /* Automatic RX diversity start antenna */
37 #define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */
38 #define B43_PHY_ENCORE_EN 0x0200 /* Encore enable */
39 #define B43_PHY_LMS B43_PHY_OFDM(0x55)
40 #define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */
41 #define B43_PHY_OFDM61_10 0x0010 /* FIXME rename */
42 #define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */
43 #define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */
44 #define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */
45 #define B43_PHY_OTABLEOFF 0x03FF /* OFDM table offset (see below) */
46 #define B43_PHY_OTABLENR 0xFC00 /* OFDM table number (see below) */
47 #define B43_PHY_OTABLENR_SHIFT 10
48 #define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */
49 #define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */
50 #define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */
51 #define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */
52 #define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B)
53 #define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */
54 #define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */
55 #define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */
56 #define B43_PHY_ANTWRSETT_ARXDIV 0x2000 /* Automatic RX diversity enabled */
57 #define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */
58 #define B43_PHY_OFDM9B B43_PHY_OFDM(0x9B) /* FIXME rename */
59 #define B43_PHY_N1P1GAIN B43_PHY_OFDM(0xA0)
60 #define B43_PHY_P1P2GAIN B43_PHY_OFDM(0xA1)
61 #define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2)
62 #define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3)
63 #define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4)
64 #define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */
65 #define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */
66 #define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
67 #define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9)
68 #define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA)
69 #define B43_PHY_DIVP1P2GAIN B43_PHY_OFDM(0xAB)
70 #define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */
71 #define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */
72 #define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (rev 1 only) */
73 #define B43_PHY_CRSTHRES2_R1 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (rev 1 only) */
74 #define B43_PHY_TSSIP_LTBASE B43_PHY_OFDM(0x380) /* TSSI power lookup table base */
75 #define B43_PHY_DC_LTBASE B43_PHY_OFDM(0x3A0) /* DC lookup table base */
76 #define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */
78 /* CCK (B) PHY Registers */
79 #define B43_PHY_VERSION_CCK B43_PHY_BASE(0x00) /* Versioning register for B-PHY */
80 #define B43_PHY_CCKBBANDCFG B43_PHY_BASE(0x01) /* Contains antenna 0/1 control bit */
81 #define B43_PHY_PGACTL B43_PHY_BASE(0x15) /* PGA control */
82 #define B43_PHY_PGACTL_LPF 0x1000 /* Low pass filter (?) */
83 #define B43_PHY_PGACTL_LOWBANDW 0x0040 /* Low bandwidth flag */
84 #define B43_PHY_PGACTL_UNKNOWN 0xEFA0
85 #define B43_PHY_FBCTL1 B43_PHY_BASE(0x18) /* Frequency bandwidth control 1 */
86 #define B43_PHY_ITSSI B43_PHY_BASE(0x29) /* Idle TSSI */
87 #define B43_PHY_LO_LEAKAGE B43_PHY_BASE(0x2D) /* Measured LO leakage */
88 #define B43_PHY_ENERGY B43_PHY_BASE(0x33) /* Energy */
89 #define B43_PHY_SYNCCTL B43_PHY_BASE(0x35)
90 #define B43_PHY_FBCTL2 B43_PHY_BASE(0x38) /* Frequency bandwidth control 2 */
91 #define B43_PHY_DACCTL B43_PHY_BASE(0x60) /* DAC control */
92 #define B43_PHY_RCCALOVER B43_PHY_BASE(0x78) /* RC calibration override */
94 /* Extended G-PHY Registers */
95 #define B43_PHY_CLASSCTL B43_PHY_EXTG(0x02) /* Classify control */
96 #define B43_PHY_GTABCTL B43_PHY_EXTG(0x03) /* G-PHY table control (see below) */
97 #define B43_PHY_GTABOFF 0x03FF /* G-PHY table offset (see below) */
98 #define B43_PHY_GTABNR 0xFC00 /* G-PHY table number (see below) */
99 #define B43_PHY_GTABNR_SHIFT 10
100 #define B43_PHY_GTABDATA B43_PHY_EXTG(0x04) /* G-PHY table data */
101 #define B43_PHY_LO_MASK B43_PHY_EXTG(0x0F) /* Local Oscillator control mask */
102 #define B43_PHY_LO_CTL B43_PHY_EXTG(0x10) /* Local Oscillator control */
103 #define B43_PHY_RFOVER B43_PHY_EXTG(0x11) /* RF override */
104 #define B43_PHY_RFOVERVAL B43_PHY_EXTG(0x12) /* RF override value */
105 #define B43_PHY_RFOVERVAL_EXTLNA 0x8000
106 #define B43_PHY_RFOVERVAL_LNA 0x7000
107 #define B43_PHY_RFOVERVAL_LNA_SHIFT 12
108 #define B43_PHY_RFOVERVAL_PGA 0x0F00
109 #define B43_PHY_RFOVERVAL_PGA_SHIFT 8
110 #define B43_PHY_RFOVERVAL_UNK 0x0010 /* Unknown, always set. */
111 #define B43_PHY_RFOVERVAL_TRSWRX 0x00E0
112 #define B43_PHY_RFOVERVAL_BW 0x0003 /* Bandwidth flags */
113 #define B43_PHY_RFOVERVAL_BW_LPF 0x0001 /* Low Pass Filter */
114 #define B43_PHY_RFOVERVAL_BW_LBW 0x0002 /* Low Bandwidth (when set), high when unset */
115 #define B43_PHY_ANALOGOVER B43_PHY_EXTG(0x14) /* Analog override */
116 #define B43_PHY_ANALOGOVERVAL B43_PHY_EXTG(0x15) /* Analog override value */
118 /*** OFDM table numbers ***/
119 #define B43_OFDMTAB(number, offset) (((number) << B43_PHY_OTABLENR_SHIFT) | (offset))
120 #define B43_OFDMTAB_AGC1 B43_OFDMTAB(0x00, 0)
121 #define B43_OFDMTAB_GAIN0 B43_OFDMTAB(0x00, 0)
122 #define B43_OFDMTAB_GAINX B43_OFDMTAB(0x01, 0) //TODO rename
123 #define B43_OFDMTAB_GAIN1 B43_OFDMTAB(0x01, 4)
124 #define B43_OFDMTAB_AGC3 B43_OFDMTAB(0x02, 0)
125 #define B43_OFDMTAB_GAIN2 B43_OFDMTAB(0x02, 3)
126 #define B43_OFDMTAB_LNAHPFGAIN1 B43_OFDMTAB(0x03, 0)
127 #define B43_OFDMTAB_WRSSI B43_OFDMTAB(0x04, 0)
128 #define B43_OFDMTAB_LNAHPFGAIN2 B43_OFDMTAB(0x04, 0)
129 #define B43_OFDMTAB_NOISESCALE B43_OFDMTAB(0x05, 0)
130 #define B43_OFDMTAB_AGC2 B43_OFDMTAB(0x06, 0)
131 #define B43_OFDMTAB_ROTOR B43_OFDMTAB(0x08, 0)
132 #define B43_OFDMTAB_ADVRETARD B43_OFDMTAB(0x09, 0)
133 #define B43_OFDMTAB_DAC B43_OFDMTAB(0x0C, 0)
134 #define B43_OFDMTAB_DC B43_OFDMTAB(0x0E, 7)
135 #define B43_OFDMTAB_PWRDYN2 B43_OFDMTAB(0x0E, 12)
136 #define B43_OFDMTAB_LNAGAIN B43_OFDMTAB(0x0E, 13)
137 #define B43_OFDMTAB_UNKNOWN_0F B43_OFDMTAB(0x0F, 0) //TODO rename
138 #define B43_OFDMTAB_UNKNOWN_APHY B43_OFDMTAB(0x0F, 7) //TODO rename
139 #define B43_OFDMTAB_LPFGAIN B43_OFDMTAB(0x0F, 12)
140 #define B43_OFDMTAB_RSSI B43_OFDMTAB(0x10, 0)
141 #define B43_OFDMTAB_UNKNOWN_11 B43_OFDMTAB(0x11, 4) //TODO rename
142 #define B43_OFDMTAB_AGC1_R1 B43_OFDMTAB(0x13, 0)
143 #define B43_OFDMTAB_GAINX_R1 B43_OFDMTAB(0x14, 0) //TODO remove!
144 #define B43_OFDMTAB_MINSIGSQ B43_OFDMTAB(0x14, 0)
145 #define B43_OFDMTAB_AGC3_R1 B43_OFDMTAB(0x15, 0)
146 #define B43_OFDMTAB_WRSSI_R1 B43_OFDMTAB(0x15, 4)
147 #define B43_OFDMTAB_TSSI B43_OFDMTAB(0x15, 0)
148 #define B43_OFDMTAB_DACRFPABB B43_OFDMTAB(0x16, 0)
149 #define B43_OFDMTAB_DACOFF B43_OFDMTAB(0x17, 0)
150 #define B43_OFDMTAB_DCBIAS B43_OFDMTAB(0x18, 0)
152 u16 b43_ofdmtab_read16(struct b43_wldev *dev, u16 table, u16 offset);
153 void b43_ofdmtab_write16(struct b43_wldev *dev, u16 table,
154 u16 offset, u16 value);
155 u32 b43_ofdmtab_read32(struct b43_wldev *dev, u16 table, u16 offset);
156 void b43_ofdmtab_write32(struct b43_wldev *dev, u16 table,
157 u16 offset, u32 value);
159 /*** G-PHY table numbers */
160 #define B43_GTAB(number, offset) (((number) << B43_PHY_GTABNR_SHIFT) | (offset))
161 #define B43_GTAB_NRSSI B43_GTAB(0x00, 0)
162 #define B43_GTAB_TRFEMW B43_GTAB(0x0C, 0x120)
163 #define B43_GTAB_ORIGTR B43_GTAB(0x2E, 0x298)
165 u16 b43_gtab_read(struct b43_wldev *dev, u16 table, u16 offset); //TODO implement
166 void b43_gtab_write(struct b43_wldev *dev, u16 table, u16 offset, u16 value); //TODO implement
168 #define B43_DEFAULT_CHANNEL_A 36
169 #define B43_DEFAULT_CHANNEL_BG 6
172 B43_ANTENNA0, /* Antenna 0 */
173 B43_ANTENNA1, /* Antenna 0 */
174 B43_ANTENNA_AUTO1, /* Automatic, starting with antenna 1 */
175 B43_ANTENNA_AUTO0, /* Automatic, starting with antenna 0 */
177 B43_ANTENNA_AUTO = B43_ANTENNA_AUTO0,
178 B43_ANTENNA_DEFAULT = B43_ANTENNA_AUTO,
183 B43_INTERFMODE_NONWLAN,
184 B43_INTERFMODE_MANUALWLAN,
185 B43_INTERFMODE_AUTOWLAN,
188 /* Masks for the different PHY versioning registers. */
189 #define B43_PHYVER_ANALOG 0xF000
190 #define B43_PHYVER_ANALOG_SHIFT 12
191 #define B43_PHYVER_TYPE 0x0F00
192 #define B43_PHYVER_TYPE_SHIFT 8
193 #define B43_PHYVER_VERSION 0x00FF
195 void b43_raw_phy_lock(struct b43_wldev *dev);
196 #define b43_phy_lock(dev, flags) \
198 local_irq_save(flags); \
199 b43_raw_phy_lock(dev); \
201 void b43_raw_phy_unlock(struct b43_wldev *dev);
202 #define b43_phy_unlock(dev, flags) \
204 b43_raw_phy_unlock(dev); \
205 local_irq_restore(flags); \
208 u16 b43_phy_read(struct b43_wldev *dev, u16 offset);
209 void b43_phy_write(struct b43_wldev *dev, u16 offset, u16 val);
211 int b43_phy_init_tssi2dbm_table(struct b43_wldev *dev);
213 void b43_phy_early_init(struct b43_wldev *dev);
214 int b43_phy_init(struct b43_wldev *dev);
216 void b43_set_rx_antenna(struct b43_wldev *dev, int antenna);
218 void b43_phy_xmitpower(struct b43_wldev *dev);
219 void b43_gphy_dc_lt_init(struct b43_wldev *dev);
221 /* Returns the boolean whether the board has HardwarePowerControl */
222 bool b43_has_hardware_pctl(struct b43_phy *phy);
223 /* Returns the boolean whether "TX Magnification" is enabled. */
224 #define has_tx_magnification(phy) \
225 (((phy)->rev >= 2) && \
226 ((phy)->radio_ver == 0x2050) && \
227 ((phy)->radio_rev == 8))
228 /* Card uses the loopback gain stuff */
229 #define has_loopback_gain(phy) \
230 (((phy)->rev > 1) || ((phy)->gmode))
232 /* Radio Attenuation (RF Attenuation) */
234 u8 att; /* Attenuation value */
235 bool with_padmix; /* Flag, PAD Mixer enabled. */
237 struct b43_rfatt_list {
238 /* Attenuation values list */
239 const struct b43_rfatt *list;
241 /* Minimum/Maximum attenuation values */
246 /* Baseband Attenuation */
248 u8 att; /* Attenuation value */
250 struct b43_bbatt_list {
251 /* Attenuation values list */
252 const struct b43_bbatt *list;
254 /* Minimum/Maximum attenuation values */
259 /* tx_control bits. */
260 #define B43_TXCTL_PA3DB 0x40 /* PA Gain 3dB */
261 #define B43_TXCTL_PA2DB 0x20 /* PA Gain 2dB */
262 #define B43_TXCTL_TXMIX 0x10 /* TX Mixer Gain */
264 /* Write BasebandAttenuation value to the device. */
265 void b43_phy_set_baseband_attenuation(struct b43_wldev *dev,
266 u16 baseband_attenuation);
268 extern const u8 b43_radio_channel_codes_bg[];
270 void b43_radio_lock(struct b43_wldev *dev);
271 void b43_radio_unlock(struct b43_wldev *dev);
273 u16 b43_radio_read16(struct b43_wldev *dev, u16 offset);
274 void b43_radio_write16(struct b43_wldev *dev, u16 offset, u16 val);
276 u16 b43_radio_init2050(struct b43_wldev *dev);
277 void b43_radio_init2060(struct b43_wldev *dev);
279 void b43_radio_turn_on(struct b43_wldev *dev);
280 void b43_radio_turn_off(struct b43_wldev *dev, bool force);
282 int b43_radio_selectchannel(struct b43_wldev *dev, u8 channel,
283 int synthetic_pu_workaround);
285 u8 b43_radio_aci_detect(struct b43_wldev *dev, u8 channel);
286 u8 b43_radio_aci_scan(struct b43_wldev *dev);
288 int b43_radio_set_interference_mitigation(struct b43_wldev *dev, int mode);
290 void b43_calc_nrssi_slope(struct b43_wldev *dev);
291 void b43_calc_nrssi_threshold(struct b43_wldev *dev);
292 s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset);
293 void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val);
294 void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val);
295 void b43_nrssi_mem_update(struct b43_wldev *dev);
297 void b43_radio_set_tx_iq(struct b43_wldev *dev);
298 u16 b43_radio_calibrationvalue(struct b43_wldev *dev);
300 void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
301 int *_bbatt, int *_rfatt);
303 void b43_set_txpower_g(struct b43_wldev *dev,
304 const struct b43_bbatt *bbatt,
305 const struct b43_rfatt *rfatt, u8 tx_control);
307 #endif /* B43_PHY_H_ */