2 * Copyright (c) 2008, Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 /* Implementation of the main "ATH" layer. */
22 static int ath_outdoor; /* enable outdoor use */
24 static const u8 ath_bcast_mac[ETH_ALEN] =
25 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
27 static u32 ath_chainmask_sel_up_rssi_thres =
28 ATH_CHAINMASK_SEL_UP_RSSI_THRES;
29 static u32 ath_chainmask_sel_down_rssi_thres =
30 ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
31 static u32 ath_chainmask_sel_period =
32 ATH_CHAINMASK_SEL_TIMEOUT;
34 /* return bus cachesize in 4B word units */
36 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
40 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
44 * This check was put in to avoid "unplesant" consequences if
45 * the bootrom has not fully initialized all PCI devices.
46 * Sometimes the cache line size register is not set
50 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
54 * Set current operating mode
56 * This function initializes and fills the rate table in the ATH object based
57 * on the operating mode. The blink rates are also set up here, although
58 * they have been superceeded by the ath_led module.
61 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
63 const struct ath9k_rate_table *rt;
66 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
67 rt = sc->sc_rates[mode];
70 for (i = 0; i < rt->rateCount; i++)
71 sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
73 memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
74 for (i = 0; i < 256; i++) {
75 u8 ix = rt->rateCodeToIndex[i];
80 sc->sc_hwmap[i].ieeerate =
81 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
82 sc->sc_hwmap[i].rateKbps = rt->info[ix].rateKbps;
84 if (rt->info[ix].shortPreamble ||
85 rt->info[ix].phy == PHY_OFDM) {
86 /* XXX: Handle this */
89 /* NB: this uses the last entry if the rate isn't found */
90 /* XXX beware of overlow */
93 sc->sc_curmode = mode;
95 * All protection frames are transmited at 2Mb/s for
96 * 11g, otherwise at 1Mb/s.
97 * XXX select protection rate index from rate table.
99 sc->sc_protrix = (mode == WIRELESS_MODE_11g ? 1 : 0);
100 /* rate index used to send mgt frames */
101 sc->sc_minrateix = 0;
107 * Based on the wireless mode passed in, the rate table in the ATH object
108 * is set to the mode specific rate table. This also calls the callback
109 * function to set the rate in the protocol layer object.
112 static int ath_rate_setup(struct ath_softc *sc, enum wireless_mode mode)
114 struct ath_hal *ah = sc->sc_ah;
115 const struct ath9k_rate_table *rt;
118 case WIRELESS_MODE_11a:
120 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11A);
122 case WIRELESS_MODE_11b:
124 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11B);
126 case WIRELESS_MODE_11g:
128 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11G);
130 case WIRELESS_MODE_11NA_HT20:
132 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11NA_HT20);
134 case WIRELESS_MODE_11NG_HT20:
136 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11NG_HT20);
138 case WIRELESS_MODE_11NA_HT40PLUS:
140 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11NA_HT40PLUS);
142 case WIRELESS_MODE_11NA_HT40MINUS:
144 ath9k_hw_getratetable(ah,
145 ATH9K_MODE_SEL_11NA_HT40MINUS);
147 case WIRELESS_MODE_11NG_HT40PLUS:
149 ath9k_hw_getratetable(ah, ATH9K_MODE_SEL_11NG_HT40PLUS);
151 case WIRELESS_MODE_11NG_HT40MINUS:
153 ath9k_hw_getratetable(ah,
154 ATH9K_MODE_SEL_11NG_HT40MINUS);
157 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid mode %u\n",
161 rt = sc->sc_rates[mode];
165 /* setup rate set in 802.11 protocol layer */
166 ath_setup_rate(sc, mode, NORMAL_RATE, rt);
172 * Set up channel list
174 static int ath_setup_channels(struct ath_softc *sc)
176 struct ath_hal *ah = sc->sc_ah;
177 int nchan, i, a = 0, b = 0;
178 u8 regclassids[ATH_REGCLASSIDS_MAX];
180 struct ieee80211_supported_band *band_2ghz;
181 struct ieee80211_supported_band *band_5ghz;
182 struct ieee80211_channel *chan_2ghz;
183 struct ieee80211_channel *chan_5ghz;
184 struct ath9k_channel *c;
186 /* Fill in ah->ah_channels */
187 if (!ath9k_regd_init_channels(ah,
197 u32 rd = ah->ah_currentRD;
199 DPRINTF(sc, ATH_DBG_FATAL,
200 "%s: unable to collect channel list; "
201 "regdomain likely %u country code %u\n",
202 __func__, rd, CTRY_DEFAULT);
206 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
207 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
208 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
209 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
211 for (i = 0; i < nchan; i++) {
212 c = &ah->ah_channels[i];
213 if (IS_CHAN_2GHZ(c)) {
214 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
215 chan_2ghz[a].center_freq = c->channel;
216 chan_2ghz[a].max_power = c->maxTxPower;
218 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
219 chan_2ghz[a].flags |=
220 IEEE80211_CHAN_NO_IBSS;
221 if (c->channelFlags & CHANNEL_PASSIVE)
222 chan_2ghz[a].flags |=
223 IEEE80211_CHAN_PASSIVE_SCAN;
225 band_2ghz->n_channels = ++a;
227 DPRINTF(sc, ATH_DBG_CONFIG,
228 "%s: 2MHz channel: %d, "
229 "channelFlags: 0x%x\n",
233 } else if (IS_CHAN_5GHZ(c)) {
234 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
235 chan_5ghz[b].center_freq = c->channel;
236 chan_5ghz[b].max_power = c->maxTxPower;
238 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
239 chan_5ghz[b].flags |=
240 IEEE80211_CHAN_NO_IBSS;
241 if (c->channelFlags & CHANNEL_PASSIVE)
242 chan_5ghz[b].flags |=
243 IEEE80211_CHAN_PASSIVE_SCAN;
245 band_5ghz->n_channels = ++b;
247 DPRINTF(sc, ATH_DBG_CONFIG,
248 "%s: 5MHz channel: %d, "
249 "channelFlags: 0x%x\n",
260 * Determine mode from channel flags
262 * This routine will provide the enumerated WIRELESSS_MODE value based
263 * on the settings of the channel flags. If ho valid set of flags
264 * exist, the lowest mode (11b) is selected.
267 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
269 if (chan->chanmode == CHANNEL_A)
270 return WIRELESS_MODE_11a;
271 else if (chan->chanmode == CHANNEL_G)
272 return WIRELESS_MODE_11g;
273 else if (chan->chanmode == CHANNEL_B)
274 return WIRELESS_MODE_11b;
275 else if (chan->chanmode == CHANNEL_A_HT20)
276 return WIRELESS_MODE_11NA_HT20;
277 else if (chan->chanmode == CHANNEL_G_HT20)
278 return WIRELESS_MODE_11NG_HT20;
279 else if (chan->chanmode == CHANNEL_A_HT40PLUS)
280 return WIRELESS_MODE_11NA_HT40PLUS;
281 else if (chan->chanmode == CHANNEL_A_HT40MINUS)
282 return WIRELESS_MODE_11NA_HT40MINUS;
283 else if (chan->chanmode == CHANNEL_G_HT40PLUS)
284 return WIRELESS_MODE_11NG_HT40PLUS;
285 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
286 return WIRELESS_MODE_11NG_HT40MINUS;
288 /* NB: should not get here */
289 return WIRELESS_MODE_11b;
295 * Performs the actions to change the channel in the hardware, and set up
296 * the current operating mode for the new channel.
299 static void ath_chan_change(struct ath_softc *sc, struct ath9k_channel *chan)
301 enum wireless_mode mode;
303 mode = ath_chan2mode(chan);
305 ath_rate_setup(sc, mode);
306 ath_setcurmode(sc, mode);
310 * Stop the device, grabbing the top-level lock to protect
311 * against concurrent entry through ath_init (which can happen
312 * if another thread does a system call and the thread doing the
313 * stop is preempted).
316 static int ath_stop(struct ath_softc *sc)
318 struct ath_hal *ah = sc->sc_ah;
320 DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %u\n",
321 __func__, sc->sc_invalid);
324 * Shutdown the hardware and driver:
325 * stop output from above
326 * reset 802.11 state machine
327 * (sends station deassoc/deauth frames)
330 * clear transmit machinery
331 * clear receive machinery
333 * reclaim beacon resources
335 * Note that some of this work is not possible if the
336 * hardware is gone (invalid).
340 ath9k_hw_set_interrupts(ah, 0);
341 ath_draintxq(sc, false);
342 if (!sc->sc_invalid) {
344 ath9k_hw_phy_disable(ah);
346 sc->sc_rxlink = NULL;
354 * This function is called when starting a channel scan. It will perform
355 * power save wakeup processing, set the filter for the scan, and get the
356 * chip ready to send broadcast packets out during the scan.
359 void ath_scan_start(struct ath_softc *sc)
361 struct ath_hal *ah = sc->sc_ah;
363 u32 now = (u32) jiffies_to_msecs(get_timestamp());
366 rfilt = ath_calcrxfilter(sc);
367 ath9k_hw_setrxfilter(ah, rfilt);
368 ath9k_hw_write_associd(ah, ath_bcast_mac, 0);
370 /* Restore previous power management state. */
372 DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0\n",
373 now / 1000, now % 1000, __func__, rfilt);
379 * This routine is called by the upper layer when the scan is completed. This
380 * will set the filters back to normal operating mode, set the BSSID to the
381 * correct value, and restore the power save state.
384 void ath_scan_end(struct ath_softc *sc)
386 struct ath_hal *ah = sc->sc_ah;
388 u32 now = (u32) jiffies_to_msecs(get_timestamp());
391 /* Request for a full reset due to rx packet filter changes */
392 sc->sc_full_reset = 1;
393 rfilt = ath_calcrxfilter(sc);
394 ath9k_hw_setrxfilter(ah, rfilt);
395 ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
397 DPRINTF(sc, ATH_DBG_CONFIG, "%d.%03d | %s: RX filter 0x%x aid 0x%x\n",
398 now / 1000, now % 1000, __func__, rfilt, sc->sc_curaid);
402 * Set the current channel
404 * Set/change channels. If the channel is really being changed, it's done
405 * by reseting the chip. To accomplish this we must first cleanup any pending
406 * DMA, then restart stuff after a la ath_init.
408 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
410 struct ath_hal *ah = sc->sc_ah;
411 bool fastcc = true, stopped;
412 enum ath9k_ht_macmode ht_macmode;
414 if (sc->sc_invalid) /* if the device is invalid or removed */
417 DPRINTF(sc, ATH_DBG_CONFIG,
418 "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
420 ath9k_hw_mhz2ieee(ah, sc->sc_curchan.channel,
421 sc->sc_curchan.channelFlags),
422 sc->sc_curchan.channel,
423 ath9k_hw_mhz2ieee(ah, hchan->channel, hchan->channelFlags),
424 hchan->channel, hchan->channelFlags);
426 ht_macmode = ath_cwm_macmode(sc);
428 if (hchan->channel != sc->sc_curchan.channel ||
429 hchan->channelFlags != sc->sc_curchan.channelFlags ||
430 sc->sc_update_chainmask || sc->sc_full_reset) {
433 * This is only performed if the channel settings have
436 * To switch channels clear any pending DMA operations;
437 * wait long enough for the RX fifo to drain, reset the
438 * hardware at the new frequency, and then re-enable
439 * the relevant bits of the h/w.
441 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
442 ath_draintxq(sc, false); /* clear pending tx frames */
443 stopped = ath_stoprecv(sc); /* turn off frame recv */
445 /* XXX: do not flush receive queue here. We don't want
446 * to flush data frames already in queue because of
447 * changing channel. */
449 if (!stopped || sc->sc_full_reset)
452 spin_lock_bh(&sc->sc_resetlock);
453 if (!ath9k_hw_reset(ah, sc->sc_opmode, hchan,
454 ht_macmode, sc->sc_tx_chainmask,
456 sc->sc_ht_extprotspacing,
458 DPRINTF(sc, ATH_DBG_FATAL,
459 "%s: unable to reset channel %u (%uMhz) "
460 "flags 0x%x hal status %u\n", __func__,
461 ath9k_hw_mhz2ieee(ah, hchan->channel,
462 hchan->channelFlags),
463 hchan->channel, hchan->channelFlags, status);
464 spin_unlock_bh(&sc->sc_resetlock);
467 spin_unlock_bh(&sc->sc_resetlock);
469 sc->sc_curchan = *hchan;
470 sc->sc_update_chainmask = 0;
471 sc->sc_full_reset = 0;
473 /* Re-enable rx framework */
474 if (ath_startrecv(sc) != 0) {
475 DPRINTF(sc, ATH_DBG_FATAL,
476 "%s: unable to restart recv logic\n", __func__);
480 * Change channels and update the h/w rate map
481 * if we're switching; e.g. 11a to 11b/g.
483 ath_chan_change(sc, hchan);
484 ath_update_txpow(sc); /* update tx power state */
486 * Re-enable interrupts.
488 ath9k_hw_set_interrupts(ah, sc->sc_imask);
493 /**********************/
494 /* Chainmask Handling */
495 /**********************/
497 static void ath_chainmask_sel_timertimeout(unsigned long data)
499 struct ath_chainmask_sel *cm = (struct ath_chainmask_sel *)data;
500 cm->switch_allowed = 1;
503 /* Start chainmask select timer */
504 static void ath_chainmask_sel_timerstart(struct ath_chainmask_sel *cm)
506 cm->switch_allowed = 0;
507 mod_timer(&cm->timer, ath_chainmask_sel_period);
510 /* Stop chainmask select timer */
511 static void ath_chainmask_sel_timerstop(struct ath_chainmask_sel *cm)
513 cm->switch_allowed = 0;
514 del_timer_sync(&cm->timer);
517 static void ath_chainmask_sel_init(struct ath_softc *sc, struct ath_node *an)
519 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
521 memzero(cm, sizeof(struct ath_chainmask_sel));
523 cm->cur_tx_mask = sc->sc_tx_chainmask;
524 cm->cur_rx_mask = sc->sc_rx_chainmask;
525 cm->tx_avgrssi = ATH_RSSI_DUMMY_MARKER;
526 setup_timer(&cm->timer,
527 ath_chainmask_sel_timertimeout, (unsigned long) cm);
530 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
532 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
535 * Disable auto-swtiching in one of the following if conditions.
536 * sc_chainmask_auto_sel is used for internal global auto-switching
537 * enabled/disabled setting
539 if (sc->sc_ah->ah_caps.tx_chainmask != ATH_CHAINMASK_SEL_3X3) {
540 cm->cur_tx_mask = sc->sc_tx_chainmask;
541 return cm->cur_tx_mask;
544 if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
545 return cm->cur_tx_mask;
547 if (cm->switch_allowed) {
548 /* Switch down from tx 3 to tx 2. */
549 if (cm->cur_tx_mask == ATH_CHAINMASK_SEL_3X3 &&
550 ATH_RSSI_OUT(cm->tx_avgrssi) >=
551 ath_chainmask_sel_down_rssi_thres) {
552 cm->cur_tx_mask = sc->sc_tx_chainmask;
554 /* Don't let another switch happen until
555 * this timer expires */
556 ath_chainmask_sel_timerstart(cm);
558 /* Switch up from tx 2 to 3. */
559 else if (cm->cur_tx_mask == sc->sc_tx_chainmask &&
560 ATH_RSSI_OUT(cm->tx_avgrssi) <=
561 ath_chainmask_sel_up_rssi_thres) {
562 cm->cur_tx_mask = ATH_CHAINMASK_SEL_3X3;
564 /* Don't let another switch happen
565 * until this timer expires */
566 ath_chainmask_sel_timerstart(cm);
570 return cm->cur_tx_mask;
574 * Update tx/rx chainmask. For legacy association,
575 * hard code chainmask to 1x1, for 11n association, use
576 * the chainmask configuration.
579 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
581 sc->sc_update_chainmask = 1;
583 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
584 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
586 sc->sc_tx_chainmask = 1;
587 sc->sc_rx_chainmask = 1;
590 DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
591 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
601 * This routine brings the VAP out of the down state into a "listen" state
602 * where it waits for association requests. This is used in AP and AdHoc
606 int ath_vap_listen(struct ath_softc *sc, int if_id)
608 struct ath_hal *ah = sc->sc_ah;
611 DECLARE_MAC_BUF(mac);
613 avp = sc->sc_vaps[if_id];
615 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
620 #ifdef CONFIG_SLOW_ANT_DIV
621 ath_slow_ant_div_stop(&sc->sc_antdiv);
624 /* update ratectrl about the new state */
625 ath_rate_newstate(sc, avp);
627 rfilt = ath_calcrxfilter(sc);
628 ath9k_hw_setrxfilter(ah, rfilt);
630 if (sc->sc_opmode == ATH9K_M_STA || sc->sc_opmode == ATH9K_M_IBSS) {
631 memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
632 ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
636 DPRINTF(sc, ATH_DBG_CONFIG,
637 "%s: RX filter 0x%x bssid %s aid 0x%x\n",
638 __func__, rfilt, print_mac(mac,
639 sc->sc_curbssid), sc->sc_curaid);
643 * Disable BMISS interrupt when we're not associated
645 ath9k_hw_set_interrupts(ah,
646 sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
647 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
648 /* need to reconfigure the beacons when it moves to RUN */
654 int ath_vap_attach(struct ath_softc *sc,
656 struct ieee80211_vif *if_data,
657 enum ath9k_opmode opmode)
661 if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
662 DPRINTF(sc, ATH_DBG_FATAL,
663 "%s: Invalid interface id = %u\n", __func__, if_id);
670 case ATH9K_M_MONITOR:
673 /* XXX not right, beacon buffer is allocated on RUN trans */
674 if (list_empty(&sc->sc_bbuf))
682 avp = kmalloc(sizeof(struct ath_vap), GFP_KERNEL);
686 memzero(avp, sizeof(struct ath_vap));
687 avp->av_if_data = if_data;
688 /* Set the VAP opmode */
689 avp->av_opmode = opmode;
691 INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
692 INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
693 spin_lock_init(&avp->av_mcastq.axq_lock);
695 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
697 sc->sc_vaps[if_id] = avp;
699 /* Set the device opmode */
700 sc->sc_opmode = opmode;
702 /* default VAP configuration */
703 avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE;
704 avp->av_config.av_fixed_retryset = 0x03030303;
709 int ath_vap_detach(struct ath_softc *sc, int if_id)
711 struct ath_hal *ah = sc->sc_ah;
714 avp = sc->sc_vaps[if_id];
716 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
722 * Quiesce the hardware while we remove the vap. In
723 * particular we need to reclaim all references to the
724 * vap state by any frames pending on the tx queues.
726 * XXX can we do this w/o affecting other vap's?
728 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
729 ath_draintxq(sc, false); /* stop xmit side */
730 ath_stoprecv(sc); /* stop recv side */
731 ath_flushrecv(sc); /* flush recv queue */
733 /* Reclaim any pending mcast bufs on the vap. */
734 ath_tx_draintxq(sc, &avp->av_mcastq, false);
737 sc->sc_vaps[if_id] = NULL;
743 int ath_vap_config(struct ath_softc *sc,
744 int if_id, struct ath_vap_config *if_config)
748 if (if_id >= ATH_BCBUF) {
749 DPRINTF(sc, ATH_DBG_FATAL,
750 "%s: Invalid interface id = %u\n", __func__, if_id);
754 avp = sc->sc_vaps[if_id];
758 memcpy(&avp->av_config, if_config, sizeof(avp->av_config));
767 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
769 struct ath_hal *ah = sc->sc_ah;
772 enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
774 DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n", __func__, sc->sc_opmode);
777 * Stop anything previously setup. This is safe
778 * whether this is the first time through or not.
782 /* Initialize chanmask selection */
783 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
784 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
786 /* Reset SERDES registers */
787 ath9k_hw_configpcipowersave(ah, 0);
790 * The basic interface to setting the hardware in a good
791 * state is ``reset''. On return the hardware is known to
792 * be powered up and with interrupts disabled. This must
793 * be followed by initialization of the appropriate bits
794 * and then setup of the interrupt mask.
796 sc->sc_curchan = *initial_chan;
798 spin_lock_bh(&sc->sc_resetlock);
799 if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan, ht_macmode,
800 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
801 sc->sc_ht_extprotspacing, false, &status)) {
802 DPRINTF(sc, ATH_DBG_FATAL,
803 "%s: unable to reset hardware; hal status %u "
804 "(freq %u flags 0x%x)\n", __func__, status,
805 sc->sc_curchan.channel, sc->sc_curchan.channelFlags);
807 spin_unlock_bh(&sc->sc_resetlock);
810 spin_unlock_bh(&sc->sc_resetlock);
812 * This is needed only to setup initial state
813 * but it's best done after a reset.
815 ath_update_txpow(sc);
818 * Setup the hardware after reset:
819 * The receive engine is set going.
820 * Frame transmit is handled entirely
821 * in the frame output path; there's nothing to do
822 * here except setup the interrupt mask.
824 if (ath_startrecv(sc) != 0) {
825 DPRINTF(sc, ATH_DBG_FATAL,
826 "%s: unable to start recv logic\n", __func__);
830 /* Setup our intr mask. */
831 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
832 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
833 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
835 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
836 sc->sc_imask |= ATH9K_INT_GTT;
838 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
839 sc->sc_imask |= ATH9K_INT_CST;
842 * Enable MIB interrupts when there are hardware phy counters.
843 * Note we only do this (at the moment) for station mode.
845 if (ath9k_hw_phycounters(ah) &&
846 ((sc->sc_opmode == ATH9K_M_STA) || (sc->sc_opmode == ATH9K_M_IBSS)))
847 sc->sc_imask |= ATH9K_INT_MIB;
849 * Some hardware processes the TIM IE and fires an
850 * interrupt when the TIM bit is set. For hardware
851 * that does, if not overridden by configuration,
852 * enable the TIM interrupt when operating as station.
854 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
855 (sc->sc_opmode == ATH9K_M_STA) &&
856 !sc->sc_config.swBeaconProcess)
857 sc->sc_imask |= ATH9K_INT_TIM;
859 * Don't enable interrupts here as we've not yet built our
860 * vap and node data structures, which will be needed as soon
861 * as we start receiving.
863 ath_chan_change(sc, initial_chan);
865 /* XXX: we must make sure h/w is ready and clear invalid flag
866 * before turning on interrupt. */
873 * Reset the hardware w/o losing operational state. This is
874 * basically a more efficient way of doing ath_stop, ath_init,
875 * followed by state transitions to the current 802.11
876 * operational state. Used to recover from errors rx overrun
877 * and to reset the hardware when rf gain settings must be reset.
880 static int ath_reset_start(struct ath_softc *sc, u32 flag)
882 struct ath_hal *ah = sc->sc_ah;
884 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
885 ath_draintxq(sc, flag & RESET_RETRY_TXQ); /* stop xmit side */
886 ath_stoprecv(sc); /* stop recv side */
887 ath_flushrecv(sc); /* flush recv queue */
892 static int ath_reset_end(struct ath_softc *sc, u32 flag)
894 struct ath_hal *ah = sc->sc_ah;
896 if (ath_startrecv(sc) != 0) /* restart recv */
897 DPRINTF(sc, ATH_DBG_FATAL,
898 "%s: unable to start recv logic\n", __func__);
901 * We may be doing a reset in response to a request
902 * that changes the channel so update any state that
903 * might change as a result.
905 ath_chan_change(sc, &sc->sc_curchan);
907 ath_update_txpow(sc); /* update tx power state */
910 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
911 ath9k_hw_set_interrupts(ah, sc->sc_imask);
913 /* Restart the txq */
914 if (flag & RESET_RETRY_TXQ) {
916 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
917 if (ATH_TXQ_SETUP(sc, i)) {
918 spin_lock_bh(&sc->sc_txq[i].axq_lock);
919 ath_txq_schedule(sc, &sc->sc_txq[i]);
920 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
927 int ath_reset(struct ath_softc *sc)
929 struct ath_hal *ah = sc->sc_ah;
932 enum ath9k_ht_macmode ht_macmode = ath_cwm_macmode(sc);
934 /* NB: indicate channel change so we do a full reset */
935 spin_lock_bh(&sc->sc_resetlock);
936 if (!ath9k_hw_reset(ah, sc->sc_opmode, &sc->sc_curchan,
938 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
939 sc->sc_ht_extprotspacing, false, &status)) {
940 DPRINTF(sc, ATH_DBG_FATAL,
941 "%s: unable to reset hardware; hal status %u\n",
945 spin_unlock_bh(&sc->sc_resetlock);
950 int ath_suspend(struct ath_softc *sc)
952 struct ath_hal *ah = sc->sc_ah;
954 /* No I/O if device has been surprise removed */
958 /* Shut off the interrupt before setting sc->sc_invalid to '1' */
959 ath9k_hw_set_interrupts(ah, 0);
961 /* XXX: we must make sure h/w will not generate any interrupt
962 * before setting the invalid flag. */
965 /* disable HAL and put h/w to sleep */
966 ath9k_hw_disable(sc->sc_ah);
968 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
973 /* Interrupt handler. Most of the actual processing is deferred.
974 * It's the caller's responsibility to ensure the chip is awake. */
976 irqreturn_t ath_isr(int irq, void *dev)
978 struct ath_softc *sc = dev;
979 struct ath_hal *ah = sc->sc_ah;
980 enum ath9k_int status;
984 if (sc->sc_invalid) {
986 * The hardware is not ready/present, don't
987 * touch anything. Note this can happen early
988 * on if the IRQ is shared.
992 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
997 * Figure out the reason(s) for the interrupt. Note
998 * that the hal returns a pseudo-ISR that may include
999 * bits we haven't explicitly enabled so we mask the
1000 * value to insure we only process bits we requested.
1002 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
1004 status &= sc->sc_imask; /* discard unasked-for bits */
1007 * If there are no status bits set, then this interrupt was not
1008 * for me (should have been caught above).
1014 sc->sc_intrstatus = status;
1016 if (status & ATH9K_INT_FATAL) {
1017 /* need a chip reset */
1019 } else if (status & ATH9K_INT_RXORN) {
1020 /* need a chip reset */
1023 if (status & ATH9K_INT_SWBA) {
1024 /* schedule a tasklet for beacon handling */
1025 tasklet_schedule(&sc->bcon_tasklet);
1027 if (status & ATH9K_INT_RXEOL) {
1029 * NB: the hardware should re-read the link when
1030 * RXE bit is written, but it doesn't work
1031 * at least on older hardware revs.
1036 if (status & ATH9K_INT_TXURN)
1037 /* bump tx trigger level */
1038 ath9k_hw_updatetxtriglevel(ah, true);
1039 /* XXX: optimize this */
1040 if (status & ATH9K_INT_RX)
1042 if (status & ATH9K_INT_TX)
1044 if (status & ATH9K_INT_BMISS)
1046 /* carrier sense timeout */
1047 if (status & ATH9K_INT_CST)
1049 if (status & ATH9K_INT_MIB) {
1051 * Disable interrupts until we service the MIB
1052 * interrupt; otherwise it will continue to
1055 ath9k_hw_set_interrupts(ah, 0);
1057 * Let the hal handle the event. We assume
1058 * it will clear whatever condition caused
1061 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
1062 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1064 if (status & ATH9K_INT_TIM_TIMER) {
1065 if (!(ah->ah_caps.hw_caps &
1066 ATH9K_HW_CAP_AUTOSLEEP)) {
1067 /* Clear RxAbort bit so that we can
1069 ath9k_hw_setrxabort(ah, 0);
1077 /* turn off every interrupt except SWBA */
1078 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
1079 tasklet_schedule(&sc->intr_tq);
1085 /* Deferred interrupt processing */
1087 static void ath9k_tasklet(unsigned long data)
1089 struct ath_softc *sc = (struct ath_softc *)data;
1090 u32 status = sc->sc_intrstatus;
1092 if (status & ATH9K_INT_FATAL) {
1093 /* need a chip reset */
1094 ath_internal_reset(sc);
1099 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
1100 /* XXX: fill me in */
1102 if (status & ATH9K_INT_RXORN) {
1104 if (status & ATH9K_INT_RXEOL) {
1107 spin_lock_bh(&sc->sc_rxflushlock);
1108 ath_rx_tasklet(sc, 0);
1109 spin_unlock_bh(&sc->sc_rxflushlock);
1111 /* XXX: optimize this */
1112 if (status & ATH9K_INT_TX)
1114 /* XXX: fill me in */
1116 if (status & ATH9K_INT_BMISS) {
1118 if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
1119 if (status & ATH9K_INT_TIM) {
1121 if (status & ATH9K_INT_DTIMSYNC) {
1127 /* re-enable hardware interrupt */
1128 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1131 int ath_init(u16 devid, struct ath_softc *sc)
1133 struct ath_hal *ah = NULL;
1139 /* XXX: hardware will not be ready until ath_open() being called */
1142 sc->sc_debug = DBG_DEFAULT;
1143 DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
1145 /* Initialize tasklet */
1146 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1147 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1151 * Cache line size is used to size and align various
1152 * structures used to communicate with the hardware.
1154 bus_read_cachesize(sc, &csz);
1155 /* XXX assert csz is non-zero */
1156 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1158 spin_lock_init(&sc->sc_resetlock);
1160 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1162 DPRINTF(sc, ATH_DBG_FATAL,
1163 "%s: unable to attach hardware; HAL status %u\n",
1170 /* Get the chipset-specific aggr limit. */
1171 sc->sc_rtsaggrlimit = ah->ah_caps.rts_aggr_limit;
1173 /* Get the hardware key cache size. */
1174 sc->sc_keymax = ah->ah_caps.keycache_size;
1175 if (sc->sc_keymax > ATH_KEYMAX) {
1176 DPRINTF(sc, ATH_DBG_KEYCACHE,
1177 "%s: Warning, using only %u entries in %u key cache\n",
1178 __func__, ATH_KEYMAX, sc->sc_keymax);
1179 sc->sc_keymax = ATH_KEYMAX;
1183 * Reset the key cache since some parts do not
1184 * reset the contents on initial power up.
1186 for (i = 0; i < sc->sc_keymax; i++)
1187 ath9k_hw_keyreset(ah, (u16) i);
1189 * Mark key cache slots associated with global keys
1190 * as in use. If we knew TKIP was not to be used we
1191 * could leave the +32, +64, and +32+64 slots free.
1192 * XXX only for splitmic.
1194 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1195 set_bit(i, sc->sc_keymap);
1196 set_bit(i + 32, sc->sc_keymap);
1197 set_bit(i + 64, sc->sc_keymap);
1198 set_bit(i + 32 + 64, sc->sc_keymap);
1201 * Collect the channel list using the default country
1202 * code and including outdoor channels. The 802.11 layer
1203 * is resposible for filtering this list based on settings
1204 * like the phy mode.
1206 rd = ah->ah_currentRD;
1208 error = ath_setup_channels(sc);
1212 /* default to STA mode */
1213 sc->sc_opmode = ATH9K_M_MONITOR;
1215 /* Setup rate tables for all potential media types. */
1216 /* 11g encompasses b,g */
1218 ath_rate_setup(sc, WIRELESS_MODE_11a);
1219 ath_rate_setup(sc, WIRELESS_MODE_11g);
1221 /* NB: setup here so ath_rate_update is happy */
1222 ath_setcurmode(sc, WIRELESS_MODE_11a);
1225 * Allocate hardware transmit queues: one queue for
1226 * beacon frames and one data queue for each QoS
1227 * priority. Note that the hal handles reseting
1228 * these queues at the needed time.
1230 sc->sc_bhalq = ath_beaconq_setup(ah);
1231 if (sc->sc_bhalq == -1) {
1232 DPRINTF(sc, ATH_DBG_FATAL,
1233 "%s: unable to setup a beacon xmit queue\n", __func__);
1237 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1238 if (sc->sc_cabq == NULL) {
1239 DPRINTF(sc, ATH_DBG_FATAL,
1240 "%s: unable to setup CAB xmit queue\n", __func__);
1245 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1246 ath_cabq_update(sc);
1248 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1249 sc->sc_haltype2q[i] = -1;
1251 /* Setup data queues */
1252 /* NB: ensure BK queue is the lowest priority h/w queue */
1253 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1254 DPRINTF(sc, ATH_DBG_FATAL,
1255 "%s: unable to setup xmit queue for BK traffic\n",
1261 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1262 DPRINTF(sc, ATH_DBG_FATAL,
1263 "%s: unable to setup xmit queue for BE traffic\n",
1268 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1269 DPRINTF(sc, ATH_DBG_FATAL,
1270 "%s: unable to setup xmit queue for VI traffic\n",
1275 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1276 DPRINTF(sc, ATH_DBG_FATAL,
1277 "%s: unable to setup xmit queue for VO traffic\n",
1283 sc->sc_rc = ath_rate_attach(ah);
1284 if (sc->sc_rc == NULL) {
1289 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1290 ATH9K_CIPHER_TKIP, NULL)) {
1292 * Whether we should enable h/w TKIP MIC.
1293 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1294 * report WMM capable, so it's always safe to turn on
1295 * TKIP MIC in this case.
1297 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1302 * Check whether the separate key cache entries
1303 * are required to handle both tx+rx MIC keys.
1304 * With split mic keys the number of stations is limited
1305 * to 27 otherwise 59.
1307 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1308 ATH9K_CIPHER_TKIP, NULL)
1309 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1310 ATH9K_CIPHER_MIC, NULL)
1311 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1313 sc->sc_splitmic = 1;
1315 /* turn on mcast key search if possible */
1316 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1317 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1320 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1321 sc->sc_config.txpowlimit_override = 0;
1323 /* 11n Capabilities */
1324 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1329 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1330 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1332 /* Configuration for rx chain detection */
1333 sc->sc_rxchaindetect_ref = 0;
1334 sc->sc_rxchaindetect_thresh5GHz = 35;
1335 sc->sc_rxchaindetect_thresh2GHz = 35;
1336 sc->sc_rxchaindetect_delta5GHz = 30;
1337 sc->sc_rxchaindetect_delta2GHz = 30;
1339 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1340 sc->sc_defant = ath9k_hw_getdefantenna(ah);
1342 ath9k_hw_getmac(ah, sc->sc_myaddr);
1343 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1344 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1345 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1346 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1348 sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1350 /* initialize beacon slots */
1351 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1352 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1354 /* save MISC configurations */
1355 sc->sc_config.swBeaconProcess = 1;
1357 #ifdef CONFIG_SLOW_ANT_DIV
1358 /* range is 40 - 255, we use something in the middle */
1359 ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1364 /* cleanup tx queues */
1365 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1366 if (ATH_TXQ_SETUP(sc, i))
1367 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1370 ath9k_hw_detach(ah);
1374 void ath_deinit(struct ath_softc *sc)
1376 struct ath_hal *ah = sc->sc_ah;
1379 DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
1382 if (!sc->sc_invalid)
1383 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1384 ath_rate_detach(sc->sc_rc);
1385 /* cleanup tx queues */
1386 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1387 if (ATH_TXQ_SETUP(sc, i))
1388 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1389 ath9k_hw_detach(ah);
1392 /*******************/
1393 /* Node Management */
1394 /*******************/
1396 struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
1398 struct ath_vap *avp;
1399 struct ath_node *an;
1400 DECLARE_MAC_BUF(mac);
1402 avp = sc->sc_vaps[if_id];
1403 ASSERT(avp != NULL);
1405 /* mac80211 sta_notify callback is from an IRQ context, so no sleep */
1406 an = kmalloc(sizeof(struct ath_node), GFP_ATOMIC);
1409 memzero(an, sizeof(*an));
1412 memcpy(an->an_addr, addr, ETH_ALEN);
1413 atomic_set(&an->an_refcnt, 1);
1415 /* set up per-node tx/rx state */
1416 ath_tx_node_init(sc, an);
1417 ath_rx_node_init(sc, an);
1419 ath_chainmask_sel_init(sc, an);
1420 ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
1421 list_add(&an->list, &sc->node_list);
1426 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1428 unsigned long flags;
1430 DECLARE_MAC_BUF(mac);
1432 ath_chainmask_sel_timerstop(&an->an_chainmask_sel);
1433 an->an_flags |= ATH_NODE_CLEAN;
1434 ath_tx_node_cleanup(sc, an, bh_flag);
1435 ath_rx_node_cleanup(sc, an);
1437 ath_tx_node_free(sc, an);
1438 ath_rx_node_free(sc, an);
1440 spin_lock_irqsave(&sc->node_lock, flags);
1442 list_del(&an->list);
1444 spin_unlock_irqrestore(&sc->node_lock, flags);
1449 /* Finds a node and increases the refcnt if found */
1451 struct ath_node *ath_node_get(struct ath_softc *sc, u8 *addr)
1453 struct ath_node *an = NULL, *an_found = NULL;
1455 if (list_empty(&sc->node_list)) /* FIXME */
1457 list_for_each_entry(an, &sc->node_list, list) {
1458 if (!compare_ether_addr(an->an_addr, addr)) {
1459 atomic_inc(&an->an_refcnt);
1468 /* Decrements the refcnt and if it drops to zero, detach the node */
1470 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1472 if (atomic_dec_and_test(&an->an_refcnt))
1473 ath_node_detach(sc, an, bh_flag);
1476 /* Finds a node, doesn't increment refcnt. Caller must hold sc->node_lock */
1477 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr)
1479 struct ath_node *an = NULL, *an_found = NULL;
1481 if (list_empty(&sc->node_list))
1484 list_for_each_entry(an, &sc->node_list, list)
1485 if (!compare_ether_addr(an->an_addr, addr)) {
1496 * Setup driver-specific state for a newly associated node. This routine
1497 * really only applies if compression or XR are enabled, there is no code
1498 * covering any other cases.
1501 void ath_newassoc(struct ath_softc *sc,
1502 struct ath_node *an, int isnew, int isuapsd)
1506 /* if station reassociates, tear down the aggregation state. */
1508 for (tidno = 0; tidno < WME_NUM_TID; tidno++) {
1510 ath_tx_aggr_teardown(sc, an, tidno);
1512 ath_rx_aggr_teardown(sc, an, tidno);
1522 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
1524 ath9k_hw_keyreset(sc->sc_ah, keyix);
1526 clear_bit(keyix, sc->sc_keymap);
1529 int ath_keyset(struct ath_softc *sc,
1531 struct ath9k_keyval *hk,
1532 const u8 mac[ETH_ALEN])
1536 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
1537 keyix, hk, mac, false);
1539 return status != false;
1542 /***********************/
1543 /* TX Power/Regulatory */
1544 /***********************/
1547 * Set Transmit power in HAL
1549 * This routine makes the actual HAL calls to set the new transmit power
1553 void ath_update_txpow(struct ath_softc *sc)
1555 struct ath_hal *ah = sc->sc_ah;
1558 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
1559 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
1560 /* read back in case value is clamped */
1561 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
1562 sc->sc_curtxpow = txpow;
1566 /* Return the current country and domain information */
1567 void ath_get_currentCountry(struct ath_softc *sc,
1568 struct ath9k_country_entry *ctry)
1570 ath9k_regd_get_current_country(sc->sc_ah, ctry);
1572 /* If HAL not specific yet, since it is band dependent,
1573 * use the one we passed in. */
1574 if (ctry->countryCode == CTRY_DEFAULT) {
1577 } else if (ctry->iso[0] && ctry->iso[1]) {
1578 if (!ctry->iso[2]) {
1587 /**************************/
1588 /* Slow Antenna Diversity */
1589 /**************************/
1591 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
1592 struct ath_softc *sc,
1597 /* antdivf_rssitrig can range from 40 - 0xff */
1598 trig = (rssitrig > 0xff) ? 0xff : rssitrig;
1599 trig = (rssitrig < 40) ? 40 : rssitrig;
1601 antdiv->antdiv_sc = sc;
1602 antdiv->antdivf_rssitrig = trig;
1605 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
1609 antdiv->antdiv_num_antcfg =
1610 num_antcfg < ATH_ANT_DIV_MAX_CFG ?
1611 num_antcfg : ATH_ANT_DIV_MAX_CFG;
1612 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1613 antdiv->antdiv_curcfg = 0;
1614 antdiv->antdiv_bestcfg = 0;
1615 antdiv->antdiv_laststatetsf = 0;
1617 memcpy(antdiv->antdiv_bssid, bssid, sizeof(antdiv->antdiv_bssid));
1619 antdiv->antdiv_start = 1;
1622 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv)
1624 antdiv->antdiv_start = 0;
1627 static int32_t ath_find_max_val(int32_t *val,
1628 u8 num_val, u8 *max_index)
1630 u32 MaxVal = *val++;
1634 while (++cur_index < num_val) {
1635 if (*val > MaxVal) {
1637 *max_index = cur_index;
1646 void ath_slow_ant_div(struct ath_antdiv *antdiv,
1647 struct ieee80211_hdr *hdr,
1648 struct ath_rx_status *rx_stats)
1650 struct ath_softc *sc = antdiv->antdiv_sc;
1651 struct ath_hal *ah = sc->sc_ah;
1653 u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
1654 __le16 fc = hdr->frame_control;
1656 if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
1657 && !compare_ether_addr(hdr->addr3, antdiv->antdiv_bssid)) {
1658 antdiv->antdiv_lastbrssi[curcfg] = rx_stats->rs_rssi;
1659 antdiv->antdiv_lastbtsf[curcfg] = ath9k_hw_gettsf64(sc->sc_ah);
1660 curtsf = antdiv->antdiv_lastbtsf[curcfg];
1665 switch (antdiv->antdiv_state) {
1666 case ATH_ANT_DIV_IDLE:
1667 if ((antdiv->antdiv_lastbrssi[curcfg] <
1668 antdiv->antdivf_rssitrig)
1669 && ((curtsf - antdiv->antdiv_laststatetsf) >
1670 ATH_ANT_DIV_MIN_IDLE_US)) {
1673 if (curcfg == antdiv->antdiv_num_antcfg)
1676 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1677 antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
1678 antdiv->antdiv_curcfg = curcfg;
1679 antdiv->antdiv_laststatetsf = curtsf;
1680 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1685 case ATH_ANT_DIV_SCAN:
1686 if ((curtsf - antdiv->antdiv_laststatetsf) <
1687 ATH_ANT_DIV_MIN_SCAN_US)
1691 if (curcfg == antdiv->antdiv_num_antcfg)
1694 if (curcfg == antdiv->antdiv_bestcfg) {
1695 ath_find_max_val(antdiv->antdiv_lastbrssi,
1696 antdiv->antdiv_num_antcfg, &bestcfg);
1697 if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
1698 antdiv->antdiv_bestcfg = bestcfg;
1699 antdiv->antdiv_curcfg = bestcfg;
1700 antdiv->antdiv_laststatetsf = curtsf;
1701 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1704 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1705 antdiv->antdiv_curcfg = curcfg;
1706 antdiv->antdiv_laststatetsf = curtsf;
1707 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1715 /***********************/
1716 /* Descriptor Handling */
1717 /***********************/
1720 * Set up DMA descriptors
1722 * This function will allocate both the DMA descriptor structure, and the
1723 * buffers it contains. These are used to contain the descriptors used
1727 int ath_descdma_setup(struct ath_softc *sc,
1728 struct ath_descdma *dd,
1729 struct list_head *head,
1734 #define DS2PHYS(_dd, _ds) \
1735 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1736 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1737 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1739 struct ath_desc *ds;
1741 int i, bsize, error;
1743 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
1744 __func__, name, nbuf, ndesc);
1746 /* ath_desc must be a multiple of DWORDs */
1747 if ((sizeof(struct ath_desc) % 4) != 0) {
1748 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
1750 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1756 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1759 * Need additional DMA memory because we can't use
1760 * descriptors that cross the 4K page boundary. Assume
1761 * one skipped descriptor per 4K page.
1763 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1765 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1768 while (ndesc_skipped) {
1769 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1770 dd->dd_desc_len += dma_len;
1772 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1776 /* allocate descriptors */
1777 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1779 &dd->dd_desc_paddr);
1780 if (dd->dd_desc == NULL) {
1785 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
1786 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
1787 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1789 /* allocate buffers */
1790 bsize = sizeof(struct ath_buf) * nbuf;
1791 bf = kmalloc(bsize, GFP_KERNEL);
1799 INIT_LIST_HEAD(head);
1800 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1802 bf->bf_daddr = DS2PHYS(dd, ds);
1804 if (!(sc->sc_ah->ah_caps.hw_caps &
1805 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1807 * Skip descriptor addresses which can cause 4KB
1808 * boundary crossing (addr + length) with a 32 dword
1811 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1812 ASSERT((caddr_t) bf->bf_desc <
1813 ((caddr_t) dd->dd_desc +
1818 bf->bf_daddr = DS2PHYS(dd, ds);
1821 list_add_tail(&bf->list, head);
1825 pci_free_consistent(sc->pdev,
1826 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1828 memzero(dd, sizeof(*dd));
1830 #undef ATH_DESC_4KB_BOUND_CHECK
1831 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1836 * Cleanup DMA descriptors
1838 * This function will free the DMA block that was allocated for the descriptor
1839 * pool. Since this was allocated as one "chunk", it is freed in the same
1843 void ath_descdma_cleanup(struct ath_softc *sc,
1844 struct ath_descdma *dd,
1845 struct list_head *head)
1847 /* Free memory associated with descriptors */
1848 pci_free_consistent(sc->pdev,
1849 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1851 INIT_LIST_HEAD(head);
1852 kfree(dd->dd_bufptr);
1853 memzero(dd, sizeof(*dd));
1860 void ath_internal_reset(struct ath_softc *sc)
1862 ath_reset_start(sc, 0);
1864 ath_reset_end(sc, 0);
1867 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1873 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1876 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1879 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1882 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1885 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1892 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1897 case ATH9K_WME_AC_VO:
1900 case ATH9K_WME_AC_VI:
1903 case ATH9K_WME_AC_BE:
1906 case ATH9K_WME_AC_BK:
1919 * Expand time stamp to TSF
1921 * Extend 15-bit time stamp from rx descriptor to
1922 * a full 64-bit TSF using the current h/w TSF.
1925 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
1929 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1930 if ((tsf & 0x7fff) < rstamp)
1932 return (tsf & ~0x7fff) | rstamp;
1936 * Set Default Antenna
1938 * Call into the HAL to set the default antenna to use. Not really valid for
1942 void ath_setdefantenna(void *context, u32 antenna)
1944 struct ath_softc *sc = (struct ath_softc *)context;
1945 struct ath_hal *ah = sc->sc_ah;
1947 /* XXX block beacon interrupts */
1948 ath9k_hw_setantenna(ah, antenna);
1949 sc->sc_defant = antenna;
1950 sc->sc_rxotherant = 0;
1956 * This will wake up the chip if required, and set the slot time for the
1957 * frame (maximum transmit time). Slot time is assumed to be already set
1958 * in the ATH object member sc_slottime
1961 void ath_setslottime(struct ath_softc *sc)
1963 ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime);
1964 sc->sc_updateslot = OK;