2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
61 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
69 MODULE_AUTHOR("Jiri Slaby");
70 MODULE_AUTHOR("Nick Kossifidis");
71 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
72 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
73 MODULE_LICENSE("Dual BSD/GPL");
74 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
78 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
79 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
80 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
81 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
82 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
83 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
84 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
85 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
86 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
88 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
94 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
95 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
96 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
97 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
100 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
103 static struct ath5k_srev_name srev_names[] = {
104 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
105 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
106 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
107 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
108 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
109 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
110 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
111 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
112 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
113 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
114 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
115 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
116 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
117 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
118 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
119 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
120 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
121 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
124 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
125 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
126 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
127 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
128 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
131 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
133 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
137 * Prototypes - PCI stack related functions
139 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
140 const struct pci_device_id *id);
141 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
143 static int ath5k_pci_suspend(struct pci_dev *pdev,
145 static int ath5k_pci_resume(struct pci_dev *pdev);
147 #define ath5k_pci_suspend NULL
148 #define ath5k_pci_resume NULL
149 #endif /* CONFIG_PM */
151 static struct pci_driver ath5k_pci_driver = {
153 .id_table = ath5k_pci_id_table,
154 .probe = ath5k_pci_probe,
155 .remove = __devexit_p(ath5k_pci_remove),
156 .suspend = ath5k_pci_suspend,
157 .resume = ath5k_pci_resume,
163 * Prototypes - MAC 802.11 stack related functions
165 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
166 static int ath5k_reset(struct ieee80211_hw *hw);
167 static int ath5k_start(struct ieee80211_hw *hw);
168 static void ath5k_stop(struct ieee80211_hw *hw);
169 static int ath5k_add_interface(struct ieee80211_hw *hw,
170 struct ieee80211_if_init_conf *conf);
171 static void ath5k_remove_interface(struct ieee80211_hw *hw,
172 struct ieee80211_if_init_conf *conf);
173 static int ath5k_config(struct ieee80211_hw *hw,
174 struct ieee80211_conf *conf);
175 static int ath5k_config_interface(struct ieee80211_hw *hw,
176 struct ieee80211_vif *vif,
177 struct ieee80211_if_conf *conf);
178 static void ath5k_configure_filter(struct ieee80211_hw *hw,
179 unsigned int changed_flags,
180 unsigned int *new_flags,
181 int mc_count, struct dev_mc_list *mclist);
182 static int ath5k_set_key(struct ieee80211_hw *hw,
183 enum set_key_cmd cmd,
184 const u8 *local_addr, const u8 *addr,
185 struct ieee80211_key_conf *key);
186 static int ath5k_get_stats(struct ieee80211_hw *hw,
187 struct ieee80211_low_level_stats *stats);
188 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
189 struct ieee80211_tx_queue_stats *stats);
190 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
191 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
192 static int ath5k_beacon_update(struct ieee80211_hw *hw,
193 struct sk_buff *skb);
195 static struct ieee80211_ops ath5k_hw_ops = {
197 .start = ath5k_start,
199 .add_interface = ath5k_add_interface,
200 .remove_interface = ath5k_remove_interface,
201 .config = ath5k_config,
202 .config_interface = ath5k_config_interface,
203 .configure_filter = ath5k_configure_filter,
204 .set_key = ath5k_set_key,
205 .get_stats = ath5k_get_stats,
207 .get_tx_stats = ath5k_get_tx_stats,
208 .get_tsf = ath5k_get_tsf,
209 .reset_tsf = ath5k_reset_tsf,
210 .beacon_update = ath5k_beacon_update,
214 * Prototypes - Internal functions
217 static int ath5k_attach(struct pci_dev *pdev,
218 struct ieee80211_hw *hw);
219 static void ath5k_detach(struct pci_dev *pdev,
220 struct ieee80211_hw *hw);
221 /* Channel/mode setup */
222 static inline short ath5k_ieee2mhz(short chan);
223 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
224 const struct ath5k_rate_table *rt,
226 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
227 struct ieee80211_channel *channels,
230 static int ath5k_getchannels(struct ieee80211_hw *hw);
231 static int ath5k_chan_set(struct ath5k_softc *sc,
232 struct ieee80211_channel *chan);
233 static void ath5k_setcurmode(struct ath5k_softc *sc,
235 static void ath5k_mode_setup(struct ath5k_softc *sc);
236 static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
238 /* Descriptor setup */
239 static int ath5k_desc_alloc(struct ath5k_softc *sc,
240 struct pci_dev *pdev);
241 static void ath5k_desc_free(struct ath5k_softc *sc,
242 struct pci_dev *pdev);
244 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
245 struct ath5k_buf *bf);
246 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
247 struct ath5k_buf *bf);
248 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
249 struct ath5k_buf *bf)
254 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
256 dev_kfree_skb(bf->skb);
261 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
262 int qtype, int subtype);
263 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
264 static int ath5k_beaconq_config(struct ath5k_softc *sc);
265 static void ath5k_txq_drainq(struct ath5k_softc *sc,
266 struct ath5k_txq *txq);
267 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
268 static void ath5k_txq_release(struct ath5k_softc *sc);
270 static int ath5k_rx_start(struct ath5k_softc *sc);
271 static void ath5k_rx_stop(struct ath5k_softc *sc);
272 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
273 struct ath5k_desc *ds,
275 struct ath5k_rx_status *rs);
276 static void ath5k_tasklet_rx(unsigned long data);
278 static void ath5k_tx_processq(struct ath5k_softc *sc,
279 struct ath5k_txq *txq);
280 static void ath5k_tasklet_tx(unsigned long data);
281 /* Beacon handling */
282 static int ath5k_beacon_setup(struct ath5k_softc *sc,
283 struct ath5k_buf *bf);
284 static void ath5k_beacon_send(struct ath5k_softc *sc);
285 static void ath5k_beacon_config(struct ath5k_softc *sc);
286 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
288 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
290 u64 tsf = ath5k_hw_get_tsf64(ah);
292 if ((tsf & 0x7fff) < rstamp)
295 return (tsf & ~0x7fff) | rstamp;
298 /* Interrupt handling */
299 static int ath5k_init(struct ath5k_softc *sc);
300 static int ath5k_stop_locked(struct ath5k_softc *sc);
301 static int ath5k_stop_hw(struct ath5k_softc *sc);
302 static irqreturn_t ath5k_intr(int irq, void *dev_id);
303 static void ath5k_tasklet_reset(unsigned long data);
305 static void ath5k_calibrate(unsigned long data);
307 static int ath5k_init_leds(struct ath5k_softc *sc);
308 static void ath5k_led_enable(struct ath5k_softc *sc);
309 static void ath5k_led_off(struct ath5k_softc *sc);
310 static void ath5k_unregister_leds(struct ath5k_softc *sc);
313 * Module init/exit functions
322 ret = pci_register_driver(&ath5k_pci_driver);
324 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
334 pci_unregister_driver(&ath5k_pci_driver);
336 ath5k_debug_finish();
339 module_init(init_ath5k_pci);
340 module_exit(exit_ath5k_pci);
343 /********************\
344 * PCI Initialization *
345 \********************/
348 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
350 const char *name = "xxxxx";
353 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
354 if (srev_names[i].sr_type != type)
356 if ((val & 0xff) < srev_names[i + 1].sr_val) {
357 name = srev_names[i].sr_name;
366 ath5k_pci_probe(struct pci_dev *pdev,
367 const struct pci_device_id *id)
370 struct ath5k_softc *sc;
371 struct ieee80211_hw *hw;
375 ret = pci_enable_device(pdev);
377 dev_err(&pdev->dev, "can't enable device\n");
381 /* XXX 32-bit addressing only */
382 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
384 dev_err(&pdev->dev, "32-bit DMA not available\n");
389 * Cache line size is used to size and align various
390 * structures used to communicate with the hardware.
392 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
395 * Linux 2.4.18 (at least) writes the cache line size
396 * register as a 16-bit wide register which is wrong.
397 * We must have this setup properly for rx buffer
398 * DMA to work so force a reasonable value here if it
401 csz = L1_CACHE_BYTES / sizeof(u32);
402 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
405 * The default setting of latency timer yields poor results,
406 * set it to the value used by other systems. It may be worth
407 * tweaking this setting more.
409 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
411 /* Enable bus mastering */
412 pci_set_master(pdev);
415 * Disable the RETRY_TIMEOUT register (0x41) to keep
416 * PCI Tx retries from interfering with C3 CPU state.
418 pci_write_config_byte(pdev, 0x41, 0);
420 ret = pci_request_region(pdev, 0, "ath5k");
422 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
426 mem = pci_iomap(pdev, 0, 0);
428 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
434 * Allocate hw (mac80211 main struct)
435 * and hw->priv (driver private data)
437 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
439 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
444 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
446 /* Initialize driver private data */
447 SET_IEEE80211_DEV(hw, &pdev->dev);
448 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
449 IEEE80211_HW_SIGNAL_DBM |
450 IEEE80211_HW_NOISE_DBM;
451 hw->extra_tx_headroom = 2;
452 hw->channel_change_time = 5000;
457 ath5k_debug_init_device(sc);
460 * Mark the device as detached to avoid processing
461 * interrupts until setup is complete.
463 __set_bit(ATH_STAT_INVALID, sc->status);
465 sc->iobase = mem; /* So we can unmap it on detach */
466 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
467 sc->opmode = IEEE80211_IF_TYPE_STA;
468 mutex_init(&sc->lock);
469 spin_lock_init(&sc->rxbuflock);
470 spin_lock_init(&sc->txbuflock);
472 /* Set private data */
473 pci_set_drvdata(pdev, hw);
475 /* Enable msi for devices that support it */
476 pci_enable_msi(pdev);
478 /* Setup interrupt handler */
479 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
481 ATH5K_ERR(sc, "request_irq failed\n");
485 /* Initialize device */
486 sc->ah = ath5k_hw_attach(sc, id->driver_data);
487 if (IS_ERR(sc->ah)) {
488 ret = PTR_ERR(sc->ah);
492 /* Finish private driver data initialization */
493 ret = ath5k_attach(pdev, hw);
497 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
498 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
500 sc->ah->ah_phy_revision);
502 if (!sc->ah->ah_single_chip) {
503 /* Single chip radio (!RF5111) */
504 if (sc->ah->ah_radio_5ghz_revision &&
505 !sc->ah->ah_radio_2ghz_revision) {
506 /* No 5GHz support -> report 2GHz radio */
507 if (!test_bit(AR5K_MODE_11A,
508 sc->ah->ah_capabilities.cap_mode)) {
509 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
510 ath5k_chip_name(AR5K_VERSION_RAD,
511 sc->ah->ah_radio_5ghz_revision),
512 sc->ah->ah_radio_5ghz_revision);
513 /* No 2GHz support (5110 and some
514 * 5Ghz only cards) -> report 5Ghz radio */
515 } else if (!test_bit(AR5K_MODE_11B,
516 sc->ah->ah_capabilities.cap_mode)) {
517 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
518 ath5k_chip_name(AR5K_VERSION_RAD,
519 sc->ah->ah_radio_5ghz_revision),
520 sc->ah->ah_radio_5ghz_revision);
521 /* Multiband radio */
523 ATH5K_INFO(sc, "RF%s multiband radio found"
525 ath5k_chip_name(AR5K_VERSION_RAD,
526 sc->ah->ah_radio_5ghz_revision),
527 sc->ah->ah_radio_5ghz_revision);
530 /* Multi chip radio (RF5111 - RF2111) ->
531 * report both 2GHz/5GHz radios */
532 else if (sc->ah->ah_radio_5ghz_revision &&
533 sc->ah->ah_radio_2ghz_revision){
534 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
535 ath5k_chip_name(AR5K_VERSION_RAD,
536 sc->ah->ah_radio_5ghz_revision),
537 sc->ah->ah_radio_5ghz_revision);
538 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
539 ath5k_chip_name(AR5K_VERSION_RAD,
540 sc->ah->ah_radio_2ghz_revision),
541 sc->ah->ah_radio_2ghz_revision);
546 /* ready to process interrupts */
547 __clear_bit(ATH_STAT_INVALID, sc->status);
551 ath5k_hw_detach(sc->ah);
553 free_irq(pdev->irq, sc);
555 pci_disable_msi(pdev);
556 ieee80211_free_hw(hw);
558 pci_iounmap(pdev, mem);
560 pci_release_region(pdev, 0);
562 pci_disable_device(pdev);
567 static void __devexit
568 ath5k_pci_remove(struct pci_dev *pdev)
570 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
571 struct ath5k_softc *sc = hw->priv;
573 ath5k_debug_finish_device(sc);
574 ath5k_detach(pdev, hw);
575 ath5k_hw_detach(sc->ah);
576 free_irq(pdev->irq, sc);
577 pci_disable_msi(pdev);
578 pci_iounmap(pdev, sc->iobase);
579 pci_release_region(pdev, 0);
580 pci_disable_device(pdev);
581 ieee80211_free_hw(hw);
586 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
588 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
589 struct ath5k_softc *sc = hw->priv;
594 pci_save_state(pdev);
595 pci_disable_device(pdev);
596 pci_set_power_state(pdev, PCI_D3hot);
602 ath5k_pci_resume(struct pci_dev *pdev)
604 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
605 struct ath5k_softc *sc = hw->priv;
606 struct ath5k_hw *ah = sc->ah;
609 err = pci_set_power_state(pdev, PCI_D0);
613 err = pci_enable_device(pdev);
617 pci_restore_state(pdev);
619 * Suspend/Resume resets the PCI configuration space, so we have to
620 * re-disable the RETRY_TIMEOUT register (0x41) to keep
621 * PCI Tx retries from interfering with C3 CPU state
623 pci_write_config_byte(pdev, 0x41, 0);
626 ath5k_led_enable(sc);
629 * Reset the key cache since some parts do not
630 * reset the contents on initial power up or resume.
632 * FIXME: This may need to be revisited when mac80211 becomes
633 * aware of suspend/resume.
635 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
636 ath5k_hw_reset_key(ah, i);
640 #endif /* CONFIG_PM */
644 /***********************\
645 * Driver Initialization *
646 \***********************/
649 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
651 struct ath5k_softc *sc = hw->priv;
652 struct ath5k_hw *ah = sc->ah;
657 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
660 * Check if the MAC has multi-rate retry support.
661 * We do this by trying to setup a fake extended
662 * descriptor. MAC's that don't have support will
663 * return false w/o doing anything. MAC's that do
664 * support it will return true w/o doing anything.
666 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
670 __set_bit(ATH_STAT_MRRETRY, sc->status);
673 * Reset the key cache since some parts do not
674 * reset the contents on initial power up.
676 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
677 ath5k_hw_reset_key(ah, i);
680 * Collect the channel list. The 802.11 layer
681 * is resposible for filtering this list based
682 * on settings like the phy mode and regulatory
683 * domain restrictions.
685 ret = ath5k_getchannels(hw);
687 ATH5K_ERR(sc, "can't get channels\n");
691 /* Set *_rates so we can map hw rate index */
692 ath5k_set_total_hw_rates(sc);
694 /* NB: setup here so ath5k_rate_update is happy */
695 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
696 ath5k_setcurmode(sc, AR5K_MODE_11A);
698 ath5k_setcurmode(sc, AR5K_MODE_11B);
701 * Allocate tx+rx descriptors and populate the lists.
703 ret = ath5k_desc_alloc(sc, pdev);
705 ATH5K_ERR(sc, "can't allocate descriptors\n");
710 * Allocate hardware transmit queues: one queue for
711 * beacon frames and one data queue for each QoS
712 * priority. Note that hw functions handle reseting
713 * these queues at the needed time.
715 ret = ath5k_beaconq_setup(ah);
717 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
722 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
723 if (IS_ERR(sc->txq)) {
724 ATH5K_ERR(sc, "can't setup xmit queue\n");
725 ret = PTR_ERR(sc->txq);
729 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
730 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
731 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
732 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
734 ath5k_hw_get_lladdr(ah, mac);
735 SET_IEEE80211_PERM_ADDR(hw, mac);
736 /* All MAC address bits matter for ACKs */
737 memset(sc->bssidmask, 0xff, ETH_ALEN);
738 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
740 ret = ieee80211_register_hw(hw);
742 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
750 ath5k_txq_release(sc);
752 ath5k_hw_release_tx_queue(ah, sc->bhalq);
754 ath5k_desc_free(sc, pdev);
760 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
762 struct ath5k_softc *sc = hw->priv;
765 * NB: the order of these is important:
766 * o call the 802.11 layer before detaching ath5k_hw to
767 * insure callbacks into the driver to delete global
768 * key cache entries can be handled
769 * o reclaim the tx queue data structures after calling
770 * the 802.11 layer as we'll get called back to reclaim
771 * node state and potentially want to use them
772 * o to cleanup the tx queues the hal is called, so detach
774 * XXX: ??? detach ath5k_hw ???
775 * Other than that, it's straightforward...
777 ieee80211_unregister_hw(hw);
778 ath5k_desc_free(sc, pdev);
779 ath5k_txq_release(sc);
780 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
781 ath5k_unregister_leds(sc);
784 * NB: can't reclaim these until after ieee80211_ifdetach
785 * returns because we'll get called back to reclaim node
786 * state and potentially want to use them.
793 /********************\
794 * Channel/mode setup *
795 \********************/
798 * Convert IEEE channel number to MHz frequency.
801 ath5k_ieee2mhz(short chan)
803 if (chan <= 14 || chan >= 27)
804 return ieee80211chan2mhz(chan);
806 return 2212 + chan * 20;
810 ath5k_copy_rates(struct ieee80211_rate *rates,
811 const struct ath5k_rate_table *rt,
814 unsigned int i, count;
819 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
820 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
821 rates[count].hw_value = rt->rates[i].rate_code;
822 rates[count].flags = rt->rates[i].modulation;
831 ath5k_copy_channels(struct ath5k_hw *ah,
832 struct ieee80211_channel *channels,
836 unsigned int i, count, size, chfreq, freq, ch;
838 if (!test_bit(mode, ah->ah_modes))
843 case AR5K_MODE_11A_TURBO:
844 /* 1..220, but 2GHz frequencies are filtered by check_channel */
846 chfreq = CHANNEL_5GHZ;
850 case AR5K_MODE_11G_TURBO:
852 chfreq = CHANNEL_2GHZ;
855 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
859 for (i = 0, count = 0; i < size && max > 0; i++) {
861 freq = ath5k_ieee2mhz(ch);
863 /* Check if channel is supported by the chipset */
864 if (!ath5k_channel_ok(ah, freq, chfreq))
867 /* Write channel info and increment counter */
868 channels[count].center_freq = freq;
869 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
870 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
874 channels[count].hw_value = chfreq | CHANNEL_OFDM;
876 case AR5K_MODE_11A_TURBO:
877 case AR5K_MODE_11G_TURBO:
878 channels[count].hw_value = chfreq |
879 CHANNEL_OFDM | CHANNEL_TURBO;
882 channels[count].hw_value = CHANNEL_B;
893 ath5k_getchannels(struct ieee80211_hw *hw)
895 struct ath5k_softc *sc = hw->priv;
896 struct ath5k_hw *ah = sc->ah;
897 struct ieee80211_supported_band *sbands = sc->sbands;
898 const struct ath5k_rate_table *hw_rates;
899 unsigned int max_r, max_c, count_r, count_c;
900 int mode2g = AR5K_MODE_11G;
902 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
904 max_r = ARRAY_SIZE(sc->rates);
905 max_c = ARRAY_SIZE(sc->channels);
906 count_r = count_c = 0;
909 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
910 mode2g = AR5K_MODE_11B;
911 if (!test_bit(AR5K_MODE_11B,
912 sc->ah->ah_capabilities.cap_mode))
917 struct ieee80211_supported_band *sband =
918 &sbands[IEEE80211_BAND_2GHZ];
920 sband->bitrates = sc->rates;
921 sband->channels = sc->channels;
923 sband->band = IEEE80211_BAND_2GHZ;
924 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
927 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
928 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
931 count_c = sband->n_channels;
932 count_r = sband->n_bitrates;
934 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
943 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
944 struct ieee80211_supported_band *sband =
945 &sbands[IEEE80211_BAND_5GHZ];
947 sband->bitrates = &sc->rates[count_r];
948 sband->channels = &sc->channels[count_c];
950 sband->band = IEEE80211_BAND_5GHZ;
951 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
952 AR5K_MODE_11A, max_c);
954 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
955 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
958 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
961 ath5k_debug_dump_bands(sc);
967 * Set/change channels. If the channel is really being changed,
968 * it's done by reseting the chip. To accomplish this we must
969 * first cleanup any pending DMA, then restart stuff after a la
973 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
975 struct ath5k_hw *ah = sc->ah;
978 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
979 sc->curchan->center_freq, chan->center_freq);
981 if (chan->center_freq != sc->curchan->center_freq ||
982 chan->hw_value != sc->curchan->hw_value) {
985 sc->curband = &sc->sbands[chan->band];
988 * To switch channels clear any pending DMA operations;
989 * wait long enough for the RX fifo to drain, reset the
990 * hardware at the new frequency, and then re-enable
991 * the relevant bits of the h/w.
993 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
994 ath5k_txq_cleanup(sc); /* clear pending tx frames */
995 ath5k_rx_stop(sc); /* turn off frame recv */
996 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
998 ATH5K_ERR(sc, "%s: unable to reset channel "
999 "(%u Mhz)\n", __func__, chan->center_freq);
1003 ath5k_hw_set_txpower_limit(sc->ah, 0);
1006 * Re-enable rx framework.
1008 ret = ath5k_rx_start(sc);
1010 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1016 * Change channels and update the h/w rate map
1017 * if we're switching; e.g. 11a to 11b/g.
1021 /* ath5k_chan_change(sc, chan); */
1023 ath5k_beacon_config(sc);
1025 * Re-enable interrupts.
1027 ath5k_hw_set_intr(ah, sc->imask);
1034 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1038 if (mode == AR5K_MODE_11A) {
1039 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1041 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1046 ath5k_mode_setup(struct ath5k_softc *sc)
1048 struct ath5k_hw *ah = sc->ah;
1051 /* configure rx filter */
1052 rfilt = sc->filter_flags;
1053 ath5k_hw_set_rx_filter(ah, rfilt);
1055 if (ath5k_hw_hasbssidmask(ah))
1056 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1058 /* configure operational mode */
1059 ath5k_hw_set_opmode(ah);
1061 ath5k_hw_set_mcast_filter(ah, 0, 0);
1062 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1066 * Match the hw provided rate index (through descriptors)
1067 * to an index for sc->curband->bitrates, so it can be used
1070 * This one is a little bit tricky but i think i'm right
1073 * We have 4 rate tables in the following order:
1077 * 802.11g (12 rates)
1078 * that make the hw rate table.
1080 * Lets take a 5211 for example that supports a and b modes only.
1081 * First comes the 802.11a table and then 802.11b (total 12 rates).
1082 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1083 * if it returns 2 it points to the second 802.11a rate etc.
1085 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1086 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1087 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1090 ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
1092 struct ath5k_hw *ah = sc->ah;
1094 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
1097 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
1100 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
1103 /* XXX: Need to see what what happens when
1104 xr disable bits in eeprom are set */
1105 if (ah->ah_version >= AR5K_AR5212)
1111 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
1115 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
1116 /* We setup a g ratetable for both b/g modes */
1118 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
1120 mac80211_rix = hw_rix - sc->xr_rates;
1123 /* Something went wrong, fallback to basic rate for this band */
1124 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1125 (mac80211_rix <= 0 ))
1128 return mac80211_rix;
1139 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1141 struct ath5k_hw *ah = sc->ah;
1142 struct sk_buff *skb = bf->skb;
1143 struct ath5k_desc *ds;
1145 if (likely(skb == NULL)) {
1149 * Allocate buffer with headroom_needed space for the
1150 * fake physical layer header at the start.
1152 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1153 if (unlikely(skb == NULL)) {
1154 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1155 sc->rxbufsize + sc->cachelsz - 1);
1159 * Cache-line-align. This is important (for the
1160 * 5210 at least) as not doing so causes bogus data
1163 off = ((unsigned long)skb->data) % sc->cachelsz;
1165 skb_reserve(skb, sc->cachelsz - off);
1168 bf->skbaddr = pci_map_single(sc->pdev,
1169 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1170 if (unlikely(pci_dma_mapping_error(bf->skbaddr))) {
1171 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1179 * Setup descriptors. For receive we always terminate
1180 * the descriptor list with a self-linked entry so we'll
1181 * not get overrun under high load (as can happen with a
1182 * 5212 when ANI processing enables PHY error frames).
1184 * To insure the last descriptor is self-linked we create
1185 * each descriptor as self-linked and add it to the end. As
1186 * each additional descriptor is added the previous self-linked
1187 * entry is ``fixed'' naturally. This should be safe even
1188 * if DMA is happening. When processing RX interrupts we
1189 * never remove/process the last, self-linked, entry on the
1190 * descriptor list. This insures the hardware always has
1191 * someplace to write a new frame.
1194 ds->ds_link = bf->daddr; /* link to self */
1195 ds->ds_data = bf->skbaddr;
1196 ath5k_hw_setup_rx_desc(ah, ds,
1197 skb_tailroom(skb), /* buffer size */
1200 if (sc->rxlink != NULL)
1201 *sc->rxlink = bf->daddr;
1202 sc->rxlink = &ds->ds_link;
1207 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1209 struct ath5k_hw *ah = sc->ah;
1210 struct ath5k_txq *txq = sc->txq;
1211 struct ath5k_desc *ds = bf->desc;
1212 struct sk_buff *skb = bf->skb;
1213 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1214 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1217 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1219 /* XXX endianness */
1220 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1223 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1224 flags |= AR5K_TXDESC_NOACK;
1228 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
1229 keyidx = info->control.hw_key->hw_key_idx;
1230 pktlen += info->control.icv_len;
1232 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1233 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1234 (sc->power_level * 2),
1235 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1236 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1241 ds->ds_data = bf->skbaddr;
1243 spin_lock_bh(&txq->lock);
1244 list_add_tail(&bf->list, &txq->q);
1245 sc->tx_stats[txq->qnum].len++;
1246 if (txq->link == NULL) /* is this first packet? */
1247 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1248 else /* no, so only link it */
1249 *txq->link = bf->daddr;
1251 txq->link = &ds->ds_link;
1252 ath5k_hw_tx_start(ah, txq->qnum);
1253 spin_unlock_bh(&txq->lock);
1257 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1261 /*******************\
1262 * Descriptors setup *
1263 \*******************/
1266 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1268 struct ath5k_desc *ds;
1269 struct ath5k_buf *bf;
1274 /* allocate descriptors */
1275 sc->desc_len = sizeof(struct ath5k_desc) *
1276 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1277 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1278 if (sc->desc == NULL) {
1279 ATH5K_ERR(sc, "can't allocate descriptors\n");
1284 da = sc->desc_daddr;
1285 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1286 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1288 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1289 sizeof(struct ath5k_buf), GFP_KERNEL);
1291 ATH5K_ERR(sc, "can't allocate bufptr\n");
1297 INIT_LIST_HEAD(&sc->rxbuf);
1298 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1301 list_add_tail(&bf->list, &sc->rxbuf);
1304 INIT_LIST_HEAD(&sc->txbuf);
1305 sc->txbuf_len = ATH_TXBUF;
1306 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1307 da += sizeof(*ds)) {
1310 list_add_tail(&bf->list, &sc->txbuf);
1320 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1327 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1329 struct ath5k_buf *bf;
1331 ath5k_txbuf_free(sc, sc->bbuf);
1332 list_for_each_entry(bf, &sc->txbuf, list)
1333 ath5k_txbuf_free(sc, bf);
1334 list_for_each_entry(bf, &sc->rxbuf, list)
1335 ath5k_txbuf_free(sc, bf);
1337 /* Free memory associated with all descriptors */
1338 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1352 static struct ath5k_txq *
1353 ath5k_txq_setup(struct ath5k_softc *sc,
1354 int qtype, int subtype)
1356 struct ath5k_hw *ah = sc->ah;
1357 struct ath5k_txq *txq;
1358 struct ath5k_txq_info qi = {
1359 .tqi_subtype = subtype,
1360 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1361 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1362 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1367 * Enable interrupts only for EOL and DESC conditions.
1368 * We mark tx descriptors to receive a DESC interrupt
1369 * when a tx queue gets deep; otherwise waiting for the
1370 * EOL to reap descriptors. Note that this is done to
1371 * reduce interrupt load and this only defers reaping
1372 * descriptors, never transmitting frames. Aside from
1373 * reducing interrupts this also permits more concurrency.
1374 * The only potential downside is if the tx queue backs
1375 * up in which case the top half of the kernel may backup
1376 * due to a lack of tx descriptors.
1378 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1379 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1380 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1383 * NB: don't print a message, this happens
1384 * normally on parts with too few tx queues
1386 return ERR_PTR(qnum);
1388 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1389 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1390 qnum, ARRAY_SIZE(sc->txqs));
1391 ath5k_hw_release_tx_queue(ah, qnum);
1392 return ERR_PTR(-EINVAL);
1394 txq = &sc->txqs[qnum];
1398 INIT_LIST_HEAD(&txq->q);
1399 spin_lock_init(&txq->lock);
1402 return &sc->txqs[qnum];
1406 ath5k_beaconq_setup(struct ath5k_hw *ah)
1408 struct ath5k_txq_info qi = {
1409 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1410 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1411 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1412 /* NB: for dynamic turbo, don't enable any other interrupts */
1413 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1416 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1420 ath5k_beaconq_config(struct ath5k_softc *sc)
1422 struct ath5k_hw *ah = sc->ah;
1423 struct ath5k_txq_info qi;
1426 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1429 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
1431 * Always burst out beacon and CAB traffic
1432 * (aifs = cwmin = cwmax = 0)
1437 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1439 * Adhoc mode; backoff between 0 and (2 * cw_min).
1443 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1446 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1447 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1448 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1450 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1452 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1453 "hardware queue!\n", __func__);
1457 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1461 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1463 struct ath5k_buf *bf, *bf0;
1466 * NB: this assumes output has been stopped and
1467 * we do not need to block ath5k_tx_tasklet
1469 spin_lock_bh(&txq->lock);
1470 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1471 ath5k_debug_printtxbuf(sc, bf);
1473 ath5k_txbuf_free(sc, bf);
1475 spin_lock_bh(&sc->txbuflock);
1476 sc->tx_stats[txq->qnum].len--;
1477 list_move_tail(&bf->list, &sc->txbuf);
1479 spin_unlock_bh(&sc->txbuflock);
1482 spin_unlock_bh(&txq->lock);
1486 * Drain the transmit queues and reclaim resources.
1489 ath5k_txq_cleanup(struct ath5k_softc *sc)
1491 struct ath5k_hw *ah = sc->ah;
1494 /* XXX return value */
1495 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1496 /* don't touch the hardware if marked invalid */
1497 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1498 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1499 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1500 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1501 if (sc->txqs[i].setup) {
1502 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1503 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1506 ath5k_hw_get_tx_buf(ah,
1511 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1513 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1514 if (sc->txqs[i].setup)
1515 ath5k_txq_drainq(sc, &sc->txqs[i]);
1519 ath5k_txq_release(struct ath5k_softc *sc)
1521 struct ath5k_txq *txq = sc->txqs;
1524 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1526 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1539 * Enable the receive h/w following a reset.
1542 ath5k_rx_start(struct ath5k_softc *sc)
1544 struct ath5k_hw *ah = sc->ah;
1545 struct ath5k_buf *bf;
1548 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1550 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1551 sc->cachelsz, sc->rxbufsize);
1555 spin_lock_bh(&sc->rxbuflock);
1556 list_for_each_entry(bf, &sc->rxbuf, list) {
1557 ret = ath5k_rxbuf_setup(sc, bf);
1559 spin_unlock_bh(&sc->rxbuflock);
1563 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1564 spin_unlock_bh(&sc->rxbuflock);
1566 ath5k_hw_put_rx_buf(ah, bf->daddr);
1567 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1568 ath5k_mode_setup(sc); /* set filters, etc. */
1569 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1577 * Disable the receive h/w in preparation for a reset.
1580 ath5k_rx_stop(struct ath5k_softc *sc)
1582 struct ath5k_hw *ah = sc->ah;
1584 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1585 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1586 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1587 mdelay(3); /* 3ms is long enough for 1 frame */
1589 ath5k_debug_printrxbuffs(sc, ah);
1591 sc->rxlink = NULL; /* just in case */
1595 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1596 struct sk_buff *skb, struct ath5k_rx_status *rs)
1598 struct ieee80211_hdr *hdr = (void *)skb->data;
1599 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1601 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1602 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1603 return RX_FLAG_DECRYPTED;
1605 /* Apparently when a default key is used to decrypt the packet
1606 the hw does not set the index used to decrypt. In such cases
1607 get the index from the packet. */
1608 if (ieee80211_has_protected(hdr->frame_control) &&
1609 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1610 skb->len >= hlen + 4) {
1611 keyix = skb->data[hlen + 3] >> 6;
1613 if (test_bit(keyix, sc->keymap))
1614 return RX_FLAG_DECRYPTED;
1622 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1623 struct ieee80211_rx_status *rxs)
1627 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1629 if (ieee80211_is_beacon(mgmt->frame_control) &&
1630 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1631 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1633 * Received an IBSS beacon with the same BSSID. Hardware *must*
1634 * have updated the local TSF. We have to work around various
1635 * hardware bugs, though...
1637 tsf = ath5k_hw_get_tsf64(sc->ah);
1638 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1639 hw_tu = TSF_TO_TU(tsf);
1641 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1642 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1643 (unsigned long long)bc_tstamp,
1644 (unsigned long long)rxs->mactime,
1645 (unsigned long long)(rxs->mactime - bc_tstamp),
1646 (unsigned long long)tsf);
1649 * Sometimes the HW will give us a wrong tstamp in the rx
1650 * status, causing the timestamp extension to go wrong.
1651 * (This seems to happen especially with beacon frames bigger
1652 * than 78 byte (incl. FCS))
1653 * But we know that the receive timestamp must be later than the
1654 * timestamp of the beacon since HW must have synced to that.
1656 * NOTE: here we assume mactime to be after the frame was
1657 * received, not like mac80211 which defines it at the start.
1659 if (bc_tstamp > rxs->mactime) {
1660 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1661 "fixing mactime from %llx to %llx\n",
1662 (unsigned long long)rxs->mactime,
1663 (unsigned long long)tsf);
1668 * Local TSF might have moved higher than our beacon timers,
1669 * in that case we have to update them to continue sending
1670 * beacons. This also takes care of synchronizing beacon sending
1671 * times with other stations.
1673 if (hw_tu >= sc->nexttbtt)
1674 ath5k_beacon_update_timers(sc, bc_tstamp);
1680 ath5k_tasklet_rx(unsigned long data)
1682 struct ieee80211_rx_status rxs = {};
1683 struct ath5k_rx_status rs = {};
1684 struct sk_buff *skb;
1685 struct ath5k_softc *sc = (void *)data;
1686 struct ath5k_buf *bf;
1687 struct ath5k_desc *ds;
1692 spin_lock(&sc->rxbuflock);
1696 if (unlikely(list_empty(&sc->rxbuf))) {
1697 ATH5K_WARN(sc, "empty rx buf pool\n");
1700 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1701 BUG_ON(bf->skb == NULL);
1705 /* TODO only one segment */
1706 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1707 sc->desc_len, PCI_DMA_FROMDEVICE);
1709 if (unlikely(ds->ds_link == bf->daddr)) /* this is the end */
1712 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1713 if (unlikely(ret == -EINPROGRESS))
1715 else if (unlikely(ret)) {
1716 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1717 spin_unlock(&sc->rxbuflock);
1721 if (unlikely(rs.rs_more)) {
1722 ATH5K_WARN(sc, "unsupported jumbo\n");
1726 if (unlikely(rs.rs_status)) {
1727 if (rs.rs_status & AR5K_RXERR_PHY)
1729 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1731 * Decrypt error. If the error occurred
1732 * because there was no hardware key, then
1733 * let the frame through so the upper layers
1734 * can process it. This is necessary for 5210
1735 * parts which have no way to setup a ``clear''
1738 * XXX do key cache faulting
1740 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1741 !(rs.rs_status & AR5K_RXERR_CRC))
1744 if (rs.rs_status & AR5K_RXERR_MIC) {
1745 rxs.flag |= RX_FLAG_MMIC_ERROR;
1749 /* let crypto-error packets fall through in MNTR */
1751 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1752 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1756 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr,
1757 rs.rs_datalen, PCI_DMA_FROMDEVICE);
1758 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1759 PCI_DMA_FROMDEVICE);
1762 skb_put(skb, rs.rs_datalen);
1765 * the hardware adds a padding to 4 byte boundaries between
1766 * the header and the payload data if the header length is
1767 * not multiples of 4 - remove it
1769 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1772 memmove(skb->data + pad, skb->data, hdrlen);
1777 * always extend the mac timestamp, since this information is
1778 * also needed for proper IBSS merging.
1780 * XXX: it might be too late to do it here, since rs_tstamp is
1781 * 15bit only. that means TSF extension has to be done within
1782 * 32768usec (about 32ms). it might be necessary to move this to
1783 * the interrupt handler, like it is done in madwifi.
1785 * Unfortunately we don't know when the hardware takes the rx
1786 * timestamp (beginning of phy frame, data frame, end of rx?).
1787 * The only thing we know is that it is hardware specific...
1788 * On AR5213 it seems the rx timestamp is at the end of the
1789 * frame, but i'm not sure.
1791 * NOTE: mac80211 defines mactime at the beginning of the first
1792 * data symbol. Since we don't have any time references it's
1793 * impossible to comply to that. This affects IBSS merge only
1794 * right now, so it's not too bad...
1796 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1797 rxs.flag |= RX_FLAG_TSFT;
1799 rxs.freq = sc->curchan->center_freq;
1800 rxs.band = sc->curband->band;
1802 rxs.noise = sc->ah->ah_noise_floor;
1803 rxs.signal = rxs.noise + rs.rs_rssi;
1804 rxs.qual = rs.rs_rssi * 100 / 64;
1806 rxs.antenna = rs.rs_antenna;
1807 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1808 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1810 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1812 /* check beacons in IBSS mode */
1813 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1814 ath5k_check_ibss_tsf(sc, skb, &rxs);
1816 __ieee80211_rx(sc->hw, skb, &rxs);
1818 list_move_tail(&bf->list, &sc->rxbuf);
1819 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1820 spin_unlock(&sc->rxbuflock);
1831 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1833 struct ath5k_tx_status ts = {};
1834 struct ath5k_buf *bf, *bf0;
1835 struct ath5k_desc *ds;
1836 struct sk_buff *skb;
1837 struct ieee80211_tx_info *info;
1840 spin_lock(&txq->lock);
1841 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1844 /* TODO only one segment */
1845 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1846 sc->desc_len, PCI_DMA_FROMDEVICE);
1847 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1848 if (unlikely(ret == -EINPROGRESS))
1850 else if (unlikely(ret)) {
1851 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1857 info = IEEE80211_SKB_CB(skb);
1860 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1863 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1864 if (unlikely(ts.ts_status)) {
1865 sc->ll_stats.dot11ACKFailureCount++;
1866 if (ts.ts_status & AR5K_TXERR_XRETRY)
1867 info->status.excessive_retries = 1;
1868 else if (ts.ts_status & AR5K_TXERR_FILT)
1869 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1871 info->flags |= IEEE80211_TX_STAT_ACK;
1872 info->status.ack_signal = ts.ts_rssi;
1875 ieee80211_tx_status(sc->hw, skb);
1876 sc->tx_stats[txq->qnum].count++;
1878 spin_lock(&sc->txbuflock);
1879 sc->tx_stats[txq->qnum].len--;
1880 list_move_tail(&bf->list, &sc->txbuf);
1882 spin_unlock(&sc->txbuflock);
1884 if (likely(list_empty(&txq->q)))
1886 spin_unlock(&txq->lock);
1887 if (sc->txbuf_len > ATH_TXBUF / 5)
1888 ieee80211_wake_queues(sc->hw);
1892 ath5k_tasklet_tx(unsigned long data)
1894 struct ath5k_softc *sc = (void *)data;
1896 ath5k_tx_processq(sc, sc->txq);
1905 * Setup the beacon frame for transmit.
1908 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1910 struct sk_buff *skb = bf->skb;
1911 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1912 struct ath5k_hw *ah = sc->ah;
1913 struct ath5k_desc *ds;
1914 int ret, antenna = 0;
1917 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1919 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1920 "skbaddr %llx\n", skb, skb->data, skb->len,
1921 (unsigned long long)bf->skbaddr);
1922 if (pci_dma_mapping_error(bf->skbaddr)) {
1923 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1929 flags = AR5K_TXDESC_NOACK;
1930 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1931 ds->ds_link = bf->daddr; /* self-linked */
1932 flags |= AR5K_TXDESC_VEOL;
1934 * Let hardware handle antenna switching if txantenna is not set
1939 * Switch antenna every 4 beacons if txantenna is not set
1940 * XXX assumes two antennas
1943 antenna = sc->bsent & 4 ? 2 : 1;
1946 ds->ds_data = bf->skbaddr;
1947 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1948 ieee80211_get_hdrlen_from_skb(skb),
1949 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1950 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1951 1, AR5K_TXKEYIX_INVALID,
1952 antenna, flags, 0, 0);
1958 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1963 * Transmit a beacon frame at SWBA. Dynamic updates to the
1964 * frame contents are done as needed and the slot time is
1965 * also adjusted based on current state.
1967 * this is usually called from interrupt context (ath5k_intr())
1968 * but also from ath5k_beacon_config() in IBSS mode which in turn
1969 * can be called from a tasklet and user context
1972 ath5k_beacon_send(struct ath5k_softc *sc)
1974 struct ath5k_buf *bf = sc->bbuf;
1975 struct ath5k_hw *ah = sc->ah;
1977 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1979 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1980 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1981 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1985 * Check if the previous beacon has gone out. If
1986 * not don't don't try to post another, skip this
1987 * period and wait for the next. Missed beacons
1988 * indicate a problem and should not occur. If we
1989 * miss too many consecutive beacons reset the device.
1991 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1993 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1994 "missed %u consecutive beacons\n", sc->bmisscount);
1995 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
1996 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1997 "stuck beacon time (%u missed)\n",
1999 tasklet_schedule(&sc->restq);
2003 if (unlikely(sc->bmisscount != 0)) {
2004 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2005 "resume beacon xmit after %u misses\n",
2011 * Stop any current dma and put the new frame on the queue.
2012 * This should never fail since we check above that no frames
2013 * are still pending on the queue.
2015 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2016 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2017 /* NB: hw still stops DMA, so proceed */
2019 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2022 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2023 ath5k_hw_tx_start(ah, sc->bhalq);
2024 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2025 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2032 * ath5k_beacon_update_timers - update beacon timers
2034 * @sc: struct ath5k_softc pointer we are operating on
2035 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2036 * beacon timer update based on the current HW TSF.
2038 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2039 * of a received beacon or the current local hardware TSF and write it to the
2040 * beacon timer registers.
2042 * This is called in a variety of situations, e.g. when a beacon is received,
2043 * when a TSF update has been detected, but also when an new IBSS is created or
2044 * when we otherwise know we have to update the timers, but we keep it in this
2045 * function to have it all together in one place.
2048 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2050 struct ath5k_hw *ah = sc->ah;
2051 u32 nexttbtt, intval, hw_tu, bc_tu;
2054 intval = sc->bintval & AR5K_BEACON_PERIOD;
2055 if (WARN_ON(!intval))
2058 /* beacon TSF converted to TU */
2059 bc_tu = TSF_TO_TU(bc_tsf);
2061 /* current TSF converted to TU */
2062 hw_tsf = ath5k_hw_get_tsf64(ah);
2063 hw_tu = TSF_TO_TU(hw_tsf);
2066 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2069 * no beacons received, called internally.
2070 * just need to refresh timers based on HW TSF.
2072 nexttbtt = roundup(hw_tu + FUDGE, intval);
2073 } else if (bc_tsf == 0) {
2075 * no beacon received, probably called by ath5k_reset_tsf().
2076 * reset TSF to start with 0.
2079 intval |= AR5K_BEACON_RESET_TSF;
2080 } else if (bc_tsf > hw_tsf) {
2082 * beacon received, SW merge happend but HW TSF not yet updated.
2083 * not possible to reconfigure timers yet, but next time we
2084 * receive a beacon with the same BSSID, the hardware will
2085 * automatically update the TSF and then we need to reconfigure
2088 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2089 "need to wait for HW TSF sync\n");
2093 * most important case for beacon synchronization between STA.
2095 * beacon received and HW TSF has been already updated by HW.
2096 * update next TBTT based on the TSF of the beacon, but make
2097 * sure it is ahead of our local TSF timer.
2099 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2103 sc->nexttbtt = nexttbtt;
2105 intval |= AR5K_BEACON_ENA;
2106 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2109 * debugging output last in order to preserve the time critical aspect
2113 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2114 "reconfigured timers based on HW TSF\n");
2115 else if (bc_tsf == 0)
2116 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2117 "reset HW TSF and timers\n");
2119 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2120 "updated timers based on beacon TSF\n");
2122 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2123 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2124 (unsigned long long) bc_tsf,
2125 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2126 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2127 intval & AR5K_BEACON_PERIOD,
2128 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2129 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2134 * ath5k_beacon_config - Configure the beacon queues and interrupts
2136 * @sc: struct ath5k_softc pointer we are operating on
2138 * When operating in station mode we want to receive a BMISS interrupt when we
2139 * stop seeing beacons from the AP we've associated with so we can look for
2140 * another AP to associate with.
2142 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2143 * interrupts to detect TSF updates only.
2145 * AP mode is missing.
2148 ath5k_beacon_config(struct ath5k_softc *sc)
2150 struct ath5k_hw *ah = sc->ah;
2152 ath5k_hw_set_intr(ah, 0);
2155 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2156 sc->imask |= AR5K_INT_BMISS;
2157 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2159 * In IBSS mode we use a self-linked tx descriptor and let the
2160 * hardware send the beacons automatically. We have to load it
2162 * We use the SWBA interrupt only to keep track of the beacon
2163 * timers in order to detect automatic TSF updates.
2165 ath5k_beaconq_config(sc);
2167 sc->imask |= AR5K_INT_SWBA;
2169 if (ath5k_hw_hasveol(ah))
2170 ath5k_beacon_send(sc);
2174 ath5k_hw_set_intr(ah, sc->imask);
2178 /********************\
2179 * Interrupt handling *
2180 \********************/
2183 ath5k_init(struct ath5k_softc *sc)
2187 mutex_lock(&sc->lock);
2189 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2192 * Stop anything previously setup. This is safe
2193 * no matter this is the first time through or not.
2195 ath5k_stop_locked(sc);
2198 * The basic interface to setting the hardware in a good
2199 * state is ``reset''. On return the hardware is known to
2200 * be powered up and with interrupts disabled. This must
2201 * be followed by initialization of the appropriate bits
2202 * and then setup of the interrupt mask.
2204 sc->curchan = sc->hw->conf.channel;
2205 sc->curband = &sc->sbands[sc->curchan->band];
2206 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2208 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2212 * This is needed only to setup initial state
2213 * but it's best done after a reset.
2215 ath5k_hw_set_txpower_limit(sc->ah, 0);
2218 * Setup the hardware after reset: the key cache
2219 * is filled as needed and the receive engine is
2220 * set going. Frame transmit is handled entirely
2221 * in the frame output path; there's nothing to do
2222 * here except setup the interrupt mask.
2224 ret = ath5k_rx_start(sc);
2229 * Enable interrupts.
2231 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2232 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2235 ath5k_hw_set_intr(sc->ah, sc->imask);
2236 /* Set ack to be sent at low bit-rates */
2237 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2239 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2240 msecs_to_jiffies(ath5k_calinterval * 1000)));
2244 mutex_unlock(&sc->lock);
2249 ath5k_stop_locked(struct ath5k_softc *sc)
2251 struct ath5k_hw *ah = sc->ah;
2253 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2254 test_bit(ATH_STAT_INVALID, sc->status));
2257 * Shutdown the hardware and driver:
2258 * stop output from above
2259 * disable interrupts
2261 * turn off the radio
2262 * clear transmit machinery
2263 * clear receive machinery
2264 * drain and release tx queues
2265 * reclaim beacon resources
2266 * power down hardware
2268 * Note that some of this work is not possible if the
2269 * hardware is gone (invalid).
2271 ieee80211_stop_queues(sc->hw);
2273 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2275 ath5k_hw_set_intr(ah, 0);
2277 ath5k_txq_cleanup(sc);
2278 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2280 ath5k_hw_phy_disable(ah);
2288 * Stop the device, grabbing the top-level lock to protect
2289 * against concurrent entry through ath5k_init (which can happen
2290 * if another thread does a system call and the thread doing the
2291 * stop is preempted).
2294 ath5k_stop_hw(struct ath5k_softc *sc)
2298 mutex_lock(&sc->lock);
2299 ret = ath5k_stop_locked(sc);
2300 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2302 * Set the chip in full sleep mode. Note that we are
2303 * careful to do this only when bringing the interface
2304 * completely to a stop. When the chip is in this state
2305 * it must be carefully woken up or references to
2306 * registers in the PCI clock domain may freeze the bus
2307 * (and system). This varies by chip and is mostly an
2308 * issue with newer parts that go to sleep more quickly.
2310 if (sc->ah->ah_mac_srev >= 0x78) {
2313 * don't put newer MAC revisions > 7.8 to sleep because
2314 * of the above mentioned problems
2316 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2317 "not putting device to sleep\n");
2319 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2320 "putting device to full sleep\n");
2321 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2324 ath5k_txbuf_free(sc, sc->bbuf);
2325 mutex_unlock(&sc->lock);
2327 del_timer_sync(&sc->calib_tim);
2333 ath5k_intr(int irq, void *dev_id)
2335 struct ath5k_softc *sc = dev_id;
2336 struct ath5k_hw *ah = sc->ah;
2337 enum ath5k_int status;
2338 unsigned int counter = 1000;
2340 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2341 !ath5k_hw_is_intr_pending(ah)))
2346 * Figure out the reason(s) for the interrupt. Note
2347 * that get_isr returns a pseudo-ISR that may include
2348 * bits we haven't explicitly enabled so we mask the
2349 * value to insure we only process bits we requested.
2351 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2352 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2354 status &= sc->imask; /* discard unasked for bits */
2355 if (unlikely(status & AR5K_INT_FATAL)) {
2357 * Fatal errors are unrecoverable.
2358 * Typically these are caused by DMA errors.
2360 tasklet_schedule(&sc->restq);
2361 } else if (unlikely(status & AR5K_INT_RXORN)) {
2362 tasklet_schedule(&sc->restq);
2364 if (status & AR5K_INT_SWBA) {
2366 * Software beacon alert--time to send a beacon.
2367 * Handle beacon transmission directly; deferring
2368 * this is too slow to meet timing constraints
2371 * In IBSS mode we use this interrupt just to
2372 * keep track of the next TBTT (target beacon
2373 * transmission time) in order to detect wether
2374 * automatic TSF updates happened.
2376 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2377 /* XXX: only if VEOL suppported */
2378 u64 tsf = ath5k_hw_get_tsf64(ah);
2379 sc->nexttbtt += sc->bintval;
2380 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2381 "SWBA nexttbtt: %x hw_tu: %x "
2385 (unsigned long long) tsf);
2387 ath5k_beacon_send(sc);
2390 if (status & AR5K_INT_RXEOL) {
2392 * NB: the hardware should re-read the link when
2393 * RXE bit is written, but it doesn't work at
2394 * least on older hardware revs.
2398 if (status & AR5K_INT_TXURN) {
2399 /* bump tx trigger level */
2400 ath5k_hw_update_tx_triglevel(ah, true);
2402 if (status & AR5K_INT_RX)
2403 tasklet_schedule(&sc->rxtq);
2404 if (status & AR5K_INT_TX)
2405 tasklet_schedule(&sc->txtq);
2406 if (status & AR5K_INT_BMISS) {
2408 if (status & AR5K_INT_MIB) {
2410 * These stats are also used for ANI i think
2411 * so how about updating them more often ?
2413 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2416 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2418 if (unlikely(!counter))
2419 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2425 ath5k_tasklet_reset(unsigned long data)
2427 struct ath5k_softc *sc = (void *)data;
2429 ath5k_reset(sc->hw);
2433 * Periodically recalibrate the PHY to account
2434 * for temperature/environment changes.
2437 ath5k_calibrate(unsigned long data)
2439 struct ath5k_softc *sc = (void *)data;
2440 struct ath5k_hw *ah = sc->ah;
2442 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2443 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2444 sc->curchan->hw_value);
2446 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2448 * Rfgain is out of bounds, reset the chip
2449 * to load new gain values.
2451 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2452 ath5k_reset(sc->hw);
2454 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2455 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2456 ieee80211_frequency_to_channel(
2457 sc->curchan->center_freq));
2459 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2460 msecs_to_jiffies(ath5k_calinterval * 1000)));
2470 ath5k_led_enable(struct ath5k_softc *sc)
2472 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2473 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2479 ath5k_led_on(struct ath5k_softc *sc)
2481 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2483 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2487 ath5k_led_off(struct ath5k_softc *sc)
2489 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2491 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2495 ath5k_led_brightness_set(struct led_classdev *led_dev,
2496 enum led_brightness brightness)
2498 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2501 if (brightness == LED_OFF)
2502 ath5k_led_off(led->sc);
2504 ath5k_led_on(led->sc);
2508 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2509 const char *name, char *trigger)
2514 strncpy(led->name, name, sizeof(led->name));
2515 led->led_dev.name = led->name;
2516 led->led_dev.default_trigger = trigger;
2517 led->led_dev.brightness_set = ath5k_led_brightness_set;
2519 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2522 ATH5K_WARN(sc, "could not register LED %s\n", name);
2529 ath5k_unregister_led(struct ath5k_led *led)
2533 led_classdev_unregister(&led->led_dev);
2534 ath5k_led_off(led->sc);
2539 ath5k_unregister_leds(struct ath5k_softc *sc)
2541 ath5k_unregister_led(&sc->rx_led);
2542 ath5k_unregister_led(&sc->tx_led);
2547 ath5k_init_leds(struct ath5k_softc *sc)
2550 struct ieee80211_hw *hw = sc->hw;
2551 struct pci_dev *pdev = sc->pdev;
2552 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2554 sc->led_on = 0; /* active low */
2557 * Auto-enable soft led processing for IBM cards and for
2558 * 5211 minipci cards.
2560 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2561 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2562 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2565 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2566 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2567 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2570 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2573 ath5k_led_enable(sc);
2575 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2576 ret = ath5k_register_led(sc, &sc->rx_led, name,
2577 ieee80211_get_rx_led_name(hw));
2581 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2582 ret = ath5k_register_led(sc, &sc->tx_led, name,
2583 ieee80211_get_tx_led_name(hw));
2589 /********************\
2590 * Mac80211 functions *
2591 \********************/
2594 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2596 struct ath5k_softc *sc = hw->priv;
2597 struct ath5k_buf *bf;
2598 unsigned long flags;
2602 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2604 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2605 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2608 * the hardware expects the header padded to 4 byte boundaries
2609 * if this is not the case we add the padding after the header
2611 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2614 if (skb_headroom(skb) < pad) {
2615 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2616 " headroom to pad %d\n", hdrlen, pad);
2620 memmove(skb->data, skb->data+pad, hdrlen);
2623 spin_lock_irqsave(&sc->txbuflock, flags);
2624 if (list_empty(&sc->txbuf)) {
2625 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2626 spin_unlock_irqrestore(&sc->txbuflock, flags);
2627 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2630 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2631 list_del(&bf->list);
2633 if (list_empty(&sc->txbuf))
2634 ieee80211_stop_queues(hw);
2635 spin_unlock_irqrestore(&sc->txbuflock, flags);
2639 if (ath5k_txbuf_setup(sc, bf)) {
2641 spin_lock_irqsave(&sc->txbuflock, flags);
2642 list_add_tail(&bf->list, &sc->txbuf);
2644 spin_unlock_irqrestore(&sc->txbuflock, flags);
2645 dev_kfree_skb_any(skb);
2653 ath5k_reset(struct ieee80211_hw *hw)
2655 struct ath5k_softc *sc = hw->priv;
2656 struct ath5k_hw *ah = sc->ah;
2659 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2661 ath5k_hw_set_intr(ah, 0);
2662 ath5k_txq_cleanup(sc);
2665 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2666 if (unlikely(ret)) {
2667 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2670 ath5k_hw_set_txpower_limit(sc->ah, 0);
2672 ret = ath5k_rx_start(sc);
2673 if (unlikely(ret)) {
2674 ATH5K_ERR(sc, "can't start recv logic\n");
2678 * We may be doing a reset in response to an ioctl
2679 * that changes the channel so update any state that
2680 * might change as a result.
2684 /* ath5k_chan_change(sc, c); */
2685 ath5k_beacon_config(sc);
2686 /* intrs are started by ath5k_beacon_config */
2688 ieee80211_wake_queues(hw);
2695 static int ath5k_start(struct ieee80211_hw *hw)
2697 return ath5k_init(hw->priv);
2700 static void ath5k_stop(struct ieee80211_hw *hw)
2702 ath5k_stop_hw(hw->priv);
2705 static int ath5k_add_interface(struct ieee80211_hw *hw,
2706 struct ieee80211_if_init_conf *conf)
2708 struct ath5k_softc *sc = hw->priv;
2711 mutex_lock(&sc->lock);
2717 sc->vif = conf->vif;
2719 switch (conf->type) {
2720 case IEEE80211_IF_TYPE_STA:
2721 case IEEE80211_IF_TYPE_IBSS:
2722 case IEEE80211_IF_TYPE_MNTR:
2723 sc->opmode = conf->type;
2731 mutex_unlock(&sc->lock);
2736 ath5k_remove_interface(struct ieee80211_hw *hw,
2737 struct ieee80211_if_init_conf *conf)
2739 struct ath5k_softc *sc = hw->priv;
2741 mutex_lock(&sc->lock);
2742 if (sc->vif != conf->vif)
2747 mutex_unlock(&sc->lock);
2751 * TODO: Phy disable/diversity etc
2754 ath5k_config(struct ieee80211_hw *hw,
2755 struct ieee80211_conf *conf)
2757 struct ath5k_softc *sc = hw->priv;
2759 sc->bintval = conf->beacon_int;
2760 sc->power_level = conf->power_level;
2762 return ath5k_chan_set(sc, conf->channel);
2766 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2767 struct ieee80211_if_conf *conf)
2769 struct ath5k_softc *sc = hw->priv;
2770 struct ath5k_hw *ah = sc->ah;
2773 /* Set to a reasonable value. Note that this will
2774 * be set to mac80211's value at ath5k_config(). */
2776 mutex_lock(&sc->lock);
2777 if (sc->vif != vif) {
2782 /* Cache for later use during resets */
2783 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2784 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2785 * a clean way of letting us retrieve this yet. */
2786 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2788 mutex_unlock(&sc->lock);
2790 return ath5k_reset(hw);
2792 mutex_unlock(&sc->lock);
2796 #define SUPPORTED_FIF_FLAGS \
2797 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2798 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2799 FIF_BCN_PRBRESP_PROMISC
2801 * o always accept unicast, broadcast, and multicast traffic
2802 * o multicast traffic for all BSSIDs will be enabled if mac80211
2804 * o maintain current state of phy ofdm or phy cck error reception.
2805 * If the hardware detects any of these type of errors then
2806 * ath5k_hw_get_rx_filter() will pass to us the respective
2807 * hardware filters to be able to receive these type of frames.
2808 * o probe request frames are accepted only when operating in
2809 * hostap, adhoc, or monitor modes
2810 * o enable promiscuous mode according to the interface state
2812 * - when operating in adhoc mode so the 802.11 layer creates
2813 * node table entries for peers,
2814 * - when operating in station mode for collecting rssi data when
2815 * the station is otherwise quiet, or
2818 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2819 unsigned int changed_flags,
2820 unsigned int *new_flags,
2821 int mc_count, struct dev_mc_list *mclist)
2823 struct ath5k_softc *sc = hw->priv;
2824 struct ath5k_hw *ah = sc->ah;
2825 u32 mfilt[2], val, rfilt;
2832 /* Only deal with supported flags */
2833 changed_flags &= SUPPORTED_FIF_FLAGS;
2834 *new_flags &= SUPPORTED_FIF_FLAGS;
2836 /* If HW detects any phy or radar errors, leave those filters on.
2837 * Also, always enable Unicast, Broadcasts and Multicast
2838 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2839 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2840 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2841 AR5K_RX_FILTER_MCAST);
2843 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2844 if (*new_flags & FIF_PROMISC_IN_BSS) {
2845 rfilt |= AR5K_RX_FILTER_PROM;
2846 __set_bit(ATH_STAT_PROMISC, sc->status);
2849 __clear_bit(ATH_STAT_PROMISC, sc->status);
2852 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2853 if (*new_flags & FIF_ALLMULTI) {
2857 for (i = 0; i < mc_count; i++) {
2860 /* calculate XOR of eight 6-bit values */
2861 val = get_unaligned_le32(mclist->dmi_addr + 0);
2862 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2863 val = get_unaligned_le32(mclist->dmi_addr + 3);
2864 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2866 mfilt[pos / 32] |= (1 << (pos % 32));
2867 /* XXX: we might be able to just do this instead,
2868 * but not sure, needs testing, if we do use this we'd
2869 * neet to inform below to not reset the mcast */
2870 /* ath5k_hw_set_mcast_filterindex(ah,
2871 * mclist->dmi_addr[5]); */
2872 mclist = mclist->next;
2876 /* This is the best we can do */
2877 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2878 rfilt |= AR5K_RX_FILTER_PHYERR;
2880 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2881 * and probes for any BSSID, this needs testing */
2882 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2883 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2885 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2886 * set we should only pass on control frames for this
2887 * station. This needs testing. I believe right now this
2888 * enables *all* control frames, which is OK.. but
2889 * but we should see if we can improve on granularity */
2890 if (*new_flags & FIF_CONTROL)
2891 rfilt |= AR5K_RX_FILTER_CONTROL;
2893 /* Additional settings per mode -- this is per ath5k */
2895 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2897 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2898 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2899 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2900 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2901 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2902 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2903 test_bit(ATH_STAT_PROMISC, sc->status))
2904 rfilt |= AR5K_RX_FILTER_PROM;
2905 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2906 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2907 rfilt |= AR5K_RX_FILTER_BEACON;
2911 ath5k_hw_set_rx_filter(ah,rfilt);
2913 /* Set multicast bits */
2914 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2915 /* Set the cached hw filter flags, this will alter actually
2917 sc->filter_flags = rfilt;
2921 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2922 const u8 *local_addr, const u8 *addr,
2923 struct ieee80211_key_conf *key)
2925 struct ath5k_softc *sc = hw->priv;
2930 /* XXX: fix hardware encryption, its not working. For now
2931 * allow software encryption */
2941 mutex_lock(&sc->lock);
2945 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2947 ATH5K_ERR(sc, "can't set the key\n");
2950 __set_bit(key->keyidx, sc->keymap);
2951 key->hw_key_idx = key->keyidx;
2954 ath5k_hw_reset_key(sc->ah, key->keyidx);
2955 __clear_bit(key->keyidx, sc->keymap);
2963 mutex_unlock(&sc->lock);
2968 ath5k_get_stats(struct ieee80211_hw *hw,
2969 struct ieee80211_low_level_stats *stats)
2971 struct ath5k_softc *sc = hw->priv;
2972 struct ath5k_hw *ah = sc->ah;
2975 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2977 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2983 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2984 struct ieee80211_tx_queue_stats *stats)
2986 struct ath5k_softc *sc = hw->priv;
2988 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2994 ath5k_get_tsf(struct ieee80211_hw *hw)
2996 struct ath5k_softc *sc = hw->priv;
2998 return ath5k_hw_get_tsf64(sc->ah);
3002 ath5k_reset_tsf(struct ieee80211_hw *hw)
3004 struct ath5k_softc *sc = hw->priv;
3007 * in IBSS mode we need to update the beacon timers too.
3008 * this will also reset the TSF if we call it with 0
3010 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3011 ath5k_beacon_update_timers(sc, 0);
3013 ath5k_hw_reset_tsf(sc->ah);
3017 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
3019 struct ath5k_softc *sc = hw->priv;
3022 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3024 mutex_lock(&sc->lock);
3026 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3031 ath5k_txbuf_free(sc, sc->bbuf);
3032 sc->bbuf->skb = skb;
3033 ret = ath5k_beacon_setup(sc, sc->bbuf);
3035 sc->bbuf->skb = NULL;
3037 ath5k_beacon_config(sc);
3040 mutex_unlock(&sc->lock);