err.no Git - linux-2.6/blob - drivers/net/ucc_geth.h

   1 /*
   2  * Copyright (C) Freescale Semicondutor, Inc. 2006. All rights reserved.
   3  *
   4  * Author: Shlomi Gridish <gridish@freescale.com>
   5  *
   6  * Description:
   7  * Internal header file for UCC Gigabit Ethernet unit routines.
   8  *
   9  * Changelog:
  10  * Jun 28, 2006 Li Yang <LeoLi@freescale.com>
  11  * - Rearrange code and style fixes
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18 #ifndef __UCC_GETH_H__
  19 #define __UCC_GETH_H__
  20
  21 #include <linux/kernel.h>
  22 #include <linux/list.h>
  23 #include <linux/fsl_devices.h>
  24
  25 #include <asm/immap_qe.h>
  26 #include <asm/qe.h>
  27
  28 #include <asm/ucc.h>
  29 #include <asm/ucc_fast.h>
  30
  31 #include "ucc_geth_mii.h"
  32
  33 #define NUM_TX_QUEUES                   8
  34 #define NUM_RX_QUEUES                   8
  35 #define NUM_BDS_IN_PREFETCHED_BDS       4
  36 #define TX_IP_OFFSET_ENTRY_MAX          8
  37 #define NUM_OF_PADDRS                   4
  38 #define ENET_INIT_PARAM_MAX_ENTRIES_RX  9
  39 #define ENET_INIT_PARAM_MAX_ENTRIES_TX  8
  40
  41 struct ucc_geth {
  42         struct ucc_fast uccf;
  43
  44         u32 maccfg1;            /* mac configuration reg. 1 */
  45         u32 maccfg2;            /* mac configuration reg. 2 */
  46         u32 ipgifg;             /* interframe gap reg.  */
  47         u32 hafdup;             /* half-duplex reg.  */
  48         u8 res1[0x10];
  49         u8 miimng[0x18];        /* MII management structure moved to _mii.h */
  50         u32 ifctl;              /* interface control reg */
  51         u32 ifstat;             /* interface statux reg */
  52         u32 macstnaddr1;        /* mac station address part 1 reg */
  53         u32 macstnaddr2;        /* mac station address part 2 reg */
  54         u8 res2[0x8];
  55         u32 uempr;              /* UCC Ethernet Mac parameter reg */
  56         u32 utbipar;            /* UCC tbi address reg */
  57         u16 uescr;              /* UCC Ethernet statistics control reg */
  58         u8 res3[0x180 - 0x15A];
  59         u32 tx64;               /* Total number of frames (including bad
  60                                    frames) transmitted that were exactly of the
  61                                    minimal length (64 for un tagged, 68 for
  62                                    tagged, or with length exactly equal to the
  63                                    parameter MINLength */
  64         u32 tx127;              /* Total number of frames (including bad
  65                                    frames) transmitted that were between
  66                                    MINLength (Including FCS length==4) and 127
  67                                    octets */
  68         u32 tx255;              /* Total number of frames (including bad
  69                                    frames) transmitted that were between 128
  70                                    (Including FCS length==4) and 255 octets */
  71         u32 rx64;               /* Total number of frames received including
  72                                    bad frames that were exactly of the mninimal
  73                                    length (64 bytes) */
  74         u32 rx127;              /* Total number of frames (including bad
  75                                    frames) received that were between MINLength
  76                                    (Including FCS length==4) and 127 octets */
  77         u32 rx255;              /* Total number of frames (including bad
  78                                    frames) received that were between 128
  79                                    (Including FCS length==4) and 255 octets */
  80         u32 txok;               /* Total number of octets residing in frames
  81                                    that where involved in succesfull
  82                                    transmission */
  83         u16 txcf;               /* Total number of PAUSE control frames
  84                                    transmitted by this MAC */
  85         u8 res4[0x2];
  86         u32 tmca;               /* Total number of frames that were transmitted
  87                                    succesfully with the group address bit set
  88                                    that are not broadcast frames */
  89         u32 tbca;               /* Total number of frames transmitted
  90                                    succesfully that had destination address
  91                                    field equal to the broadcast address */
  92         u32 rxfok;              /* Total number of frames received OK */
  93         u32 rxbok;              /* Total number of octets received OK */
  94         u32 rbyt;               /* Total number of octets received including
  95                                    octets in bad frames. Must be implemented in
  96                                    HW because it includes octets in frames that
  97                                    never even reach the UCC */
  98         u32 rmca;               /* Total number of frames that were received
  99                                    succesfully with the group address bit set
 100                                    that are not broadcast frames */
 101         u32 rbca;               /* Total number of frames received succesfully
 102                                    that had destination address equal to the
 103                                    broadcast address */
 104         u32 scar;               /* Statistics carry register */
 105         u32 scam;               /* Statistics caryy mask register */
 106         u8 res5[0x200 - 0x1c4];
 107 } __attribute__ ((packed));
 108
 109 /* UCC GETH TEMODR Register */
 110 #define TEMODER_TX_RMON_STATISTICS_ENABLE       0x0100  /* enable Tx statistics
 111                                                          */
 112 #define TEMODER_SCHEDULER_ENABLE                0x2000  /* enable scheduler */
 113 #define TEMODER_IP_CHECKSUM_GENERATE            0x0400  /* generate IPv4
 114                                                            checksums */
 115 #define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1  0x0200  /* enable performance
 116                                                            optimization
 117                                                            enhancement (mode1) */
 118 #define TEMODER_RMON_STATISTICS                 0x0100  /* enable tx statistics
 119                                                          */
 120 #define TEMODER_NUM_OF_QUEUES_SHIFT             (15-15) /* Number of queues <<
 121                                                            shift */
 122
 123 /* UCC GETH TEMODR Register */
 124 #define REMODER_RX_RMON_STATISTICS_ENABLE       0x00001000      /* enable Rx
 125                                                                    statistics */
 126 #define REMODER_RX_EXTENDED_FEATURES            0x80000000      /* enable
 127                                                                    extended
 128                                                                    features */
 129 #define REMODER_VLAN_OPERATION_TAGGED_SHIFT     (31-9 ) /* vlan operation
 130                                                            tagged << shift */
 131 #define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31-10) /* vlan operation non
 132                                                            tagged << shift */
 133 #define REMODER_RX_QOS_MODE_SHIFT               (31-15) /* rx QoS mode << shift
 134                                                          */
 135 #define REMODER_RMON_STATISTICS                 0x00001000      /* enable rx
 136                                                                    statistics */
 137 #define REMODER_RX_EXTENDED_FILTERING           0x00000800      /* extended
 138                                                                    filtering
 139                                                                    vs.
 140                                                                    mpc82xx-like
 141                                                                    filtering */
 142 #define REMODER_NUM_OF_QUEUES_SHIFT             (31-23) /* Number of queues <<
 143                                                            shift */
 144 #define REMODER_DYNAMIC_MAX_FRAME_LENGTH        0x00000008      /* enable
 145                                                                    dynamic max
 146                                                                    frame length
 147                                                                  */
 148 #define REMODER_DYNAMIC_MIN_FRAME_LENGTH        0x00000004      /* enable
 149                                                                    dynamic min
 150                                                                    frame length
 151                                                                  */
 152 #define REMODER_IP_CHECKSUM_CHECK               0x00000002      /* check IPv4
 153                                                                    checksums */
 154 #define REMODER_IP_ADDRESS_ALIGNMENT            0x00000001      /* align ip
 155                                                                    address to
 156                                                                    4-byte
 157                                                                    boundary */
 158
 159 /* UCC GETH Event Register */
 160 #define UCCE_MPD                                0x80000000      /* Magic packet
 161                                                                    detection */
 162 #define UCCE_SCAR                               0x40000000
 163 #define UCCE_GRA                                0x20000000      /* Tx graceful
 164                                                                    stop
 165                                                                    complete */
 166 #define UCCE_CBPR                               0x10000000
 167 #define UCCE_BSY                                0x08000000
 168 #define UCCE_RXC                                0x04000000
 169 #define UCCE_TXC                                0x02000000
 170 #define UCCE_TXE                                0x01000000
 171 #define UCCE_TXB7                               0x00800000
 172 #define UCCE_TXB6                               0x00400000
 173 #define UCCE_TXB5                               0x00200000
 174 #define UCCE_TXB4                               0x00100000
 175 #define UCCE_TXB3                               0x00080000
 176 #define UCCE_TXB2                               0x00040000
 177 #define UCCE_TXB1                               0x00020000
 178 #define UCCE_TXB0                               0x00010000
 179 #define UCCE_RXB7                               0x00008000
 180 #define UCCE_RXB6                               0x00004000
 181 #define UCCE_RXB5                               0x00002000
 182 #define UCCE_RXB4                               0x00001000
 183 #define UCCE_RXB3                               0x00000800
 184 #define UCCE_RXB2                               0x00000400
 185 #define UCCE_RXB1                               0x00000200
 186 #define UCCE_RXB0                               0x00000100
 187 #define UCCE_RXF7                               0x00000080
 188 #define UCCE_RXF6                               0x00000040
 189 #define UCCE_RXF5                               0x00000020
 190 #define UCCE_RXF4                               0x00000010
 191 #define UCCE_RXF3                               0x00000008
 192 #define UCCE_RXF2                               0x00000004
 193 #define UCCE_RXF1                               0x00000002
 194 #define UCCE_RXF0                               0x00000001
 195
 196 #define UCCE_RXBF_SINGLE_MASK                   (UCCE_RXF0)
 197 #define UCCE_TXBF_SINGLE_MASK                   (UCCE_TXB0)
 198
 199 #define UCCE_TXB         (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 |\
 200                         UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
 201 #define UCCE_RXB         (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 |\
 202                         UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
 203 #define UCCE_RXF         (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 |\
 204                         UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
 205 #define UCCE_OTHER       (UCCE_SCAR | UCCE_GRA  | UCCE_CBPR | UCCE_BSY  |\
 206                         UCCE_RXC  | UCCE_TXC  | UCCE_TXE)
 207
 208 /* UCC GETH UPSMR (Protocol Specific Mode Register) */
 209 #define UPSMR_ECM                               0x04000000      /* Enable CAM
 210                                                                    Miss or
 211                                                                    Enable
 212                                                                    Filtering
 213                                                                    Miss */
 214 #define UPSMR_HSE                               0x02000000      /* Hardware
 215                                                                    Statistics
 216                                                                    Enable */
 217 #define UPSMR_PRO                               0x00400000      /* Promiscuous*/
 218 #define UPSMR_CAP                               0x00200000      /* CAM polarity
 219                                                                  */
 220 #define UPSMR_RSH                               0x00100000      /* Receive
 221                                                                    Short Frames
 222                                                                  */
 223 #define UPSMR_RPM                               0x00080000      /* Reduced Pin
 224                                                                    Mode
 225                                                                    interfaces */
 226 #define UPSMR_R10M                              0x00040000      /* RGMII/RMII
 227                                                                    10 Mode */
 228 #define UPSMR_RLPB                              0x00020000      /* RMII
 229                                                                    Loopback
 230                                                                    Mode */
 231 #define UPSMR_TBIM                              0x00010000      /* Ten-bit
 232                                                                    Interface
 233                                                                    Mode */
 234 #define UPSMR_RMM                               0x00001000      /* RMII/RGMII
 235                                                                    Mode */
 236 #define UPSMR_CAM                               0x00000400      /* CAM Address
 237                                                                    Matching */
 238 #define UPSMR_BRO                               0x00000200      /* Broadcast
 239                                                                    Address */
 240 #define UPSMR_RES1                              0x00002000      /* Reserved
 241                                                                    feild - must
 242                                                                    be 1 */
 243
 244 /* UCC GETH MACCFG1 (MAC Configuration 1 Register) */
 245 #define MACCFG1_FLOW_RX                         0x00000020      /* Flow Control
 246                                                                    Rx */
 247 #define MACCFG1_FLOW_TX                         0x00000010      /* Flow Control
 248                                                                    Tx */
 249 #define MACCFG1_ENABLE_SYNCHED_RX               0x00000008      /* Rx Enable
 250                                                                    synchronized
 251                                                                    to Rx stream
 252                                                                  */
 253 #define MACCFG1_ENABLE_RX                       0x00000004      /* Enable Rx */
 254 #define MACCFG1_ENABLE_SYNCHED_TX               0x00000002      /* Tx Enable
 255                                                                    synchronized
 256                                                                    to Tx stream
 257                                                                  */
 258 #define MACCFG1_ENABLE_TX                       0x00000001      /* Enable Tx */
 259
 260 /* UCC GETH MACCFG2 (MAC Configuration 2 Register) */
 261 #define MACCFG2_PREL_SHIFT                      (31 - 19)       /* Preamble
 262                                                                    Length <<
 263                                                                    shift */
 264 #define MACCFG2_PREL_MASK                       0x0000f000      /* Preamble
 265                                                                    Length mask */
 266 #define MACCFG2_SRP                             0x00000080      /* Soft Receive
 267                                                                    Preamble */
 268 #define MACCFG2_STP                             0x00000040      /* Soft
 269                                                                    Transmit
 270                                                                    Preamble */
 271 #define MACCFG2_RESERVED_1                      0x00000020      /* Reserved -
 272                                                                    must be set
 273                                                                    to 1 */
 274 #define MACCFG2_LC                              0x00000010      /* Length Check
 275                                                                  */
 276 #define MACCFG2_MPE                             0x00000008      /* Magic packet
 277                                                                    detect */
 278 #define MACCFG2_FDX                             0x00000001      /* Full Duplex */
 279 #define MACCFG2_FDX_MASK                        0x00000001      /* Full Duplex
 280                                                                    mask */
 281 #define MACCFG2_PAD_CRC                         0x00000004
 282 #define MACCFG2_CRC_EN                          0x00000002
 283 #define MACCFG2_PAD_AND_CRC_MODE_NONE           0x00000000      /* Neither
 284                                                                    Padding
 285                                                                    short frames
 286                                                                    nor CRC */
 287 #define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY       0x00000002      /* Append CRC
 288                                                                    only */
 289 #define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC    0x00000004
 290 #define MACCFG2_INTERFACE_MODE_NIBBLE           0x00000100      /* nibble mode
 291                                                                    (MII/RMII/RGMII
 292                                                                    10/100bps) */
 293 #define MACCFG2_INTERFACE_MODE_BYTE             0x00000200      /* byte mode
 294                                                                    (GMII/TBI/RTB/RGMII
 295                                                                    1000bps ) */
 296 #define MACCFG2_INTERFACE_MODE_MASK             0x00000300      /* mask
 297                                                                    covering all
 298                                                                    relevant
 299                                                                    bits */
 300
 301 /* UCC GETH IPGIFG (Inter-frame Gap / Inter-Frame Gap Register) */
 302 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT (31 -  7)       /* Non
 303                                                                    back-to-back
 304                                                                    inter frame
 305                                                                    gap part 1.
 306                                                                    << shift */
 307 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT (31 - 15)       /* Non
 308                                                                    back-to-back
 309                                                                    inter frame
 310                                                                    gap part 2.
 311                                                                    << shift */
 312 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT    (31 - 23)       /* Mimimum IFG
 313                                                                    Enforcement
 314                                                                    << shift */
 315 #define IPGIFG_BACK_TO_BACK_IFG_SHIFT           (31 - 31)       /* back-to-back
 316                                                                    inter frame
 317                                                                    gap << shift
 318                                                                  */
 319 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX   127     /* Non back-to-back
 320                                                            inter frame gap part
 321                                                            1. max val */
 322 #define IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX   127     /* Non back-to-back
 323                                                            inter frame gap part
 324                                                            2. max val */
 325 #define IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX      255     /* Mimimum IFG
 326                                                            Enforcement max val */
 327 #define IPGIFG_BACK_TO_BACK_IFG_MAX             127     /* back-to-back inter
 328                                                            frame gap max val */
 329 #define IPGIFG_NBTB_CS_IPG_MASK                 0x7F000000
 330 #define IPGIFG_NBTB_IPG_MASK                    0x007F0000
 331 #define IPGIFG_MIN_IFG_MASK                     0x0000FF00
 332 #define IPGIFG_BTB_IPG_MASK                     0x0000007F
 333
 334 /* UCC GETH HAFDUP (Half Duplex Register) */
 335 #define HALFDUP_ALT_BEB_TRUNCATION_SHIFT        (31 - 11)       /* Alternate
 336                                                                    Binary
 337                                                                    Exponential
 338                                                                    Backoff
 339                                                                    Truncation
 340                                                                    << shift */
 341 #define HALFDUP_ALT_BEB_TRUNCATION_MAX          0xf     /* Alternate Binary
 342                                                            Exponential Backoff
 343                                                            Truncation max val */
 344 #define HALFDUP_ALT_BEB                         0x00080000      /* Alternate
 345                                                                    Binary
 346                                                                    Exponential
 347                                                                    Backoff */
 348 #define HALFDUP_BACK_PRESSURE_NO_BACKOFF        0x00040000      /* Back
 349                                                                    pressure no
 350                                                                    backoff */
 351 #define HALFDUP_NO_BACKOFF                      0x00020000      /* No Backoff */
 352 #define HALFDUP_EXCESSIVE_DEFER                 0x00010000      /* Excessive
 353                                                                    Defer */
 354 #define HALFDUP_MAX_RETRANSMISSION_SHIFT        (31 - 19)       /* Maximum
 355                                                                    Retransmission
 356                                                                    << shift */
 357 #define HALFDUP_MAX_RETRANSMISSION_MAX          0xf     /* Maximum
 358                                                            Retransmission max
 359                                                            val */
 360 #define HALFDUP_COLLISION_WINDOW_SHIFT          (31 - 31)       /* Collision
 361                                                                    Window <<
 362                                                                    shift */
 363 #define HALFDUP_COLLISION_WINDOW_MAX            0x3f    /* Collision Window max
 364                                                            val */
 365 #define HALFDUP_ALT_BEB_TR_MASK                 0x00F00000
 366 #define HALFDUP_RETRANS_MASK                    0x0000F000
 367 #define HALFDUP_COL_WINDOW_MASK                 0x0000003F
 368
 369 /* UCC GETH UCCS (Ethernet Status Register) */
 370 #define UCCS_BPR                                0x02    /* Back pressure (in
 371                                                            half duplex mode) */
 372 #define UCCS_PAU                                0x02    /* Pause state (in full
 373                                                            duplex mode) */
 374 #define UCCS_MPD                                0x01    /* Magic Packet
 375                                                            Detected */
 376
 377 /* UCC GETH IFSTAT (Interface Status Register) */
 378 #define IFSTAT_EXCESS_DEFER                     0x00000200      /* Excessive
 379                                                                    transmission
 380                                                                    defer */
 381
 382 /* UCC GETH MACSTNADDR1 (Station Address Part 1 Register) */
 383 #define MACSTNADDR1_OCTET_6_SHIFT               (31 -  7)       /* Station
 384                                                                    address 6th
 385                                                                    octet <<
 386                                                                    shift */
 387 #define MACSTNADDR1_OCTET_5_SHIFT               (31 - 15)       /* Station
 388                                                                    address 5th
 389                                                                    octet <<
 390                                                                    shift */
 391 #define MACSTNADDR1_OCTET_4_SHIFT               (31 - 23)       /* Station
 392                                                                    address 4th
 393                                                                    octet <<
 394                                                                    shift */
 395 #define MACSTNADDR1_OCTET_3_SHIFT               (31 - 31)       /* Station
 396                                                                    address 3rd
 397                                                                    octet <<
 398                                                                    shift */
 399
 400 /* UCC GETH MACSTNADDR2 (Station Address Part 2 Register) */
 401 #define MACSTNADDR2_OCTET_2_SHIFT               (31 -  7)       /* Station
 402                                                                    address 2nd
 403                                                                    octet <<
 404                                                                    shift */
 405 #define MACSTNADDR2_OCTET_1_SHIFT               (31 - 15)       /* Station
 406                                                                    address 1st
 407                                                                    octet <<
 408                                                                    shift */
 409
 410 /* UCC GETH UEMPR (Ethernet Mac Parameter Register) */
 411 #define UEMPR_PAUSE_TIME_VALUE_SHIFT            (31 - 15)       /* Pause time
 412                                                                    value <<
 413                                                                    shift */
 414 #define UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT   (31 - 31)       /* Extended
 415                                                                    pause time
 416                                                                    value <<
 417                                                                    shift */
 418
 419 /* UCC GETH UTBIPAR (Ten Bit Interface Physical Address Register) */
 420 #define UTBIPAR_PHY_ADDRESS_SHIFT               (31 - 31)       /* Phy address
 421                                                                    << shift */
 422 #define UTBIPAR_PHY_ADDRESS_MASK                0x0000001f      /* Phy address
 423                                                                    mask */
 424
 425 /* UCC GETH UESCR (Ethernet Statistics Control Register) */
 426 #define UESCR_AUTOZ                             0x8000  /* Automatically zero
 427                                                            addressed
 428                                                            statistical counter
 429                                                            values */
 430 #define UESCR_CLRCNT                            0x4000  /* Clear all statistics
 431                                                            counters */
 432 #define UESCR_MAXCOV_SHIFT                      (15 -  7)       /* Max
 433                                                                    Coalescing
 434                                                                    Value <<
 435                                                                    shift */
 436 #define UESCR_SCOV_SHIFT                        (15 - 15)       /* Status
 437                                                                    Coalescing
 438                                                                    Value <<
 439                                                                    shift */
 440
 441 /* UCC GETH UDSR (Data Synchronization Register) */
 442 #define UDSR_MAGIC                              0x067E
 443
 444 struct ucc_geth_thread_data_tx {
 445         u8 res0[104];
 446 } __attribute__ ((packed));
 447
 448 struct ucc_geth_thread_data_rx {
 449         u8 res0[40];
 450 } __attribute__ ((packed));
 451
 452 /* Send Queue Queue-Descriptor */
 453 struct ucc_geth_send_queue_qd {
 454         u32 bd_ring_base;       /* pointer to BD ring base address */
 455         u8 res0[0x8];
 456         u32 last_bd_completed_address;/* initialize to last entry in BD ring */
 457         u8 res1[0x30];
 458 } __attribute__ ((packed));
 459
 460 struct ucc_geth_send_queue_mem_region {
 461         struct ucc_geth_send_queue_qd sqqd[NUM_TX_QUEUES];
 462 } __attribute__ ((packed));
 463
 464 struct ucc_geth_thread_tx_pram {
 465         u8 res0[64];
 466 } __attribute__ ((packed));
 467
 468 struct ucc_geth_thread_rx_pram {
 469         u8 res0[128];
 470 } __attribute__ ((packed));
 471
 472 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING        64
 473 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8      64
 474 #define THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16     96
 475
 476 struct ucc_geth_scheduler {
 477         u16 cpucount0;          /* CPU packet counter */
 478         u16 cpucount1;          /* CPU packet counter */
 479         u16 cecount0;           /* QE packet counter */
 480         u16 cecount1;           /* QE packet counter */
 481         u16 cpucount2;          /* CPU packet counter */
 482         u16 cpucount3;          /* CPU packet counter */
 483         u16 cecount2;           /* QE packet counter */
 484         u16 cecount3;           /* QE packet counter */
 485         u16 cpucount4;          /* CPU packet counter */
 486         u16 cpucount5;          /* CPU packet counter */
 487         u16 cecount4;           /* QE packet counter */
 488         u16 cecount5;           /* QE packet counter */
 489         u16 cpucount6;          /* CPU packet counter */
 490         u16 cpucount7;          /* CPU packet counter */
 491         u16 cecount6;           /* QE packet counter */
 492         u16 cecount7;           /* QE packet counter */
 493         u32 weightstatus[NUM_TX_QUEUES];        /* accumulated weight factor */
 494         u32 rtsrshadow;         /* temporary variable handled by QE */
 495         u32 time;               /* temporary variable handled by QE */
 496         u32 ttl;                /* temporary variable handled by QE */
 497         u32 mblinterval;        /* max burst length interval */
 498         u16 nortsrbytetime;     /* normalized value of byte time in tsr units */
 499         u8 fracsiz;             /* radix 2 log value of denom. of
 500                                    NorTSRByteTime */
 501         u8 res0[1];
 502         u8 strictpriorityq;     /* Strict Priority Mask register */
 503         u8 txasap;              /* Transmit ASAP register */
 504         u8 extrabw;             /* Extra BandWidth register */
 505         u8 oldwfqmask;          /* temporary variable handled by QE */
 506         u8 weightfactor[NUM_TX_QUEUES];
 507                                       /**< weight factor for queues   */
 508         u32 minw;               /* temporary variable handled by QE */
 509         u8 res1[0x70 - 0x64];
 510 } __attribute__ ((packed));
 511
 512 struct ucc_geth_tx_firmware_statistics_pram {
 513         u32 sicoltx;            /* single collision */
 514         u32 mulcoltx;           /* multiple collision */
 515         u32 latecoltxfr;        /* late collision */
 516         u32 frabortduecol;      /* frames aborted due to transmit collision */
 517         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 518                                    transmission that are not counted on any
 519                                    other counter */
 520         u32 carriersenseertx;   /* carrier sense error */
 521         u32 frtxok;             /* frames transmitted OK */
 522         u32 txfrexcessivedefer; /* frames with defferal time greater than
 523                                    specified threshold */
 524         u32 txpkts256;          /* total packets (including bad) between 256
 525                                    and 511 octets */
 526         u32 txpkts512;          /* total packets (including bad) between 512
 527                                    and 1023 octets */
 528         u32 txpkts1024;         /* total packets (including bad) between 1024
 529                                    and 1518 octets */
 530         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 531                                    and MAXLength octets */
 532 } __attribute__ ((packed));
 533
 534 struct ucc_geth_rx_firmware_statistics_pram {
 535         u32 frrxfcser;          /* frames with crc error */
 536         u32 fraligner;          /* frames with alignment error */
 537         u32 inrangelenrxer;     /* in range length error */
 538         u32 outrangelenrxer;    /* out of range length error */
 539         u32 frtoolong;          /* frame too long */
 540         u32 runt;               /* runt */
 541         u32 verylongevent;      /* very long event */
 542         u32 symbolerror;        /* symbol error */
 543         u32 dropbsy;            /* drop because of BD not ready */
 544         u8 res0[0x8];
 545         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 546                                    or type mismatch) */
 547         u32 underpkts;          /* total frames less than 64 octets */
 548         u32 pkts256;            /* total frames (including bad) between 256 and
 549                                    511 octets */
 550         u32 pkts512;            /* total frames (including bad) between 512 and
 551                                    1023 octets */
 552         u32 pkts1024;           /* total frames (including bad) between 1024
 553                                    and 1518 octets */
 554         u32 pktsjumbo;          /* total frames (including bad) between 1024
 555                                    and MAXLength octets */
 556         u32 frlossinmacer;      /* frames lost because of internal MAC error
 557                                    that is not counted in any other counter */
 558         u32 pausefr;            /* pause frames */
 559         u8 res1[0x4];
 560         u32 removevlan;         /* total frames that had their VLAN tag removed
 561                                  */
 562         u32 replacevlan;        /* total frames that had their VLAN tag
 563                                    replaced */
 564         u32 insertvlan;         /* total frames that had their VLAN tag
 565                                    inserted */
 566 } __attribute__ ((packed));
 567
 568 struct ucc_geth_rx_interrupt_coalescing_entry {
 569         u32 interruptcoalescingmaxvalue;        /* interrupt coalescing max
 570                                                    value */
 571         u32 interruptcoalescingcounter; /* interrupt coalescing counter,
 572                                            initialize to
 573                                            interruptcoalescingmaxvalue */
 574 } __attribute__ ((packed));
 575
 576 struct ucc_geth_rx_interrupt_coalescing_table {
 577         struct ucc_geth_rx_interrupt_coalescing_entry coalescingentry[NUM_RX_QUEUES];
 578                                        /**< interrupt coalescing entry */
 579 } __attribute__ ((packed));
 580
 581 struct ucc_geth_rx_prefetched_bds {
 582         struct qe_bd bd[NUM_BDS_IN_PREFETCHED_BDS];     /* prefetched bd */
 583 } __attribute__ ((packed));
 584
 585 struct ucc_geth_rx_bd_queues_entry {
 586         u32 bdbaseptr;          /* BD base pointer */
 587         u32 bdptr;              /* BD pointer */
 588         u32 externalbdbaseptr;  /* external BD base pointer */
 589         u32 externalbdptr;      /* external BD pointer */
 590 } __attribute__ ((packed));
 591
 592 struct ucc_geth_tx_global_pram {
 593         u16 temoder;
 594         u8 res0[0x38 - 0x02];
 595         u32 sqptr;              /* a base pointer to send queue memory region */
 596         u32 schedulerbasepointer;       /* a base pointer to scheduler memory
 597                                            region */
 598         u32 txrmonbaseptr;      /* base pointer to Tx RMON statistics counter */
 599         u32 tstate;             /* tx internal state. High byte contains
 600                                    function code */
 601         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
 602         u32 vtagtable[0x8];     /* 8 4-byte VLAN tags */
 603         u32 tqptr;              /* a base pointer to the Tx Queues Memory
 604                                    Region */
 605         u8 res2[0x80 - 0x74];
 606 } __attribute__ ((packed));
 607
 608 /* structure representing Extended Filtering Global Parameters in PRAM */
 609 struct ucc_geth_exf_global_pram {
 610         u32 l2pcdptr;           /* individual address filter, high */
 611         u8 res0[0x10 - 0x04];
 612 } __attribute__ ((packed));
 613
 614 struct ucc_geth_rx_global_pram {
 615         u32 remoder;            /* ethernet mode reg. */
 616         u32 rqptr;              /* base pointer to the Rx Queues Memory Region*/
 617         u32 res0[0x1];
 618         u8 res1[0x20 - 0xC];
 619         u16 typeorlen;          /* cutoff point less than which, type/len field
 620                                    is considered length */
 621         u8 res2[0x1];
 622         u8 rxgstpack;           /* acknowledgement on GRACEFUL STOP RX command*/
 623         u32 rxrmonbaseptr;      /* base pointer to Rx RMON statistics counter */
 624         u8 res3[0x30 - 0x28];
 625         u32 intcoalescingptr;   /* Interrupt coalescing table pointer */
 626         u8 res4[0x36 - 0x34];
 627         u8 rstate;              /* rx internal state. High byte contains
 628                                    function code */
 629         u8 res5[0x46 - 0x37];
 630         u16 mrblr;              /* max receive buffer length reg. */
 631         u32 rbdqptr;            /* base pointer to RxBD parameter table
 632                                    description */
 633         u16 mflr;               /* max frame length reg. */
 634         u16 minflr;             /* min frame length reg. */
 635         u16 maxd1;              /* max dma1 length reg. */
 636         u16 maxd2;              /* max dma2 length reg. */
 637         u32 ecamptr;            /* external CAM address */
 638         u32 l2qt;               /* VLAN priority mapping table. */
 639         u32 l3qt[0x8];          /* IP priority mapping table. */
 640         u16 vlantype;           /* vlan type */
 641         u16 vlantci;            /* default vlan tci */
 642         u8 addressfiltering[64];        /* address filtering data structure */
 643         u32 exfGlobalParam;     /* base address for extended filtering global
 644                                    parameters */
 645         u8 res6[0x100 - 0xC4];  /* Initialize to zero */
 646 } __attribute__ ((packed));
 647
 648 #define GRACEFUL_STOP_ACKNOWLEDGE_RX            0x01
 649
 650 /* structure representing InitEnet command */
 651 struct ucc_geth_init_pram {
 652         u8 resinit1;
 653         u8 resinit2;
 654         u8 resinit3;
 655         u8 resinit4;
 656         u16 resinit5;
 657         u8 res1[0x1];
 658         u8 largestexternallookupkeysize;
 659         u32 rgftgfrxglobal;
 660         u32 rxthread[ENET_INIT_PARAM_MAX_ENTRIES_RX];   /* rx threads */
 661         u8 res2[0x38 - 0x30];
 662         u32 txglobal;           /* tx global */
 663         u32 txthread[ENET_INIT_PARAM_MAX_ENTRIES_TX];   /* tx threads */
 664         u8 res3[0x1];
 665 } __attribute__ ((packed));
 666
 667 #define ENET_INIT_PARAM_RGF_SHIFT               (32 - 4)
 668 #define ENET_INIT_PARAM_TGF_SHIFT               (32 - 8)
 669
 670 #define ENET_INIT_PARAM_RISC_MASK               0x0000003f
 671 #define ENET_INIT_PARAM_PTR_MASK                0x00ffffc0
 672 #define ENET_INIT_PARAM_SNUM_MASK               0xff000000
 673 #define ENET_INIT_PARAM_SNUM_SHIFT              24
 674
 675 #define ENET_INIT_PARAM_MAGIC_RES_INIT1         0x06
 676 #define ENET_INIT_PARAM_MAGIC_RES_INIT2         0x30
 677 #define ENET_INIT_PARAM_MAGIC_RES_INIT3         0xff
 678 #define ENET_INIT_PARAM_MAGIC_RES_INIT4         0x00
 679 #define ENET_INIT_PARAM_MAGIC_RES_INIT5         0x0400
 680
 681 /* structure representing 82xx Address Filtering Enet Address in PRAM */
 682 struct ucc_geth_82xx_enet_address {
 683         u8 res1[0x2];
 684         u16 h;                  /* address (MSB) */
 685         u16 m;                  /* address */
 686         u16 l;                  /* address (LSB) */
 687 } __attribute__ ((packed));
 688
 689 /* structure representing 82xx Address Filtering PRAM */
 690 struct ucc_geth_82xx_address_filtering_pram {
 691         u32 iaddr_h;            /* individual address filter, high */
 692         u32 iaddr_l;            /* individual address filter, low */
 693         u32 gaddr_h;            /* group address filter, high */
 694         u32 gaddr_l;            /* group address filter, low */
 695         struct ucc_geth_82xx_enet_address taddr;
 696         struct ucc_geth_82xx_enet_address paddr[NUM_OF_PADDRS];
 697         u8 res0[0x40 - 0x38];
 698 } __attribute__ ((packed));
 699
 700 /* GETH Tx firmware statistics structure, used when calling
 701    UCC_GETH_GetStatistics. */
 702 struct ucc_geth_tx_firmware_statistics {
 703         u32 sicoltx;            /* single collision */
 704         u32 mulcoltx;           /* multiple collision */
 705         u32 latecoltxfr;        /* late collision */
 706         u32 frabortduecol;      /* frames aborted due to transmit collision */
 707         u32 frlostinmactxer;    /* frames lost due to internal MAC error
 708                                    transmission that are not counted on any
 709                                    other counter */
 710         u32 carriersenseertx;   /* carrier sense error */
 711         u32 frtxok;             /* frames transmitted OK */
 712         u32 txfrexcessivedefer; /* frames with defferal time greater than
 713                                    specified threshold */
 714         u32 txpkts256;          /* total packets (including bad) between 256
 715                                    and 511 octets */
 716         u32 txpkts512;          /* total packets (including bad) between 512
 717                                    and 1023 octets */
 718         u32 txpkts1024;         /* total packets (including bad) between 1024
 719                                    and 1518 octets */
 720         u32 txpktsjumbo;        /* total packets (including bad) between 1024
 721                                    and MAXLength octets */
 722 } __attribute__ ((packed));
 723
 724 /* GETH Rx firmware statistics structure, used when calling
 725    UCC_GETH_GetStatistics. */
 726 struct ucc_geth_rx_firmware_statistics {
 727         u32 frrxfcser;          /* frames with crc error */
 728         u32 fraligner;          /* frames with alignment error */
 729         u32 inrangelenrxer;     /* in range length error */
 730         u32 outrangelenrxer;    /* out of range length error */
 731         u32 frtoolong;          /* frame too long */
 732         u32 runt;               /* runt */
 733         u32 verylongevent;      /* very long event */
 734         u32 symbolerror;        /* symbol error */
 735         u32 dropbsy;            /* drop because of BD not ready */
 736         u8 res0[0x8];
 737         u32 mismatchdrop;       /* drop because of MAC filtering (e.g. address
 738                                    or type mismatch) */
 739         u32 underpkts;          /* total frames less than 64 octets */
 740         u32 pkts256;            /* total frames (including bad) between 256 and
 741                                    511 octets */
 742         u32 pkts512;            /* total frames (including bad) between 512 and
 743                                    1023 octets */
 744         u32 pkts1024;           /* total frames (including bad) between 1024
 745                                    and 1518 octets */
 746         u32 pktsjumbo;          /* total frames (including bad) between 1024
 747                                    and MAXLength octets */
 748         u32 frlossinmacer;      /* frames lost because of internal MAC error
 749                                    that is not counted in any other counter */
 750         u32 pausefr;            /* pause frames */
 751         u8 res1[0x4];
 752         u32 removevlan;         /* total frames that had their VLAN tag removed
 753                                  */
 754         u32 replacevlan;        /* total frames that had their VLAN tag
 755                                    replaced */
 756         u32 insertvlan;         /* total frames that had their VLAN tag
 757                                    inserted */
 758 } __attribute__ ((packed));
 759
 760 /* GETH hardware statistics structure, used when calling
 761    UCC_GETH_GetStatistics. */
 762 struct ucc_geth_hardware_statistics {
 763         u32 tx64;               /* Total number of frames (including bad
 764                                    frames) transmitted that were exactly of the
 765                                    minimal length (64 for un tagged, 68 for
 766                                    tagged, or with length exactly equal to the
 767                                    parameter MINLength */
 768         u32 tx127;              /* Total number of frames (including bad
 769                                    frames) transmitted that were between
 770                                    MINLength (Including FCS length==4) and 127
 771                                    octets */
 772         u32 tx255;              /* Total number of frames (including bad
 773                                    frames) transmitted that were between 128
 774                                    (Including FCS length==4) and 255 octets */
 775         u32 rx64;               /* Total number of frames received including
 776                                    bad frames that were exactly of the mninimal
 777                                    length (64 bytes) */
 778         u32 rx127;              /* Total number of frames (including bad
 779                                    frames) received that were between MINLength
 780                                    (Including FCS length==4) and 127 octets */
 781         u32 rx255;              /* Total number of frames (including bad
 782                                    frames) received that were between 128
 783                                    (Including FCS length==4) and 255 octets */
 784         u32 txok;               /* Total number of octets residing in frames
 785                                    that where involved in succesfull
 786                                    transmission */
 787         u16 txcf;               /* Total number of PAUSE control frames
 788                                    transmitted by this MAC */
 789         u32 tmca;               /* Total number of frames that were transmitted
 790                                    succesfully with the group address bit set
 791                                    that are not broadcast frames */
 792         u32 tbca;               /* Total number of frames transmitted
 793                                    succesfully that had destination address
 794                                    field equal to the broadcast address */
 795         u32 rxfok;              /* Total number of frames received OK */
 796         u32 rxbok;              /* Total number of octets received OK */
 797         u32 rbyt;               /* Total number of octets received including
 798                                    octets in bad frames. Must be implemented in
 799                                    HW because it includes octets in frames that
 800                                    never even reach the UCC */
 801         u32 rmca;               /* Total number of frames that were received
 802                                    succesfully with the group address bit set
 803                                    that are not broadcast frames */
 804         u32 rbca;               /* Total number of frames received succesfully
 805                                    that had destination address equal to the
 806                                    broadcast address */
 807 } __attribute__ ((packed));
 808
 809 /* UCC GETH Tx errors returned via TxConf callback */
 810 #define TX_ERRORS_DEF      0x0200
 811 #define TX_ERRORS_EXDEF    0x0100
 812 #define TX_ERRORS_LC       0x0080
 813 #define TX_ERRORS_RL       0x0040
 814 #define TX_ERRORS_RC_MASK  0x003C
 815 #define TX_ERRORS_RC_SHIFT 2
 816 #define TX_ERRORS_UN       0x0002
 817 #define TX_ERRORS_CSL      0x0001
 818
 819 /* UCC GETH Rx errors returned via RxStore callback */
 820 #define RX_ERRORS_CMR      0x0200
 821 #define RX_ERRORS_M        0x0100
 822 #define RX_ERRORS_BC       0x0080
 823 #define RX_ERRORS_MC       0x0040
 824
 825 /* Transmit BD. These are in addition to values defined in uccf. */
 826 #define T_VID      0x003c0000   /* insert VLAN id index mask. */
 827 #define T_DEF      (((u32) TX_ERRORS_DEF     ) << 16)
 828 #define T_EXDEF    (((u32) TX_ERRORS_EXDEF   ) << 16)
 829 #define T_LC       (((u32) TX_ERRORS_LC      ) << 16)
 830 #define T_RL       (((u32) TX_ERRORS_RL      ) << 16)
 831 #define T_RC_MASK  (((u32) TX_ERRORS_RC_MASK ) << 16)
 832 #define T_UN       (((u32) TX_ERRORS_UN      ) << 16)
 833 #define T_CSL      (((u32) TX_ERRORS_CSL     ) << 16)
 834 #define T_ERRORS_REPORT  (T_DEF | T_EXDEF | T_LC | T_RL | T_RC_MASK \
 835                 | T_UN | T_CSL) /* transmit errors to report */
 836
 837 /* Receive BD. These are in addition to values defined in uccf. */
 838 #define R_LG    0x00200000      /* Frame length violation.  */
 839 #define R_NO    0x00100000      /* Non-octet aligned frame.  */
 840 #define R_SH    0x00080000      /* Short frame.  */
 841 #define R_CR    0x00040000      /* CRC error.  */
 842 #define R_OV    0x00020000      /* Overrun.  */
 843 #define R_IPCH  0x00010000      /* IP checksum check failed. */
 844 #define R_CMR   (((u32) RX_ERRORS_CMR  ) << 16)
 845 #define R_M     (((u32) RX_ERRORS_M    ) << 16)
 846 #define R_BC    (((u32) RX_ERRORS_BC   ) << 16)
 847 #define R_MC    (((u32) RX_ERRORS_MC   ) << 16)
 848 #define R_ERRORS_REPORT (R_CMR | R_M | R_BC | R_MC)     /* receive errors to
 849                                                            report */
 850 #define R_ERRORS_FATAL  (R_LG  | R_NO | R_SH | R_CR | \
 851                 R_OV | R_IPCH)  /* receive errors to discard */
 852
 853 /* Alignments */
 854 #define UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT       256
 855 #define UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT       128
 856 #define UCC_GETH_THREAD_RX_PRAM_ALIGNMENT       128
 857 #define UCC_GETH_THREAD_TX_PRAM_ALIGNMENT       64
 858 #define UCC_GETH_THREAD_DATA_ALIGNMENT          256     /* spec gives values
 859                                                            based on num of
 860                                                            threads, but always
 861                                                            using the maximum is
 862                                                            easier */
 863 #define UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT  32
 864 #define UCC_GETH_SCHEDULER_ALIGNMENT            4       /* This is a guess */
 865 #define UCC_GETH_TX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 866 #define UCC_GETH_RX_STATISTICS_ALIGNMENT        4       /* This is a guess */
 867 #define UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT      4       /* This is a
 868                                                                    guess */
 869 #define UCC_GETH_RX_BD_QUEUES_ALIGNMENT         8       /* This is a guess */
 870 #define UCC_GETH_RX_PREFETCHED_BDS_ALIGNMENT    128     /* This is a guess */
 871 #define UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4    /* This
 872                                                                            is a
 873                                                                            guess
 874                                                                          */
 875 #define UCC_GETH_RX_BD_RING_ALIGNMENT           32
 876 #define UCC_GETH_TX_BD_RING_ALIGNMENT           32
 877 #define UCC_GETH_MRBLR_ALIGNMENT                128
 878 #define UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT      4
 879 #define UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT       32
 880 #define UCC_GETH_RX_DATA_BUF_ALIGNMENT          64
 881
 882 #define UCC_GETH_TAD_EF                         0x80
 883 #define UCC_GETH_TAD_V                          0x40
 884 #define UCC_GETH_TAD_REJ                        0x20
 885 #define UCC_GETH_TAD_VTAG_OP_RIGHT_SHIFT        2
 886 #define UCC_GETH_TAD_VTAG_OP_SHIFT              6
 887 #define UCC_GETH_TAD_V_NON_VTAG_OP              0x20
 888 #define UCC_GETH_TAD_RQOS_SHIFT                 0
 889 #define UCC_GETH_TAD_V_PRIORITY_SHIFT           5
 890 #define UCC_GETH_TAD_CFI                        0x10
 891
 892 #define UCC_GETH_VLAN_PRIORITY_MAX              8
 893 #define UCC_GETH_IP_PRIORITY_MAX                64
 894 #define UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX        8
 895 #define UCC_GETH_RX_BD_RING_SIZE_MIN            8
 896 #define UCC_GETH_TX_BD_RING_SIZE_MIN            2
 897
 898 #define UCC_GETH_SIZE_OF_BD                     QE_SIZEOF_BD
 899
 900 /* Driver definitions */
 901 #define TX_BD_RING_LEN                          0x10
 902 #define RX_BD_RING_LEN                          0x10
 903 #define UCC_GETH_DEV_WEIGHT                     TX_BD_RING_LEN
 904
 905 #define TX_RING_MOD_MASK(size)                  (size-1)
 906 #define RX_RING_MOD_MASK(size)                  (size-1)
 907
 908 #define ENET_NUM_OCTETS_PER_ADDRESS             6
 909 #define ENET_GROUP_ADDR                         0x01    /* Group address mask
 910                                                            for ethernet
 911                                                            addresses */
 912
 913 #define TX_TIMEOUT                              (1*HZ)
 914 #define SKB_ALLOC_TIMEOUT                       100000
 915 #define PHY_INIT_TIMEOUT                        100000
 916 #define PHY_CHANGE_TIME                         2
 917
 918 /* Fast Ethernet (10/100 Mbps) */
 919 #define UCC_GETH_URFS_INIT                      512     /* Rx virtual FIFO size
 920                                                          */
 921 #define UCC_GETH_URFET_INIT                     256     /* 1/2 urfs */
 922 #define UCC_GETH_URFSET_INIT                    384     /* 3/4 urfs */
 923 #define UCC_GETH_UTFS_INIT                      512     /* Tx virtual FIFO size
 924                                                          */
 925 #define UCC_GETH_UTFET_INIT                     256     /* 1/2 utfs */
 926 #define UCC_GETH_UTFTT_INIT                     128
 927 /* Gigabit Ethernet (1000 Mbps) */
 928 #define UCC_GETH_URFS_GIGA_INIT                 4096/*2048*/    /* Rx virtual
 929                                                                    FIFO size */
 930 #define UCC_GETH_URFET_GIGA_INIT                2048/*1024*/    /* 1/2 urfs */
 931 #define UCC_GETH_URFSET_GIGA_INIT               3072/*1536*/    /* 3/4 urfs */
 932 #define UCC_GETH_UTFS_GIGA_INIT                 8192/*2048*/    /* Tx virtual
 933                                                                    FIFO size */
 934 #define UCC_GETH_UTFET_GIGA_INIT                4096/*1024*/    /* 1/2 utfs */
 935 #define UCC_GETH_UTFTT_GIGA_INIT                0x400/*0x40*/   /* */
 936
 937 #define UCC_GETH_REMODER_INIT                   0       /* bits that must be
 938                                                            set */
 939 #define UCC_GETH_TEMODER_INIT                   0xC000  /* bits that must */
 940 #define UCC_GETH_UPSMR_INIT                     (UPSMR_RES1)    /* Start value
 941                                                                    for this
 942                                                                    register */
 943 #define UCC_GETH_MACCFG1_INIT                   0
 944 #define UCC_GETH_MACCFG2_INIT                   (MACCFG2_RESERVED_1)
 945
 946 /* Ethernet Address Type. */
 947 enum enet_addr_type {
 948         ENET_ADDR_TYPE_INDIVIDUAL,
 949         ENET_ADDR_TYPE_GROUP,
 950         ENET_ADDR_TYPE_BROADCAST
 951 };
 952
 953 /* UCC GETH 82xx Ethernet Address Recognition Location */
 954 enum ucc_geth_enet_address_recognition_location {
 955         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_STATION_ADDRESS,/* station
 956                                                                       address */
 957         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_FIRST, /* additional
 958                                                                    station
 959                                                                    address
 960                                                                    paddr1 */
 961         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR2,      /* additional
 962                                                                    station
 963                                                                    address
 964                                                                    paddr2 */
 965         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR3,      /* additional
 966                                                                    station
 967                                                                    address
 968                                                                    paddr3 */
 969         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_PADDR_LAST,  /* additional
 970                                                                    station
 971                                                                    address
 972                                                                    paddr4 */
 973         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH,  /* group hash */
 974         UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH /* individual
 975                                                                       hash */
 976 };
 977
 978 /* UCC GETH vlan operation tagged */
 979 enum ucc_geth_vlan_operation_tagged {
 980         UCC_GETH_VLAN_OPERATION_TAGGED_NOP = 0x0,       /* Tagged - nop */
 981         UCC_GETH_VLAN_OPERATION_TAGGED_REPLACE_VID_PORTION_OF_Q_TAG
 982                 = 0x1,  /* Tagged - replace vid portion of q tag */
 983         UCC_GETH_VLAN_OPERATION_TAGGED_IF_VID0_REPLACE_VID_WITH_DEFAULT_VALUE
 984                 = 0x2,  /* Tagged - if vid0 replace vid with default value  */
 985         UCC_GETH_VLAN_OPERATION_TAGGED_EXTRACT_Q_TAG_FROM_FRAME
 986                 = 0x3   /* Tagged - extract q tag from frame */
 987 };
 988
 989 /* UCC GETH vlan operation non-tagged */
 990 enum ucc_geth_vlan_operation_non_tagged {
 991         UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP = 0x0,   /* Non tagged - nop */
 992         UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT = 0x1   /* Non tagged -
 993                                                                    q tag insert
 994                                                                  */
 995 };
 996
 997 /* UCC GETH Rx Quality of Service Mode */
 998 enum ucc_geth_qos_mode {
 999         UCC_GETH_QOS_MODE_DEFAULT = 0x0,        /* default queue */
1000         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L2_CRITERIA = 0x1,     /* queue
1001                                                                    determined
1002                                                                    by L2
1003                                                                    criteria */
1004         UCC_GETH_QOS_MODE_QUEUE_NUM_FROM_L3_CRITERIA = 0x2      /* queue
1005                                                                    determined
1006                                                                    by L3
1007                                                                    criteria */
1008 };
1009
1010 /* UCC GETH Statistics Gathering Mode - These are bit flags, 'or' them together
1011    for combined functionality */
1012 enum ucc_geth_statistics_gathering_mode {
1013         UCC_GETH_STATISTICS_GATHERING_MODE_NONE = 0x00000000,   /* No
1014                                                                    statistics
1015                                                                    gathering */
1016         UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE = 0x00000001,/* Enable
1017                                                                     hardware
1018                                                                     statistics
1019                                                                     gathering
1020                                                                   */
1021         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX = 0x00000004,/*Enable
1022                                                                       firmware
1023                                                                       tx
1024                                                                       statistics
1025                                                                       gathering
1026                                                                      */
1027         UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX = 0x00000008/* Enable
1028                                                                       firmware
1029                                                                       rx
1030                                                                       statistics
1031                                                                       gathering
1032                                                                     */
1033 };
1034
1035 /* UCC GETH Pad and CRC Mode - Note, Padding without CRC is not possible */
1036 enum ucc_geth_maccfg2_pad_and_crc_mode {
1037         UCC_GETH_PAD_AND_CRC_MODE_NONE
1038                 = MACCFG2_PAD_AND_CRC_MODE_NONE,        /* Neither Padding
1039                                                            short frames
1040                                                            nor CRC */
1041         UCC_GETH_PAD_AND_CRC_MODE_CRC_ONLY
1042                 = MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY,    /* Append
1043                                                            CRC only */
1044         UCC_GETH_PAD_AND_CRC_MODE_PAD_AND_CRC =
1045             MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
1046 };
1047
1048 /* UCC GETH upsmr Flow Control Mode */
1049 enum ucc_geth_flow_control_mode {
1050         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE = 0x00000000,    /* No automatic
1051                                                                    flow control
1052                                                                  */
1053         UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_PAUSE_WHEN_EMERGENCY
1054                 = 0x00004000    /* Send pause frame when RxFIFO reaches its
1055                                    emergency threshold */
1056 };
1057
1058 /* UCC GETH number of threads */
1059 enum ucc_geth_num_of_threads {
1060         UCC_GETH_NUM_OF_THREADS_1 = 0x1,        /* 1 */
1061         UCC_GETH_NUM_OF_THREADS_2 = 0x2,        /* 2 */
1062         UCC_GETH_NUM_OF_THREADS_4 = 0x0,        /* 4 */
1063         UCC_GETH_NUM_OF_THREADS_6 = 0x3,        /* 6 */
1064         UCC_GETH_NUM_OF_THREADS_8 = 0x4 /* 8 */
1065 };
1066
1067 /* UCC GETH number of station addresses */
1068 enum ucc_geth_num_of_station_addresses {
1069         UCC_GETH_NUM_OF_STATION_ADDRESSES_1,    /* 1 */
1070         UCC_GETH_NUM_OF_STATION_ADDRESSES_5     /* 5 */
1071 };
1072
1073 /* UCC GETH 82xx Ethernet Address Container */
1074 struct enet_addr_container {
1075         u8 address[ENET_NUM_OCTETS_PER_ADDRESS];        /* ethernet address */
1076         enum ucc_geth_enet_address_recognition_location location;       /* location in
1077                                                                    82xx address
1078                                                                    recognition
1079                                                                    hardware */
1080         struct list_head node;
1081 };
1082
1083 #define ENET_ADDR_CONT_ENTRY(ptr) list_entry(ptr, struct enet_addr_container, node)
1084
1085 /* UCC GETH Termination Action Descriptor (TAD) structure. */
1086 struct ucc_geth_tad_params {
1087         int rx_non_dynamic_extended_features_mode;
1088         int reject_frame;
1089         enum ucc_geth_vlan_operation_tagged vtag_op;
1090         enum ucc_geth_vlan_operation_non_tagged vnontag_op;
1091         enum ucc_geth_qos_mode rqos;
1092         u8 vpri;
1093         u16 vid;
1094 };
1095
1096 /* GETH protocol initialization structure */
1097 struct ucc_geth_info {
1098         struct ucc_fast_info uf_info;
1099         u8 numQueuesTx;
1100         u8 numQueuesRx;
1101         int ipCheckSumCheck;
1102         int ipCheckSumGenerate;
1103         int rxExtendedFiltering;
1104         u32 extendedFilteringChainPointer;
1105         u16 typeorlen;
1106         int dynamicMaxFrameLength;
1107         int dynamicMinFrameLength;
1108         u8 nonBackToBackIfgPart1;
1109         u8 nonBackToBackIfgPart2;
1110         u8 miminumInterFrameGapEnforcement;
1111         u8 backToBackInterFrameGap;
1112         int ipAddressAlignment;
1113         int lengthCheckRx;
1114         u32 mblinterval;
1115         u16 nortsrbytetime;
1116         u8 fracsiz;
1117         u8 strictpriorityq;
1118         u8 txasap;
1119         u8 extrabw;
1120         int miiPreambleSupress;
1121         u8 altBebTruncation;
1122         int altBeb;
1123         int backPressureNoBackoff;
1124         int noBackoff;
1125         int excessDefer;
1126         u8 maxRetransmission;
1127         u8 collisionWindow;
1128         int pro;
1129         int cap;
1130         int rsh;
1131         int rlpb;
1132         int cam;
1133         int bro;
1134         int ecm;
1135         int receiveFlowControl;
1136         u8 maxGroupAddrInHash;
1137         u8 maxIndAddrInHash;
1138         u8 prel;
1139         u16 maxFrameLength;
1140         u16 minFrameLength;
1141         u16 maxD1Length;
1142         u16 maxD2Length;
1143         u16 vlantype;
1144         u16 vlantci;
1145         u32 ecamptr;
1146         u32 eventRegMask;
1147         u16 pausePeriod;
1148         u16 extensionField;
1149         u8 phy_address;
1150         u32 mdio_bus;
1151         u8 weightfactor[NUM_TX_QUEUES];
1152         u8 interruptcoalescingmaxvalue[NUM_RX_QUEUES];
1153         u8 l2qt[UCC_GETH_VLAN_PRIORITY_MAX];
1154         u8 l3qt[UCC_GETH_IP_PRIORITY_MAX];
1155         u32 vtagtable[UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX];
1156         u8 iphoffset[TX_IP_OFFSET_ENTRY_MAX];
1157         u16 bdRingLenTx[NUM_TX_QUEUES];
1158         u16 bdRingLenRx[NUM_RX_QUEUES];
1159         enum ucc_geth_num_of_station_addresses numStationAddresses;
1160         enum qe_fltr_largest_external_tbl_lookup_key_size
1161             largestexternallookupkeysize;
1162         enum ucc_geth_statistics_gathering_mode statisticsMode;
1163         enum ucc_geth_vlan_operation_tagged vlanOperationTagged;
1164         enum ucc_geth_vlan_operation_non_tagged vlanOperationNonTagged;
1165         enum ucc_geth_qos_mode rxQoSMode;
1166         enum ucc_geth_flow_control_mode aufc;
1167         enum ucc_geth_maccfg2_pad_and_crc_mode padAndCrc;
1168         enum ucc_geth_num_of_threads numThreadsTx;
1169         enum ucc_geth_num_of_threads numThreadsRx;
1170         enum qe_risc_allocation riscTx;
1171         enum qe_risc_allocation riscRx;
1172 };
1173
1174 /* structure representing UCC GETH */
1175 struct ucc_geth_private {
1176         struct ucc_geth_info *ug_info;
1177         struct ucc_fast_private *uccf;
1178         struct net_device *dev;
1179         struct net_device_stats stats;  /* linux network statistics */
1180         struct ucc_geth *ug_regs;
1181         struct ucc_geth_init_pram *p_init_enet_param_shadow;
1182         struct ucc_geth_exf_global_pram *p_exf_glbl_param;
1183         u32 exf_glbl_param_offset;
1184         struct ucc_geth_rx_global_pram *p_rx_glbl_pram;
1185         u32 rx_glbl_pram_offset;
1186         struct ucc_geth_tx_global_pram *p_tx_glbl_pram;
1187         u32 tx_glbl_pram_offset;
1188         struct ucc_geth_send_queue_mem_region *p_send_q_mem_reg;
1189         u32 send_q_mem_reg_offset;
1190         struct ucc_geth_thread_data_tx *p_thread_data_tx;
1191         u32 thread_dat_tx_offset;
1192         struct ucc_geth_thread_data_rx *p_thread_data_rx;
1193         u32 thread_dat_rx_offset;
1194         struct ucc_geth_scheduler *p_scheduler;
1195         u32 scheduler_offset;
1196         struct ucc_geth_tx_firmware_statistics_pram *p_tx_fw_statistics_pram;
1197         u32 tx_fw_statistics_pram_offset;
1198         struct ucc_geth_rx_firmware_statistics_pram *p_rx_fw_statistics_pram;
1199         u32 rx_fw_statistics_pram_offset;
1200         struct ucc_geth_rx_interrupt_coalescing_table *p_rx_irq_coalescing_tbl;
1201         u32 rx_irq_coalescing_tbl_offset;
1202         struct ucc_geth_rx_bd_queues_entry *p_rx_bd_qs_tbl;
1203         u32 rx_bd_qs_tbl_offset;
1204         u8 *p_tx_bd_ring[NUM_TX_QUEUES];
1205         u32 tx_bd_ring_offset[NUM_TX_QUEUES];
1206         u8 *p_rx_bd_ring[NUM_RX_QUEUES];
1207         u32 rx_bd_ring_offset[NUM_RX_QUEUES];
1208         u8 *confBd[NUM_TX_QUEUES];
1209         u8 *txBd[NUM_TX_QUEUES];
1210         u8 *rxBd[NUM_RX_QUEUES];
1211         int badFrame[NUM_RX_QUEUES];
1212         u16 cpucount[NUM_TX_QUEUES];
1213         volatile u16 *p_cpucount[NUM_TX_QUEUES];
1214         int indAddrRegUsed[NUM_OF_PADDRS];
1215         u8 paddr[NUM_OF_PADDRS][ENET_NUM_OCTETS_PER_ADDRESS];   /* ethernet address */
1216         u8 numGroupAddrInHash;
1217         u8 numIndAddrInHash;
1218         u8 numIndAddrInReg;
1219         int rx_extended_features;
1220         int rx_non_dynamic_extended_features;
1221         struct list_head conf_skbs;
1222         struct list_head group_hash_q;
1223         struct list_head ind_hash_q;
1224         u32 saved_uccm;
1225         spinlock_t lock;
1226         /* pointers to arrays of skbuffs for tx and rx */
1227         struct sk_buff **tx_skbuff[NUM_TX_QUEUES];
1228         struct sk_buff **rx_skbuff[NUM_RX_QUEUES];
1229         /* indices pointing to the next free sbk in skb arrays */
1230         u16 skb_curtx[NUM_TX_QUEUES];
1231         u16 skb_currx[NUM_RX_QUEUES];
1232         /* index of the first skb which hasn't been transmitted yet. */
1233         u16 skb_dirtytx[NUM_TX_QUEUES];
1234
1235         struct ugeth_mii_info *mii_info;
1236         struct phy_device *phydev;
1237         phy_interface_t phy_interface;
1238         int max_speed;
1239         uint32_t msg_enable;
1240         int oldspeed;
1241         int oldduplex;
1242         int oldlink;
1243 };
1244
1245 #endif                          /* __UCC_GETH_H__ */