2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
15 #define DRV_NAME "uli526x"
16 #define DRV_VERSION "0.9.3"
17 #define DRV_RELDATE "2005-7-29"
19 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/string.h>
23 #include <linux/timer.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/dma-mapping.h>
38 #include <asm/processor.h>
39 #include <asm/bitops.h>
42 #include <asm/uaccess.h>
45 /* Board/System/Debug information/definition ---------------- */
46 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
49 #define ULI526X_IO_SIZE 0x100
50 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55 #define TX_BUF_ALLOC 0x600
56 #define RX_ALLOC_SIZE 0x620
57 #define ULI526X_RESET 1
59 #define CR6_DEFAULT 0x22200000
60 #define CR7_DEFAULT 0x180c1
61 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63 #define MAX_PACKET_SIZE 1514
64 #define ULI5261_MAX_MULTICAST 14
65 #define RX_COPY_SIZE 100
66 #define MAX_CHECK_PACKET 0x8000
68 #define ULI526X_10MHF 0
69 #define ULI526X_100MHF 1
70 #define ULI526X_10MFD 4
71 #define ULI526X_100MFD 5
72 #define ULI526X_AUTO 8
74 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
81 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
85 #define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
87 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ 0x4800
94 #define CR9_CRDOUT 0x8
95 #define SROM_DATA_0 0x0
96 #define SROM_DATA_1 0x4
97 #define PHY_DATA_1 0x20000
98 #define PHY_DATA_0 0x00000
99 #define MDCLKH 0x10000
101 #define PHY_POWER_DOWN 0x800
103 #define SROM_V41_CODE 0x14
105 #define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
113 /* Structure/enum declaration ------------------------------- */
115 u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118 } __attribute__(( aligned(32) ));
121 u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124 } __attribute__(( aligned(32) ));
126 struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
128 struct net_device *next_dev; /* next device */
129 struct pci_dev *pdev; /* PCI device */
132 long ioaddr; /* I/O base address */
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
171 /* System defined statistic counter */
172 struct net_device_stats stats;
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
187 unsigned char srom[128];
191 enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
198 enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
204 /* Global variable declaration ----------------------------- */
205 static int __devinitdata printed_version;
206 static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
210 static int uli526x_debug;
211 static unsigned char uli526x_media_mode = ULI526X_AUTO;
212 static u32 uli526x_cr6_user_set;
214 /* For module input parameter */
219 /* function declaration ------------------------------------- */
220 static int uli526x_open(struct net_device *);
221 static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222 static int uli526x_stop(struct net_device *);
223 static struct net_device_stats * uli526x_get_stats(struct net_device *);
224 static void uli526x_set_filter_mode(struct net_device *);
225 static const struct ethtool_ops netdev_ethtool_ops;
226 static u16 read_srom_word(long, int);
227 static irqreturn_t uli526x_interrupt(int, void *);
228 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
229 static void allocate_rx_buffer(struct uli526x_board_info *);
230 static void update_cr6(u32, unsigned long);
231 static void send_filter_frame(struct net_device *, int);
232 static u16 phy_read(unsigned long, u8, u8, u32);
233 static u16 phy_readby_cr10(unsigned long, u8, u8);
234 static void phy_write(unsigned long, u8, u8, u16, u32);
235 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
236 static void phy_write_1bit(unsigned long, u32, u32);
237 static u16 phy_read_1bit(unsigned long, u32);
238 static u8 uli526x_sense_speed(struct uli526x_board_info *);
239 static void uli526x_process_mode(struct uli526x_board_info *);
240 static void uli526x_timer(unsigned long);
241 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
242 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
243 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
244 static void uli526x_dynamic_reset(struct net_device *);
245 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
246 static void uli526x_init(struct net_device *);
247 static void uli526x_set_phyxcer(struct uli526x_board_info *);
249 /* ULI526X network board routine ---------------------------- */
252 * Search ULI526X board, allocate space and register it
255 static int __devinit uli526x_init_one (struct pci_dev *pdev,
256 const struct pci_device_id *ent)
258 struct uli526x_board_info *db; /* board information structure */
259 struct net_device *dev;
262 ULI526X_DBUG(0, "uli526x_init_one()", 0);
264 if (!printed_version++)
267 /* Init network device */
268 dev = alloc_etherdev(sizeof(*db));
271 SET_NETDEV_DEV(dev, &pdev->dev);
273 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
274 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
279 /* Enable Master/IO access, Disable memory access */
280 err = pci_enable_device(pdev);
284 if (!pci_resource_start(pdev, 0)) {
285 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
287 goto err_out_disable;
290 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
291 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
293 goto err_out_disable;
296 if (pci_request_regions(pdev, DRV_NAME)) {
297 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
299 goto err_out_disable;
302 /* Init system & device */
303 db = netdev_priv(dev);
305 /* Allocate Tx/Rx descriptor memory */
306 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
307 if(db->desc_pool_ptr == NULL)
312 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
313 if(db->buf_pool_ptr == NULL)
319 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
320 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
321 db->buf_pool_start = db->buf_pool_ptr;
322 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
324 db->chip_id = ent->driver_data;
325 db->ioaddr = pci_resource_start(pdev, 0);
330 dev->base_addr = db->ioaddr;
331 dev->irq = pdev->irq;
332 pci_set_drvdata(pdev, dev);
334 /* Register some necessary functions */
335 dev->open = &uli526x_open;
336 dev->hard_start_xmit = &uli526x_start_xmit;
337 dev->stop = &uli526x_stop;
338 dev->get_stats = &uli526x_get_stats;
339 dev->set_multicast_list = &uli526x_set_filter_mode;
340 dev->ethtool_ops = &netdev_ethtool_ops;
341 spin_lock_init(&db->lock);
344 /* read 64 word srom data */
345 for (i = 0; i < 64; i++)
346 ((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
348 /* Set Node address */
349 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
351 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
352 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
353 outl(0, db->ioaddr + DCR14); //Clear reset port
354 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
355 outl(0, db->ioaddr + DCR14); //Clear reset port
356 outl(0, db->ioaddr + DCR13); //Clear CR13
357 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
358 //Read MAC address from CR14
359 for (i = 0; i < 6; i++)
360 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
362 outl(0, db->ioaddr + DCR13); //Clear CR13
363 outl(0, db->ioaddr + DCR0); //Clear CR0
368 for (i = 0; i < 6; i++)
369 dev->dev_addr[i] = db->srom[20 + i];
371 err = register_netdev (dev);
375 printk(KERN_INFO "%s: ULi M%04lx at pci%s,",dev->name,ent->driver_data >> 16,pci_name(pdev));
377 for (i = 0; i < 6; i++)
378 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
379 printk(", irq %d.\n", dev->irq);
381 pci_set_master(pdev);
386 pci_release_regions(pdev);
388 if(db->desc_pool_ptr)
389 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
390 db->desc_pool_ptr, db->desc_pool_dma_ptr);
392 if(db->buf_pool_ptr != NULL)
393 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
394 db->buf_pool_ptr, db->buf_pool_dma_ptr);
396 pci_disable_device(pdev);
398 pci_set_drvdata(pdev, NULL);
405 static void __devexit uli526x_remove_one (struct pci_dev *pdev)
407 struct net_device *dev = pci_get_drvdata(pdev);
408 struct uli526x_board_info *db = netdev_priv(dev);
410 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
412 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
413 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
414 db->desc_pool_dma_ptr);
415 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
416 db->buf_pool_ptr, db->buf_pool_dma_ptr);
417 unregister_netdev(dev);
418 pci_release_regions(pdev);
419 free_netdev(dev); /* free board information */
420 pci_set_drvdata(pdev, NULL);
421 pci_disable_device(pdev);
422 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
427 * Open the interface.
428 * The interface is opened whenever "ifconfig" activates it.
431 static int uli526x_open(struct net_device *dev)
434 struct uli526x_board_info *db = netdev_priv(dev);
436 ULI526X_DBUG(0, "uli526x_open", 0);
438 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
442 /* system variable init */
443 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
444 db->tx_packet_cnt = 0;
445 db->rx_avail_cnt = 0;
447 netif_carrier_off(dev);
450 db->NIC_capability = 0xf; /* All capability*/
451 db->PHY_reg4 = 0x1e0;
453 /* CR6 operation mode decision */
454 db->cr6_data |= ULI526X_TXTH_256;
455 db->cr0_data = CR0_DEFAULT;
457 /* Initialize ULI526X board */
460 /* Active System Interface */
461 netif_wake_queue(dev);
463 /* set and active a timer process */
464 init_timer(&db->timer);
465 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
466 db->timer.data = (unsigned long)dev;
467 db->timer.function = &uli526x_timer;
468 add_timer(&db->timer);
474 /* Initialize ULI526X board
475 * Reset ULI526X board
476 * Initialize TX/Rx descriptor chain structure
477 * Send the set-up frame
478 * Enable Tx/Rx machine
481 static void uli526x_init(struct net_device *dev)
483 struct uli526x_board_info *db = netdev_priv(dev);
484 unsigned long ioaddr = db->ioaddr;
489 ULI526X_DBUG(0, "uli526x_init()", 0);
491 /* Reset M526x MAC controller */
492 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
494 outl(db->cr0_data, ioaddr + DCR0);
497 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
499 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
501 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
502 if(phy_value != 0xffff&&phy_value!=0)
504 db->phy_addr = phy_tmp;
509 printk(KERN_WARNING "Can not find the phy address!!!");
510 /* Parser SROM and media mode */
511 db->media_mode = uli526x_media_mode;
513 /* Phyxcer capability setting */
514 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
515 phy_reg_reset = (phy_reg_reset | 0x8000);
516 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
519 /* Process Phyxcer Media Mode */
520 uli526x_set_phyxcer(db);
522 /* Media Mode Process */
523 if ( !(db->media_mode & ULI526X_AUTO) )
524 db->op_mode = db->media_mode; /* Force Mode */
526 /* Initialize Transmit/Receive decriptor and CR3/4 */
527 uli526x_descriptor_init(db, ioaddr);
529 /* Init CR6 to program M526X operation */
530 update_cr6(db->cr6_data, ioaddr);
532 /* Send setup frame */
533 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
535 /* Init CR7, interrupt active bit */
536 db->cr7_data = CR7_DEFAULT;
537 outl(db->cr7_data, ioaddr + DCR7);
539 /* Init CR15, Tx jabber and Rx watchdog timer */
540 outl(db->cr15_data, ioaddr + DCR15);
542 /* Enable ULI526X Tx/Rx function */
543 db->cr6_data |= CR6_RXSC | CR6_TXSC;
544 update_cr6(db->cr6_data, ioaddr);
549 * Hardware start transmission.
550 * Send a packet to media from the upper layer.
553 static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
555 struct uli526x_board_info *db = netdev_priv(dev);
556 struct tx_desc *txptr;
559 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
561 /* Resource flag check */
562 netif_stop_queue(dev);
564 /* Too large packet check */
565 if (skb->len > MAX_PACKET_SIZE) {
566 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
571 spin_lock_irqsave(&db->lock, flags);
573 /* No Tx resource check, it never happen nromally */
574 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
575 spin_unlock_irqrestore(&db->lock, flags);
576 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
580 /* Disable NIC interrupt */
581 outl(0, dev->base_addr + DCR7);
583 /* transmit this packet */
584 txptr = db->tx_insert_ptr;
585 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
586 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
588 /* Point to next transmit free descriptor */
589 db->tx_insert_ptr = txptr->next_tx_desc;
591 /* Transmit Packet Process */
592 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
593 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
594 db->tx_packet_cnt++; /* Ready to send */
595 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
596 dev->trans_start = jiffies; /* saved time stamp */
599 /* Tx resource check */
600 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
601 netif_wake_queue(dev);
603 /* Restore CR7 to enable interrupt */
604 spin_unlock_irqrestore(&db->lock, flags);
605 outl(db->cr7_data, dev->base_addr + DCR7);
615 * Stop the interface.
616 * The interface is stopped when it is brought.
619 static int uli526x_stop(struct net_device *dev)
621 struct uli526x_board_info *db = netdev_priv(dev);
622 unsigned long ioaddr = dev->base_addr;
624 ULI526X_DBUG(0, "uli526x_stop", 0);
627 netif_stop_queue(dev);
630 del_timer_sync(&db->timer);
632 /* Reset & stop ULI526X board */
633 outl(ULI526X_RESET, ioaddr + DCR0);
635 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
638 free_irq(dev->irq, dev);
640 /* free allocated rx buffer */
641 uli526x_free_rxbuffer(db);
644 /* show statistic counter */
645 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
646 db->tx_fifo_underrun, db->tx_excessive_collision,
647 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
648 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
649 db->reset_fatal, db->reset_TXtimeout);
657 * M5261/M5263 insterrupt handler
658 * receive the packet to upper layer, free the transmitted packet
661 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
663 struct net_device *dev = dev_id;
664 struct uli526x_board_info *db = netdev_priv(dev);
665 unsigned long ioaddr = dev->base_addr;
669 ULI526X_DBUG(1, "uli526x_interrupt() without DEVICE arg", 0);
673 spin_lock_irqsave(&db->lock, flags);
674 outl(0, ioaddr + DCR7);
676 /* Got ULI526X status */
677 db->cr5_data = inl(ioaddr + DCR5);
678 outl(db->cr5_data, ioaddr + DCR5);
679 if ( !(db->cr5_data & 0x180c1) ) {
680 spin_unlock_irqrestore(&db->lock, flags);
681 outl(db->cr7_data, ioaddr + DCR7);
685 /* Check system status */
686 if (db->cr5_data & 0x2000) {
687 /* system bus error happen */
688 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
690 db->wait_reset = 1; /* Need to RESET */
691 spin_unlock_irqrestore(&db->lock, flags);
695 /* Received the coming packet */
696 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
697 uli526x_rx_packet(dev, db);
699 /* reallocate rx descriptor buffer */
700 if (db->rx_avail_cnt<RX_DESC_CNT)
701 allocate_rx_buffer(db);
703 /* Free the transmitted descriptor */
704 if ( db->cr5_data & 0x01)
705 uli526x_free_tx_pkt(dev, db);
707 /* Restore CR7 to enable interrupt mask */
708 outl(db->cr7_data, ioaddr + DCR7);
710 spin_unlock_irqrestore(&db->lock, flags);
716 * Free TX resource after TX complete
719 static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
721 struct tx_desc *txptr;
724 txptr = db->tx_remove_ptr;
725 while(db->tx_packet_cnt) {
726 tdes0 = le32_to_cpu(txptr->tdes0);
727 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
728 if (tdes0 & 0x80000000)
731 /* A packet sent completed */
733 db->stats.tx_packets++;
735 /* Transmit statistic counter */
736 if ( tdes0 != 0x7fffffff ) {
737 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
738 db->stats.collisions += (tdes0 >> 3) & 0xf;
739 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
740 if (tdes0 & TDES0_ERR_MASK) {
741 db->stats.tx_errors++;
742 if (tdes0 & 0x0002) { /* UnderRun */
743 db->tx_fifo_underrun++;
744 if ( !(db->cr6_data & CR6_SFT) ) {
745 db->cr6_data = db->cr6_data | CR6_SFT;
746 update_cr6(db->cr6_data, db->ioaddr);
750 db->tx_excessive_collision++;
752 db->tx_late_collision++;
756 db->tx_loss_carrier++;
758 db->tx_jabber_timeout++;
762 txptr = txptr->next_tx_desc;
765 /* Update TX remove pointer to next */
766 db->tx_remove_ptr = txptr;
768 /* Resource available check */
769 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
770 netif_wake_queue(dev); /* Active upper layer, send again */
775 * Receive the come packet and pass to upper layer
778 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
780 struct rx_desc *rxptr;
785 rxptr = db->rx_ready_ptr;
787 while(db->rx_avail_cnt) {
788 rdes0 = le32_to_cpu(rxptr->rdes0);
789 if (rdes0 & 0x80000000) /* packet owner check */
795 db->interval_rx_cnt++;
797 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
798 if ( (rdes0 & 0x300) != 0x300) {
799 /* A packet without First/Last flag */
801 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
802 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
804 /* A packet with First/Last flag */
805 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
807 /* error summary bit check */
808 if (rdes0 & 0x8000) {
809 /* This is a error packet */
810 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
811 db->stats.rx_errors++;
813 db->stats.rx_fifo_errors++;
815 db->stats.rx_crc_errors++;
817 db->stats.rx_length_errors++;
820 if ( !(rdes0 & 0x8000) ||
821 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
822 skb = rxptr->rx_skb_ptr;
824 /* Good packet, send to upper layer */
825 /* Shorst packet used new SKB */
826 if ( (rxlen < RX_COPY_SIZE) &&
827 ( (skb = dev_alloc_skb(rxlen + 2) )
829 /* size less than COPY_SIZE, allocate a rxlen SKB */
830 skb_reserve(skb, 2); /* 16byte align */
831 memcpy(skb_put(skb, rxlen),
832 skb_tail_pointer(rxptr->rx_skb_ptr),
834 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
838 skb->protocol = eth_type_trans(skb, dev);
840 dev->last_rx = jiffies;
841 db->stats.rx_packets++;
842 db->stats.rx_bytes += rxlen;
845 /* Reuse SKB buffer when the packet is error */
846 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
847 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
851 rxptr = rxptr->next_rx_desc;
854 db->rx_ready_ptr = rxptr;
859 * Get statistics from driver.
862 static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
864 struct uli526x_board_info *db = netdev_priv(dev);
866 ULI526X_DBUG(0, "uli526x_get_stats", 0);
872 * Set ULI526X multicast address
875 static void uli526x_set_filter_mode(struct net_device * dev)
877 struct uli526x_board_info *db = dev->priv;
880 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
881 spin_lock_irqsave(&db->lock, flags);
883 if (dev->flags & IFF_PROMISC) {
884 ULI526X_DBUG(0, "Enable PROM Mode", 0);
885 db->cr6_data |= CR6_PM | CR6_PBF;
886 update_cr6(db->cr6_data, db->ioaddr);
887 spin_unlock_irqrestore(&db->lock, flags);
891 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
892 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
893 db->cr6_data &= ~(CR6_PM | CR6_PBF);
894 db->cr6_data |= CR6_PAM;
895 spin_unlock_irqrestore(&db->lock, flags);
899 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
900 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
901 spin_unlock_irqrestore(&db->lock, flags);
905 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
907 ecmd->supported = (SUPPORTED_10baseT_Half |
908 SUPPORTED_10baseT_Full |
909 SUPPORTED_100baseT_Half |
910 SUPPORTED_100baseT_Full |
914 ecmd->advertising = (ADVERTISED_10baseT_Half |
915 ADVERTISED_10baseT_Full |
916 ADVERTISED_100baseT_Half |
917 ADVERTISED_100baseT_Full |
922 ecmd->port = PORT_MII;
923 ecmd->phy_address = db->phy_addr;
925 ecmd->transceiver = XCVR_EXTERNAL;
928 ecmd->duplex = DUPLEX_HALF;
930 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
934 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
936 ecmd->duplex = DUPLEX_FULL;
944 if (db->media_mode & ULI526X_AUTO)
946 ecmd->autoneg = AUTONEG_ENABLE;
950 static void netdev_get_drvinfo(struct net_device *dev,
951 struct ethtool_drvinfo *info)
953 struct uli526x_board_info *np = netdev_priv(dev);
955 strcpy(info->driver, DRV_NAME);
956 strcpy(info->version, DRV_VERSION);
958 strcpy(info->bus_info, pci_name(np->pdev));
960 sprintf(info->bus_info, "EISA 0x%lx %d",
961 dev->base_addr, dev->irq);
964 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
965 struct uli526x_board_info *np = netdev_priv(dev);
967 ULi_ethtool_gset(np, cmd);
972 static u32 netdev_get_link(struct net_device *dev) {
973 struct uli526x_board_info *np = netdev_priv(dev);
981 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
983 wol->supported = WAKE_PHY | WAKE_MAGIC;
987 static const struct ethtool_ops netdev_ethtool_ops = {
988 .get_drvinfo = netdev_get_drvinfo,
989 .get_settings = netdev_get_settings,
990 .get_link = netdev_get_link,
991 .get_wol = uli526x_get_wol,
995 * A periodic timer routine
996 * Dynamic media sense, allocate Rx buffer...
999 static void uli526x_timer(unsigned long data)
1002 unsigned char tmp_cr12=0;
1003 struct net_device *dev = (struct net_device *) data;
1004 struct uli526x_board_info *db = netdev_priv(dev);
1005 unsigned long flags;
1008 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1009 spin_lock_irqsave(&db->lock, flags);
1012 /* Dynamic reset ULI526X : system error or transmit time-out */
1013 tmp_cr8 = inl(db->ioaddr + DCR8);
1014 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1018 db->interval_rx_cnt = 0;
1020 /* TX polling kick monitor */
1021 if ( db->tx_packet_cnt &&
1022 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
1023 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1026 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1027 db->reset_TXtimeout++;
1029 printk( "%s: Tx timeout - resetting\n",
1034 if (db->wait_reset) {
1035 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1037 uli526x_dynamic_reset(dev);
1038 db->timer.expires = ULI526X_TIMER_WUT;
1039 add_timer(&db->timer);
1040 spin_unlock_irqrestore(&db->lock, flags);
1044 /* Link status check, Dynamic media type change */
1045 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1048 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1050 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1051 netif_carrier_off(dev);
1052 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1053 db->link_failed = 1;
1055 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1056 /* AUTO don't need */
1057 if ( !(db->media_mode & 0x8) )
1058 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1060 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1061 if (db->media_mode & ULI526X_AUTO) {
1062 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1063 update_cr6(db->cr6_data, db->ioaddr);
1066 if ((tmp_cr12 & 0x3) && db->link_failed) {
1067 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1068 db->link_failed = 0;
1070 /* Auto Sense Speed */
1071 if ( (db->media_mode & ULI526X_AUTO) &&
1072 uli526x_sense_speed(db) )
1073 db->link_failed = 1;
1074 uli526x_process_mode(db);
1076 if(db->link_failed==0)
1078 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1082 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1084 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1088 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1090 netif_carrier_on(dev);
1092 /* SHOW_MEDIA_TYPE(db->op_mode); */
1094 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1098 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1099 netif_carrier_off(dev);
1104 /* Timer active again */
1105 db->timer.expires = ULI526X_TIMER_WUT;
1106 add_timer(&db->timer);
1107 spin_unlock_irqrestore(&db->lock, flags);
1112 * Stop ULI526X board
1113 * Free Tx/Rx allocated memory
1114 * Init system variable
1117 static void uli526x_reset_prepare(struct net_device *dev)
1119 struct uli526x_board_info *db = netdev_priv(dev);
1121 /* Sopt MAC controller */
1122 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1123 update_cr6(db->cr6_data, dev->base_addr);
1124 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1125 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1127 /* Disable upper layer interface */
1128 netif_stop_queue(dev);
1130 /* Free Rx Allocate buffer */
1131 uli526x_free_rxbuffer(db);
1133 /* system variable init */
1134 db->tx_packet_cnt = 0;
1135 db->rx_avail_cnt = 0;
1136 db->link_failed = 1;
1143 * Dynamic reset the ULI526X board
1144 * Stop ULI526X board
1145 * Free Tx/Rx allocated memory
1146 * Reset ULI526X board
1147 * Re-initialize ULI526X board
1150 static void uli526x_dynamic_reset(struct net_device *dev)
1152 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1154 uli526x_reset_prepare(dev);
1156 /* Re-initialize ULI526X board */
1159 /* Restart upper layer interface */
1160 netif_wake_queue(dev);
1167 * Suspend the interface.
1170 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1172 struct net_device *dev = pci_get_drvdata(pdev);
1173 pci_power_t power_state;
1176 ULI526X_DBUG(0, "uli526x_suspend", 0);
1178 if (!netdev_priv(dev))
1181 pci_save_state(pdev);
1183 if (!netif_running(dev))
1186 netif_device_detach(dev);
1187 uli526x_reset_prepare(dev);
1189 power_state = pci_choose_state(pdev, state);
1190 pci_enable_wake(pdev, power_state, 0);
1191 err = pci_set_power_state(pdev, power_state);
1193 netif_device_attach(dev);
1194 /* Re-initialize ULI526X board */
1196 /* Restart upper layer interface */
1197 netif_wake_queue(dev);
1204 * Resume the interface.
1207 static int uli526x_resume(struct pci_dev *pdev)
1209 struct net_device *dev = pci_get_drvdata(pdev);
1212 ULI526X_DBUG(0, "uli526x_resume", 0);
1214 if (!netdev_priv(dev))
1217 pci_restore_state(pdev);
1219 if (!netif_running(dev))
1222 err = pci_set_power_state(pdev, PCI_D0);
1224 printk(KERN_WARNING "%s: Could not put device into D0\n",
1229 netif_device_attach(dev);
1230 /* Re-initialize ULI526X board */
1232 /* Restart upper layer interface */
1233 netif_wake_queue(dev);
1238 #else /* !CONFIG_PM */
1240 #define uli526x_suspend NULL
1241 #define uli526x_resume NULL
1243 #endif /* !CONFIG_PM */
1247 * free all allocated rx buffer
1250 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1252 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1254 /* free allocated rx buffer */
1255 while (db->rx_avail_cnt) {
1256 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1257 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1264 * Reuse the SK buffer
1267 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1269 struct rx_desc *rxptr = db->rx_insert_ptr;
1271 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1272 rxptr->rx_skb_ptr = skb;
1273 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1274 skb_tail_pointer(skb),
1276 PCI_DMA_FROMDEVICE));
1278 rxptr->rdes0 = cpu_to_le32(0x80000000);
1280 db->rx_insert_ptr = rxptr->next_rx_desc;
1282 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1287 * Initialize transmit/Receive descriptor
1288 * Using Chain structure, and allocate Tx/Rx buffer
1291 static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1293 struct tx_desc *tmp_tx;
1294 struct rx_desc *tmp_rx;
1295 unsigned char *tmp_buf;
1296 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1297 dma_addr_t tmp_buf_dma;
1300 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1302 /* tx descriptor start pointer */
1303 db->tx_insert_ptr = db->first_tx_desc;
1304 db->tx_remove_ptr = db->first_tx_desc;
1305 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1307 /* rx descriptor start pointer */
1308 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1309 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1310 db->rx_insert_ptr = db->first_rx_desc;
1311 db->rx_ready_ptr = db->first_rx_desc;
1312 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1314 /* Init Transmit chain */
1315 tmp_buf = db->buf_pool_start;
1316 tmp_buf_dma = db->buf_pool_dma_start;
1317 tmp_tx_dma = db->first_tx_desc_dma;
1318 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1319 tmp_tx->tx_buf_ptr = tmp_buf;
1320 tmp_tx->tdes0 = cpu_to_le32(0);
1321 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1322 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1323 tmp_tx_dma += sizeof(struct tx_desc);
1324 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1325 tmp_tx->next_tx_desc = tmp_tx + 1;
1326 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1327 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1329 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1330 tmp_tx->next_tx_desc = db->first_tx_desc;
1332 /* Init Receive descriptor chain */
1333 tmp_rx_dma=db->first_rx_desc_dma;
1334 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1335 tmp_rx->rdes0 = cpu_to_le32(0);
1336 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1337 tmp_rx_dma += sizeof(struct rx_desc);
1338 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1339 tmp_rx->next_rx_desc = tmp_rx + 1;
1341 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1342 tmp_rx->next_rx_desc = db->first_rx_desc;
1344 /* pre-allocate Rx buffer */
1345 allocate_rx_buffer(db);
1351 * Firstly stop ULI526X, then written value and start
1354 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1357 outl(cr6_data, ioaddr + DCR6);
1363 * Send a setup frame for M5261/M5263
1364 * This setup frame initialize ULI526X address filter mode
1367 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1369 struct uli526x_board_info *db = netdev_priv(dev);
1370 struct dev_mc_list *mcptr;
1371 struct tx_desc *txptr;
1376 ULI526X_DBUG(0, "send_filter_frame()", 0);
1378 txptr = db->tx_insert_ptr;
1379 suptr = (u32 *) txptr->tx_buf_ptr;
1382 addrptr = (u16 *) dev->dev_addr;
1383 *suptr++ = addrptr[0];
1384 *suptr++ = addrptr[1];
1385 *suptr++ = addrptr[2];
1387 /* broadcast address */
1392 /* fit the multicast address */
1393 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1394 addrptr = (u16 *) mcptr->dmi_addr;
1395 *suptr++ = addrptr[0];
1396 *suptr++ = addrptr[1];
1397 *suptr++ = addrptr[2];
1406 /* prepare the setup frame */
1407 db->tx_insert_ptr = txptr->next_tx_desc;
1408 txptr->tdes1 = cpu_to_le32(0x890000c0);
1410 /* Resource Check and Send the setup packet */
1411 if (db->tx_packet_cnt < TX_DESC_CNT) {
1412 /* Resource Empty */
1413 db->tx_packet_cnt++;
1414 txptr->tdes0 = cpu_to_le32(0x80000000);
1415 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1416 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1417 update_cr6(db->cr6_data, dev->base_addr);
1418 dev->trans_start = jiffies;
1420 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1425 * Allocate rx buffer,
1426 * As possible as allocate maxiumn Rx buffer
1429 static void allocate_rx_buffer(struct uli526x_board_info *db)
1431 struct rx_desc *rxptr;
1432 struct sk_buff *skb;
1434 rxptr = db->rx_insert_ptr;
1436 while(db->rx_avail_cnt < RX_DESC_CNT) {
1437 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1439 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1440 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1441 skb_tail_pointer(skb),
1443 PCI_DMA_FROMDEVICE));
1445 rxptr->rdes0 = cpu_to_le32(0x80000000);
1446 rxptr = rxptr->next_rx_desc;
1450 db->rx_insert_ptr = rxptr;
1455 * Read one word data from the serial ROM
1458 static u16 read_srom_word(long ioaddr, int offset)
1462 long cr9_ioaddr = ioaddr + DCR9;
1464 outl(CR9_SROM_READ, cr9_ioaddr);
1465 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1467 /* Send the Read Command 110b */
1468 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1469 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1470 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1472 /* Send the offset */
1473 for (i = 5; i >= 0; i--) {
1474 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1475 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1478 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1480 for (i = 16; i > 0; i--) {
1481 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1483 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1484 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1488 outl(CR9_SROM_READ, cr9_ioaddr);
1494 * Auto sense the media mode
1497 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1502 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1503 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1505 if ( (phy_mode & 0x24) == 0x24 ) {
1507 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1510 else if(phy_mode&0x4000)
1512 else if(phy_mode&0x2000)
1517 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1519 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1520 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1521 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1522 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1523 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1526 db->op_mode = ULI526X_10MHF;
1527 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1536 * Set 10/100 phyxcer capability
1537 * AUTO mode : phyxcer register4 is NIC capability
1538 * Force mode: phyxcer register4 is the force media
1541 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1545 /* Phyxcer capability setting */
1546 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1548 if (db->media_mode & ULI526X_AUTO) {
1550 phy_reg |= db->PHY_reg4;
1553 switch(db->media_mode) {
1554 case ULI526X_10MHF: phy_reg |= 0x20; break;
1555 case ULI526X_10MFD: phy_reg |= 0x40; break;
1556 case ULI526X_100MHF: phy_reg |= 0x80; break;
1557 case ULI526X_100MFD: phy_reg |= 0x100; break;
1562 /* Write new capability to Phyxcer Reg4 */
1563 if ( !(phy_reg & 0x01e0)) {
1564 phy_reg|=db->PHY_reg4;
1565 db->media_mode|=ULI526X_AUTO;
1567 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1569 /* Restart Auto-Negotiation */
1570 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1577 AUTO mode : PHY controller in Auto-negotiation Mode
1578 * Force mode: PHY controller in force mode with HUB
1579 * N-way force capability with SWITCH
1582 static void uli526x_process_mode(struct uli526x_board_info *db)
1586 /* Full Duplex Mode Check */
1587 if (db->op_mode & 0x4)
1588 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1590 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1592 update_cr6(db->cr6_data, db->ioaddr);
1594 /* 10/100M phyxcer force mode need */
1595 if ( !(db->media_mode & 0x8)) {
1597 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1598 if ( !(phy_reg & 0x1) ) {
1599 /* parter without N-Way capability */
1601 switch(db->op_mode) {
1602 case ULI526X_10MHF: phy_reg = 0x0; break;
1603 case ULI526X_10MFD: phy_reg = 0x100; break;
1604 case ULI526X_100MHF: phy_reg = 0x2000; break;
1605 case ULI526X_100MFD: phy_reg = 0x2100; break;
1607 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1608 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1615 * Write a word to Phy register
1618 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1621 unsigned long ioaddr;
1623 if(chip_id == PCI_ULI5263_ID)
1625 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1628 /* M5261/M5263 Chip */
1629 ioaddr = iobase + DCR9;
1631 /* Send 33 synchronization clock to Phy controller */
1632 for (i = 0; i < 35; i++)
1633 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1635 /* Send start command(01) to Phy */
1636 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1637 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1639 /* Send write command(01) to Phy */
1640 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1641 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1643 /* Send Phy address */
1644 for (i = 0x10; i > 0; i = i >> 1)
1645 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1647 /* Send register address */
1648 for (i = 0x10; i > 0; i = i >> 1)
1649 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1651 /* written trasnition */
1652 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1653 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1655 /* Write a word data to PHY controller */
1656 for ( i = 0x8000; i > 0; i >>= 1)
1657 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1663 * Read a word data from phy register
1666 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1670 unsigned long ioaddr;
1672 if(chip_id == PCI_ULI5263_ID)
1673 return phy_readby_cr10(iobase, phy_addr, offset);
1674 /* M5261/M5263 Chip */
1675 ioaddr = iobase + DCR9;
1677 /* Send 33 synchronization clock to Phy controller */
1678 for (i = 0; i < 35; i++)
1679 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1681 /* Send start command(01) to Phy */
1682 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1683 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1685 /* Send read command(10) to Phy */
1686 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1687 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1689 /* Send Phy address */
1690 for (i = 0x10; i > 0; i = i >> 1)
1691 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1693 /* Send register address */
1694 for (i = 0x10; i > 0; i = i >> 1)
1695 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1697 /* Skip transition state */
1698 phy_read_1bit(ioaddr, chip_id);
1700 /* read 16bit data */
1701 for (phy_data = 0, i = 0; i < 16; i++) {
1703 phy_data |= phy_read_1bit(ioaddr, chip_id);
1709 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1711 unsigned long ioaddr,cr10_value;
1713 ioaddr = iobase + DCR10;
1714 cr10_value = phy_addr;
1715 cr10_value = (cr10_value<<5) + offset;
1716 cr10_value = (cr10_value<<16) + 0x08000000;
1717 outl(cr10_value,ioaddr);
1721 cr10_value = inl(ioaddr);
1722 if(cr10_value&0x10000000)
1725 return (cr10_value&0x0ffff);
1728 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1730 unsigned long ioaddr,cr10_value;
1732 ioaddr = iobase + DCR10;
1733 cr10_value = phy_addr;
1734 cr10_value = (cr10_value<<5) + offset;
1735 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1736 outl(cr10_value,ioaddr);
1740 * Write one bit data to Phy Controller
1743 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1745 outl(phy_data , ioaddr); /* MII Clock Low */
1747 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1749 outl(phy_data , ioaddr); /* MII Clock Low */
1755 * Read one bit phy data from PHY controller
1758 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1762 outl(0x50000 , ioaddr);
1764 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1765 outl(0x40000 , ioaddr);
1772 static struct pci_device_id uli526x_pci_tbl[] = {
1773 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1774 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1777 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1780 static struct pci_driver uli526x_driver = {
1782 .id_table = uli526x_pci_tbl,
1783 .probe = uli526x_init_one,
1784 .remove = __devexit_p(uli526x_remove_one),
1785 .suspend = uli526x_suspend,
1786 .resume = uli526x_resume,
1789 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1790 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1791 MODULE_LICENSE("GPL");
1793 module_param(debug, int, 0644);
1794 module_param(mode, int, 0);
1795 module_param(cr6set, int, 0);
1796 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1797 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1800 * when user used insmod to add module, system invoked init_module()
1801 * to register the services.
1804 static int __init uli526x_init_module(void)
1808 printed_version = 1;
1810 ULI526X_DBUG(0, "init_module() ", debug);
1813 uli526x_debug = debug; /* set debug flag */
1815 uli526x_cr6_user_set = cr6set;
1819 case ULI526X_100MHF:
1821 case ULI526X_100MFD:
1822 uli526x_media_mode = mode;
1825 uli526x_media_mode = ULI526X_AUTO;
1829 return pci_register_driver(&uli526x_driver);
1835 * when user used rmmod to delete module, system invoked clean_module()
1836 * to un-register all registered services.
1839 static void __exit uli526x_cleanup_module(void)
1841 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1842 pci_unregister_driver(&uli526x_driver);
1845 module_init(uli526x_init_module);
1846 module_exit(uli526x_cleanup_module);