2 A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
3 ethernet driver for Linux.
4 Copyright (C) 1997 Sten Wang
6 This program is free software; you can redistribute it and/or
7 modify it under the terms of the GNU General Public License
8 as published by the Free Software Foundation; either version 2
9 of the License, or (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 DAVICOM Web-Site: www.davicom.com.tw
18 Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
19 Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
21 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
23 Marcelo Tosatti <marcelo@conectiva.com.br> :
24 Made it compile in 2.3 (device to net_device)
26 Alan Cox <alan@redhat.com> :
27 Cleaned up for kernel merge.
28 Removed the back compatibility support
29 Reformatted, fixing spelling etc as I went
30 Removed IRQ 0-15 assumption
32 Jeff Garzik <jgarzik@pobox.com> :
33 Updated to use new PCI driver API.
34 Resource usage cleanups.
35 Report driver version to user.
37 Tobias Ringstrom <tori@unhappy.mine.nu> :
38 Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
39 Andrew Morton and Frank Davis for the SMP safety fixes.
41 Vojtech Pavlik <vojtech@suse.cz> :
42 Cleaned up pointer arithmetics.
43 Fixed a lot of 64bit issues.
44 Cleaned up printk()s a bit.
45 Fixed some obvious big endian problems.
47 Tobias Ringstrom <tori@unhappy.mine.nu> :
48 Use time_after for jiffies calculation. Added ethtool
49 support. Updated PCI resource allocation. Do not
50 forget to unmap PCI mapped skbs.
52 Alan Cox <alan@redhat.com>
53 Added new PCI identifiers provided by Clear Zhang at ALi
54 for their 1563 ethernet device.
58 Check on 64 bit boxes.
59 Check and fix on big endian boxes.
61 Test and make sure PCI latency is now correct for all cases.
64 #define DRV_NAME "dmfe"
65 #define DRV_VERSION "1.36.4"
66 #define DRV_RELDATE "2002-01-17"
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/string.h>
71 #include <linux/timer.h>
72 #include <linux/ptrace.h>
73 #include <linux/errno.h>
74 #include <linux/ioport.h>
75 #include <linux/slab.h>
76 #include <linux/interrupt.h>
77 #include <linux/pci.h>
78 #include <linux/dma-mapping.h>
79 #include <linux/init.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/ethtool.h>
83 #include <linux/skbuff.h>
84 #include <linux/delay.h>
85 #include <linux/spinlock.h>
86 #include <linux/crc32.h>
87 #include <linux/bitops.h>
89 #include <asm/processor.h>
92 #include <asm/uaccess.h>
96 /* Board/System/Debug information/definition ---------------- */
97 #define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
98 #define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
99 #define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
100 #define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
102 #define DM9102_IO_SIZE 0x80
103 #define DM9102A_IO_SIZE 0x100
104 #define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
105 #define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
106 #define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
107 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
108 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
109 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
110 #define TX_BUF_ALLOC 0x600
111 #define RX_ALLOC_SIZE 0x620
112 #define DM910X_RESET 1
113 #define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
114 #define CR6_DEFAULT 0x00080000 /* HD */
115 #define CR7_DEFAULT 0x180c1
116 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
117 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
118 #define MAX_PACKET_SIZE 1514
119 #define DMFE_MAX_MULTICAST 14
120 #define RX_COPY_SIZE 100
121 #define MAX_CHECK_PACKET 0x8000
122 #define DM9801_NOISE_FLOOR 8
123 #define DM9802_NOISE_FLOOR 5
125 #define DMFE_WOL_LINKCHANGE 0x20000000
126 #define DMFE_WOL_SAMPLEPACKET 0x10000000
127 #define DMFE_WOL_MAGICPACKET 0x08000000
131 #define DMFE_100MHF 1
133 #define DMFE_100MFD 5
135 #define DMFE_1M_HPNA 0x10
137 #define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
138 #define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
139 #define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
140 #define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
141 #define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
142 #define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
144 #define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
145 #define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
146 #define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
148 #define DMFE_DBUG(dbug_now, msg, value) \
150 if (dmfe_debug || (dbug_now)) \
151 printk(KERN_ERR DRV_NAME ": %s %lx\n",\
152 (msg), (long) (value)); \
155 #define SHOW_MEDIA_TYPE(mode) \
156 printk (KERN_INFO DRV_NAME ": Change Speed to %sMhz %s duplex\n" , \
157 (mode & 1) ? "100":"10", (mode & 4) ? "full":"half");
160 /* CR9 definition: SROM/MII */
161 #define CR9_SROM_READ 0x4800
163 #define CR9_SRCLK 0x2
164 #define CR9_CRDOUT 0x8
165 #define SROM_DATA_0 0x0
166 #define SROM_DATA_1 0x4
167 #define PHY_DATA_1 0x20000
168 #define PHY_DATA_0 0x00000
169 #define MDCLKH 0x10000
171 #define PHY_POWER_DOWN 0x800
173 #define SROM_V41_CODE 0x14
175 #define SROM_CLK_WRITE(data, ioaddr) \
176 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
178 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
180 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
183 #define __CHK_IO_SIZE(pci_id, dev_rev) \
184 (( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x30) ) ? \
185 DM9102A_IO_SIZE: DM9102_IO_SIZE)
187 #define CHK_IO_SIZE(pci_dev) \
188 (__CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, \
189 (pci_dev)->revision))
192 #define DEVICE net_device
194 /* Structure/enum declaration ------------------------------- */
196 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
197 char *tx_buf_ptr; /* Data for us */
198 struct tx_desc *next_tx_desc;
199 } __attribute__(( aligned(32) ));
202 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
203 struct sk_buff *rx_skb_ptr; /* Data for us */
204 struct rx_desc *next_rx_desc;
205 } __attribute__(( aligned(32) ));
207 struct dmfe_board_info {
208 u32 chip_id; /* Chip vendor/Device ID */
209 u8 chip_revision; /* Chip revision */
210 struct DEVICE *next_dev; /* next device */
211 struct pci_dev *pdev; /* PCI device */
214 long ioaddr; /* I/O base address */
221 /* pointer for memory physical address */
222 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
223 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
224 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
225 dma_addr_t first_tx_desc_dma;
226 dma_addr_t first_rx_desc_dma;
228 /* descriptor pointer */
229 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
230 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
231 unsigned char *desc_pool_ptr; /* descriptor pool memory */
232 struct tx_desc *first_tx_desc;
233 struct tx_desc *tx_insert_ptr;
234 struct tx_desc *tx_remove_ptr;
235 struct rx_desc *first_rx_desc;
236 struct rx_desc *rx_insert_ptr;
237 struct rx_desc *rx_ready_ptr; /* packet come pointer */
238 unsigned long tx_packet_cnt; /* transmitted packet count */
239 unsigned long tx_queue_cnt; /* wait to send packet count */
240 unsigned long rx_avail_cnt; /* available rx descriptor count */
241 unsigned long interval_rx_cnt; /* rx packet count a callback time */
243 u16 HPNA_command; /* For HPNA register 16 */
244 u16 HPNA_timer; /* For HPNA remote device check */
246 u16 NIC_capability; /* NIC media capability */
247 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
249 u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
250 u8 chip_type; /* Keep DM9102A chip type */
251 u8 media_mode; /* user specify media mode */
252 u8 op_mode; /* real work media mode */
254 u8 wait_reset; /* Hardware failed, need to reset */
255 u8 dm910x_chk_mode; /* Operating mode check */
256 u8 first_in_callback; /* Flag to record state */
257 u8 wol_mode; /* user WOL settings */
258 struct timer_list timer;
260 /* System defined statistic counter */
261 struct net_device_stats stats;
263 /* Driver defined statistic counter */
264 unsigned long tx_fifo_underrun;
265 unsigned long tx_loss_carrier;
266 unsigned long tx_no_carrier;
267 unsigned long tx_late_collision;
268 unsigned long tx_excessive_collision;
269 unsigned long tx_jabber_timeout;
270 unsigned long reset_count;
271 unsigned long reset_cr8;
272 unsigned long reset_fatal;
273 unsigned long reset_TXtimeout;
276 unsigned char srom[128];
280 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
281 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
282 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
287 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
288 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
289 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
292 /* Global variable declaration ----------------------------- */
293 static int __devinitdata printed_version;
294 static char version[] __devinitdata =
295 KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
296 DRV_VERSION " (" DRV_RELDATE ")\n";
298 static int dmfe_debug;
299 static unsigned char dmfe_media_mode = DMFE_AUTO;
300 static u32 dmfe_cr6_user_set;
302 /* For module input parameter */
305 static unsigned char mode = 8;
306 static u8 chkmode = 1;
307 static u8 HPNA_mode; /* Default: Low Power/High Speed */
308 static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
309 static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
310 static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
311 static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
312 4: TX pause packet */
315 /* function declaration ------------------------------------- */
316 static int dmfe_open(struct DEVICE *);
317 static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
318 static int dmfe_stop(struct DEVICE *);
319 static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
320 static void dmfe_set_filter_mode(struct DEVICE *);
321 static const struct ethtool_ops netdev_ethtool_ops;
322 static u16 read_srom_word(long ,int);
323 static irqreturn_t dmfe_interrupt(int , void *);
324 #ifdef CONFIG_NET_POLL_CONTROLLER
325 static void poll_dmfe (struct net_device *dev);
327 static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
328 static void allocate_rx_buffer(struct dmfe_board_info *);
329 static void update_cr6(u32, unsigned long);
330 static void send_filter_frame(struct DEVICE * ,int);
331 static void dm9132_id_table(struct DEVICE * ,int);
332 static u16 phy_read(unsigned long, u8, u8, u32);
333 static void phy_write(unsigned long, u8, u8, u16, u32);
334 static void phy_write_1bit(unsigned long, u32);
335 static u16 phy_read_1bit(unsigned long);
336 static u8 dmfe_sense_speed(struct dmfe_board_info *);
337 static void dmfe_process_mode(struct dmfe_board_info *);
338 static void dmfe_timer(unsigned long);
339 static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
340 static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
341 static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
342 static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
343 static void dmfe_dynamic_reset(struct DEVICE *);
344 static void dmfe_free_rxbuffer(struct dmfe_board_info *);
345 static void dmfe_init_dm910x(struct DEVICE *);
346 static void dmfe_parse_srom(struct dmfe_board_info *);
347 static void dmfe_program_DM9801(struct dmfe_board_info *, int);
348 static void dmfe_program_DM9802(struct dmfe_board_info *);
349 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
350 static void dmfe_set_phyxcer(struct dmfe_board_info *);
352 /* DM910X network board routine ---------------------------- */
355 * Search DM910X board ,allocate space and register it
358 static int __devinit dmfe_init_one (struct pci_dev *pdev,
359 const struct pci_device_id *ent)
361 struct dmfe_board_info *db; /* board information structure */
362 struct net_device *dev;
366 DMFE_DBUG(0, "dmfe_init_one()", 0);
368 if (!printed_version++)
371 /* Init network device */
372 dev = alloc_etherdev(sizeof(*db));
375 SET_NETDEV_DEV(dev, &pdev->dev);
377 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
378 printk(KERN_WARNING DRV_NAME
379 ": 32-bit PCI DMA not available.\n");
384 /* Enable Master/IO access, Disable memory access */
385 err = pci_enable_device(pdev);
389 if (!pci_resource_start(pdev, 0)) {
390 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
392 goto err_out_disable;
395 if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev)) ) {
396 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
398 goto err_out_disable;
401 #if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
403 /* Set Latency Timer 80h */
404 /* FIXME: setting values > 32 breaks some SiS 559x stuff.
405 Need a PCI quirk.. */
407 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
410 if (pci_request_regions(pdev, DRV_NAME)) {
411 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
413 goto err_out_disable;
416 /* Init system & device */
417 db = netdev_priv(dev);
419 /* Allocate Tx/Rx descriptor memory */
420 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) *
421 DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
423 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC *
424 TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
426 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
427 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
428 db->buf_pool_start = db->buf_pool_ptr;
429 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
431 db->chip_id = ent->driver_data;
432 db->ioaddr = pci_resource_start(pdev, 0);
433 db->chip_revision = pdev->revision;
438 dev->base_addr = db->ioaddr;
439 dev->irq = pdev->irq;
440 pci_set_drvdata(pdev, dev);
441 dev->open = &dmfe_open;
442 dev->hard_start_xmit = &dmfe_start_xmit;
443 dev->stop = &dmfe_stop;
444 dev->get_stats = &dmfe_get_stats;
445 dev->set_multicast_list = &dmfe_set_filter_mode;
446 #ifdef CONFIG_NET_POLL_CONTROLLER
447 dev->poll_controller = &poll_dmfe;
449 dev->ethtool_ops = &netdev_ethtool_ops;
450 netif_carrier_off(dev);
451 spin_lock_init(&db->lock);
453 pci_read_config_dword(pdev, 0x50, &pci_pmr);
455 if ( (pci_pmr == 0x10000) && (db->chip_revision == 0x31) )
456 db->chip_type = 1; /* DM9102A E3 */
460 /* read 64 word srom data */
461 for (i = 0; i < 64; i++)
462 ((__le16 *) db->srom)[i] =
463 cpu_to_le16(read_srom_word(db->ioaddr, i));
465 /* Set Node address */
466 for (i = 0; i < 6; i++)
467 dev->dev_addr[i] = db->srom[20 + i];
469 err = register_netdev (dev);
473 printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
475 ent->driver_data >> 16,
477 for (i = 0; i < 6; i++)
478 printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
479 printk(", irq %d.\n", dev->irq);
481 pci_set_master(pdev);
486 pci_release_regions(pdev);
488 pci_disable_device(pdev);
490 pci_set_drvdata(pdev, NULL);
497 static void __devexit dmfe_remove_one (struct pci_dev *pdev)
499 struct net_device *dev = pci_get_drvdata(pdev);
500 struct dmfe_board_info *db = netdev_priv(dev);
502 DMFE_DBUG(0, "dmfe_remove_one()", 0);
506 unregister_netdev(dev);
508 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
509 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
510 db->desc_pool_dma_ptr);
511 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
512 db->buf_pool_ptr, db->buf_pool_dma_ptr);
513 pci_release_regions(pdev);
514 free_netdev(dev); /* free board information */
516 pci_set_drvdata(pdev, NULL);
519 DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
524 * Open the interface.
525 * The interface is opened whenever "ifconfig" actives it.
528 static int dmfe_open(struct DEVICE *dev)
531 struct dmfe_board_info *db = netdev_priv(dev);
533 DMFE_DBUG(0, "dmfe_open", 0);
535 ret = request_irq(dev->irq, &dmfe_interrupt,
536 IRQF_SHARED, dev->name, dev);
540 /* system variable init */
541 db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
542 db->tx_packet_cnt = 0;
543 db->tx_queue_cnt = 0;
544 db->rx_avail_cnt = 0;
547 db->first_in_callback = 0;
548 db->NIC_capability = 0xf; /* All capability*/
549 db->PHY_reg4 = 0x1e0;
551 /* CR6 operation mode decision */
552 if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
553 (db->chip_revision >= 0x30) ) {
554 db->cr6_data |= DMFE_TXTH_256;
555 db->cr0_data = CR0_DEFAULT;
556 db->dm910x_chk_mode=4; /* Enter the normal mode */
558 db->cr6_data |= CR6_SFT; /* Store & Forward mode */
560 db->dm910x_chk_mode = 1; /* Enter the check mode */
563 /* Initilize DM910X board */
564 dmfe_init_dm910x(dev);
566 /* Active System Interface */
567 netif_wake_queue(dev);
569 /* set and active a timer process */
570 init_timer(&db->timer);
571 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
572 db->timer.data = (unsigned long)dev;
573 db->timer.function = &dmfe_timer;
574 add_timer(&db->timer);
580 /* Initilize DM910X board
582 * Initilize TX/Rx descriptor chain structure
583 * Send the set-up frame
584 * Enable Tx/Rx machine
587 static void dmfe_init_dm910x(struct DEVICE *dev)
589 struct dmfe_board_info *db = netdev_priv(dev);
590 unsigned long ioaddr = db->ioaddr;
592 DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
594 /* Reset DM910x MAC controller */
595 outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
597 outl(db->cr0_data, ioaddr + DCR0);
600 /* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
603 /* Parser SROM and media mode */
605 db->media_mode = dmfe_media_mode;
607 /* RESET Phyxcer Chip by GPR port bit 7 */
608 outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
609 if (db->chip_id == PCI_DM9009_ID) {
610 outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
611 mdelay(300); /* Delay 300 ms */
613 outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
615 /* Process Phyxcer Media Mode */
616 if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
617 dmfe_set_phyxcer(db);
619 /* Media Mode Process */
620 if ( !(db->media_mode & DMFE_AUTO) )
621 db->op_mode = db->media_mode; /* Force Mode */
623 /* Initiliaze Transmit/Receive decriptor and CR3/4 */
624 dmfe_descriptor_init(db, ioaddr);
626 /* Init CR6 to program DM910x operation */
627 update_cr6(db->cr6_data, ioaddr);
629 /* Send setup frame */
630 if (db->chip_id == PCI_DM9132_ID)
631 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
633 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
635 /* Init CR7, interrupt active bit */
636 db->cr7_data = CR7_DEFAULT;
637 outl(db->cr7_data, ioaddr + DCR7);
639 /* Init CR15, Tx jabber and Rx watchdog timer */
640 outl(db->cr15_data, ioaddr + DCR15);
642 /* Enable DM910X Tx/Rx function */
643 db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
644 update_cr6(db->cr6_data, ioaddr);
649 * Hardware start transmission.
650 * Send a packet to media from the upper layer.
653 static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
655 struct dmfe_board_info *db = netdev_priv(dev);
656 struct tx_desc *txptr;
659 DMFE_DBUG(0, "dmfe_start_xmit", 0);
661 /* Resource flag check */
662 netif_stop_queue(dev);
664 /* Too large packet check */
665 if (skb->len > MAX_PACKET_SIZE) {
666 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
671 spin_lock_irqsave(&db->lock, flags);
673 /* No Tx resource check, it never happen nromally */
674 if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
675 spin_unlock_irqrestore(&db->lock, flags);
676 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n",
681 /* Disable NIC interrupt */
682 outl(0, dev->base_addr + DCR7);
684 /* transmit this packet */
685 txptr = db->tx_insert_ptr;
686 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
687 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
689 /* Point to next transmit free descriptor */
690 db->tx_insert_ptr = txptr->next_tx_desc;
692 /* Transmit Packet Process */
693 if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
694 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
695 db->tx_packet_cnt++; /* Ready to send */
696 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
697 dev->trans_start = jiffies; /* saved time stamp */
699 db->tx_queue_cnt++; /* queue TX packet */
700 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
703 /* Tx resource check */
704 if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
705 netif_wake_queue(dev);
707 /* Restore CR7 to enable interrupt */
708 spin_unlock_irqrestore(&db->lock, flags);
709 outl(db->cr7_data, dev->base_addr + DCR7);
719 * Stop the interface.
720 * The interface is stopped when it is brought.
723 static int dmfe_stop(struct DEVICE *dev)
725 struct dmfe_board_info *db = netdev_priv(dev);
726 unsigned long ioaddr = dev->base_addr;
728 DMFE_DBUG(0, "dmfe_stop", 0);
731 netif_stop_queue(dev);
734 del_timer_sync(&db->timer);
736 /* Reset & stop DM910X board */
737 outl(DM910X_RESET, ioaddr + DCR0);
739 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
742 free_irq(dev->irq, dev);
744 /* free allocated rx buffer */
745 dmfe_free_rxbuffer(db);
748 /* show statistic counter */
749 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx"
750 " LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
751 db->tx_fifo_underrun, db->tx_excessive_collision,
752 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
753 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
754 db->reset_fatal, db->reset_TXtimeout);
762 * DM9102 insterrupt handler
763 * receive the packet to upper layer, free the transmitted packet
766 static irqreturn_t dmfe_interrupt(int irq, void *dev_id)
768 struct DEVICE *dev = dev_id;
769 struct dmfe_board_info *db = netdev_priv(dev);
770 unsigned long ioaddr = dev->base_addr;
773 DMFE_DBUG(0, "dmfe_interrupt()", 0);
775 spin_lock_irqsave(&db->lock, flags);
777 /* Got DM910X status */
778 db->cr5_data = inl(ioaddr + DCR5);
779 outl(db->cr5_data, ioaddr + DCR5);
780 if ( !(db->cr5_data & 0xc1) ) {
781 spin_unlock_irqrestore(&db->lock, flags);
785 /* Disable all interrupt in CR7 to solve the interrupt edge problem */
786 outl(0, ioaddr + DCR7);
788 /* Check system status */
789 if (db->cr5_data & 0x2000) {
790 /* system bus error happen */
791 DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
793 db->wait_reset = 1; /* Need to RESET */
794 spin_unlock_irqrestore(&db->lock, flags);
798 /* Received the coming packet */
799 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
800 dmfe_rx_packet(dev, db);
802 /* reallocate rx descriptor buffer */
803 if (db->rx_avail_cnt<RX_DESC_CNT)
804 allocate_rx_buffer(db);
806 /* Free the transmitted descriptor */
807 if ( db->cr5_data & 0x01)
808 dmfe_free_tx_pkt(dev, db);
811 if (db->dm910x_chk_mode & 0x2) {
812 db->dm910x_chk_mode = 0x4;
813 db->cr6_data |= 0x100;
814 update_cr6(db->cr6_data, db->ioaddr);
817 /* Restore CR7 to enable interrupt mask */
818 outl(db->cr7_data, ioaddr + DCR7);
820 spin_unlock_irqrestore(&db->lock, flags);
825 #ifdef CONFIG_NET_POLL_CONTROLLER
827 * Polling 'interrupt' - used by things like netconsole to send skbs
828 * without having to re-enable interrupts. It's not called while
829 * the interrupt routine is executing.
832 static void poll_dmfe (struct net_device *dev)
834 /* disable_irq here is not very nice, but with the lockless
835 interrupt handler we have no other choice. */
836 disable_irq(dev->irq);
837 dmfe_interrupt (dev->irq, dev);
838 enable_irq(dev->irq);
843 * Free TX resource after TX complete
846 static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
848 struct tx_desc *txptr;
849 unsigned long ioaddr = dev->base_addr;
852 txptr = db->tx_remove_ptr;
853 while(db->tx_packet_cnt) {
854 tdes0 = le32_to_cpu(txptr->tdes0);
855 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
856 if (tdes0 & 0x80000000)
859 /* A packet sent completed */
861 db->stats.tx_packets++;
863 /* Transmit statistic counter */
864 if ( tdes0 != 0x7fffffff ) {
865 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
866 db->stats.collisions += (tdes0 >> 3) & 0xf;
867 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
868 if (tdes0 & TDES0_ERR_MASK) {
869 db->stats.tx_errors++;
871 if (tdes0 & 0x0002) { /* UnderRun */
872 db->tx_fifo_underrun++;
873 if ( !(db->cr6_data & CR6_SFT) ) {
874 db->cr6_data = db->cr6_data | CR6_SFT;
875 update_cr6(db->cr6_data, db->ioaddr);
879 db->tx_excessive_collision++;
881 db->tx_late_collision++;
885 db->tx_loss_carrier++;
887 db->tx_jabber_timeout++;
891 txptr = txptr->next_tx_desc;
894 /* Update TX remove pointer to next */
895 db->tx_remove_ptr = txptr;
897 /* Send the Tx packet in queue */
898 if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
899 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
900 db->tx_packet_cnt++; /* Ready to send */
902 outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
903 dev->trans_start = jiffies; /* saved time stamp */
906 /* Resource available check */
907 if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
908 netif_wake_queue(dev); /* Active upper layer, send again */
913 * Calculate the CRC valude of the Rx packet
914 * flag = 1 : return the reverse CRC (for the received packet CRC)
915 * 0 : return the normal CRC (for Hash Table index)
918 static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
920 u32 crc = crc32(~0, Data, Len);
921 if (flag) crc = ~crc;
927 * Receive the come packet and pass to upper layer
930 static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
932 struct rx_desc *rxptr;
933 struct sk_buff *skb, *newskb;
937 rxptr = db->rx_ready_ptr;
939 while(db->rx_avail_cnt) {
940 rdes0 = le32_to_cpu(rxptr->rdes0);
941 if (rdes0 & 0x80000000) /* packet owner check */
945 db->interval_rx_cnt++;
947 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2),
948 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
950 if ( (rdes0 & 0x300) != 0x300) {
951 /* A packet without First/Last flag */
953 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
954 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
956 /* A packet with First/Last flag */
957 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
959 /* error summary bit check */
960 if (rdes0 & 0x8000) {
961 /* This is a error packet */
962 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
963 db->stats.rx_errors++;
965 db->stats.rx_fifo_errors++;
967 db->stats.rx_crc_errors++;
969 db->stats.rx_length_errors++;
972 if ( !(rdes0 & 0x8000) ||
973 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
974 skb = rxptr->rx_skb_ptr;
976 /* Received Packet CRC check need or not */
977 if ( (db->dm910x_chk_mode & 1) &&
978 (cal_CRC(skb->data, rxlen, 1) !=
979 (*(u32 *) (skb->data+rxlen) ))) { /* FIXME (?) */
980 /* Found a error received packet */
981 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
982 db->dm910x_chk_mode = 3;
984 /* Good packet, send to upper layer */
985 /* Shorst packet used new SKB */
986 if ((rxlen < RX_COPY_SIZE) &&
987 ((newskb = dev_alloc_skb(rxlen + 2))
991 /* size less than COPY_SIZE, allocate a rxlen SKB */
992 skb_reserve(skb, 2); /* 16byte align */
993 skb_copy_from_linear_data(rxptr->rx_skb_ptr,
996 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1000 skb->protocol = eth_type_trans(skb, dev);
1002 dev->last_rx = jiffies;
1003 db->stats.rx_packets++;
1004 db->stats.rx_bytes += rxlen;
1007 /* Reuse SKB buffer when the packet is error */
1008 DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
1009 dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
1013 rxptr = rxptr->next_rx_desc;
1016 db->rx_ready_ptr = rxptr;
1021 * Get statistics from driver.
1024 static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
1026 struct dmfe_board_info *db = netdev_priv(dev);
1028 DMFE_DBUG(0, "dmfe_get_stats", 0);
1034 * Set DM910X multicast address
1037 static void dmfe_set_filter_mode(struct DEVICE * dev)
1039 struct dmfe_board_info *db = netdev_priv(dev);
1040 unsigned long flags;
1042 DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
1043 spin_lock_irqsave(&db->lock, flags);
1045 if (dev->flags & IFF_PROMISC) {
1046 DMFE_DBUG(0, "Enable PROM Mode", 0);
1047 db->cr6_data |= CR6_PM | CR6_PBF;
1048 update_cr6(db->cr6_data, db->ioaddr);
1049 spin_unlock_irqrestore(&db->lock, flags);
1053 if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
1054 DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
1055 db->cr6_data &= ~(CR6_PM | CR6_PBF);
1056 db->cr6_data |= CR6_PAM;
1057 spin_unlock_irqrestore(&db->lock, flags);
1061 DMFE_DBUG(0, "Set multicast address", dev->mc_count);
1062 if (db->chip_id == PCI_DM9132_ID)
1063 dm9132_id_table(dev, dev->mc_count); /* DM9132 */
1065 send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
1066 spin_unlock_irqrestore(&db->lock, flags);
1073 static void dmfe_ethtool_get_drvinfo(struct net_device *dev,
1074 struct ethtool_drvinfo *info)
1076 struct dmfe_board_info *np = netdev_priv(dev);
1078 strcpy(info->driver, DRV_NAME);
1079 strcpy(info->version, DRV_VERSION);
1081 strcpy(info->bus_info, pci_name(np->pdev));
1083 sprintf(info->bus_info, "EISA 0x%lx %d",
1084 dev->base_addr, dev->irq);
1087 static int dmfe_ethtool_set_wol(struct net_device *dev,
1088 struct ethtool_wolinfo *wolinfo)
1090 struct dmfe_board_info *db = netdev_priv(dev);
1092 if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
1093 WAKE_ARP | WAKE_MAGICSECURE))
1096 db->wol_mode = wolinfo->wolopts;
1100 static void dmfe_ethtool_get_wol(struct net_device *dev,
1101 struct ethtool_wolinfo *wolinfo)
1103 struct dmfe_board_info *db = netdev_priv(dev);
1105 wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
1106 wolinfo->wolopts = db->wol_mode;
1111 static const struct ethtool_ops netdev_ethtool_ops = {
1112 .get_drvinfo = dmfe_ethtool_get_drvinfo,
1113 .get_link = ethtool_op_get_link,
1114 .set_wol = dmfe_ethtool_set_wol,
1115 .get_wol = dmfe_ethtool_get_wol,
1119 * A periodic timer routine
1120 * Dynamic media sense, allocate Rx buffer...
1123 static void dmfe_timer(unsigned long data)
1126 unsigned char tmp_cr12;
1127 struct DEVICE *dev = (struct DEVICE *) data;
1128 struct dmfe_board_info *db = netdev_priv(dev);
1129 unsigned long flags;
1131 int link_ok, link_ok_phy;
1133 DMFE_DBUG(0, "dmfe_timer()", 0);
1134 spin_lock_irqsave(&db->lock, flags);
1136 /* Media mode process when Link OK before enter this route */
1137 if (db->first_in_callback == 0) {
1138 db->first_in_callback = 1;
1139 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
1140 db->cr6_data &= ~0x40000;
1141 update_cr6(db->cr6_data, db->ioaddr);
1142 phy_write(db->ioaddr,
1143 db->phy_addr, 0, 0x1000, db->chip_id);
1144 db->cr6_data |= 0x40000;
1145 update_cr6(db->cr6_data, db->ioaddr);
1146 db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
1147 add_timer(&db->timer);
1148 spin_unlock_irqrestore(&db->lock, flags);
1154 /* Operating Mode Check */
1155 if ( (db->dm910x_chk_mode & 0x1) &&
1156 (db->stats.rx_packets > MAX_CHECK_PACKET) )
1157 db->dm910x_chk_mode = 0x4;
1159 /* Dynamic reset DM910X : system error or transmit time-out */
1160 tmp_cr8 = inl(db->ioaddr + DCR8);
1161 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1165 db->interval_rx_cnt = 0;
1167 /* TX polling kick monitor */
1168 if ( db->tx_packet_cnt &&
1169 time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
1170 outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
1173 if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
1174 db->reset_TXtimeout++;
1176 printk(KERN_WARNING "%s: Tx timeout - resetting\n",
1181 if (db->wait_reset) {
1182 DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1184 dmfe_dynamic_reset(dev);
1185 db->first_in_callback = 0;
1186 db->timer.expires = DMFE_TIMER_WUT;
1187 add_timer(&db->timer);
1188 spin_unlock_irqrestore(&db->lock, flags);
1192 /* Link status check, Dynamic media type change */
1193 if (db->chip_id == PCI_DM9132_ID)
1194 tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
1196 tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
1198 if ( ((db->chip_id == PCI_DM9102_ID) &&
1199 (db->chip_revision == 0x30)) ||
1200 ((db->chip_id == PCI_DM9132_ID) &&
1201 (db->chip_revision == 0x10)) ) {
1209 /*0x43 is used instead of 0x3 because bit 6 should represent
1210 link status of external PHY */
1211 link_ok = (tmp_cr12 & 0x43) ? 1 : 0;
1214 /* If chip reports that link is failed it could be because external
1215 PHY link status pin is not conected correctly to chip
1216 To be sure ask PHY too.
1219 /* need a dummy read because of PHY's register latch*/
1220 phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
1221 link_ok_phy = (phy_read (db->ioaddr,
1222 db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
1224 if (link_ok_phy != link_ok) {
1225 DMFE_DBUG (0, "PHY and chip report different link status", 0);
1226 link_ok = link_ok | link_ok_phy;
1229 if ( !link_ok && netif_carrier_ok(dev)) {
1231 DMFE_DBUG(0, "Link Failed", tmp_cr12);
1232 netif_carrier_off(dev);
1234 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1235 /* AUTO or force 1M Homerun/Longrun don't need */
1236 if ( !(db->media_mode & 0x38) )
1237 phy_write(db->ioaddr, db->phy_addr,
1238 0, 0x1000, db->chip_id);
1240 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1241 if (db->media_mode & DMFE_AUTO) {
1242 /* 10/100M link failed, used 1M Home-Net */
1243 db->cr6_data|=0x00040000; /* bit18=1, MII */
1244 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1245 update_cr6(db->cr6_data, db->ioaddr);
1247 } else if (!netif_carrier_ok(dev)) {
1249 DMFE_DBUG(0, "Link link OK", tmp_cr12);
1251 /* Auto Sense Speed */
1252 if ( !(db->media_mode & DMFE_AUTO) || !dmfe_sense_speed(db)) {
1253 netif_carrier_on(dev);
1254 SHOW_MEDIA_TYPE(db->op_mode);
1257 dmfe_process_mode(db);
1260 /* HPNA remote command check */
1261 if (db->HPNA_command & 0xf00) {
1263 if (!db->HPNA_timer)
1264 dmfe_HPNA_remote_cmd_chk(db);
1267 /* Timer active again */
1268 db->timer.expires = DMFE_TIMER_WUT;
1269 add_timer(&db->timer);
1270 spin_unlock_irqrestore(&db->lock, flags);
1275 * Dynamic reset the DM910X board
1277 * Free Tx/Rx allocated memory
1278 * Reset DM910X board
1279 * Re-initilize DM910X board
1282 static void dmfe_dynamic_reset(struct DEVICE *dev)
1284 struct dmfe_board_info *db = netdev_priv(dev);
1286 DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
1288 /* Sopt MAC controller */
1289 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1290 update_cr6(db->cr6_data, dev->base_addr);
1291 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1292 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1294 /* Disable upper layer interface */
1295 netif_stop_queue(dev);
1297 /* Free Rx Allocate buffer */
1298 dmfe_free_rxbuffer(db);
1300 /* system variable init */
1301 db->tx_packet_cnt = 0;
1302 db->tx_queue_cnt = 0;
1303 db->rx_avail_cnt = 0;
1304 netif_carrier_off(dev);
1307 /* Re-initilize DM910X board */
1308 dmfe_init_dm910x(dev);
1310 /* Restart upper layer interface */
1311 netif_wake_queue(dev);
1316 * free all allocated rx buffer
1319 static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
1321 DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
1323 /* free allocated rx buffer */
1324 while (db->rx_avail_cnt) {
1325 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1326 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1333 * Reuse the SK buffer
1336 static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
1338 struct rx_desc *rxptr = db->rx_insert_ptr;
1340 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1341 rxptr->rx_skb_ptr = skb;
1342 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev,
1343 skb->data, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1345 rxptr->rdes0 = cpu_to_le32(0x80000000);
1347 db->rx_insert_ptr = rxptr->next_rx_desc;
1349 DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1354 * Initialize transmit/Receive descriptor
1355 * Using Chain structure, and allocate Tx/Rx buffer
1358 static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
1360 struct tx_desc *tmp_tx;
1361 struct rx_desc *tmp_rx;
1362 unsigned char *tmp_buf;
1363 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1364 dma_addr_t tmp_buf_dma;
1367 DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
1369 /* tx descriptor start pointer */
1370 db->tx_insert_ptr = db->first_tx_desc;
1371 db->tx_remove_ptr = db->first_tx_desc;
1372 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1374 /* rx descriptor start pointer */
1375 db->first_rx_desc = (void *)db->first_tx_desc +
1376 sizeof(struct tx_desc) * TX_DESC_CNT;
1378 db->first_rx_desc_dma = db->first_tx_desc_dma +
1379 sizeof(struct tx_desc) * TX_DESC_CNT;
1380 db->rx_insert_ptr = db->first_rx_desc;
1381 db->rx_ready_ptr = db->first_rx_desc;
1382 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1384 /* Init Transmit chain */
1385 tmp_buf = db->buf_pool_start;
1386 tmp_buf_dma = db->buf_pool_dma_start;
1387 tmp_tx_dma = db->first_tx_desc_dma;
1388 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1389 tmp_tx->tx_buf_ptr = tmp_buf;
1390 tmp_tx->tdes0 = cpu_to_le32(0);
1391 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1392 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1393 tmp_tx_dma += sizeof(struct tx_desc);
1394 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1395 tmp_tx->next_tx_desc = tmp_tx + 1;
1396 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1397 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1399 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1400 tmp_tx->next_tx_desc = db->first_tx_desc;
1402 /* Init Receive descriptor chain */
1403 tmp_rx_dma=db->first_rx_desc_dma;
1404 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1405 tmp_rx->rdes0 = cpu_to_le32(0);
1406 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1407 tmp_rx_dma += sizeof(struct rx_desc);
1408 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1409 tmp_rx->next_rx_desc = tmp_rx + 1;
1411 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1412 tmp_rx->next_rx_desc = db->first_rx_desc;
1414 /* pre-allocate Rx buffer */
1415 allocate_rx_buffer(db);
1421 * Firstly stop DM910X , then written value and start
1424 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1428 cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
1429 outl(cr6_tmp, ioaddr + DCR6);
1431 outl(cr6_data, ioaddr + DCR6);
1437 * Send a setup frame for DM9132
1438 * This setup frame initilize DM910X address filter mode
1441 static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
1443 struct dev_mc_list *mcptr;
1445 unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
1447 u16 i, hash_table[4];
1449 DMFE_DBUG(0, "dm9132_id_table()", 0);
1452 addrptr = (u16 *) dev->dev_addr;
1453 outw(addrptr[0], ioaddr);
1455 outw(addrptr[1], ioaddr);
1457 outw(addrptr[2], ioaddr);
1460 /* Clear Hash Table */
1461 for (i = 0; i < 4; i++)
1462 hash_table[i] = 0x0;
1464 /* broadcast address */
1465 hash_table[3] = 0x8000;
1467 /* the multicast address in Hash Table : 64 bits */
1468 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1469 hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
1470 hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
1473 /* Write the hash table to MAC MD table */
1474 for (i = 0; i < 4; i++, ioaddr += 4)
1475 outw(hash_table[i], ioaddr);
1480 * Send a setup frame for DM9102/DM9102A
1481 * This setup frame initilize DM910X address filter mode
1484 static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
1486 struct dmfe_board_info *db = netdev_priv(dev);
1487 struct dev_mc_list *mcptr;
1488 struct tx_desc *txptr;
1493 DMFE_DBUG(0, "send_filter_frame()", 0);
1495 txptr = db->tx_insert_ptr;
1496 suptr = (u32 *) txptr->tx_buf_ptr;
1499 addrptr = (u16 *) dev->dev_addr;
1500 *suptr++ = addrptr[0];
1501 *suptr++ = addrptr[1];
1502 *suptr++ = addrptr[2];
1504 /* broadcast address */
1509 /* fit the multicast address */
1510 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1511 addrptr = (u16 *) mcptr->dmi_addr;
1512 *suptr++ = addrptr[0];
1513 *suptr++ = addrptr[1];
1514 *suptr++ = addrptr[2];
1523 /* prepare the setup frame */
1524 db->tx_insert_ptr = txptr->next_tx_desc;
1525 txptr->tdes1 = cpu_to_le32(0x890000c0);
1527 /* Resource Check and Send the setup packet */
1528 if (!db->tx_packet_cnt) {
1529 /* Resource Empty */
1530 db->tx_packet_cnt++;
1531 txptr->tdes0 = cpu_to_le32(0x80000000);
1532 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1533 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1534 update_cr6(db->cr6_data, dev->base_addr);
1535 dev->trans_start = jiffies;
1537 db->tx_queue_cnt++; /* Put in TX queue */
1542 * Allocate rx buffer,
1543 * As possible as allocate maxiumn Rx buffer
1546 static void allocate_rx_buffer(struct dmfe_board_info *db)
1548 struct rx_desc *rxptr;
1549 struct sk_buff *skb;
1551 rxptr = db->rx_insert_ptr;
1553 while(db->rx_avail_cnt < RX_DESC_CNT) {
1554 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1556 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1557 rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->data,
1558 RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
1560 rxptr->rdes0 = cpu_to_le32(0x80000000);
1561 rxptr = rxptr->next_rx_desc;
1565 db->rx_insert_ptr = rxptr;
1570 * Read one word data from the serial ROM
1573 static u16 read_srom_word(long ioaddr, int offset)
1577 long cr9_ioaddr = ioaddr + DCR9;
1579 outl(CR9_SROM_READ, cr9_ioaddr);
1580 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1582 /* Send the Read Command 110b */
1583 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1584 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1585 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1587 /* Send the offset */
1588 for (i = 5; i >= 0; i--) {
1589 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1590 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1593 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1595 for (i = 16; i > 0; i--) {
1596 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1598 srom_data = (srom_data << 1) |
1599 ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1600 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1604 outl(CR9_SROM_READ, cr9_ioaddr);
1610 * Auto sense the media mode
1613 static u8 dmfe_sense_speed(struct dmfe_board_info * db)
1618 /* CR6 bit18=0, select 10/100M */
1619 update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
1621 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1622 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1624 if ( (phy_mode & 0x24) == 0x24 ) {
1625 if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
1626 phy_mode = phy_read(db->ioaddr,
1627 db->phy_addr, 7, db->chip_id) & 0xf000;
1628 else /* DM9102/DM9102A */
1629 phy_mode = phy_read(db->ioaddr,
1630 db->phy_addr, 17, db->chip_id) & 0xf000;
1631 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1633 case 0x1000: db->op_mode = DMFE_10MHF; break;
1634 case 0x2000: db->op_mode = DMFE_10MFD; break;
1635 case 0x4000: db->op_mode = DMFE_100MHF; break;
1636 case 0x8000: db->op_mode = DMFE_100MFD; break;
1637 default: db->op_mode = DMFE_10MHF;
1642 db->op_mode = DMFE_10MHF;
1643 DMFE_DBUG(0, "Link Failed :", phy_mode);
1652 * Set 10/100 phyxcer capability
1653 * AUTO mode : phyxcer register4 is NIC capability
1654 * Force mode: phyxcer register4 is the force media
1657 static void dmfe_set_phyxcer(struct dmfe_board_info *db)
1661 /* Select 10/100M phyxcer */
1662 db->cr6_data &= ~0x40000;
1663 update_cr6(db->cr6_data, db->ioaddr);
1665 /* DM9009 Chip: Phyxcer reg18 bit12=0 */
1666 if (db->chip_id == PCI_DM9009_ID) {
1667 phy_reg = phy_read(db->ioaddr,
1668 db->phy_addr, 18, db->chip_id) & ~0x1000;
1670 phy_write(db->ioaddr,
1671 db->phy_addr, 18, phy_reg, db->chip_id);
1674 /* Phyxcer capability setting */
1675 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1677 if (db->media_mode & DMFE_AUTO) {
1679 phy_reg |= db->PHY_reg4;
1682 switch(db->media_mode) {
1683 case DMFE_10MHF: phy_reg |= 0x20; break;
1684 case DMFE_10MFD: phy_reg |= 0x40; break;
1685 case DMFE_100MHF: phy_reg |= 0x80; break;
1686 case DMFE_100MFD: phy_reg |= 0x100; break;
1688 if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
1691 /* Write new capability to Phyxcer Reg4 */
1692 if ( !(phy_reg & 0x01e0)) {
1693 phy_reg|=db->PHY_reg4;
1694 db->media_mode|=DMFE_AUTO;
1696 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1698 /* Restart Auto-Negotiation */
1699 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1700 phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
1701 if ( !db->chip_type )
1702 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1708 * AUTO mode : PHY controller in Auto-negotiation Mode
1709 * Force mode: PHY controller in force mode with HUB
1710 * N-way force capability with SWITCH
1713 static void dmfe_process_mode(struct dmfe_board_info *db)
1717 /* Full Duplex Mode Check */
1718 if (db->op_mode & 0x4)
1719 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1721 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1723 /* Transciver Selection */
1724 if (db->op_mode & 0x10) /* 1M HomePNA */
1725 db->cr6_data |= 0x40000;/* External MII select */
1727 db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
1729 update_cr6(db->cr6_data, db->ioaddr);
1731 /* 10/100M phyxcer force mode need */
1732 if ( !(db->media_mode & 0x18)) {
1734 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1735 if ( !(phy_reg & 0x1) ) {
1736 /* parter without N-Way capability */
1738 switch(db->op_mode) {
1739 case DMFE_10MHF: phy_reg = 0x0; break;
1740 case DMFE_10MFD: phy_reg = 0x100; break;
1741 case DMFE_100MHF: phy_reg = 0x2000; break;
1742 case DMFE_100MFD: phy_reg = 0x2100; break;
1744 phy_write(db->ioaddr,
1745 db->phy_addr, 0, phy_reg, db->chip_id);
1746 if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
1748 phy_write(db->ioaddr,
1749 db->phy_addr, 0, phy_reg, db->chip_id);
1756 * Write a word to Phy register
1759 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset,
1760 u16 phy_data, u32 chip_id)
1763 unsigned long ioaddr;
1765 if (chip_id == PCI_DM9132_ID) {
1766 ioaddr = iobase + 0x80 + offset * 4;
1767 outw(phy_data, ioaddr);
1769 /* DM9102/DM9102A Chip */
1770 ioaddr = iobase + DCR9;
1772 /* Send 33 synchronization clock to Phy controller */
1773 for (i = 0; i < 35; i++)
1774 phy_write_1bit(ioaddr, PHY_DATA_1);
1776 /* Send start command(01) to Phy */
1777 phy_write_1bit(ioaddr, PHY_DATA_0);
1778 phy_write_1bit(ioaddr, PHY_DATA_1);
1780 /* Send write command(01) to Phy */
1781 phy_write_1bit(ioaddr, PHY_DATA_0);
1782 phy_write_1bit(ioaddr, PHY_DATA_1);
1784 /* Send Phy address */
1785 for (i = 0x10; i > 0; i = i >> 1)
1786 phy_write_1bit(ioaddr,
1787 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1789 /* Send register address */
1790 for (i = 0x10; i > 0; i = i >> 1)
1791 phy_write_1bit(ioaddr,
1792 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1794 /* written trasnition */
1795 phy_write_1bit(ioaddr, PHY_DATA_1);
1796 phy_write_1bit(ioaddr, PHY_DATA_0);
1798 /* Write a word data to PHY controller */
1799 for ( i = 0x8000; i > 0; i >>= 1)
1800 phy_write_1bit(ioaddr,
1801 phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
1807 * Read a word data from phy register
1810 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1814 unsigned long ioaddr;
1816 if (chip_id == PCI_DM9132_ID) {
1818 ioaddr = iobase + 0x80 + offset * 4;
1819 phy_data = inw(ioaddr);
1821 /* DM9102/DM9102A Chip */
1822 ioaddr = iobase + DCR9;
1824 /* Send 33 synchronization clock to Phy controller */
1825 for (i = 0; i < 35; i++)
1826 phy_write_1bit(ioaddr, PHY_DATA_1);
1828 /* Send start command(01) to Phy */
1829 phy_write_1bit(ioaddr, PHY_DATA_0);
1830 phy_write_1bit(ioaddr, PHY_DATA_1);
1832 /* Send read command(10) to Phy */
1833 phy_write_1bit(ioaddr, PHY_DATA_1);
1834 phy_write_1bit(ioaddr, PHY_DATA_0);
1836 /* Send Phy address */
1837 for (i = 0x10; i > 0; i = i >> 1)
1838 phy_write_1bit(ioaddr,
1839 phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
1841 /* Send register address */
1842 for (i = 0x10; i > 0; i = i >> 1)
1843 phy_write_1bit(ioaddr,
1844 offset & i ? PHY_DATA_1 : PHY_DATA_0);
1846 /* Skip transition state */
1847 phy_read_1bit(ioaddr);
1849 /* read 16bit data */
1850 for (phy_data = 0, i = 0; i < 16; i++) {
1852 phy_data |= phy_read_1bit(ioaddr);
1861 * Write one bit data to Phy Controller
1864 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
1866 outl(phy_data, ioaddr); /* MII Clock Low */
1868 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1870 outl(phy_data, ioaddr); /* MII Clock Low */
1876 * Read one bit phy data from PHY controller
1879 static u16 phy_read_1bit(unsigned long ioaddr)
1883 outl(0x50000, ioaddr);
1885 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1886 outl(0x40000, ioaddr);
1894 * Parser SROM and media mode
1897 static void dmfe_parse_srom(struct dmfe_board_info * db)
1899 char * srom = db->srom;
1900 int dmfe_mode, tmp_reg;
1902 DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
1905 db->cr15_data = CR15_DEFAULT;
1907 /* Check SROM Version */
1908 if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
1910 /* Get NIC support media mode */
1911 db->NIC_capability = le16_to_cpup((__le16 *)srom + 34/2);
1913 for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
1914 switch( db->NIC_capability & tmp_reg ) {
1915 case 0x1: db->PHY_reg4 |= 0x0020; break;
1916 case 0x2: db->PHY_reg4 |= 0x0040; break;
1917 case 0x4: db->PHY_reg4 |= 0x0080; break;
1918 case 0x8: db->PHY_reg4 |= 0x0100; break;
1922 /* Media Mode Force or not check */
1923 dmfe_mode = le32_to_cpup((__le32 *)srom + 34/4) &
1924 le32_to_cpup((__le32 *)srom + 36/4);
1926 case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
1927 case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
1928 case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
1930 case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
1933 /* Special Function setting */
1935 if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
1936 db->cr15_data |= 0x40;
1939 if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
1940 db->cr15_data |= 0x400;
1942 /* TX pause packet */
1943 if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
1944 db->cr15_data |= 0x9800;
1947 /* Parse HPNA parameter */
1948 db->HPNA_command = 1;
1950 /* Accept remote command or not */
1951 if (HPNA_rx_cmd == 0)
1952 db->HPNA_command |= 0x8000;
1954 /* Issue remote command & operation mode */
1955 if (HPNA_tx_cmd == 1)
1956 switch(HPNA_mode) { /* Issue Remote Command */
1957 case 0: db->HPNA_command |= 0x0904; break;
1958 case 1: db->HPNA_command |= 0x0a00; break;
1959 case 2: db->HPNA_command |= 0x0506; break;
1960 case 3: db->HPNA_command |= 0x0602; break;
1963 switch(HPNA_mode) { /* Don't Issue */
1964 case 0: db->HPNA_command |= 0x0004; break;
1965 case 1: db->HPNA_command |= 0x0000; break;
1966 case 2: db->HPNA_command |= 0x0006; break;
1967 case 3: db->HPNA_command |= 0x0002; break;
1970 /* Check DM9801 or DM9802 present or not */
1971 db->HPNA_present = 0;
1972 update_cr6(db->cr6_data|0x40000, db->ioaddr);
1973 tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
1974 if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
1975 /* DM9801 or DM9802 present */
1977 if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
1978 /* DM9801 HomeRun */
1979 db->HPNA_present = 1;
1980 dmfe_program_DM9801(db, tmp_reg);
1982 /* DM9802 LongRun */
1983 db->HPNA_present = 2;
1984 dmfe_program_DM9802(db);
1992 * Init HomeRun DM9801
1995 static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
1999 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
2001 case 0xb900: /* DM9801 E3 */
2002 db->HPNA_command |= 0x1000;
2003 reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
2004 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
2005 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2007 case 0xb901: /* DM9801 E4 */
2008 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2009 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
2010 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2011 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
2013 case 0xb902: /* DM9801 E5 */
2014 case 0xb903: /* DM9801 E6 */
2016 db->HPNA_command |= 0x1000;
2017 reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2018 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
2019 reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
2020 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
2023 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2024 phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
2025 phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
2030 * Init HomeRun DM9802
2033 static void dmfe_program_DM9802(struct dmfe_board_info * db)
2037 if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
2038 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
2039 phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
2040 phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
2041 phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
2046 * Check remote HPNA power and speed status. If not correct,
2047 * issue command again.
2050 static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
2054 /* Got remote device status */
2055 phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
2057 case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
2058 case 0x20: phy_reg = 0x0900;break; /* LP/HS */
2059 case 0x40: phy_reg = 0x0600;break; /* HP/LS */
2060 case 0x60: phy_reg = 0x0500;break; /* HP/HS */
2063 /* Check remote device status match our setting ot not */
2064 if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
2065 phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
2069 db->HPNA_timer=600; /* Match, every 10 minutes, check */
2074 static struct pci_device_id dmfe_pci_tbl[] = {
2075 { 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
2076 { 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
2077 { 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
2078 { 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
2081 MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
2085 static int dmfe_suspend(struct pci_dev *pci_dev, pm_message_t state)
2087 struct net_device *dev = pci_get_drvdata(pci_dev);
2088 struct dmfe_board_info *db = netdev_priv(dev);
2091 /* Disable upper layer interface */
2092 netif_device_detach(dev);
2095 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC);
2096 update_cr6(db->cr6_data, dev->base_addr);
2098 /* Disable Interrupt */
2099 outl(0, dev->base_addr + DCR7);
2100 outl(inl (dev->base_addr + DCR5), dev->base_addr + DCR5);
2102 /* Fre RX buffers */
2103 dmfe_free_rxbuffer(db);
2106 pci_read_config_dword(pci_dev, 0x40, &tmp);
2107 tmp &= ~(DMFE_WOL_LINKCHANGE|DMFE_WOL_MAGICPACKET);
2109 if (db->wol_mode & WAKE_PHY)
2110 tmp |= DMFE_WOL_LINKCHANGE;
2111 if (db->wol_mode & WAKE_MAGIC)
2112 tmp |= DMFE_WOL_MAGICPACKET;
2114 pci_write_config_dword(pci_dev, 0x40, tmp);
2116 pci_enable_wake(pci_dev, PCI_D3hot, 1);
2117 pci_enable_wake(pci_dev, PCI_D3cold, 1);
2119 /* Power down device*/
2120 pci_set_power_state(pci_dev, pci_choose_state (pci_dev,state));
2121 pci_save_state(pci_dev);
2126 static int dmfe_resume(struct pci_dev *pci_dev)
2128 struct net_device *dev = pci_get_drvdata(pci_dev);
2131 pci_restore_state(pci_dev);
2132 pci_set_power_state(pci_dev, PCI_D0);
2134 /* Re-initilize DM910X board */
2135 dmfe_init_dm910x(dev);
2138 pci_read_config_dword(pci_dev, 0x40, &tmp);
2140 tmp &= ~(DMFE_WOL_LINKCHANGE | DMFE_WOL_MAGICPACKET);
2141 pci_write_config_dword(pci_dev, 0x40, tmp);
2143 pci_enable_wake(pci_dev, PCI_D3hot, 0);
2144 pci_enable_wake(pci_dev, PCI_D3cold, 0);
2146 /* Restart upper layer interface */
2147 netif_device_attach(dev);
2152 #define dmfe_suspend NULL
2153 #define dmfe_resume NULL
2156 static struct pci_driver dmfe_driver = {
2158 .id_table = dmfe_pci_tbl,
2159 .probe = dmfe_init_one,
2160 .remove = __devexit_p(dmfe_remove_one),
2161 .suspend = dmfe_suspend,
2162 .resume = dmfe_resume
2165 MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
2166 MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
2167 MODULE_LICENSE("GPL");
2168 MODULE_VERSION(DRV_VERSION);
2170 module_param(debug, int, 0);
2171 module_param(mode, byte, 0);
2172 module_param(cr6set, int, 0);
2173 module_param(chkmode, byte, 0);
2174 module_param(HPNA_mode, byte, 0);
2175 module_param(HPNA_rx_cmd, byte, 0);
2176 module_param(HPNA_tx_cmd, byte, 0);
2177 module_param(HPNA_NoiseFloor, byte, 0);
2178 module_param(SF_mode, byte, 0);
2179 MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
2180 MODULE_PARM_DESC(mode, "Davicom DM9xxx: "
2181 "Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
2183 MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function "
2184 "(bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
2187 * when user used insmod to add module, system invoked init_module()
2188 * to initilize and register.
2191 static int __init dmfe_init_module(void)
2196 printed_version = 1;
2198 DMFE_DBUG(0, "init_module() ", debug);
2201 dmfe_debug = debug; /* set debug flag */
2203 dmfe_cr6_user_set = cr6set;
2211 dmfe_media_mode = mode;
2213 default:dmfe_media_mode = DMFE_AUTO;
2218 HPNA_mode = 0; /* Default: LP/HS */
2219 if (HPNA_rx_cmd > 1)
2220 HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
2221 if (HPNA_tx_cmd > 1)
2222 HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
2223 if (HPNA_NoiseFloor > 15)
2224 HPNA_NoiseFloor = 0;
2226 rc = pci_register_driver(&dmfe_driver);
2236 * when user used rmmod to delete module, system invoked clean_module()
2237 * to un-register all registered services.
2240 static void __exit dmfe_cleanup_module(void)
2242 DMFE_DBUG(0, "dmfe_clean_module() ", debug);
2243 pci_unregister_driver(&dmfe_driver);
2246 module_init(dmfe_init_module);
2247 module_exit(dmfe_cleanup_module);