1 /* de4x5.c: A DIGITAL DC21x4x DECchip and DE425/DE434/DE435/DE450/DE500
2 ethernet driver for Linux.
4 Copyright 1994, 1995 Digital Equipment Corporation.
6 Testing resources for this driver have been made available
7 in part by NASA Ames Research Center (mjacob@nas.nasa.gov).
9 The author may be reached at davies@maniac.ultranet.com.
11 This program is free software; you can redistribute it and/or modify it
12 under the terms of the GNU General Public License as published by the
13 Free Software Foundation; either version 2 of the License, or (at your
14 option) any later version.
16 THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 You should have received a copy of the GNU General Public License along
28 with this program; if not, write to the Free Software Foundation, Inc.,
29 675 Mass Ave, Cambridge, MA 02139, USA.
31 Originally, this driver was written for the Digital Equipment
32 Corporation series of EtherWORKS ethernet cards:
38 DE500 10/100 PCI Fasternet
40 but it will now attempt to support all cards which conform to the
41 Digital Semiconductor SROM Specification. The driver currently
42 recognises the following chips:
50 So far the driver is known to work with the following cards:
58 ZNYX346 10/100 4 port (can act as a 10/100 bridge!)
60 The driver has been tested on a relatively busy network using the DE425,
61 DE434, DE435 and DE500 cards and benchmarked with 'ttcp': it transferred
62 16M of data to a DECstation 5000/200 as follows:
66 DE425 1030k 997k 1170k 1128k
67 DE434 1063k 995k 1170k 1125k
68 DE435 1063k 995k 1170k 1125k
69 DE500 1063k 998k 1170k 1125k in 10Mb/s mode
71 All values are typical (in kBytes/sec) from a sample of 4 for each
72 measurement. Their error is +/-20k on a quiet (private) network and also
73 depend on what load the CPU has.
75 =========================================================================
76 This driver has been written substantially from scratch, although its
77 inheritance of style and stack interface from 'ewrk3.c' and in turn from
78 Donald Becker's 'lance.c' should be obvious. With the module autoload of
79 every usable DECchip board, I pinched Donald's 'next_module' field to
80 link my modules together.
82 Upto 15 EISA cards can be supported under this driver, limited primarily
83 by the available IRQ lines. I have checked different configurations of
84 multiple depca, EtherWORKS 3 cards and de4x5 cards and have not found a
85 problem yet (provided you have at least depca.c v0.38) ...
87 PCI support has been added to allow the driver to work with the DE434,
88 DE435, DE450 and DE500 cards. The I/O accesses are a bit of a kludge due
89 to the differences in the EISA and PCI CSR address offsets from the base
92 The ability to load this driver as a loadable module has been included
93 and used extensively during the driver development (to save those long
94 reboot sequences). Loadable module support under PCI and EISA has been
95 achieved by letting the driver autoprobe as if it were compiled into the
96 kernel. Do make sure you're not sharing interrupts with anything that
97 cannot accommodate interrupt sharing!
99 To utilise this ability, you have to do 8 things:
101 0) have a copy of the loadable modules code installed on your system.
102 1) copy de4x5.c from the /linux/drivers/net directory to your favourite
104 2) for fixed autoprobes (not recommended), edit the source code near
105 line 5594 to reflect the I/O address you're using, or assign these when
108 insmod de4x5 io=0xghh where g = bus number
111 NB: autoprobing for modules is now supported by default. You may just
116 to load all available boards. For a specific board, still use
118 3) compile de4x5.c, but include -DMODULE in the command line to ensure
119 that the correct bits are compiled (see end of source code).
120 4) if you are wanting to add a new card, goto 5. Otherwise, recompile a
121 kernel with the de4x5 configuration turned off and reboot.
122 5) insmod de4x5 [io=0xghh]
123 6) run the net startup bits for your new eth?? interface(s) manually
124 (usually /etc/rc.inet[12] at boot time).
127 To unload a module, turn off the associated interface(s)
128 'ifconfig eth?? down' then 'rmmod de4x5'.
130 Automedia detection is included so that in principal you can disconnect
131 from, e.g. TP, reconnect to BNC and things will still work (after a
132 pause whilst the driver figures out where its media went). My tests
133 using ping showed that it appears to work....
135 By default, the driver will now autodetect any DECchip based card.
136 Should you have a need to restrict the driver to DIGITAL only cards, you
137 can compile with a DEC_ONLY define, or if loading as a module, use the
138 'dec_only=1' parameter.
140 I've changed the timing routines to use the kernel timer and scheduling
141 functions so that the hangs and other assorted problems that occurred
142 while autosensing the media should be gone. A bonus for the DC21040
143 auto media sense algorithm is that it can now use one that is more in
144 line with the rest (the DC21040 chip doesn't have a hardware timer).
145 The downside is the 1 'jiffies' (10ms) resolution.
147 IEEE 802.3u MII interface code has been added in anticipation that some
148 products may use it in the future.
150 The SMC9332 card has a non-compliant SROM which needs fixing - I have
151 patched this driver to detect it because the SROM format used complies
152 to a previous DEC-STD format.
154 I have removed the buffer copies needed for receive on Intels. I cannot
155 remove them for Alphas since the Tulip hardware only does longword
156 aligned DMA transfers and the Alphas get alignment traps with non
157 longword aligned data copies (which makes them really slow). No comment.
159 I have added SROM decoding routines to make this driver work with any
160 card that supports the Digital Semiconductor SROM spec. This will help
161 all cards running the dc2114x series chips in particular. Cards using
162 the dc2104x chips should run correctly with the basic driver. I'm in
163 debt to <mjacob@feral.com> for the testing and feedback that helped get
164 this feature working. So far we have tested KINGSTON, SMC8432, SMC9332
165 (with the latest SROM complying with the SROM spec V3: their first was
166 broken), ZNYX342 and LinkSys. ZYNX314 (dual 21041 MAC) and ZNYX 315
167 (quad 21041 MAC) cards also appear to work despite their incorrectly
170 I have added a temporary fix for interrupt problems when some SCSI cards
171 share the same interrupt as the DECchip based cards. The problem occurs
172 because the SCSI card wants to grab the interrupt as a fast interrupt
173 (runs the service routine with interrupts turned off) vs. this card
174 which really needs to run the service routine with interrupts turned on.
175 This driver will now add the interrupt service routine as a fast
176 interrupt if it is bounced from the slow interrupt. THIS IS NOT A
177 RECOMMENDED WAY TO RUN THE DRIVER and has been done for a limited time
178 until people sort out their compatibility issues and the kernel
179 interrupt service code is fixed. YOU SHOULD SEPARATE OUT THE FAST
180 INTERRUPT CARDS FROM THE SLOW INTERRUPT CARDS to ensure that they do not
181 run on the same interrupt. PCMCIA/CardBus is another can of worms...
183 Finally, I think I have really fixed the module loading problem with
184 more than one DECchip based card. As a side effect, I don't mess with
185 the device structure any more which means that if more than 1 card in
186 2.0.x is installed (4 in 2.1.x), the user will have to edit
187 linux/drivers/net/Space.c to make room for them. Hence, module loading
188 is the preferred way to use this driver, since it doesn't have this
191 Where SROM media detection is used and full duplex is specified in the
192 SROM, the feature is ignored unless lp->params.fdx is set at compile
193 time OR during a module load (insmod de4x5 args='eth??:fdx' [see
194 below]). This is because there is no way to automatically detect full
195 duplex links except through autonegotiation. When I include the
196 autonegotiation feature in the SROM autoconf code, this detection will
197 occur automatically for that case.
199 Command line arguments are now allowed, similar to passing arguments
200 through LILO. This will allow a per adapter board set up of full duplex
201 and media. The only lexical constraints are: the board name (dev->name)
202 appears in the list before its parameters. The list of parameters ends
203 either at the end of the parameter list or with another board name. The
204 following parameters are allowed:
207 autosense to set the media/speed; with the following
209 TP, TP_NW, BNC, AUI, BNC_AUI, 100Mb, 10Mb, AUTO
211 Case sensitivity is important for the sub-parameters. They *must* be
212 upper case. Examples:
214 insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
216 For a compiled in driver, at or above line 548, place e.g.
217 #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
219 Yes, I know full duplex isn't permissible on BNC or AUI; they're just
220 examples. By default, full duplex is turned off and AUTO is the default
221 autosense setting. In reality, I expect only the full duplex option to
222 be used. Note the use of single quotes in the two examples above and the
223 lack of commas to separate items. ALSO, you must get the requested media
224 correct in relation to what the adapter SROM says it has. There's no way
225 to determine this in advance other than by trial and error and common
226 sense, e.g. call a BNC connectored port 'BNC', not '10Mb'.
228 Changed the bus probing. EISA used to be done first, followed by PCI.
229 Most people probably don't even know what a de425 is today and the EISA
230 probe has messed up some SCSI cards in the past, so now PCI is always
231 probed first followed by EISA if a) the architecture allows EISA and
232 either b) there have been no PCI cards detected or c) an EISA probe is
233 forced by the user. To force a probe include "force_eisa" in your
234 insmod "args" line; for built-in kernels either change the driver to do
235 this automatically or include #define DE4X5_FORCE_EISA on or before
236 line 1040 in the driver.
244 Version Date Description
246 0.1 17-Nov-94 Initial writing. ALPHA code release.
247 0.2 13-Jan-95 Added PCI support for DE435's.
248 0.21 19-Jan-95 Added auto media detection.
249 0.22 10-Feb-95 Fix interrupt handler call <chris@cosy.sbg.ac.at>.
250 Fix recognition bug reported by <bkm@star.rl.ac.uk>.
251 Add request/release_region code.
252 Add loadable modules support for PCI.
253 Clean up loadable modules support.
254 0.23 28-Feb-95 Added DC21041 and DC21140 support.
255 Fix missed frame counter value and initialisation.
257 0.24 11-Apr-95 Change delay routine to use <linux/udelay>.
258 Change TX_BUFFS_AVAIL macro.
259 Change media autodetection to allow manual setting.
260 Completed DE500 (DC21140) support.
261 0.241 18-Apr-95 Interim release without DE500 Autosense Algorithm.
262 0.242 10-May-95 Minor changes.
263 0.30 12-Jun-95 Timer fix for DC21140.
265 Add ALPHA changes from <jestabro@ant.tay1.dec.com>.
266 Add DE500 semi automatic autosense.
267 Add Link Fail interrupt TP failure detection.
268 Add timer based link change detection.
269 Plugged a memory leak in de4x5_queue_pkt().
270 0.31 13-Jun-95 Fixed PCI stuff for 1.3.1.
271 0.32 26-Jun-95 Added verify_area() calls in de4x5_ioctl() from a
272 suggestion by <heiko@colossus.escape.de>.
273 0.33 8-Aug-95 Add shared interrupt support (not released yet).
274 0.331 21-Aug-95 Fix de4x5_open() with fast CPUs.
275 Fix de4x5_interrupt().
276 Fix dc21140_autoconf() mess.
277 No shared interrupt support.
278 0.332 11-Sep-95 Added MII management interface routines.
279 0.40 5-Mar-96 Fix setup frame timeout <maartenb@hpkuipc.cern.ch>.
280 Add kernel timer code (h/w is too flaky).
281 Add MII based PHY autosense.
282 Add new multicasting code.
283 Add new autosense algorithms for media/mode
284 selection using kernel scheduling/timing.
286 Made changes suggested by <jeff@router.patch.net>:
287 Change driver to detect all DECchip based cards
288 with DEC_ONLY restriction a special case.
289 Changed driver to autoprobe as a module. No irq
290 checking is done now - assume BIOS is good!
291 Added SMC9332 detection <manabe@Roy.dsl.tutics.ac.jp>
292 0.41 21-Mar-96 Don't check for get_hw_addr checksum unless DEC card
293 only <niles@axp745gsfc.nasa.gov>
294 Fix for multiple PCI cards reported by <jos@xos.nl>
295 Duh, put the IRQF_SHARED flag into request_interrupt().
296 Fix SMC ethernet address in enet_det[].
297 Print chip name instead of "UNKNOWN" during boot.
298 0.42 26-Apr-96 Fix MII write TA bit error.
299 Fix bug in dc21040 and dc21041 autosense code.
300 Remove buffer copies on receive for Intels.
301 Change sk_buff handling during media disconnects to
302 eliminate DUP packets.
303 Add dynamic TX thresholding.
304 Change all chips to use perfect multicast filtering.
305 Fix alloc_device() bug <jari@markkus2.fimr.fi>
306 0.43 21-Jun-96 Fix unconnected media TX retry bug.
307 Add Accton to the list of broken cards.
308 Fix TX under-run bug for non DC21140 chips.
309 Fix boot command probe bug in alloc_device() as
310 reported by <koen.gadeyne@barco.com> and
311 <orava@nether.tky.hut.fi>.
312 Add cache locks to prevent a race condition as
313 reported by <csd@microplex.com> and
314 <baba@beckman.uiuc.edu>.
315 Upgraded alloc_device() code.
316 0.431 28-Jun-96 Fix potential bug in queue_pkt() from discussion
317 with <csd@microplex.com>
318 0.44 13-Aug-96 Fix RX overflow bug in 2114[023] chips.
319 Fix EISA probe bugs reported by <os2@kpi.kharkov.ua>
320 and <michael@compurex.com>.
321 0.441 9-Sep-96 Change dc21041_autoconf() to probe quiet BNC media
322 with a loopback packet.
323 0.442 9-Sep-96 Include AUI in dc21041 media printout. Bug reported
324 by <bhat@mundook.cs.mu.OZ.AU>
325 0.45 8-Dec-96 Include endian functions for PPC use, from work
326 by <cort@cs.nmt.edu> and <g.thomas@opengroup.org>.
327 0.451 28-Dec-96 Added fix to allow autoprobe for modules after
328 suggestion from <mjacob@feral.com>.
329 0.5 30-Jan-97 Added SROM decoding functions.
331 Fix sleep/wakeup calls for PCI cards, bug reported
332 by <cross@gweep.lkg.dec.com>.
333 Added multi-MAC, one SROM feature from discussion
334 with <mjacob@feral.com>.
335 Added full module autoprobe capability.
336 Added attempt to use an SMC9332 with broken SROM.
337 Added fix for ZYNX multi-mac cards that didn't
338 get their IRQs wired correctly.
339 0.51 13-Feb-97 Added endian fixes for the SROM accesses from
341 Fix init_connection() to remove extra device reset.
342 Fix MAC/PHY reset ordering in dc21140m_autoconf().
343 Fix initialisation problem with lp->timeout in
344 typeX_infoblock() from <paubert@iram.es>.
345 Fix MII PHY reset problem from work done by
347 0.52 26-Apr-97 Some changes may not credit the right people -
348 a disk crash meant I lost some mail.
349 Change RX interrupt routine to drop rather than
350 defer packets to avoid hang reported by
351 <g.thomas@opengroup.org>.
352 Fix srom_exec() to return for COMPACT and type 1
354 Added DC21142 and DC21143 functions.
355 Added byte counters from <phil@tazenda.demon.co.uk>
356 Added IRQF_DISABLED temporary fix from
358 0.53 12-Nov-97 Fix the *_probe() to include 'eth??' name during
359 module load: bug reported by
360 <Piete.Brooks@cl.cam.ac.uk>
361 Fix multi-MAC, one SROM, to work with 2114x chips:
362 bug reported by <cmetz@inner.net>.
363 Make above search independent of BIOS device scan
365 Completed DC2114[23] autosense functions.
366 0.531 21-Dec-97 Fix DE500-XA 100Mb/s bug reported by
368 Fix type1_infoblock() bug introduced in 0.53, from
370 <parmee@postecss.ncrfran.france.ncr.com> and
371 <jo@ice.dillingen.baynet.de>.
372 Added argument list to set up each board from either
373 a module's command line or a compiled in #define.
374 Added generic MII PHY functionality to deal with
376 Fix the mess in 2.1.67.
377 0.532 5-Jan-98 Fix bug in mii_get_phy() reported by
379 Fix bug in pci_probe() for 64 bit systems reported
380 by <belliott@accessone.com>.
381 0.533 9-Jan-98 Fix more 64 bit bugs reported by <jal@cs.brown.edu>.
382 0.534 24-Jan-98 Fix last (?) endian bug from <geert@linux-m68k.org>
383 0.535 21-Feb-98 Fix Ethernet Address PROM reset bug for DC21040.
384 0.536 21-Mar-98 Change pci_probe() to use the pci_dev structure.
385 **Incompatible with 2.0.x from here.**
386 0.540 5-Jul-98 Atomicize assertion of dev->interrupt for SMP
387 from <lma@varesearch.com>
388 Add TP, AUI and BNC cases to 21140m_autoconf() for
389 case where a 21140 under SROM control uses, e.g. AUI
390 from problem report by <delchini@lpnp09.in2p3.fr>
391 Add MII parallel detection to 2114x_autoconf() for
392 case where no autonegotiation partner exists from
393 problem report by <mlapsley@ndirect.co.uk>.
394 Add ability to force connection type directly even
395 when using SROM control from problem report by
397 Updated the PCI interface to conform with the latest
398 version. I hope nothing is broken...
399 Add TX done interrupt modification from suggestion
400 by <Austin.Donnelly@cl.cam.ac.uk>.
401 Fix is_anc_capable() bug reported by
402 <Austin.Donnelly@cl.cam.ac.uk>.
403 Fix type[13]_infoblock() bug: during MII search, PHY
404 lp->rst not run because lp->ibn not initialised -
405 from report & fix by <paubert@iram.es>.
406 Fix probe bug with EISA & PCI cards present from
407 report by <eirik@netcom.com>.
408 0.541 24-Aug-98 Fix compiler problems associated with i386-string
409 ops from multiple bug reports and temporary fix
410 from <paubert@iram.es>.
411 Fix pci_probe() to correctly emulate the old
412 pcibios_find_class() function.
413 Add an_exception() for old ZYNX346 and fix compile
414 warning on PPC & SPARC, from <ecd@skynet.be>.
415 Fix lastPCI to correctly work with compiled in
416 kernels and modules from bug report by
417 <Zlatko.Calusic@CARNet.hr> et al.
418 0.542 15-Sep-98 Fix dc2114x_autoconf() to stop multiple messages
419 when media is unconnected.
420 Change dev->interrupt to lp->interrupt to ensure
421 alignment for Alpha's and avoid their unaligned
422 access traps. This flag is merely for log messages:
423 should do something more definitive though...
424 0.543 30-Dec-98 Add SMP spin locking.
425 0.544 8-May-99 Fix for buggy SROM in Motorola embedded boards using
426 a 21143 by <mmporter@home.com>.
427 Change PCI/EISA bus probing order.
428 0.545 28-Nov-99 Further Moto SROM bug fix from
429 <mporter@eng.mcd.mot.com>
430 Remove double checking for DEBUG_RX in de4x5_dbg_rx()
431 from report by <geert@linux-m68k.org>
432 0.546 22-Feb-01 Fixes Alpha XP1000 oops. The srom_search function
433 was causing a page fault when initializing the
434 variable 'pb', on a non de4x5 PCI device, in this
435 case a PCI bridge (DEC chip 21152). The value of
436 'pb' is now only initialized if a de4x5 chip is
438 <france@handhelds.org>
439 0.547 08-Nov-01 Use library crc32 functions by <Matt_Domsch@dell.com>
440 0.548 30-Aug-03 Big 2.6 cleanup. Ported to PCI/EISA probing and
441 generic DMA APIs. Fixed DE425 support on Alpha.
442 <maz@wild-wind.fr.eu.org>
443 =========================================================================
446 #include <linux/module.h>
447 #include <linux/kernel.h>
448 #include <linux/string.h>
449 #include <linux/interrupt.h>
450 #include <linux/ptrace.h>
451 #include <linux/errno.h>
452 #include <linux/ioport.h>
453 #include <linux/slab.h>
454 #include <linux/pci.h>
455 #include <linux/eisa.h>
456 #include <linux/delay.h>
457 #include <linux/init.h>
458 #include <linux/spinlock.h>
459 #include <linux/crc32.h>
460 #include <linux/netdevice.h>
461 #include <linux/etherdevice.h>
462 #include <linux/skbuff.h>
463 #include <linux/time.h>
464 #include <linux/types.h>
465 #include <linux/unistd.h>
466 #include <linux/ctype.h>
467 #include <linux/dma-mapping.h>
468 #include <linux/moduleparam.h>
469 #include <linux/bitops.h>
473 #include <asm/byteorder.h>
474 #include <asm/unaligned.h>
475 #include <asm/uaccess.h>
476 #ifdef CONFIG_PPC_PMAC
477 #include <asm/machdep.h>
478 #endif /* CONFIG_PPC_PMAC */
482 static char version[] __devinitdata = "de4x5.c:V0.546 2001/02/22 davies@maniac.ultranet.com\n";
484 #define c_char const char
485 #define TWIDDLE(a) (u_short)le16_to_cpu(get_unaligned((u_short *)(a)))
491 int reset; /* Hard reset required? */
492 int id; /* IEEE OUI */
493 int ta; /* One cycle TA time - 802.3u is confusing here */
494 struct { /* Non autonegotiation (parallel) speed det. */
502 int reset; /* Hard reset required? */
503 int id; /* IEEE OUI */
504 int ta; /* One cycle TA time */
505 struct { /* Non autonegotiation (parallel) speed det. */
510 int addr; /* MII address for the PHY */
511 u_char *gep; /* Start of GEP sequence block in SROM */
512 u_char *rst; /* Start of reset sequence in SROM */
513 u_int mc; /* Media Capabilities */
514 u_int ana; /* NWay Advertisement */
515 u_int fdx; /* Full DupleX capabilities for each media */
516 u_int ttm; /* Transmit Threshold Mode for each media */
517 u_int mci; /* 21142 MII Connector Interrupt info */
520 #define DE4X5_MAX_PHY 8 /* Allow upto 8 attached PHY devices per board */
523 u_char mc; /* Media Code */
524 u_char ext; /* csr13-15 valid when set */
525 int csr13; /* SIA Connectivity Register */
526 int csr14; /* SIA TX/RX Register */
527 int csr15; /* SIA General Register */
528 int gepc; /* SIA GEP Control Information */
529 int gep; /* SIA GEP Data */
533 ** Define the know universe of PHY devices that can be
534 ** recognised by this driver.
536 static struct phy_table phy_info[] = {
537 {0, NATIONAL_TX, 1, {0x19, 0x40, 0x00}}, /* National TX */
538 {1, BROADCOM_T4, 1, {0x10, 0x02, 0x02}}, /* Broadcom T4 */
539 {0, SEEQ_T4 , 1, {0x12, 0x10, 0x10}}, /* SEEQ T4 */
540 {0, CYPRESS_T4 , 1, {0x05, 0x20, 0x20}}, /* Cypress T4 */
541 {0, 0x7810 , 1, {0x14, 0x0800, 0x0800}} /* Level One LTX970 */
545 ** These GENERIC values assumes that the PHY devices follow 802.3u and
546 ** allow parallel detection to set the link partner ability register.
547 ** Detection of 100Base-TX [H/F Duplex] and 100Base-T4 is supported.
549 #define GENERIC_REG 0x05 /* Autoneg. Link Partner Advertisement Reg. */
550 #define GENERIC_MASK MII_ANLPA_100M /* All 100Mb/s Technologies */
551 #define GENERIC_VALUE MII_ANLPA_100M /* 100B-TX, 100B-TX FDX, 100B-T4 */
554 ** Define special SROM detection cases
556 static c_char enet_det[][ETH_ALEN] = {
557 {0x00, 0x00, 0xc0, 0x00, 0x00, 0x00},
558 {0x00, 0x00, 0xe8, 0x00, 0x00, 0x00}
565 ** SROM Repair definitions. If a broken SROM is detected a card may
566 ** use this information to help figure out what to do. This is a
567 ** "stab in the dark" and so far for SMC9332's only.
569 static c_char srom_repair_info[][100] = {
570 {0x00,0x1e,0x00,0x00,0x00,0x08, /* SMC9332 */
571 0x1f,0x01,0x8f,0x01,0x00,0x01,0x00,0x02,
572 0x01,0x00,0x00,0x78,0xe0,0x01,0x00,0x50,
578 static int de4x5_debug = DE4X5_DEBUG;
580 /*static int de4x5_debug = (DEBUG_MII | DEBUG_SROM | DEBUG_PCICFG | DEBUG_MEDIA | DEBUG_VERSION);*/
581 static int de4x5_debug = (DEBUG_MEDIA | DEBUG_VERSION);
585 ** Allow per adapter set up. For modules this is simply a command line
587 ** insmod de4x5 args='eth1:fdx autosense=BNC eth0:autosense=100Mb'.
589 ** For a compiled in driver, place e.g.
590 ** #define DE4X5_PARM "eth0:fdx autosense=AUI eth2:autosense=TP"
594 static char *args = DE4X5_PARM;
604 #define DE4X5_AUTOSENSE_MS 250 /* msec autosense tick (DE500) */
606 #define DE4X5_NDA 0xffe0 /* No Device (I/O) Address */
609 ** Ethernet PROM defines
611 #define PROBE_LENGTH 32
612 #define ETH_PROM_SIG 0xAA5500FFUL
617 #define PKT_BUF_SZ 1536 /* Buffer size for each Tx/Rx buffer */
618 #define IEEE802_3_SZ 1518 /* Packet + CRC */
619 #define MAX_PKT_SZ 1514 /* Maximum ethernet packet length */
620 #define MAX_DAT_SZ 1500 /* Maximum ethernet data length */
621 #define MIN_DAT_SZ 1 /* Minimum ethernet data length */
622 #define PKT_HDR_LEN 14 /* Addresses and data length info */
623 #define FAKE_FRAME_LEN (MAX_PKT_SZ + 1)
624 #define QUEUE_PKT_TIMEOUT (3*HZ) /* 3 second timeout */
630 #define DE4X5_EISA_IO_PORTS 0x0c00 /* I/O port base address, slot 0 */
631 #define DE4X5_EISA_TOTAL_SIZE 0x100 /* I/O address extent */
633 #define EISA_ALLOWED_IRQ_LIST {5, 9, 10, 11}
635 #define DE4X5_SIGNATURE {"DE425","DE434","DE435","DE450","DE500"}
636 #define DE4X5_NAME_LENGTH 8
638 static c_char *de4x5_signatures[] = DE4X5_SIGNATURE;
641 ** Ethernet PROM defines for DC21040
643 #define PROBE_LENGTH 32
644 #define ETH_PROM_SIG 0xAA5500FFUL
649 #define PCI_MAX_BUS_NUM 8
650 #define DE4X5_PCI_TOTAL_SIZE 0x80 /* I/O address extent */
651 #define DE4X5_CLASS_CODE 0x00020000 /* Network controller, Ethernet */
654 ** Memory Alignment. Each descriptor is 4 longwords long. To force a
655 ** particular alignment on the TX descriptor, adjust DESC_SKIP_LEN and
656 ** DESC_ALIGN. ALIGN aligns the start address of the private memory area
657 ** and hence the RX descriptor ring's first entry.
659 #define DE4X5_ALIGN4 ((u_long)4 - 1) /* 1 longword align */
660 #define DE4X5_ALIGN8 ((u_long)8 - 1) /* 2 longword align */
661 #define DE4X5_ALIGN16 ((u_long)16 - 1) /* 4 longword align */
662 #define DE4X5_ALIGN32 ((u_long)32 - 1) /* 8 longword align */
663 #define DE4X5_ALIGN64 ((u_long)64 - 1) /* 16 longword align */
664 #define DE4X5_ALIGN128 ((u_long)128 - 1) /* 32 longword align */
666 #define DE4X5_ALIGN DE4X5_ALIGN32 /* Keep the DC21040 happy... */
667 #define DE4X5_CACHE_ALIGN CAL_16LONG
668 #define DESC_SKIP_LEN DSL_0 /* Must agree with DESC_ALIGN */
669 /*#define DESC_ALIGN u32 dummy[4]; / * Must agree with DESC_SKIP_LEN */
672 #ifndef DEC_ONLY /* See README.de4x5 for using this */
675 static int dec_only = 1;
679 ** DE4X5 IRQ ENABLE/DISABLE
681 #define ENABLE_IRQs { \
683 outl(imr, DE4X5_IMR); /* Enable the IRQs */\
686 #define DISABLE_IRQs {\
687 imr = inl(DE4X5_IMR);\
689 outl(imr, DE4X5_IMR); /* Disable the IRQs */\
692 #define UNMASK_IRQs {\
693 imr |= lp->irq_mask;\
694 outl(imr, DE4X5_IMR); /* Unmask the IRQs */\
698 imr = inl(DE4X5_IMR);\
699 imr &= ~lp->irq_mask;\
700 outl(imr, DE4X5_IMR); /* Mask the IRQs */\
706 #define START_DE4X5 {\
707 omr = inl(DE4X5_OMR);\
708 omr |= OMR_ST | OMR_SR;\
709 outl(omr, DE4X5_OMR); /* Enable the TX and/or RX */\
712 #define STOP_DE4X5 {\
713 omr = inl(DE4X5_OMR);\
714 omr &= ~(OMR_ST|OMR_SR);\
715 outl(omr, DE4X5_OMR); /* Disable the TX and/or RX */ \
721 #define RESET_SIA outl(0, DE4X5_SICR); /* Reset SIA connectivity regs */
724 ** DE500 AUTOSENSE TIMER INTERVAL (MILLISECS)
726 #define DE4X5_AUTOSENSE_MS 250
732 char sub_vendor_id[2];
733 char sub_system_id[2];
738 char num_controllers;
743 #define SUB_VENDOR_ID 0x500a
746 ** DE4X5 Descriptors. Make sure that all the RX buffers are contiguous
747 ** and have sizes of both a power of 2 and a multiple of 4.
748 ** A size of 256 bytes for each buffer could be chosen because over 90% of
749 ** all packets in our network are <256 bytes long and 64 longword alignment
750 ** is possible. 1536 showed better 'ttcp' performance. Take your pick. 32 TX
751 ** descriptors are needed for machines with an ALPHA CPU.
753 #define NUM_RX_DESC 8 /* Number of RX descriptors */
754 #define NUM_TX_DESC 32 /* Number of TX descriptors */
755 #define RX_BUFF_SZ 1536 /* Power of 2 for kmalloc and */
756 /* Multiple of 4 for DC21040 */
757 /* Allows 512 byte alignment */
767 ** The DE4X5 private structure
769 #define DE4X5_PKT_STAT_SZ 16
770 #define DE4X5_PKT_BIN_SZ 128 /* Should be >=100 unless you
771 increase DE4X5_PKT_STAT_SZ */
774 u_int bins[DE4X5_PKT_STAT_SZ]; /* Private stats counters */
778 u_int excessive_collisions;
780 u_int excessive_underruns;
781 u_int rx_runt_frames;
787 struct de4x5_private {
788 char adapter_name[80]; /* Adapter name */
789 u_long interrupt; /* Aligned ISR flag */
790 struct de4x5_desc *rx_ring; /* RX descriptor ring */
791 struct de4x5_desc *tx_ring; /* TX descriptor ring */
792 struct sk_buff *tx_skb[NUM_TX_DESC]; /* TX skb for freeing when sent */
793 struct sk_buff *rx_skb[NUM_RX_DESC]; /* RX skb's */
794 int rx_new, rx_old; /* RX descriptor ring pointers */
795 int tx_new, tx_old; /* TX descriptor ring pointers */
796 char setup_frame[SETUP_FRAME_LEN]; /* Holds MCA and PA info. */
797 char frame[64]; /* Min sized packet for loopback*/
798 spinlock_t lock; /* Adapter specific spinlock */
799 struct net_device_stats stats; /* Public stats */
800 struct pkt_stats pktStats; /* Private stats counters */
803 int bus; /* EISA or PCI */
804 int bus_num; /* PCI Bus number */
805 int device; /* Device number on PCI bus */
806 int state; /* Adapter OPENED or CLOSED */
807 int chipset; /* DC21040, DC21041 or DC21140 */
808 s32 irq_mask; /* Interrupt Mask (Enable) bits */
809 s32 irq_en; /* Summary interrupt bits */
810 int media; /* Media (eg TP), mode (eg 100B)*/
811 int c_media; /* Remember the last media conn */
812 int fdx; /* media full duplex flag */
813 int linkOK; /* Link is OK */
814 int autosense; /* Allow/disallow autosensing */
815 int tx_enable; /* Enable descriptor polling */
816 int setup_f; /* Setup frame filtering type */
817 int local_state; /* State within a 'media' state */
818 struct mii_phy phy[DE4X5_MAX_PHY]; /* List of attached PHY devices */
819 struct sia_phy sia; /* SIA PHY Information */
820 int active; /* Index to active PHY device */
821 int mii_cnt; /* Number of attached PHY's */
822 int timeout; /* Scheduling counter */
823 struct timer_list timer; /* Timer info for kernel */
824 int tmp; /* Temporary global per card */
826 u_long lock; /* Lock the cache accesses */
827 s32 csr0; /* Saved Bus Mode Register */
828 s32 csr6; /* Saved Operating Mode Reg. */
829 s32 csr7; /* Saved IRQ Mask Register */
830 s32 gep; /* Saved General Purpose Reg. */
831 s32 gepc; /* Control info for GEP */
832 s32 csr13; /* Saved SIA Connectivity Reg. */
833 s32 csr14; /* Saved SIA TX/RX Register */
834 s32 csr15; /* Saved SIA General Register */
835 int save_cnt; /* Flag if state already saved */
836 struct sk_buff *skb; /* Save the (re-ordered) skb's */
838 struct de4x5_srom srom; /* A copy of the SROM */
839 int cfrv; /* Card CFRV copy */
840 int rx_ovf; /* Check for 'RX overflow' tag */
841 int useSROM; /* For non-DEC card use SROM */
842 int useMII; /* Infoblock using the MII */
843 int asBitValid; /* Autosense bits in GEP? */
844 int asPolarity; /* 0 => asserted high */
845 int asBit; /* Autosense bit number in GEP */
846 int defMedium; /* SROM default medium */
847 int tcount; /* Last infoblock number */
848 int infoblock_init; /* Initialised this infoblock? */
849 int infoleaf_offset; /* SROM infoleaf for controller */
850 s32 infoblock_csr6; /* csr6 value in SROM infoblock */
851 int infoblock_media; /* infoblock media */
852 int (*infoleaf_fn)(struct net_device *); /* Pointer to infoleaf function */
853 u_char *rst; /* Pointer to Type 5 reset info */
854 u_char ibn; /* Infoblock number */
855 struct parameters params; /* Command line/ #defined params */
856 struct device *gendev; /* Generic device */
857 dma_addr_t dma_rings; /* DMA handle for rings */
858 int dma_size; /* Size of the DMA area */
859 char *rx_bufs; /* rx bufs on alpha, sparc, ... */
863 ** To get around certain poxy cards that don't provide an SROM
864 ** for the second and more DECchip, I have to key off the first
865 ** chip's address. I'll assume there's not a bad SROM iff:
867 ** o the chipset is the same
868 ** o the bus number is the same and > 0
869 ** o the sum of all the returned hw address bytes is 0 or 0x5fa
871 ** Also have to save the irq for those cards whose hardware designers
872 ** can't follow the PCI to PCI Bridge Architecture spec.
878 u_char addr[ETH_ALEN];
882 ** The transmit ring full condition is described by the tx_old and tx_new
884 ** tx_old = tx_new Empty ring
885 ** tx_old = tx_new+1 Full ring
886 ** tx_old+txRingSize = tx_new+1 Full ring (wrapped condition)
888 #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
889 lp->tx_old+lp->txRingSize-lp->tx_new-1:\
890 lp->tx_old -lp->tx_new-1)
892 #define TX_PKT_PENDING (lp->tx_old != lp->tx_new)
897 static int de4x5_open(struct net_device *dev);
898 static int de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev);
899 static irqreturn_t de4x5_interrupt(int irq, void *dev_id);
900 static int de4x5_close(struct net_device *dev);
901 static struct net_device_stats *de4x5_get_stats(struct net_device *dev);
902 static void de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len);
903 static void set_multicast_list(struct net_device *dev);
904 static int de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
909 static int de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev);
910 static int de4x5_init(struct net_device *dev);
911 static int de4x5_sw_reset(struct net_device *dev);
912 static int de4x5_rx(struct net_device *dev);
913 static int de4x5_tx(struct net_device *dev);
914 static int de4x5_ast(struct net_device *dev);
915 static int de4x5_txur(struct net_device *dev);
916 static int de4x5_rx_ovfc(struct net_device *dev);
918 static int autoconf_media(struct net_device *dev);
919 static void create_packet(struct net_device *dev, char *frame, int len);
920 static void load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb);
921 static int dc21040_autoconf(struct net_device *dev);
922 static int dc21041_autoconf(struct net_device *dev);
923 static int dc21140m_autoconf(struct net_device *dev);
924 static int dc2114x_autoconf(struct net_device *dev);
925 static int srom_autoconf(struct net_device *dev);
926 static int de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state, int (*fn)(struct net_device *, int), int (*asfn)(struct net_device *));
927 static int dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout, int next_state, int suspect_state, int (*fn)(struct net_device *, int));
928 static int test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec);
929 static int test_for_100Mb(struct net_device *dev, int msec);
930 static int wait_for_link(struct net_device *dev);
931 static int test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec);
932 static int is_spd_100(struct net_device *dev);
933 static int is_100_up(struct net_device *dev);
934 static int is_10_up(struct net_device *dev);
935 static int is_anc_capable(struct net_device *dev);
936 static int ping_media(struct net_device *dev, int msec);
937 static struct sk_buff *de4x5_alloc_rx_buff(struct net_device *dev, int index, int len);
938 static void de4x5_free_rx_buffs(struct net_device *dev);
939 static void de4x5_free_tx_buffs(struct net_device *dev);
940 static void de4x5_save_skbs(struct net_device *dev);
941 static void de4x5_rst_desc_ring(struct net_device *dev);
942 static void de4x5_cache_state(struct net_device *dev, int flag);
943 static void de4x5_put_cache(struct net_device *dev, struct sk_buff *skb);
944 static void de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb);
945 static struct sk_buff *de4x5_get_cache(struct net_device *dev);
946 static void de4x5_setup_intr(struct net_device *dev);
947 static void de4x5_init_connection(struct net_device *dev);
948 static int de4x5_reset_phy(struct net_device *dev);
949 static void reset_init_sia(struct net_device *dev, s32 sicr, s32 strr, s32 sigr);
950 static int test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec);
951 static int test_tp(struct net_device *dev, s32 msec);
952 static int EISA_signature(char *name, struct device *device);
953 static int PCI_signature(char *name, struct de4x5_private *lp);
954 static void DevicePresent(struct net_device *dev, u_long iobase);
955 static void enet_addr_rst(u_long aprom_addr);
956 static int de4x5_bad_srom(struct de4x5_private *lp);
957 static short srom_rd(u_long address, u_char offset);
958 static void srom_latch(u_int command, u_long address);
959 static void srom_command(u_int command, u_long address);
960 static void srom_address(u_int command, u_long address, u_char offset);
961 static short srom_data(u_int command, u_long address);
962 /*static void srom_busy(u_int command, u_long address);*/
963 static void sendto_srom(u_int command, u_long addr);
964 static int getfrom_srom(u_long addr);
965 static int srom_map_media(struct net_device *dev);
966 static int srom_infoleaf_info(struct net_device *dev);
967 static void srom_init(struct net_device *dev);
968 static void srom_exec(struct net_device *dev, u_char *p);
969 static int mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr);
970 static void mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr);
971 static int mii_rdata(u_long ioaddr);
972 static void mii_wdata(int data, int len, u_long ioaddr);
973 static void mii_ta(u_long rw, u_long ioaddr);
974 static int mii_swap(int data, int len);
975 static void mii_address(u_char addr, u_long ioaddr);
976 static void sendto_mii(u32 command, int data, u_long ioaddr);
977 static int getfrom_mii(u32 command, u_long ioaddr);
978 static int mii_get_oui(u_char phyaddr, u_long ioaddr);
979 static int mii_get_phy(struct net_device *dev);
980 static void SetMulticastFilter(struct net_device *dev);
981 static int get_hw_addr(struct net_device *dev);
982 static void srom_repair(struct net_device *dev, int card);
983 static int test_bad_enet(struct net_device *dev, int status);
984 static int an_exception(struct de4x5_private *lp);
985 static char *build_setup_frame(struct net_device *dev, int mode);
986 static void disable_ast(struct net_device *dev);
987 static void enable_ast(struct net_device *dev, u32 time_out);
988 static long de4x5_switch_mac_port(struct net_device *dev);
989 static int gep_rd(struct net_device *dev);
990 static void gep_wr(s32 data, struct net_device *dev);
991 static void timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec);
992 static void yawn(struct net_device *dev, int state);
993 static void de4x5_parse_params(struct net_device *dev);
994 static void de4x5_dbg_open(struct net_device *dev);
995 static void de4x5_dbg_mii(struct net_device *dev, int k);
996 static void de4x5_dbg_media(struct net_device *dev);
997 static void de4x5_dbg_srom(struct de4x5_srom *p);
998 static void de4x5_dbg_rx(struct sk_buff *skb, int len);
999 static int de4x5_strncmp(char *a, char *b, int n);
1000 static int dc21041_infoleaf(struct net_device *dev);
1001 static int dc21140_infoleaf(struct net_device *dev);
1002 static int dc21142_infoleaf(struct net_device *dev);
1003 static int dc21143_infoleaf(struct net_device *dev);
1004 static int type0_infoblock(struct net_device *dev, u_char count, u_char *p);
1005 static int type1_infoblock(struct net_device *dev, u_char count, u_char *p);
1006 static int type2_infoblock(struct net_device *dev, u_char count, u_char *p);
1007 static int type3_infoblock(struct net_device *dev, u_char count, u_char *p);
1008 static int type4_infoblock(struct net_device *dev, u_char count, u_char *p);
1009 static int type5_infoblock(struct net_device *dev, u_char count, u_char *p);
1010 static int compact_infoblock(struct net_device *dev, u_char count, u_char *p);
1013 ** Note now that module autoprobing is allowed under EISA and PCI. The
1014 ** IRQ lines will not be auto-detected; instead I'll rely on the BIOSes
1015 ** to "do the right thing".
1018 static int io=0x0;/* EDIT THIS LINE FOR YOUR CONFIGURATION IF NEEDED */
1020 module_param(io, int, 0);
1021 module_param(de4x5_debug, int, 0);
1022 module_param(dec_only, int, 0);
1023 module_param(args, charp, 0);
1025 MODULE_PARM_DESC(io, "de4x5 I/O base address");
1026 MODULE_PARM_DESC(de4x5_debug, "de4x5 debug mask");
1027 MODULE_PARM_DESC(dec_only, "de4x5 probe only for Digital boards (0-1)");
1028 MODULE_PARM_DESC(args, "de4x5 full duplex and media type settings; see de4x5.c for details");
1029 MODULE_LICENSE("GPL");
1032 ** List the SROM infoleaf functions and chipsets
1036 int (*fn)(struct net_device *);
1038 static struct InfoLeaf infoleaf_array[] = {
1039 {DC21041, dc21041_infoleaf},
1040 {DC21140, dc21140_infoleaf},
1041 {DC21142, dc21142_infoleaf},
1042 {DC21143, dc21143_infoleaf}
1044 #define INFOLEAF_SIZE (sizeof(infoleaf_array)/(sizeof(int)+sizeof(int *)))
1047 ** List the SROM info block functions
1049 static int (*dc_infoblock[])(struct net_device *dev, u_char, u_char *) = {
1059 #define COMPACT (sizeof(dc_infoblock)/sizeof(int *) - 1)
1062 ** Miscellaneous defines...
1064 #define RESET_DE4X5 {\
1068 outl(i | BMR_SWR, DE4X5_BMR);\
1070 outl(i, DE4X5_BMR);\
1072 for (i=0;i<5;i++) {inl(DE4X5_BMR); mdelay(1);}\
1076 #define PHY_HARD_RESET {\
1077 outl(GEP_HRST, DE4X5_GEP); /* Hard RESET the PHY dev. */\
1078 mdelay(1); /* Assert for 1ms */\
1079 outl(0x00, DE4X5_GEP);\
1080 mdelay(2); /* Wait for 2ms */\
1084 static int __devinit
1085 de4x5_hw_init(struct net_device *dev, u_long iobase, struct device *gendev)
1087 char name[DE4X5_NAME_LENGTH + 1];
1088 struct de4x5_private *lp = netdev_priv(dev);
1089 struct pci_dev *pdev = NULL;
1092 gendev->driver_data = dev;
1094 /* Ensure we're not sleeping */
1095 if (lp->bus == EISA) {
1096 outb(WAKEUP, PCI_CFPM);
1098 pdev = to_pci_dev (gendev);
1099 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
1105 if ((inl(DE4X5_STS) & (STS_TS | STS_RS)) != 0) {
1106 return -ENXIO; /* Hardware could not reset */
1110 ** Now find out what kind of DC21040/DC21041/DC21140 board we have.
1112 lp->useSROM = FALSE;
1113 if (lp->bus == PCI) {
1114 PCI_signature(name, lp);
1116 EISA_signature(name, gendev);
1119 if (*name == '\0') { /* Not found a board signature */
1123 dev->base_addr = iobase;
1124 printk ("%s: %s at 0x%04lx", gendev->bus_id, name, iobase);
1126 printk(", h/w address ");
1127 status = get_hw_addr(dev);
1128 for (i = 0; i < ETH_ALEN - 1; i++) { /* get the ethernet addr. */
1129 printk("%2.2x:", dev->dev_addr[i]);
1131 printk("%2.2x,\n", dev->dev_addr[i]);
1134 printk(" which has an Ethernet PROM CRC error.\n");
1137 lp->cache.gepc = GEP_INIT;
1138 lp->asBit = GEP_SLNK;
1139 lp->asPolarity = GEP_SLNK;
1140 lp->asBitValid = TRUE;
1142 lp->gendev = gendev;
1143 spin_lock_init(&lp->lock);
1144 init_timer(&lp->timer);
1145 de4x5_parse_params(dev);
1148 ** Choose correct autosensing in case someone messed up
1150 lp->autosense = lp->params.autosense;
1151 if (lp->chipset != DC21140) {
1152 if ((lp->chipset==DC21040) && (lp->params.autosense&TP_NW)) {
1153 lp->params.autosense = TP;
1155 if ((lp->chipset==DC21041) && (lp->params.autosense&BNC_AUI)) {
1156 lp->params.autosense = BNC;
1159 lp->fdx = lp->params.fdx;
1160 sprintf(lp->adapter_name,"%s (%s)", name, gendev->bus_id);
1162 lp->dma_size = (NUM_RX_DESC + NUM_TX_DESC) * sizeof(struct de4x5_desc);
1163 #if defined(__alpha__) || defined(__powerpc__) || defined(__sparc_v9__) || defined(DE4X5_DO_MEMCPY)
1164 lp->dma_size += RX_BUFF_SZ * NUM_RX_DESC + DE4X5_ALIGN;
1166 lp->rx_ring = dma_alloc_coherent(gendev, lp->dma_size,
1167 &lp->dma_rings, GFP_ATOMIC);
1168 if (lp->rx_ring == NULL) {
1172 lp->tx_ring = lp->rx_ring + NUM_RX_DESC;
1175 ** Set up the RX descriptor ring (Intels)
1176 ** Allocate contiguous receive buffers, long word aligned (Alphas)
1178 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
1179 for (i=0; i<NUM_RX_DESC; i++) {
1180 lp->rx_ring[i].status = 0;
1181 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1182 lp->rx_ring[i].buf = 0;
1183 lp->rx_ring[i].next = 0;
1184 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1189 dma_addr_t dma_rx_bufs;
1191 dma_rx_bufs = lp->dma_rings + (NUM_RX_DESC + NUM_TX_DESC)
1192 * sizeof(struct de4x5_desc);
1193 dma_rx_bufs = (dma_rx_bufs + DE4X5_ALIGN) & ~DE4X5_ALIGN;
1194 lp->rx_bufs = (char *)(((long)(lp->rx_ring + NUM_RX_DESC
1195 + NUM_TX_DESC) + DE4X5_ALIGN) & ~DE4X5_ALIGN);
1196 for (i=0; i<NUM_RX_DESC; i++) {
1197 lp->rx_ring[i].status = 0;
1198 lp->rx_ring[i].des1 = cpu_to_le32(RX_BUFF_SZ);
1199 lp->rx_ring[i].buf =
1200 cpu_to_le32(dma_rx_bufs+i*RX_BUFF_SZ);
1201 lp->rx_ring[i].next = 0;
1202 lp->rx_skb[i] = (struct sk_buff *) 1; /* Dummy entry */
1210 lp->rxRingSize = NUM_RX_DESC;
1211 lp->txRingSize = NUM_TX_DESC;
1213 /* Write the end of list marker to the descriptor lists */
1214 lp->rx_ring[lp->rxRingSize - 1].des1 |= cpu_to_le32(RD_RER);
1215 lp->tx_ring[lp->txRingSize - 1].des1 |= cpu_to_le32(TD_TER);
1217 /* Tell the adapter where the TX/RX rings are located. */
1218 outl(lp->dma_rings, DE4X5_RRBA);
1219 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1222 /* Initialise the IRQ mask and Enable/Disable */
1223 lp->irq_mask = IMR_RIM | IMR_TIM | IMR_TUM | IMR_UNM;
1224 lp->irq_en = IMR_NIM | IMR_AIM;
1226 /* Create a loopback packet frame for later media probing */
1227 create_packet(dev, lp->frame, sizeof(lp->frame));
1229 /* Check if the RX overflow bug needs testing for */
1230 i = lp->cfrv & 0x000000fe;
1231 if ((lp->chipset == DC21140) && (i == 0x20)) {
1235 /* Initialise the SROM pointers if possible */
1237 lp->state = INITIALISED;
1238 if (srom_infoleaf_info(dev)) {
1239 dma_free_coherent (gendev, lp->dma_size,
1240 lp->rx_ring, lp->dma_rings);
1249 ** Check for an MII interface
1251 if ((lp->chipset != DC21040) && (lp->chipset != DC21041)) {
1255 #ifndef __sparc_v9__
1256 printk(" and requires IRQ%d (provided by %s).\n", dev->irq,
1258 printk(" and requires IRQ%x (provided by %s).\n", dev->irq,
1260 ((lp->bus == PCI) ? "PCI BIOS" : "EISA CNFG"));
1263 if (de4x5_debug & DEBUG_VERSION) {
1267 /* The DE4X5-specific entries in the device structure. */
1268 SET_MODULE_OWNER(dev);
1269 SET_NETDEV_DEV(dev, gendev);
1270 dev->open = &de4x5_open;
1271 dev->hard_start_xmit = &de4x5_queue_pkt;
1272 dev->stop = &de4x5_close;
1273 dev->get_stats = &de4x5_get_stats;
1274 dev->set_multicast_list = &set_multicast_list;
1275 dev->do_ioctl = &de4x5_ioctl;
1279 /* Fill in the generic fields of the device structure. */
1280 if ((status = register_netdev (dev))) {
1281 dma_free_coherent (gendev, lp->dma_size,
1282 lp->rx_ring, lp->dma_rings);
1286 /* Let the adapter sleep to save power */
1294 de4x5_open(struct net_device *dev)
1296 struct de4x5_private *lp = netdev_priv(dev);
1297 u_long iobase = dev->base_addr;
1301 /* Allocate the RX buffers */
1302 for (i=0; i<lp->rxRingSize; i++) {
1303 if (de4x5_alloc_rx_buff(dev, i, 0) == NULL) {
1304 de4x5_free_rx_buffs(dev);
1310 ** Wake up the adapter
1315 ** Re-initialize the DE4X5...
1317 status = de4x5_init(dev);
1318 spin_lock_init(&lp->lock);
1320 de4x5_dbg_open(dev);
1322 if (request_irq(dev->irq, (void *)de4x5_interrupt, IRQF_SHARED,
1323 lp->adapter_name, dev)) {
1324 printk("de4x5_open(): Requested IRQ%d is busy - attemping FAST/SHARE...", dev->irq);
1325 if (request_irq(dev->irq, de4x5_interrupt, IRQF_DISABLED | IRQF_SHARED,
1326 lp->adapter_name, dev)) {
1327 printk("\n Cannot get IRQ- reconfigure your hardware.\n");
1329 de4x5_free_rx_buffs(dev);
1330 de4x5_free_tx_buffs(dev);
1335 printk("\n Succeeded, but you should reconfigure your hardware to avoid this.\n");
1336 printk("WARNING: there may be IRQ related problems in heavily loaded systems.\n");
1340 lp->interrupt = UNMASK_INTERRUPTS;
1341 dev->trans_start = jiffies;
1345 de4x5_setup_intr(dev);
1347 if (de4x5_debug & DEBUG_OPEN) {
1348 printk("\tsts: 0x%08x\n", inl(DE4X5_STS));
1349 printk("\tbmr: 0x%08x\n", inl(DE4X5_BMR));
1350 printk("\timr: 0x%08x\n", inl(DE4X5_IMR));
1351 printk("\tomr: 0x%08x\n", inl(DE4X5_OMR));
1352 printk("\tsisr: 0x%08x\n", inl(DE4X5_SISR));
1353 printk("\tsicr: 0x%08x\n", inl(DE4X5_SICR));
1354 printk("\tstrr: 0x%08x\n", inl(DE4X5_STRR));
1355 printk("\tsigr: 0x%08x\n", inl(DE4X5_SIGR));
1362 ** Initialize the DE4X5 operating conditions. NB: a chip problem with the
1363 ** DC21140 requires using perfect filtering mode for that chip. Since I can't
1364 ** see why I'd want > 14 multicast addresses, I have changed all chips to use
1365 ** the perfect filtering mode. Keep the DMA burst length at 8: there seems
1366 ** to be data corruption problems if it is larger (UDP errors seen from a
1370 de4x5_init(struct net_device *dev)
1372 /* Lock out other processes whilst setting up the hardware */
1373 netif_stop_queue(dev);
1375 de4x5_sw_reset(dev);
1377 /* Autoconfigure the connected port */
1378 autoconf_media(dev);
1384 de4x5_sw_reset(struct net_device *dev)
1386 struct de4x5_private *lp = netdev_priv(dev);
1387 u_long iobase = dev->base_addr;
1388 int i, j, status = 0;
1391 /* Select the MII or SRL port now and RESET the MAC */
1393 if (lp->phy[lp->active].id != 0) {
1394 lp->infoblock_csr6 = OMR_SDP | OMR_PS | OMR_HBD;
1396 lp->infoblock_csr6 = OMR_SDP | OMR_TTM;
1398 de4x5_switch_mac_port(dev);
1402 ** Set the programmable burst length to 8 longwords for all the DC21140
1403 ** Fasternet chips and 4 longwords for all others: DMA errors result
1404 ** without these values. Cache align 16 long.
1406 bmr = (lp->chipset==DC21140 ? PBL_8 : PBL_4) | DESC_SKIP_LEN | DE4X5_CACHE_ALIGN;
1407 bmr |= ((lp->chipset & ~0x00ff)==DC2114x ? BMR_RML : 0);
1408 outl(bmr, DE4X5_BMR);
1410 omr = inl(DE4X5_OMR) & ~OMR_PR; /* Turn off promiscuous mode */
1411 if (lp->chipset == DC21140) {
1412 omr |= (OMR_SDP | OMR_SB);
1414 lp->setup_f = PERFECT;
1415 outl(lp->dma_rings, DE4X5_RRBA);
1416 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
1419 lp->rx_new = lp->rx_old = 0;
1420 lp->tx_new = lp->tx_old = 0;
1422 for (i = 0; i < lp->rxRingSize; i++) {
1423 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
1426 for (i = 0; i < lp->txRingSize; i++) {
1427 lp->tx_ring[i].status = cpu_to_le32(0);
1432 /* Build the setup frame depending on filtering mode */
1433 SetMulticastFilter(dev);
1435 load_packet(dev, lp->setup_frame, PERFECT_F|TD_SET|SETUP_FRAME_LEN, (struct sk_buff *)1);
1436 outl(omr|OMR_ST, DE4X5_OMR);
1438 /* Poll for setup frame completion (adapter interrupts are disabled now) */
1440 for (j=0, i=0;(i<500) && (j==0);i++) { /* Upto 500ms delay */
1442 if ((s32)le32_to_cpu(lp->tx_ring[lp->tx_new].status) >= 0) j=1;
1444 outl(omr, DE4X5_OMR); /* Stop everything! */
1447 printk("%s: Setup frame timed out, status %08x\n", dev->name,
1452 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1453 lp->tx_old = lp->tx_new;
1459 ** Writes a socket buffer address to the next available transmit descriptor.
1462 de4x5_queue_pkt(struct sk_buff *skb, struct net_device *dev)
1464 struct de4x5_private *lp = netdev_priv(dev);
1465 u_long iobase = dev->base_addr;
1469 netif_stop_queue(dev);
1470 if (lp->tx_enable == NO) { /* Cannot send for now */
1475 ** Clean out the TX ring asynchronously to interrupts - sometimes the
1476 ** interrupts are lost by delayed descriptor status updates relative to
1477 ** the irq assertion, especially with a busy PCI bus.
1479 spin_lock_irqsave(&lp->lock, flags);
1481 spin_unlock_irqrestore(&lp->lock, flags);
1483 /* Test if cache is already locked - requeue skb if so */
1484 if (test_and_set_bit(0, (void *)&lp->cache.lock) && !lp->interrupt)
1487 /* Transmit descriptor ring full or stale skb */
1488 if (netif_queue_stopped(dev) || (u_long) lp->tx_skb[lp->tx_new] > 1) {
1489 if (lp->interrupt) {
1490 de4x5_putb_cache(dev, skb); /* Requeue the buffer */
1492 de4x5_put_cache(dev, skb);
1494 if (de4x5_debug & DEBUG_TX) {
1495 printk("%s: transmit busy, lost media or stale skb found:\n STS:%08x\n tbusy:%d\n IMR:%08x\n OMR:%08x\n Stale skb: %s\n",dev->name, inl(DE4X5_STS), netif_queue_stopped(dev), inl(DE4X5_IMR), inl(DE4X5_OMR), ((u_long) lp->tx_skb[lp->tx_new] > 1) ? "YES" : "NO");
1497 } else if (skb->len > 0) {
1498 /* If we already have stuff queued locally, use that first */
1499 if (lp->cache.skb && !lp->interrupt) {
1500 de4x5_put_cache(dev, skb);
1501 skb = de4x5_get_cache(dev);
1504 while (skb && !netif_queue_stopped(dev) &&
1505 (u_long) lp->tx_skb[lp->tx_new] <= 1) {
1506 spin_lock_irqsave(&lp->lock, flags);
1507 netif_stop_queue(dev);
1508 load_packet(dev, skb->data, TD_IC | TD_LS | TD_FS | skb->len, skb);
1509 lp->stats.tx_bytes += skb->len;
1510 outl(POLL_DEMAND, DE4X5_TPD);/* Start the TX */
1512 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1513 dev->trans_start = jiffies;
1515 if (TX_BUFFS_AVAIL) {
1516 netif_start_queue(dev); /* Another pkt may be queued */
1518 skb = de4x5_get_cache(dev);
1519 spin_unlock_irqrestore(&lp->lock, flags);
1521 if (skb) de4x5_putb_cache(dev, skb);
1530 ** The DE4X5 interrupt handler.
1532 ** I/O Read/Writes through intermediate PCI bridges are never 'posted',
1533 ** so that the asserted interrupt always has some real data to work with -
1534 ** if these I/O accesses are ever changed to memory accesses, ensure the
1535 ** STS write is read immediately to complete the transaction if the adapter
1536 ** is not on bus 0. Lost interrupts can still occur when the PCI bus load
1537 ** is high and descriptor status bits cannot be set before the associated
1538 ** interrupt is asserted and this routine entered.
1541 de4x5_interrupt(int irq, void *dev_id)
1543 struct net_device *dev = dev_id;
1544 struct de4x5_private *lp;
1545 s32 imr, omr, sts, limit;
1547 unsigned int handled = 0;
1549 lp = netdev_priv(dev);
1550 spin_lock(&lp->lock);
1551 iobase = dev->base_addr;
1553 DISABLE_IRQs; /* Ensure non re-entrancy */
1555 if (test_and_set_bit(MASK_INTERRUPTS, (void*) &lp->interrupt))
1556 printk("%s: Re-entering the interrupt handler.\n", dev->name);
1558 synchronize_irq(dev->irq);
1560 for (limit=0; limit<8; limit++) {
1561 sts = inl(DE4X5_STS); /* Read IRQ status */
1562 outl(sts, DE4X5_STS); /* Reset the board interrupts */
1564 if (!(sts & lp->irq_mask)) break;/* All done */
1567 if (sts & (STS_RI | STS_RU)) /* Rx interrupt (packet[s] arrived) */
1570 if (sts & (STS_TI | STS_TU)) /* Tx interrupt (packet sent) */
1573 if (sts & STS_LNF) { /* TP Link has failed */
1574 lp->irq_mask &= ~IMR_LFM;
1577 if (sts & STS_UNF) { /* Transmit underrun */
1581 if (sts & STS_SE) { /* Bus Error */
1583 printk("%s: Fatal bus error occurred, sts=%#8x, device stopped.\n",
1585 spin_unlock(&lp->lock);
1590 /* Load the TX ring with any locally stored packets */
1591 if (!test_and_set_bit(0, (void *)&lp->cache.lock)) {
1592 while (lp->cache.skb && !netif_queue_stopped(dev) && lp->tx_enable) {
1593 de4x5_queue_pkt(de4x5_get_cache(dev), dev);
1598 lp->interrupt = UNMASK_INTERRUPTS;
1600 spin_unlock(&lp->lock);
1602 return IRQ_RETVAL(handled);
1606 de4x5_rx(struct net_device *dev)
1608 struct de4x5_private *lp = netdev_priv(dev);
1609 u_long iobase = dev->base_addr;
1613 for (entry=lp->rx_new; (s32)le32_to_cpu(lp->rx_ring[entry].status)>=0;
1615 status = (s32)le32_to_cpu(lp->rx_ring[entry].status);
1618 if (inl(DE4X5_MFC) & MFC_FOCM) {
1624 if (status & RD_FS) { /* Remember the start of frame */
1628 if (status & RD_LS) { /* Valid frame status */
1629 if (lp->tx_enable) lp->linkOK++;
1630 if (status & RD_ES) { /* There was an error. */
1631 lp->stats.rx_errors++; /* Update the error stats. */
1632 if (status & (RD_RF | RD_TL)) lp->stats.rx_frame_errors++;
1633 if (status & RD_CE) lp->stats.rx_crc_errors++;
1634 if (status & RD_OF) lp->stats.rx_fifo_errors++;
1635 if (status & RD_TL) lp->stats.rx_length_errors++;
1636 if (status & RD_RF) lp->pktStats.rx_runt_frames++;
1637 if (status & RD_CS) lp->pktStats.rx_collision++;
1638 if (status & RD_DB) lp->pktStats.rx_dribble++;
1639 if (status & RD_OF) lp->pktStats.rx_overflow++;
1640 } else { /* A valid frame received */
1641 struct sk_buff *skb;
1642 short pkt_len = (short)(le32_to_cpu(lp->rx_ring[entry].status)
1645 if ((skb = de4x5_alloc_rx_buff(dev, entry, pkt_len)) == NULL) {
1646 printk("%s: Insufficient memory; nuking packet.\n",
1648 lp->stats.rx_dropped++;
1650 de4x5_dbg_rx(skb, pkt_len);
1652 /* Push up the protocol stack */
1653 skb->protocol=eth_type_trans(skb,dev);
1654 de4x5_local_stats(dev, skb->data, pkt_len);
1658 dev->last_rx = jiffies;
1659 lp->stats.rx_packets++;
1660 lp->stats.rx_bytes += pkt_len;
1664 /* Change buffer ownership for this frame, back to the adapter */
1665 for (;lp->rx_old!=entry;lp->rx_old=(++lp->rx_old)%lp->rxRingSize) {
1666 lp->rx_ring[lp->rx_old].status = cpu_to_le32(R_OWN);
1669 lp->rx_ring[entry].status = cpu_to_le32(R_OWN);
1674 ** Update entry information
1676 lp->rx_new = (++lp->rx_new) % lp->rxRingSize;
1683 de4x5_free_tx_buff(struct de4x5_private *lp, int entry)
1685 dma_unmap_single(lp->gendev, le32_to_cpu(lp->tx_ring[entry].buf),
1686 le32_to_cpu(lp->tx_ring[entry].des1) & TD_TBS1,
1688 if ((u_long) lp->tx_skb[entry] > 1)
1689 dev_kfree_skb_irq(lp->tx_skb[entry]);
1690 lp->tx_skb[entry] = NULL;
1694 ** Buffer sent - check for TX buffer errors.
1697 de4x5_tx(struct net_device *dev)
1699 struct de4x5_private *lp = netdev_priv(dev);
1700 u_long iobase = dev->base_addr;
1704 for (entry = lp->tx_old; entry != lp->tx_new; entry = lp->tx_old) {
1705 status = (s32)le32_to_cpu(lp->tx_ring[entry].status);
1706 if (status < 0) { /* Buffer not sent yet */
1708 } else if (status != 0x7fffffff) { /* Not setup frame */
1709 if (status & TD_ES) { /* An error happened */
1710 lp->stats.tx_errors++;
1711 if (status & TD_NC) lp->stats.tx_carrier_errors++;
1712 if (status & TD_LC) lp->stats.tx_window_errors++;
1713 if (status & TD_UF) lp->stats.tx_fifo_errors++;
1714 if (status & TD_EC) lp->pktStats.excessive_collisions++;
1715 if (status & TD_DE) lp->stats.tx_aborted_errors++;
1717 if (TX_PKT_PENDING) {
1718 outl(POLL_DEMAND, DE4X5_TPD);/* Restart a stalled TX */
1720 } else { /* Packet sent */
1721 lp->stats.tx_packets++;
1722 if (lp->tx_enable) lp->linkOK++;
1724 /* Update the collision counter */
1725 lp->stats.collisions += ((status & TD_EC) ? 16 :
1726 ((status & TD_CC) >> 3));
1728 /* Free the buffer. */
1729 if (lp->tx_skb[entry] != NULL)
1730 de4x5_free_tx_buff(lp, entry);
1733 /* Update all the pointers */
1734 lp->tx_old = (++lp->tx_old) % lp->txRingSize;
1737 /* Any resources available? */
1738 if (TX_BUFFS_AVAIL && netif_queue_stopped(dev)) {
1740 netif_wake_queue(dev);
1742 netif_start_queue(dev);
1749 de4x5_ast(struct net_device *dev)
1751 struct de4x5_private *lp = netdev_priv(dev);
1752 int next_tick = DE4X5_AUTOSENSE_MS;
1757 next_tick = srom_autoconf(dev);
1758 } else if (lp->chipset == DC21140) {
1759 next_tick = dc21140m_autoconf(dev);
1760 } else if (lp->chipset == DC21041) {
1761 next_tick = dc21041_autoconf(dev);
1762 } else if (lp->chipset == DC21040) {
1763 next_tick = dc21040_autoconf(dev);
1766 enable_ast(dev, next_tick);
1772 de4x5_txur(struct net_device *dev)
1774 struct de4x5_private *lp = netdev_priv(dev);
1775 u_long iobase = dev->base_addr;
1778 omr = inl(DE4X5_OMR);
1779 if (!(omr & OMR_SF) || (lp->chipset==DC21041) || (lp->chipset==DC21040)) {
1780 omr &= ~(OMR_ST|OMR_SR);
1781 outl(omr, DE4X5_OMR);
1782 while (inl(DE4X5_STS) & STS_TS);
1783 if ((omr & OMR_TR) < OMR_TR) {
1788 outl(omr | OMR_ST | OMR_SR, DE4X5_OMR);
1795 de4x5_rx_ovfc(struct net_device *dev)
1797 struct de4x5_private *lp = netdev_priv(dev);
1798 u_long iobase = dev->base_addr;
1801 omr = inl(DE4X5_OMR);
1802 outl(omr & ~OMR_SR, DE4X5_OMR);
1803 while (inl(DE4X5_STS) & STS_RS);
1805 for (; (s32)le32_to_cpu(lp->rx_ring[lp->rx_new].status)>=0;) {
1806 lp->rx_ring[lp->rx_new].status = cpu_to_le32(R_OWN);
1807 lp->rx_new = (++lp->rx_new % lp->rxRingSize);
1810 outl(omr, DE4X5_OMR);
1816 de4x5_close(struct net_device *dev)
1818 struct de4x5_private *lp = netdev_priv(dev);
1819 u_long iobase = dev->base_addr;
1824 netif_stop_queue(dev);
1826 if (de4x5_debug & DEBUG_CLOSE) {
1827 printk("%s: Shutting down ethercard, status was %8.8x.\n",
1828 dev->name, inl(DE4X5_STS));
1832 ** We stop the DE4X5 here... mask interrupts and stop TX & RX
1837 /* Free the associated irq */
1838 free_irq(dev->irq, dev);
1841 /* Free any socket buffers */
1842 de4x5_free_rx_buffs(dev);
1843 de4x5_free_tx_buffs(dev);
1845 /* Put the adapter to sleep to save power */
1851 static struct net_device_stats *
1852 de4x5_get_stats(struct net_device *dev)
1854 struct de4x5_private *lp = netdev_priv(dev);
1855 u_long iobase = dev->base_addr;
1857 lp->stats.rx_missed_errors = (int)(inl(DE4X5_MFC) & (MFC_OVFL | MFC_CNTR));
1863 de4x5_local_stats(struct net_device *dev, char *buf, int pkt_len)
1865 struct de4x5_private *lp = netdev_priv(dev);
1868 for (i=1; i<DE4X5_PKT_STAT_SZ-1; i++) {
1869 if (pkt_len < (i*DE4X5_PKT_BIN_SZ)) {
1870 lp->pktStats.bins[i]++;
1871 i = DE4X5_PKT_STAT_SZ;
1874 if (buf[0] & 0x01) { /* Multicast/Broadcast */
1875 if ((*(s32 *)&buf[0] == -1) && (*(s16 *)&buf[4] == -1)) {
1876 lp->pktStats.broadcast++;
1878 lp->pktStats.multicast++;
1880 } else if ((*(s32 *)&buf[0] == *(s32 *)&dev->dev_addr[0]) &&
1881 (*(s16 *)&buf[4] == *(s16 *)&dev->dev_addr[4])) {
1882 lp->pktStats.unicast++;
1885 lp->pktStats.bins[0]++; /* Duplicates stats.rx_packets */
1886 if (lp->pktStats.bins[0] == 0) { /* Reset counters */
1887 memset((char *)&lp->pktStats, 0, sizeof(lp->pktStats));
1894 ** Removes the TD_IC flag from previous descriptor to improve TX performance.
1895 ** If the flag is changed on a descriptor that is being read by the hardware,
1896 ** I assume PCI transaction ordering will mean you are either successful or
1897 ** just miss asserting the change to the hardware. Anyway you're messing with
1898 ** a descriptor you don't own, but this shouldn't kill the chip provided
1899 ** the descriptor register is read only to the hardware.
1902 load_packet(struct net_device *dev, char *buf, u32 flags, struct sk_buff *skb)
1904 struct de4x5_private *lp = netdev_priv(dev);
1905 int entry = (lp->tx_new ? lp->tx_new-1 : lp->txRingSize-1);
1906 dma_addr_t buf_dma = dma_map_single(lp->gendev, buf, flags & TD_TBS1, DMA_TO_DEVICE);
1908 lp->tx_ring[lp->tx_new].buf = cpu_to_le32(buf_dma);
1909 lp->tx_ring[lp->tx_new].des1 &= cpu_to_le32(TD_TER);
1910 lp->tx_ring[lp->tx_new].des1 |= cpu_to_le32(flags);
1911 lp->tx_skb[lp->tx_new] = skb;
1912 lp->tx_ring[entry].des1 &= cpu_to_le32(~TD_IC);
1915 lp->tx_ring[lp->tx_new].status = cpu_to_le32(T_OWN);
1920 ** Set or clear the multicast filter for this adaptor.
1923 set_multicast_list(struct net_device *dev)
1925 struct de4x5_private *lp = netdev_priv(dev);
1926 u_long iobase = dev->base_addr;
1928 /* First, double check that the adapter is open */
1929 if (lp->state == OPEN) {
1930 if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
1932 omr = inl(DE4X5_OMR);
1934 outl(omr, DE4X5_OMR);
1936 SetMulticastFilter(dev);
1937 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
1938 SETUP_FRAME_LEN, (struct sk_buff *)1);
1940 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
1941 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
1942 dev->trans_start = jiffies;
1948 ** Calculate the hash code and update the logical address filter
1949 ** from a list of ethernet multicast addresses.
1950 ** Little endian crc one liner from Matt Thomas, DEC.
1953 SetMulticastFilter(struct net_device *dev)
1955 struct de4x5_private *lp = netdev_priv(dev);
1956 struct dev_mc_list *dmi=dev->mc_list;
1957 u_long iobase = dev->base_addr;
1958 int i, j, bit, byte;
1962 unsigned char *addrs;
1964 omr = inl(DE4X5_OMR);
1965 omr &= ~(OMR_PR | OMR_PM);
1966 pa = build_setup_frame(dev, ALL); /* Build the basic frame */
1968 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 14)) {
1969 omr |= OMR_PM; /* Pass all multicasts */
1970 } else if (lp->setup_f == HASH_PERF) { /* Hash Filtering */
1971 for (i=0;i<dev->mc_count;i++) { /* for each address in the list */
1972 addrs=dmi->dmi_addr;
1974 if ((*addrs & 0x01) == 1) { /* multicast address? */
1975 crc = ether_crc_le(ETH_ALEN, addrs);
1976 hashcode = crc & HASH_BITS; /* hashcode is 9 LSb of CRC */
1978 byte = hashcode >> 3; /* bit[3-8] -> byte in filter */
1979 bit = 1 << (hashcode & 0x07);/* bit[0-2] -> bit in byte */
1981 byte <<= 1; /* calc offset into setup frame */
1985 lp->setup_frame[byte] |= bit;
1988 } else { /* Perfect filtering */
1989 for (j=0; j<dev->mc_count; j++) {
1990 addrs=dmi->dmi_addr;
1992 for (i=0; i<ETH_ALEN; i++) {
1993 *(pa + (i&1)) = *addrs++;
1994 if (i & 0x01) pa += 4;
1998 outl(omr, DE4X5_OMR);
2005 static u_char de4x5_irq[] = EISA_ALLOWED_IRQ_LIST;
2007 static int __init de4x5_eisa_probe (struct device *gendev)
2009 struct eisa_device *edev;
2015 struct net_device *dev;
2016 struct de4x5_private *lp;
2018 edev = to_eisa_device (gendev);
2019 iobase = edev->base_addr;
2021 if (!request_region (iobase, DE4X5_EISA_TOTAL_SIZE, "de4x5"))
2024 if (!request_region (iobase + DE4X5_EISA_IO_PORTS,
2025 DE4X5_EISA_TOTAL_SIZE, "de4x5")) {
2030 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2034 lp = netdev_priv(dev);
2036 cfid = (u32) inl(PCI_CFID);
2037 lp->cfrv = (u_short) inl(PCI_CFRV);
2038 device = (cfid >> 8) & 0x00ffff00;
2039 vendor = (u_short) cfid;
2041 /* Read the EISA Configuration Registers */
2042 regval = inb(EISA_REG0) & (ER0_INTL | ER0_INTT);
2044 /* Looks like the Jensen firmware (rev 2.2) doesn't really
2045 * care about the EISA configuration, and thus doesn't
2046 * configure the PLX bridge properly. Oh well... Simply mimic
2047 * the EISA config file to sort it out. */
2049 /* EISA REG1: Assert DecChip 21040 HW Reset */
2050 outb (ER1_IAM | 1, EISA_REG1);
2053 /* EISA REG1: Deassert DecChip 21040 HW Reset */
2054 outb (ER1_IAM, EISA_REG1);
2057 /* EISA REG3: R/W Burst Transfer Enable */
2058 outb (ER3_BWE | ER3_BRE, EISA_REG3);
2060 /* 32_bit slave/master, Preempt Time=23 bclks, Unlatched Interrupt */
2061 outb (ER0_BSW | ER0_BMW | ER0_EPT | regval, EISA_REG0);
2063 irq = de4x5_irq[(regval >> 1) & 0x03];
2066 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2068 lp->chipset = device;
2071 /* Write the PCI Configuration Registers */
2072 outl(PCI_COMMAND_IO | PCI_COMMAND_MASTER, PCI_CFCS);
2073 outl(0x00006000, PCI_CFLT);
2074 outl(iobase, PCI_CBIO);
2076 DevicePresent(dev, EISA_APROM);
2080 if (!(status = de4x5_hw_init (dev, iobase, gendev))) {
2086 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2088 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2093 static int __devexit de4x5_eisa_remove (struct device *device)
2095 struct net_device *dev;
2098 dev = device->driver_data;
2099 iobase = dev->base_addr;
2101 unregister_netdev (dev);
2103 release_region (iobase + DE4X5_EISA_IO_PORTS, DE4X5_EISA_TOTAL_SIZE);
2104 release_region (iobase, DE4X5_EISA_TOTAL_SIZE);
2109 static struct eisa_device_id de4x5_eisa_ids[] = {
2110 { "DEC4250", 0 }, /* 0 is the board name index... */
2113 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2115 static struct eisa_driver de4x5_eisa_driver = {
2116 .id_table = de4x5_eisa_ids,
2119 .probe = de4x5_eisa_probe,
2120 .remove = __devexit_p (de4x5_eisa_remove),
2123 MODULE_DEVICE_TABLE(eisa, de4x5_eisa_ids);
2129 ** This function searches the current bus (which is >0) for a DECchip with an
2130 ** SROM, so that in multiport cards that have one SROM shared between multiple
2131 ** DECchips, we can find the base SROM irrespective of the BIOS scan direction.
2132 ** For single port cards this is a time waster...
2134 static void __devinit
2135 srom_search(struct net_device *dev, struct pci_dev *pdev)
2138 u_short vendor, status;
2139 u_int irq = 0, device;
2140 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2142 struct de4x5_private *lp = netdev_priv(dev);
2143 struct list_head *walk;
2145 list_for_each(walk, &pdev->bus_list) {
2146 struct pci_dev *this_dev = pci_dev_b(walk);
2148 /* Skip the pci_bus list entry */
2149 if (list_entry(walk, struct pci_bus, devices) == pdev->bus) continue;
2151 vendor = this_dev->vendor;
2152 device = this_dev->device << 8;
2153 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x)) continue;
2155 /* Get the chip configuration revision register */
2156 pb = this_dev->bus->number;
2157 pci_read_config_dword(this_dev, PCI_REVISION_ID, &cfrv);
2159 /* Set the device number information */
2160 lp->device = PCI_SLOT(this_dev->devfn);
2163 /* Set the chipset information */
2165 device = ((cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2167 lp->chipset = device;
2169 /* Get the board I/O address (64 bits on sparc64) */
2170 iobase = pci_resource_start(this_dev, 0);
2172 /* Fetch the IRQ to be used */
2173 irq = this_dev->irq;
2174 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) continue;
2176 /* Check if I/O accesses are enabled */
2177 pci_read_config_word(this_dev, PCI_COMMAND, &status);
2178 if (!(status & PCI_COMMAND_IO)) continue;
2180 /* Search for a valid SROM attached to this DECchip */
2181 DevicePresent(dev, DE4X5_APROM);
2182 for (j=0, i=0; i<ETH_ALEN; i++) {
2183 j += (u_char) *((u_char *)&lp->srom + SROM_HWADD + i);
2185 if ((j != 0) && (j != 0x5fa)) {
2186 last.chipset = device;
2189 for (i=0; i<ETH_ALEN; i++) {
2190 last.addr[i] = (u_char)*((u_char *)&lp->srom + SROM_HWADD + i);
2200 ** PCI bus I/O device probe
2201 ** NB: PCI I/O accesses and Bus Mastering are enabled by the PCI BIOS, not
2202 ** the driver. Some PCI BIOS's, pre V2.1, need the slot + features to be
2203 ** enabled by the user first in the set up utility. Hence we just check for
2204 ** enabled features and silently ignore the card if they're not.
2206 ** STOP PRESS: Some BIOS's __require__ the driver to enable the bus mastering
2207 ** bit. Here, check for I/O accesses and then set BM. If you put the card in
2208 ** a non BM slot, you're on your own (and complain to the PC vendor that your
2209 ** PC doesn't conform to the PCI standard)!
2211 ** This function is only compatible with the *latest* 2.1.x kernels. For 2.0.x
2212 ** kernels use the V0.535[n] drivers.
2215 static int __devinit de4x5_pci_probe (struct pci_dev *pdev,
2216 const struct pci_device_id *ent)
2218 u_char pb, pbus = 0, dev_num, dnum = 0, timer;
2219 u_short vendor, status;
2220 u_int irq = 0, device;
2221 u_long iobase = 0; /* Clear upper 32 bits in Alphas */
2223 struct net_device *dev;
2224 struct de4x5_private *lp;
2226 dev_num = PCI_SLOT(pdev->devfn);
2227 pb = pdev->bus->number;
2229 if (io) { /* probe a single PCI device */
2230 pbus = (u_short)(io >> 8);
2231 dnum = (u_short)(io & 0xff);
2232 if ((pbus != pb) || (dnum != dev_num))
2236 vendor = pdev->vendor;
2237 device = pdev->device << 8;
2238 if (!(is_DC21040 || is_DC21041 || is_DC21140 || is_DC2114x))
2241 /* Ok, the device seems to be for us. */
2242 if ((error = pci_enable_device (pdev)))
2245 if (!(dev = alloc_etherdev (sizeof (struct de4x5_private)))) {
2250 lp = netdev_priv(dev);
2254 /* Search for an SROM on this bus */
2255 if (lp->bus_num != pb) {
2257 srom_search(dev, pdev);
2260 /* Get the chip configuration revision register */
2261 pci_read_config_dword(pdev, PCI_REVISION_ID, &lp->cfrv);
2263 /* Set the device number information */
2264 lp->device = dev_num;
2267 /* Set the chipset information */
2269 device = ((lp->cfrv & CFRV_RN) < DC2114x_BRK ? DC21142 : DC21143);
2271 lp->chipset = device;
2273 /* Get the board I/O address (64 bits on sparc64) */
2274 iobase = pci_resource_start(pdev, 0);
2276 /* Fetch the IRQ to be used */
2278 if ((irq == 0) || (irq == 0xff) || ((int)irq == -1)) {
2283 /* Check if I/O accesses and Bus Mastering are enabled */
2284 pci_read_config_word(pdev, PCI_COMMAND, &status);
2286 if (!(status & PCI_COMMAND_IO)) {
2287 status |= PCI_COMMAND_IO;
2288 pci_write_config_word(pdev, PCI_COMMAND, status);
2289 pci_read_config_word(pdev, PCI_COMMAND, &status);
2291 #endif /* __powerpc__ */
2292 if (!(status & PCI_COMMAND_IO)) {
2297 if (!(status & PCI_COMMAND_MASTER)) {
2298 status |= PCI_COMMAND_MASTER;
2299 pci_write_config_word(pdev, PCI_COMMAND, status);
2300 pci_read_config_word(pdev, PCI_COMMAND, &status);
2302 if (!(status & PCI_COMMAND_MASTER)) {
2307 /* Check the latency timer for values >= 0x60 */
2308 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &timer);
2310 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x60);
2313 DevicePresent(dev, DE4X5_APROM);
2315 if (!request_region (iobase, DE4X5_PCI_TOTAL_SIZE, "de4x5")) {
2322 if ((error = de4x5_hw_init(dev, iobase, &pdev->dev))) {
2329 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2333 pci_disable_device (pdev);
2337 static void __devexit de4x5_pci_remove (struct pci_dev *pdev)
2339 struct net_device *dev;
2342 dev = pdev->dev.driver_data;
2343 iobase = dev->base_addr;
2345 unregister_netdev (dev);
2347 release_region (iobase, DE4X5_PCI_TOTAL_SIZE);
2348 pci_disable_device (pdev);
2351 static struct pci_device_id de4x5_pci_tbl[] = {
2352 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP,
2353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
2354 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_PLUS,
2355 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
2356 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TULIP_FAST,
2357 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
2358 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142,
2359 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
2363 static struct pci_driver de4x5_pci_driver = {
2365 .id_table = de4x5_pci_tbl,
2366 .probe = de4x5_pci_probe,
2367 .remove = __devexit_p (de4x5_pci_remove),
2373 ** Auto configure the media here rather than setting the port at compile
2374 ** time. This routine is called by de4x5_init() and when a loss of media is
2375 ** detected (excessive collisions, loss of carrier, no carrier or link fail
2376 ** [TP] or no recent receive activity) to check whether the user has been
2377 ** sneaky and changed the port on us.
2380 autoconf_media(struct net_device *dev)
2382 struct de4x5_private *lp = netdev_priv(dev);
2383 u_long iobase = dev->base_addr;
2384 int next_tick = DE4X5_AUTOSENSE_MS;
2387 lp->c_media = AUTO; /* Bogus last media */
2389 inl(DE4X5_MFC); /* Zero the lost frames counter */
2394 next_tick = srom_autoconf(dev);
2395 } else if (lp->chipset == DC21040) {
2396 next_tick = dc21040_autoconf(dev);
2397 } else if (lp->chipset == DC21041) {
2398 next_tick = dc21041_autoconf(dev);
2399 } else if (lp->chipset == DC21140) {
2400 next_tick = dc21140m_autoconf(dev);
2403 enable_ast(dev, next_tick);
2409 ** Autoconfigure the media when using the DC21040. AUI cannot be distinguished
2410 ** from BNC as the port has a jumper to set thick or thin wire. When set for
2411 ** BNC, the BNC port will indicate activity if it's not terminated correctly.
2412 ** The only way to test for that is to place a loopback packet onto the
2413 ** network and watch for errors. Since we're messing with the interrupt mask
2414 ** register, disable the board interrupts and do not allow any more packets to
2415 ** be queued to the hardware. Re-enable everything only when the media is
2417 ** I may have to "age out" locally queued packets so that the higher layer
2418 ** timeouts don't effectively duplicate packets on the network.
2421 dc21040_autoconf(struct net_device *dev)
2423 struct de4x5_private *lp = netdev_priv(dev);
2424 u_long iobase = dev->base_addr;
2425 int next_tick = DE4X5_AUTOSENSE_MS;
2428 switch (lp->media) {
2433 de4x5_save_skbs(dev);
2434 if ((lp->autosense == AUTO) || (lp->autosense == TP)) {
2436 } else if ((lp->autosense == BNC) || (lp->autosense == AUI) || (lp->autosense == BNC_AUI)) {
2437 lp->media = BNC_AUI;
2438 } else if (lp->autosense == EXT_SIA) {
2439 lp->media = EXT_SIA;
2443 lp->local_state = 0;
2444 next_tick = dc21040_autoconf(dev);
2448 next_tick = dc21040_state(dev, 0x8f01, 0xffff, 0x0000, 3000, BNC_AUI,
2449 TP_SUSPECT, test_tp);
2453 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21040_autoconf);
2459 next_tick = dc21040_state(dev, 0x8f09, 0x0705, 0x0006, 3000, EXT_SIA,
2460 BNC_AUI_SUSPECT, ping_media);
2463 case BNC_AUI_SUSPECT:
2464 next_tick = de4x5_suspect_state(dev, 1000, BNC_AUI, ping_media, dc21040_autoconf);
2468 next_tick = dc21040_state(dev, 0x3041, 0x0000, 0x0006, 3000,
2469 NC, EXT_SIA_SUSPECT, ping_media);
2472 case EXT_SIA_SUSPECT:
2473 next_tick = de4x5_suspect_state(dev, 1000, EXT_SIA, ping_media, dc21040_autoconf);
2477 /* default to TP for all */
2478 reset_init_sia(dev, 0x8f01, 0xffff, 0x0000);
2479 if (lp->media != lp->c_media) {
2480 de4x5_dbg_media(dev);
2481 lp->c_media = lp->media;
2492 dc21040_state(struct net_device *dev, int csr13, int csr14, int csr15, int timeout,
2493 int next_state, int suspect_state,
2494 int (*fn)(struct net_device *, int))
2496 struct de4x5_private *lp = netdev_priv(dev);
2497 int next_tick = DE4X5_AUTOSENSE_MS;
2500 switch (lp->local_state) {
2502 reset_init_sia(dev, csr13, csr14, csr15);
2508 if (!lp->tx_enable) {
2509 linkBad = fn(dev, timeout);
2511 next_tick = linkBad & ~TIMER_CB;
2513 if (linkBad && (lp->autosense == AUTO)) {
2514 lp->local_state = 0;
2515 lp->media = next_state;
2517 de4x5_init_connection(dev);
2520 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2521 lp->media = suspect_state;
2531 de4x5_suspect_state(struct net_device *dev, int timeout, int prev_state,
2532 int (*fn)(struct net_device *, int),
2533 int (*asfn)(struct net_device *))
2535 struct de4x5_private *lp = netdev_priv(dev);
2536 int next_tick = DE4X5_AUTOSENSE_MS;
2539 switch (lp->local_state) {
2542 lp->media = prev_state;
2545 next_tick = asfn(dev);
2550 linkBad = fn(dev, timeout);
2552 next_tick = linkBad & ~TIMER_CB;
2553 } else if (!linkBad) {
2555 lp->media = prev_state;
2566 ** Autoconfigure the media when using the DC21041. AUI needs to be tested
2567 ** before BNC, because the BNC port will indicate activity if it's not
2568 ** terminated correctly. The only way to test for that is to place a loopback
2569 ** packet onto the network and watch for errors. Since we're messing with
2570 ** the interrupt mask register, disable the board interrupts and do not allow
2571 ** any more packets to be queued to the hardware. Re-enable everything only
2572 ** when the media is found.
2575 dc21041_autoconf(struct net_device *dev)
2577 struct de4x5_private *lp = netdev_priv(dev);
2578 u_long iobase = dev->base_addr;
2579 s32 sts, irqs, irq_mask, imr, omr;
2580 int next_tick = DE4X5_AUTOSENSE_MS;
2582 switch (lp->media) {
2587 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2588 if ((lp->autosense == AUTO) || (lp->autosense == TP_NW)) {
2589 lp->media = TP; /* On chip auto negotiation is broken */
2590 } else if (lp->autosense == TP) {
2592 } else if (lp->autosense == BNC) {
2594 } else if (lp->autosense == AUI) {
2599 lp->local_state = 0;
2600 next_tick = dc21041_autoconf(dev);
2604 if (lp->timeout < 0) {
2605 omr = inl(DE4X5_OMR);/* Set up full duplex for the autonegotiate */
2606 outl(omr | OMR_FDX, DE4X5_OMR);
2608 irqs = STS_LNF | STS_LNP;
2609 irq_mask = IMR_LFM | IMR_LPM;
2610 sts = test_media(dev, irqs, irq_mask, 0xef01, 0xffff, 0x0008, 2400);
2612 next_tick = sts & ~TIMER_CB;
2614 if (sts & STS_LNP) {
2619 next_tick = dc21041_autoconf(dev);
2624 if (!lp->tx_enable) {
2627 sts = test_ans(dev, irqs, irq_mask, 3000);
2629 next_tick = sts & ~TIMER_CB;
2631 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2633 next_tick = dc21041_autoconf(dev);
2635 lp->local_state = 1;
2636 de4x5_init_connection(dev);
2639 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2640 lp->media = ANS_SUSPECT;
2646 next_tick = de4x5_suspect_state(dev, 1000, ANS, test_tp, dc21041_autoconf);
2650 if (!lp->tx_enable) {
2651 if (lp->timeout < 0) {
2652 omr = inl(DE4X5_OMR); /* Set up half duplex for TP */
2653 outl(omr & ~OMR_FDX, DE4X5_OMR);
2655 irqs = STS_LNF | STS_LNP;
2656 irq_mask = IMR_LFM | IMR_LPM;
2657 sts = test_media(dev,irqs, irq_mask, 0xef01, 0xff3f, 0x0008, 2400);
2659 next_tick = sts & ~TIMER_CB;
2661 if (!(sts & STS_LNP) && (lp->autosense == AUTO)) {
2662 if (inl(DE4X5_SISR) & SISR_NRA) {
2663 lp->media = AUI; /* Non selected port activity */
2667 next_tick = dc21041_autoconf(dev);
2669 lp->local_state = 1;
2670 de4x5_init_connection(dev);
2673 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2674 lp->media = TP_SUSPECT;
2680 next_tick = de4x5_suspect_state(dev, 1000, TP, test_tp, dc21041_autoconf);
2684 if (!lp->tx_enable) {
2685 if (lp->timeout < 0) {
2686 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
2687 outl(omr & ~OMR_FDX, DE4X5_OMR);
2691 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x000e, 1000);
2693 next_tick = sts & ~TIMER_CB;
2695 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
2697 next_tick = dc21041_autoconf(dev);
2699 lp->local_state = 1;
2700 de4x5_init_connection(dev);
2703 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2704 lp->media = AUI_SUSPECT;
2710 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc21041_autoconf);
2714 switch (lp->local_state) {
2716 if (lp->timeout < 0) {
2717 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
2718 outl(omr & ~OMR_FDX, DE4X5_OMR);
2722 sts = test_media(dev,irqs, irq_mask, 0xef09, 0xf73d, 0x0006, 1000);
2724 next_tick = sts & ~TIMER_CB;
2726 lp->local_state++; /* Ensure media connected */
2727 next_tick = dc21041_autoconf(dev);
2732 if (!lp->tx_enable) {
2733 if ((sts = ping_media(dev, 3000)) < 0) {
2734 next_tick = sts & ~TIMER_CB;
2737 lp->local_state = 0;
2740 de4x5_init_connection(dev);
2743 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
2744 lp->media = BNC_SUSPECT;
2752 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc21041_autoconf);
2756 omr = inl(DE4X5_OMR); /* Set up full duplex for the autonegotiate */
2757 outl(omr | OMR_FDX, DE4X5_OMR);
2758 reset_init_sia(dev, 0xef01, 0xffff, 0x0008);/* Initialise the SIA */
2759 if (lp->media != lp->c_media) {
2760 de4x5_dbg_media(dev);
2761 lp->c_media = lp->media;
2772 ** Some autonegotiation chips are broken in that they do not return the
2773 ** acknowledge bit (anlpa & MII_ANLPA_ACK) in the link partner advertisement
2774 ** register, except at the first power up negotiation.
2777 dc21140m_autoconf(struct net_device *dev)
2779 struct de4x5_private *lp = netdev_priv(dev);
2780 int ana, anlpa, cap, cr, slnk, sr;
2781 int next_tick = DE4X5_AUTOSENSE_MS;
2782 u_long imr, omr, iobase = dev->base_addr;
2786 if (lp->timeout < 0) {
2788 lp->tx_enable = FALSE;
2790 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2792 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2793 next_tick &= ~TIMER_CB;
2796 if (srom_map_media(dev) < 0) {
2800 srom_exec(dev, lp->phy[lp->active].gep);
2801 if (lp->infoblock_media == ANS) {
2802 ana = lp->phy[lp->active].ana | MII_ANA_CSMA;
2803 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2806 lp->tmp = MII_SR_ASSC; /* Fake out the MII speed set */
2808 if (lp->autosense == _100Mb) {
2810 } else if (lp->autosense == _10Mb) {
2812 } else if ((lp->autosense == AUTO) &&
2813 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
2814 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
2815 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
2816 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2818 } else if (lp->autosense == AUTO) {
2819 lp->media = SPD_DET;
2820 } else if (is_spd_100(dev) && is_100_up(dev)) {
2826 lp->local_state = 0;
2827 next_tick = dc21140m_autoconf(dev);
2832 switch (lp->local_state) {
2834 if (lp->timeout < 0) {
2835 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
2837 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
2839 next_tick = cr & ~TIMER_CB;
2842 lp->local_state = 0;
2843 lp->media = SPD_DET;
2847 next_tick = dc21140m_autoconf(dev);
2852 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
2853 next_tick = sr & ~TIMER_CB;
2855 lp->media = SPD_DET;
2856 lp->local_state = 0;
2857 if (sr) { /* Success! */
2858 lp->tmp = MII_SR_ASSC;
2859 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
2860 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
2861 if (!(anlpa & MII_ANLPA_RF) &&
2862 (cap = anlpa & MII_ANLPA_TAF & ana)) {
2863 if (cap & MII_ANA_100M) {
2864 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
2866 } else if (cap & MII_ANA_10M) {
2867 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
2872 } /* Auto Negotiation failed to finish */
2873 next_tick = dc21140m_autoconf(dev);
2874 } /* Auto Negotiation failed to start */
2879 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
2880 if (lp->timeout < 0) {
2881 lp->tmp = (lp->phy[lp->active].id ? MII_SR_LKS :
2882 (~gep_rd(dev) & GEP_LNP));
2885 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
2886 next_tick = slnk & ~TIMER_CB;
2888 if (is_spd_100(dev) && is_100_up(dev)) {
2890 } else if ((!is_spd_100(dev) && (is_10_up(dev) & lp->tmp))) {
2895 next_tick = dc21140m_autoconf(dev);
2899 case _100Mb: /* Set 100Mb/s */
2901 if (!lp->tx_enable) {
2903 de4x5_init_connection(dev);
2905 if (!lp->linkOK && (lp->autosense == AUTO)) {
2906 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
2909 next_tick = DE4X5_AUTOSENSE_MS;
2917 case _10Mb: /* Set 10Mb/s */
2919 if (!lp->tx_enable) {
2921 de4x5_init_connection(dev);
2923 if (!lp->linkOK && (lp->autosense == AUTO)) {
2924 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
2927 next_tick = DE4X5_AUTOSENSE_MS;
2934 if (lp->media != lp->c_media) {
2935 de4x5_dbg_media(dev);
2936 lp->c_media = lp->media;
2939 lp->tx_enable = FALSE;
2947 ** This routine may be merged into dc21140m_autoconf() sometime as I'm
2948 ** changing how I figure out the media - but trying to keep it backwards
2949 ** compatible with the de500-xa and de500-aa.
2950 ** Whether it's BNC, AUI, SYM or MII is sorted out in the infoblock
2951 ** functions and set during de4x5_mac_port() and/or de4x5_reset_phy().
2952 ** This routine just has to figure out whether 10Mb/s or 100Mb/s is
2954 ** When autonegotiation is working, the ANS part searches the SROM for
2955 ** the highest common speed (TP) link that both can run and if that can
2956 ** be full duplex. That infoblock is executed and then the link speed set.
2958 ** Only _10Mb and _100Mb are tested here.
2961 dc2114x_autoconf(struct net_device *dev)
2963 struct de4x5_private *lp = netdev_priv(dev);
2964 u_long iobase = dev->base_addr;
2965 s32 cr, anlpa, ana, cap, irqs, irq_mask, imr, omr, slnk, sr, sts;
2966 int next_tick = DE4X5_AUTOSENSE_MS;
2968 switch (lp->media) {
2970 if (lp->timeout < 0) {
2972 lp->tx_enable = FALSE;
2975 de4x5_save_skbs(dev); /* Save non transmitted skb's */
2976 if (lp->params.autosense & ~AUTO) {
2977 srom_map_media(dev); /* Fixed media requested */
2978 if (lp->media != lp->params.autosense) {
2986 if ((next_tick = de4x5_reset_phy(dev)) < 0) {
2987 next_tick &= ~TIMER_CB;
2989 if (lp->autosense == _100Mb) {
2991 } else if (lp->autosense == _10Mb) {
2993 } else if (lp->autosense == TP) {
2995 } else if (lp->autosense == BNC) {
2997 } else if (lp->autosense == AUI) {
3000 lp->media = SPD_DET;
3001 if ((lp->infoblock_media == ANS) &&
3002 ((sr=is_anc_capable(dev)) & MII_SR_ANC)) {
3003 ana = (((sr >> 6) & MII_ANA_TAF) | MII_ANA_CSMA);
3004 ana &= (lp->fdx ? ~0 : ~MII_ANA_FDAM);
3005 mii_wr(ana, MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3009 lp->local_state = 0;
3010 next_tick = dc2114x_autoconf(dev);
3015 switch (lp->local_state) {
3017 if (lp->timeout < 0) {
3018 mii_wr(MII_CR_ASSE | MII_CR_RAN, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3020 cr = test_mii_reg(dev, MII_CR, MII_CR_RAN, FALSE, 500);
3022 next_tick = cr & ~TIMER_CB;
3025 lp->local_state = 0;
3026 lp->media = SPD_DET;
3030 next_tick = dc2114x_autoconf(dev);
3035 if ((sr=test_mii_reg(dev, MII_SR, MII_SR_ASSC, TRUE, 2000)) < 0) {
3036 next_tick = sr & ~TIMER_CB;
3038 lp->media = SPD_DET;
3039 lp->local_state = 0;
3040 if (sr) { /* Success! */
3041 lp->tmp = MII_SR_ASSC;
3042 anlpa = mii_rd(MII_ANLPA, lp->phy[lp->active].addr, DE4X5_MII);
3043 ana = mii_rd(MII_ANA, lp->phy[lp->active].addr, DE4X5_MII);
3044 if (!(anlpa & MII_ANLPA_RF) &&
3045 (cap = anlpa & MII_ANLPA_TAF & ana)) {
3046 if (cap & MII_ANA_100M) {
3047 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_100M) ? TRUE : FALSE);
3049 } else if (cap & MII_ANA_10M) {
3050 lp->fdx = ((ana & anlpa & MII_ANA_FDAM & MII_ANA_10M) ? TRUE : FALSE);
3054 } /* Auto Negotiation failed to finish */
3055 next_tick = dc2114x_autoconf(dev);
3056 } /* Auto Negotiation failed to start */
3062 if (!lp->tx_enable) {
3063 if (lp->timeout < 0) {
3064 omr = inl(DE4X5_OMR); /* Set up half duplex for AUI */
3065 outl(omr & ~OMR_FDX, DE4X5_OMR);
3069 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3071 next_tick = sts & ~TIMER_CB;
3073 if (!(inl(DE4X5_SISR) & SISR_SRA) && (lp->autosense == AUTO)) {
3075 next_tick = dc2114x_autoconf(dev);
3077 lp->local_state = 1;
3078 de4x5_init_connection(dev);
3081 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3082 lp->media = AUI_SUSPECT;
3088 next_tick = de4x5_suspect_state(dev, 1000, AUI, ping_media, dc2114x_autoconf);
3092 switch (lp->local_state) {
3094 if (lp->timeout < 0) {
3095 omr = inl(DE4X5_OMR); /* Set up half duplex for BNC */
3096 outl(omr & ~OMR_FDX, DE4X5_OMR);
3100 sts = test_media(dev,irqs, irq_mask, 0, 0, 0, 1000);
3102 next_tick = sts & ~TIMER_CB;
3104 lp->local_state++; /* Ensure media connected */
3105 next_tick = dc2114x_autoconf(dev);
3110 if (!lp->tx_enable) {
3111 if ((sts = ping_media(dev, 3000)) < 0) {
3112 next_tick = sts & ~TIMER_CB;
3115 lp->local_state = 0;
3119 de4x5_init_connection(dev);
3122 } else if (!lp->linkOK && (lp->autosense == AUTO)) {
3123 lp->media = BNC_SUSPECT;
3131 next_tick = de4x5_suspect_state(dev, 1000, BNC, ping_media, dc2114x_autoconf);
3134 case SPD_DET: /* Choose 10Mb/s or 100Mb/s */
3135 if (srom_map_media(dev) < 0) {
3140 if (lp->media == _100Mb) {
3141 if ((slnk = test_for_100Mb(dev, 6500)) < 0) {
3142 lp->media = SPD_DET;
3143 return (slnk & ~TIMER_CB);
3146 if (wait_for_link(dev) < 0) {
3147 lp->media = SPD_DET;
3148 return PDET_LINK_WAIT;
3151 if (lp->media == ANS) { /* Do MII parallel detection */
3152 if (is_spd_100(dev)) {
3157 next_tick = dc2114x_autoconf(dev);
3158 } else if (((lp->media == _100Mb) && is_100_up(dev)) ||
3159 (((lp->media == _10Mb) || (lp->media == TP) ||
3160 (lp->media == BNC) || (lp->media == AUI)) &&
3162 next_tick = dc2114x_autoconf(dev);
3171 if (!lp->tx_enable) {
3173 de4x5_init_connection(dev);
3175 if (!lp->linkOK && (lp->autosense == AUTO)) {
3176 if (!is_10_up(dev) || (!lp->useSROM && is_spd_100(dev))) {
3179 next_tick = DE4X5_AUTOSENSE_MS;
3187 if (!lp->tx_enable) {
3189 de4x5_init_connection(dev);
3191 if (!lp->linkOK && (lp->autosense == AUTO)) {
3192 if (!is_100_up(dev) || (!lp->useSROM && !is_spd_100(dev))) {
3195 next_tick = DE4X5_AUTOSENSE_MS;
3203 printk("Huh?: media:%02x\n", lp->media);
3212 srom_autoconf(struct net_device *dev)
3214 struct de4x5_private *lp = netdev_priv(dev);
3216 return lp->infoleaf_fn(dev);
3220 ** This mapping keeps the original media codes and FDX flag unchanged.
3221 ** While it isn't strictly necessary, it helps me for the moment...
3222 ** The early return avoids a media state / SROM media space clash.
3225 srom_map_media(struct net_device *dev)
3227 struct de4x5_private *lp = netdev_priv(dev);
3230 if (lp->infoblock_media == lp->media)
3233 switch(lp->infoblock_media) {
3235 if (!lp->params.fdx) return -1;
3238 if (lp->params.fdx && !lp->fdx) return -1;
3239 if ((lp->chipset == DC21140) || ((lp->chipset & ~0x00ff) == DC2114x)) {
3254 case SROM_100BASETF:
3255 if (!lp->params.fdx) return -1;
3258 if (lp->params.fdx && !lp->fdx) return -1;
3262 case SROM_100BASET4:
3266 case SROM_100BASEFF:
3267 if (!lp->params.fdx) return -1;
3270 if (lp->params.fdx && !lp->fdx) return -1;
3276 lp->fdx = lp->params.fdx;
3280 printk("%s: Bad media code [%d] detected in SROM!\n", dev->name,
3281 lp->infoblock_media);
3290 de4x5_init_connection(struct net_device *dev)
3292 struct de4x5_private *lp = netdev_priv(dev);
3293 u_long iobase = dev->base_addr;
3296 if (lp->media != lp->c_media) {
3297 de4x5_dbg_media(dev);
3298 lp->c_media = lp->media; /* Stop scrolling media messages */
3301 spin_lock_irqsave(&lp->lock, flags);
3302 de4x5_rst_desc_ring(dev);
3303 de4x5_setup_intr(dev);
3304 lp->tx_enable = YES;
3305 spin_unlock_irqrestore(&lp->lock, flags);
3306 outl(POLL_DEMAND, DE4X5_TPD);
3308 netif_wake_queue(dev);
3314 ** General PHY reset function. Some MII devices don't reset correctly
3315 ** since their MII address pins can float at voltages that are dependent
3316 ** on the signal pin use. Do a double reset to ensure a reset.
3319 de4x5_reset_phy(struct net_device *dev)
3321 struct de4x5_private *lp = netdev_priv(dev);
3322 u_long iobase = dev->base_addr;
3325 if ((lp->useSROM) || (lp->phy[lp->active].id)) {
3326 if (lp->timeout < 0) {
3328 if (lp->phy[lp->active].rst) {
3329 srom_exec(dev, lp->phy[lp->active].rst);
3330 srom_exec(dev, lp->phy[lp->active].rst);
3331 } else if (lp->rst) { /* Type 5 infoblock reset */
3332 srom_exec(dev, lp->rst);
3333 srom_exec(dev, lp->rst);
3339 mii_wr(MII_CR_RST, MII_CR, lp->phy[lp->active].addr, DE4X5_MII);
3343 next_tick = test_mii_reg(dev, MII_CR, MII_CR_RST, FALSE, 500);
3345 } else if (lp->chipset == DC21140) {
3353 test_media(struct net_device *dev, s32 irqs, s32 irq_mask, s32 csr13, s32 csr14, s32 csr15, s32 msec)
3355 struct de4x5_private *lp = netdev_priv(dev);
3356 u_long iobase = dev->base_addr;
3359 if (lp->timeout < 0) {
3360 lp->timeout = msec/100;
3361 if (!lp->useSROM) { /* Already done if by SROM, else dc2104[01] */
3362 reset_init_sia(dev, csr13, csr14, csr15);
3365 /* set up the interrupt mask */
3366 outl(irq_mask, DE4X5_IMR);
3368 /* clear all pending interrupts */
3369 sts = inl(DE4X5_STS);
3370 outl(sts, DE4X5_STS);
3372 /* clear csr12 NRA and SRA bits */
3373 if ((lp->chipset == DC21041) || lp->useSROM) {
3374 csr12 = inl(DE4X5_SISR);
3375 outl(csr12, DE4X5_SISR);
3379 sts = inl(DE4X5_STS) & ~TIMER_CB;
3381 if (!(sts & irqs) && --lp->timeout) {
3382 sts = 100 | TIMER_CB;
3391 test_tp(struct net_device *dev, s32 msec)
3393 struct de4x5_private *lp = netdev_priv(dev);
3394 u_long iobase = dev->base_addr;
3397 if (lp->timeout < 0) {
3398 lp->timeout = msec/100;
3401 sisr = (inl(DE4X5_SISR) & ~TIMER_CB) & (SISR_LKF | SISR_NCR);
3403 if (sisr && --lp->timeout) {
3404 sisr = 100 | TIMER_CB;
3413 ** Samples the 100Mb Link State Signal. The sample interval is important
3414 ** because too fast a rate can give erroneous results and confuse the
3415 ** speed sense algorithm.
3417 #define SAMPLE_INTERVAL 500 /* ms */
3418 #define SAMPLE_DELAY 2000 /* ms */
3420 test_for_100Mb(struct net_device *dev, int msec)
3422 struct de4x5_private *lp = netdev_priv(dev);
3423 int gep = 0, ret = ((lp->chipset & ~0x00ff)==DC2114x? -1 :GEP_SLNK);
3425 if (lp->timeout < 0) {
3426 if ((msec/SAMPLE_INTERVAL) <= 0) return 0;
3427 if (msec > SAMPLE_DELAY) {
3428 lp->timeout = (msec - SAMPLE_DELAY)/SAMPLE_INTERVAL;
3429 gep = SAMPLE_DELAY | TIMER_CB;
3432 lp->timeout = msec/SAMPLE_INTERVAL;
3436 if (lp->phy[lp->active].id || lp->useSROM) {
3437 gep = is_100_up(dev) | is_spd_100(dev);
3439 gep = (~gep_rd(dev) & (GEP_SLNK | GEP_LNP));
3441 if (!(gep & ret) && --lp->timeout) {
3442 gep = SAMPLE_INTERVAL | TIMER_CB;
3451 wait_for_link(struct net_device *dev)
3453 struct de4x5_private *lp = netdev_priv(dev);
3455 if (lp->timeout < 0) {
3459 if (lp->timeout--) {
3473 test_mii_reg(struct net_device *dev, int reg, int mask, int pol, long msec)
3475 struct de4x5_private *lp = netdev_priv(dev);
3477 u_long iobase = dev->base_addr;
3479 if (lp->timeout < 0) {
3480 lp->timeout = msec/100;
3484 reg = mii_rd((u_char)reg, lp->phy[lp->active].addr, DE4X5_MII) & mask;
3485 test = (reg ^ pol) & mask;
3487 if (test && --lp->timeout) {
3488 reg = 100 | TIMER_CB;
3497 is_spd_100(struct net_device *dev)
3499 struct de4x5_private *lp = netdev_priv(dev);
3500 u_long iobase = dev->base_addr;
3504 spd = mii_rd(lp->phy[lp->active].spd.reg, lp->phy[lp->active].addr, DE4X5_MII);
3505 spd = ~(spd ^ lp->phy[lp->active].spd.value);
3506 spd &= lp->phy[lp->active].spd.mask;
3507 } else if (!lp->useSROM) { /* de500-xa */
3508 spd = ((~gep_rd(dev)) & GEP_SLNK);
3510 if ((lp->ibn == 2) || !lp->asBitValid)
3511 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3513 spd = (lp->asBitValid & (lp->asPolarity ^ (gep_rd(dev) & lp->asBit))) |
3514 (lp->linkOK & ~lp->asBitValid);
3521 is_100_up(struct net_device *dev)
3523 struct de4x5_private *lp = netdev_priv(dev);
3524 u_long iobase = dev->base_addr;
3527 /* Double read for sticky bits & temporary drops */
3528 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3529 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3530 } else if (!lp->useSROM) { /* de500-xa */
3531 return ((~gep_rd(dev)) & GEP_SLNK);
3533 if ((lp->ibn == 2) || !lp->asBitValid)
3534 return ((lp->chipset == DC21143)?(~inl(DE4X5_SISR)&SISR_LS100):0);
3536 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3537 (lp->linkOK & ~lp->asBitValid));
3542 is_10_up(struct net_device *dev)
3544 struct de4x5_private *lp = netdev_priv(dev);
3545 u_long iobase = dev->base_addr;
3548 /* Double read for sticky bits & temporary drops */
3549 mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII);
3550 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII) & MII_SR_LKS);
3551 } else if (!lp->useSROM) { /* de500-xa */
3552 return ((~gep_rd(dev)) & GEP_LNP);
3554 if ((lp->ibn == 2) || !lp->asBitValid)
3555 return (((lp->chipset & ~0x00ff) == DC2114x) ?
3556 (~inl(DE4X5_SISR)&SISR_LS10):
3559 return ((lp->asBitValid&(lp->asPolarity^(gep_rd(dev)&lp->asBit))) |
3560 (lp->linkOK & ~lp->asBitValid));
3565 is_anc_capable(struct net_device *dev)
3567 struct de4x5_private *lp = netdev_priv(dev);
3568 u_long iobase = dev->base_addr;
3570 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
3571 return (mii_rd(MII_SR, lp->phy[lp->active].addr, DE4X5_MII));
3572 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
3573 return (inl(DE4X5_SISR) & SISR_LPN) >> 12;
3580 ** Send a packet onto the media and watch for send errors that indicate the
3581 ** media is bad or unconnected.
3584 ping_media(struct net_device *dev, int msec)
3586 struct de4x5_private *lp = netdev_priv(dev);
3587 u_long iobase = dev->base_addr;
3590 if (lp->timeout < 0) {
3591 lp->timeout = msec/100;
3593 lp->tmp = lp->tx_new; /* Remember the ring position */
3594 load_packet(dev, lp->frame, TD_LS | TD_FS | sizeof(lp->frame), (struct sk_buff *)1);
3595 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
3596 outl(POLL_DEMAND, DE4X5_TPD);
3599 sisr = inl(DE4X5_SISR);
3601 if ((!(sisr & SISR_NCR)) &&
3602 ((s32)le32_to_cpu(lp->tx_ring[lp->tmp].status) < 0) &&
3604 sisr = 100 | TIMER_CB;
3606 if ((!(sisr & SISR_NCR)) &&
3607 !(le32_to_cpu(lp->tx_ring[lp->tmp].status) & (T_OWN | TD_ES)) &&
3620 ** This function does 2 things: on Intels it kmalloc's another buffer to
3621 ** replace the one about to be passed up. On Alpha's it kmallocs a buffer
3622 ** into which the packet is copied.
3624 static struct sk_buff *
3625 de4x5_alloc_rx_buff(struct net_device *dev, int index, int len)
3627 struct de4x5_private *lp = netdev_priv(dev);
3630 #if !defined(__alpha__) && !defined(__powerpc__) && !defined(__sparc_v9__) && !defined(DE4X5_DO_MEMCPY)
3631 struct sk_buff *ret;
3634 p = dev_alloc_skb(IEEE802_3_SZ + DE4X5_ALIGN + 2);
3635 if (!p) return NULL;
3637 tmp = virt_to_bus(p->data);
3638 i = ((tmp + DE4X5_ALIGN) & ~DE4X5_ALIGN) - tmp;
3640 lp->rx_ring[index].buf = cpu_to_le32(tmp + i);
3642 ret = lp->rx_skb[index];
3643 lp->rx_skb[index] = p;
3645 if ((u_long) ret > 1) {
3652 if (lp->state != OPEN) return (struct sk_buff *)1; /* Fake out the open */
3654 p = dev_alloc_skb(len + 2);
3655 if (!p) return NULL;
3657 skb_reserve(p, 2); /* Align */
3658 if (index < lp->rx_old) { /* Wrapped buffer */
3659 short tlen = (lp->rxRingSize - lp->rx_old) * RX_BUFF_SZ;
3660 memcpy(skb_put(p,tlen),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,tlen);
3661 memcpy(skb_put(p,len-tlen),lp->rx_bufs,len-tlen);
3662 } else { /* Linear buffer */
3663 memcpy(skb_put(p,len),lp->rx_bufs + lp->rx_old * RX_BUFF_SZ,len);
3671 de4x5_free_rx_buffs(struct net_device *dev)
3673 struct de4x5_private *lp = netdev_priv(dev);
3676 for (i=0; i<lp->rxRingSize; i++) {
3677 if ((u_long) lp->rx_skb[i] > 1) {
3678 dev_kfree_skb(lp->rx_skb[i]);
3680 lp->rx_ring[i].status = 0;
3681 lp->rx_skb[i] = (struct sk_buff *)1; /* Dummy entry */
3688 de4x5_free_tx_buffs(struct net_device *dev)
3690 struct de4x5_private *lp = netdev_priv(dev);
3693 for (i=0; i<lp->txRingSize; i++) {
3695 de4x5_free_tx_buff(lp, i);
3696 lp->tx_ring[i].status = 0;
3699 /* Unload the locally queued packets */
3700 while (lp->cache.skb) {
3701 dev_kfree_skb(de4x5_get_cache(dev));
3708 ** When a user pulls a connection, the DECchip can end up in a
3709 ** 'running - waiting for end of transmission' state. This means that we
3710 ** have to perform a chip soft reset to ensure that we can synchronize
3711 ** the hardware and software and make any media probes using a loopback
3712 ** packet meaningful.
3715 de4x5_save_skbs(struct net_device *dev)
3717 struct de4x5_private *lp = netdev_priv(dev);
3718 u_long iobase = dev->base_addr;
3721 if (!lp->cache.save_cnt) {
3723 de4x5_tx(dev); /* Flush any sent skb's */
3724 de4x5_free_tx_buffs(dev);
3725 de4x5_cache_state(dev, DE4X5_SAVE_STATE);
3726 de4x5_sw_reset(dev);
3727 de4x5_cache_state(dev, DE4X5_RESTORE_STATE);
3728 lp->cache.save_cnt++;
3736 de4x5_rst_desc_ring(struct net_device *dev)
3738 struct de4x5_private *lp = netdev_priv(dev);
3739 u_long iobase = dev->base_addr;
3743 if (lp->cache.save_cnt) {
3745 outl(lp->dma_rings, DE4X5_RRBA);
3746 outl(lp->dma_rings + NUM_RX_DESC * sizeof(struct de4x5_desc),
3749 lp->rx_new = lp->rx_old = 0;
3750 lp->tx_new = lp->tx_old = 0;
3752 for (i = 0; i < lp->rxRingSize; i++) {
3753 lp->rx_ring[i].status = cpu_to_le32(R_OWN);
3756 for (i = 0; i < lp->txRingSize; i++) {
3757 lp->tx_ring[i].status = cpu_to_le32(0);
3761 lp->cache.save_cnt--;
3769 de4x5_cache_state(struct net_device *dev, int flag)
3771 struct de4x5_private *lp = netdev_priv(dev);
3772 u_long iobase = dev->base_addr;
3775 case DE4X5_SAVE_STATE:
3776 lp->cache.csr0 = inl(DE4X5_BMR);
3777 lp->cache.csr6 = (inl(DE4X5_OMR) & ~(OMR_ST | OMR_SR));
3778 lp->cache.csr7 = inl(DE4X5_IMR);
3781 case DE4X5_RESTORE_STATE:
3782 outl(lp->cache.csr0, DE4X5_BMR);
3783 outl(lp->cache.csr6, DE4X5_OMR);
3784 outl(lp->cache.csr7, DE4X5_IMR);
3785 if (lp->chipset == DC21140) {
3786 gep_wr(lp->cache.gepc, dev);
3787 gep_wr(lp->cache.gep, dev);
3789 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14,
3799 de4x5_put_cache(struct net_device *dev, struct sk_buff *skb)
3801 struct de4x5_private *lp = netdev_priv(dev);
3804 if (lp->cache.skb) {
3805 for (p=lp->cache.skb; p->next; p=p->next);
3808 lp->cache.skb = skb;
3816 de4x5_putb_cache(struct net_device *dev, struct sk_buff *skb)
3818 struct de4x5_private *lp = netdev_priv(dev);
3819 struct sk_buff *p = lp->cache.skb;
3821 lp->cache.skb = skb;
3827 static struct sk_buff *
3828 de4x5_get_cache(struct net_device *dev)
3830 struct de4x5_private *lp = netdev_priv(dev);
3831 struct sk_buff *p = lp->cache.skb;
3834 lp->cache.skb = p->next;
3842 ** Check the Auto Negotiation State. Return OK when a link pass interrupt
3843 ** is received and the auto-negotiation status is NWAY OK.
3846 test_ans(struct net_device *dev, s32 irqs, s32 irq_mask, s32 msec)
3848 struct de4x5_private *lp = netdev_priv(dev);
3849 u_long iobase = dev->base_addr;
3852 if (lp->timeout < 0) {
3853 lp->timeout = msec/100;
3854 outl(irq_mask, DE4X5_IMR);
3856 /* clear all pending interrupts */
3857 sts = inl(DE4X5_STS);
3858 outl(sts, DE4X5_STS);
3861 ans = inl(DE4X5_SISR) & SISR_ANS;
3862 sts = inl(DE4X5_STS) & ~TIMER_CB;
3864 if (!(sts & irqs) && (ans ^ ANS_NWOK) && --lp->timeout) {
3865 sts = 100 | TIMER_CB;
3874 de4x5_setup_intr(struct net_device *dev)
3876 struct de4x5_private *lp = netdev_priv(dev);
3877 u_long iobase = dev->base_addr;
3880 if (inl(DE4X5_OMR) & OMR_SR) { /* Only unmask if TX/RX is enabled */
3883 sts = inl(DE4X5_STS); /* Reset any pending (stale) interrupts */
3884 outl(sts, DE4X5_STS);
3895 reset_init_sia(struct net_device *dev, s32 csr13, s32 csr14, s32 csr15)
3897 struct de4x5_private *lp = netdev_priv(dev);
3898 u_long iobase = dev->base_addr;
3903 srom_exec(dev, lp->phy[lp->active].rst);
3904 srom_exec(dev, lp->phy[lp->active].gep);
3905 outl(1, DE4X5_SICR);
3908 csr15 = lp->cache.csr15;
3909 csr14 = lp->cache.csr14;
3910 csr13 = lp->cache.csr13;
3911 outl(csr15 | lp->cache.gepc, DE4X5_SIGR);
3912 outl(csr15 | lp->cache.gep, DE4X5_SIGR);
3915 outl(csr15, DE4X5_SIGR);
3917 outl(csr14, DE4X5_STRR);
3918 outl(csr13, DE4X5_SICR);
3926 ** Create a loopback ethernet packet
3929 create_packet(struct net_device *dev, char *frame, int len)
3934 for (i=0; i<ETH_ALEN; i++) { /* Use this source address */
3935 *buf++ = dev->dev_addr[i];
3937 for (i=0; i<ETH_ALEN; i++) { /* Use this destination address */
3938 *buf++ = dev->dev_addr[i];
3941 *buf++ = 0; /* Packet length (2 bytes) */
3948 ** Look for a particular board name in the EISA configuration space
3951 EISA_signature(char *name, struct device *device)
3953 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3954 struct eisa_device *edev;
3957 edev = to_eisa_device (device);
3958 i = edev->id.driver_data;
3960 if (i >= 0 && i < siglen) {
3961 strcpy (name, de4x5_signatures[i]);
3965 return status; /* return the device name string */
3969 ** Look for a particular board name in the PCI configuration space
3972 PCI_signature(char *name, struct de4x5_private *lp)
3974 int i, status = 0, siglen = sizeof(de4x5_signatures)/sizeof(c_char *);
3976 if (lp->chipset == DC21040) {
3977 strcpy(name, "DE434/5");
3979 } else { /* Search for a DEC name in the SROM */
3980 int i = *((char *)&lp->srom + 19) * 3;
3981 strncpy(name, (char *)&lp->srom + 26 + i, 8);
3984 for (i=0; i<siglen; i++) {
3985 if (strstr(name,de4x5_signatures[i])!=NULL) break;
3990 } else { /* Use chip name to avoid confusion */
3991 strcpy(name, (((lp->chipset == DC21040) ? "DC21040" :
3992 ((lp->chipset == DC21041) ? "DC21041" :
3993 ((lp->chipset == DC21140) ? "DC21140" :
3994 ((lp->chipset == DC21142) ? "DC21142" :
3995 ((lp->chipset == DC21143) ? "DC21143" : "UNKNOWN"
3998 if (lp->chipset != DC21041) {
3999 lp->useSROM = TRUE; /* card is not recognisably DEC */
4001 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
4009 ** Set up the Ethernet PROM counter to the start of the Ethernet address on
4010 ** the DC21040, else read the SROM for the other chips.
4011 ** The SROM may not be present in a multi-MAC card, so first read the
4012 ** MAC address and check for a bad address. If there is a bad one then exit
4013 ** immediately with the prior srom contents intact (the h/w address will
4014 ** be fixed up later).
4017 DevicePresent(struct net_device *dev, u_long aprom_addr)
4020 struct de4x5_private *lp = netdev_priv(dev);
4022 if (lp->chipset == DC21040) {
4023 if (lp->bus == EISA) {
4024 enet_addr_rst(aprom_addr); /* Reset Ethernet Address ROM Pointer */
4026 outl(0, aprom_addr); /* Reset Ethernet Address ROM Pointer */
4028 } else { /* Read new srom */
4029 u_short tmp, *p = (short *)((char *)&lp->srom + SROM_HWADD);
4030 for (i=0; i<(ETH_ALEN>>1); i++) {
4031 tmp = srom_rd(aprom_addr, (SROM_HWADD>>1) + i);
4032 *p = le16_to_cpu(tmp);
4035 if ((j == 0) || (j == 0x2fffd)) {
4039 p=(short *)&lp->srom;
4040 for (i=0; i<(sizeof(struct de4x5_srom)>>1); i++) {
4041 tmp = srom_rd(aprom_addr, i);
4042 *p++ = le16_to_cpu(tmp);
4044 de4x5_dbg_srom((struct de4x5_srom *)&lp->srom);
4051 ** Since the write on the Enet PROM register doesn't seem to reset the PROM
4052 ** pointer correctly (at least on my DE425 EISA card), this routine should do
4053 ** it...from depca.c.
4056 enet_addr_rst(u_long aprom_addr)
4063 char Sig[sizeof(u32) << 1];
4069 dev.llsig.a = ETH_PROM_SIG;
4070 dev.llsig.b = ETH_PROM_SIG;
4071 sigLength = sizeof(u32) << 1;
4073 for (i=0,j=0;j<sigLength && i<PROBE_LENGTH+sigLength-1;i++) {
4074 data = inb(aprom_addr);
4075 if (dev.Sig[j] == data) { /* track signature */
4077 } else { /* lost signature; begin search again */
4078 if (data == dev.Sig[0]) { /* rare case.... */
4090 ** For the bad status case and no SROM, then add one to the previous
4091 ** address. However, need to add one backwards in case we have 0xff
4092 ** as one or more of the bytes. Only the last 3 bytes should be checked
4093 ** as the first three are invariant - assigned to an organisation.
4096 get_hw_addr(struct net_device *dev)
4098 u_long iobase = dev->base_addr;
4099 int broken, i, k, tmp, status = 0;
4101 struct de4x5_private *lp = netdev_priv(dev);
4103 broken = de4x5_bad_srom(lp);
4105 for (i=0,k=0,j=0;j<3;j++) {
4107 if (k > 0xffff) k-=0xffff;
4109 if (lp->bus == PCI) {
4110 if (lp->chipset == DC21040) {
4111 while ((tmp = inl(DE4X5_APROM)) < 0);
4113 dev->dev_addr[i++] = (u_char) tmp;
4114 while ((tmp = inl(DE4X5_APROM)) < 0);
4115 k += (u_short) (tmp << 8);
4116 dev->dev_addr[i++] = (u_char) tmp;
4117 } else if (!broken) {
4118 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4119 dev->dev_addr[i] = (u_char) lp->srom.ieee_addr[i]; i++;
4120 } else if ((broken == SMC) || (broken == ACCTON)) {
4121 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4122 dev->dev_addr[i] = *((u_char *)&lp->srom + i); i++;
4125 k += (u_char) (tmp = inb(EISA_APROM));
4126 dev->dev_addr[i++] = (u_char) tmp;
4127 k += (u_short) ((tmp = inb(EISA_APROM)) << 8);
4128 dev->dev_addr[i++] = (u_char) tmp;
4131 if (k > 0xffff) k-=0xffff;
4133 if (k == 0xffff) k=0;
4135 if (lp->bus == PCI) {
4136 if (lp->chipset == DC21040) {
4137 while ((tmp = inl(DE4X5_APROM)) < 0);
4138 chksum = (u_char) tmp;
4139 while ((tmp = inl(DE4X5_APROM)) < 0);
4140 chksum |= (u_short) (tmp << 8);
4141 if ((k != chksum) && (dec_only)) status = -1;
4144 chksum = (u_char) inb(EISA_APROM);
4145 chksum |= (u_short) (inb(EISA_APROM) << 8);
4146 if ((k != chksum) && (dec_only)) status = -1;
4149 /* If possible, try to fix a broken card - SMC only so far */
4150 srom_repair(dev, broken);
4152 #ifdef CONFIG_PPC_PMAC
4154 ** If the address starts with 00 a0, we have to bit-reverse
4155 ** each byte of the address.
4157 if ( machine_is(powermac) &&
4158 (dev->dev_addr[0] == 0) &&
4159 (dev->dev_addr[1] == 0xa0) )
4161 for (i = 0; i < ETH_ALEN; ++i)
4163 int x = dev->dev_addr[i];
4164 x = ((x & 0xf) << 4) + ((x & 0xf0) >> 4);
4165 x = ((x & 0x33) << 2) + ((x & 0xcc) >> 2);
4166 dev->dev_addr[i] = ((x & 0x55) << 1) + ((x & 0xaa) >> 1);
4169 #endif /* CONFIG_PPC_PMAC */
4171 /* Test for a bad enet address */
4172 status = test_bad_enet(dev, status);
4178 ** Test for enet addresses in the first 32 bytes. The built-in strncmp
4179 ** didn't seem to work here...?
4182 de4x5_bad_srom(struct de4x5_private *lp)
4186 for (i=0; i<sizeof(enet_det)/ETH_ALEN; i++) {
4187 if (!de4x5_strncmp((char *)&lp->srom, (char *)&enet_det[i], 3) &&
4188 !de4x5_strncmp((char *)&lp->srom+0x10, (char *)&enet_det[i], 3)) {
4191 } else if (i == 1) {
4202 de4x5_strncmp(char *a, char *b, int n)
4206 for (;n && !ret;n--) {
4214 srom_repair(struct net_device *dev, int card)
4216 struct de4x5_private *lp = netdev_priv(dev);
4220 memset((char *)&lp->srom, 0, sizeof(struct de4x5_srom));
4221 memcpy(lp->srom.ieee_addr, (char *)dev->dev_addr, ETH_ALEN);
4222 memcpy(lp->srom.info, (char *)&srom_repair_info[SMC-1], 100);
4231 ** Assume that the irq's do not follow the PCI spec - this is seems
4232 ** to be true so far (2 for 2).
4235 test_bad_enet(struct net_device *dev, int status)
4237 struct de4x5_private *lp = netdev_priv(dev);
4240 for (tmp=0,i=0; i<ETH_ALEN; i++) tmp += (u_char)dev->dev_addr[i];
4241 if ((tmp == 0) || (tmp == 0x5fa)) {
4242 if ((lp->chipset == last.chipset) &&
4243 (lp->bus_num == last.bus) && (lp->bus_num > 0)) {
4244 for (i=0; i<ETH_ALEN; i++) dev->dev_addr[i] = last.addr[i];
4245 for (i=ETH_ALEN-1; i>2; --i) {
4246 dev->dev_addr[i] += 1;
4247 if (dev->dev_addr[i] != 0) break;
4249 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4250 if (!an_exception(lp)) {
4251 dev->irq = last.irq;
4256 } else if (!status) {
4257 last.chipset = lp->chipset;
4258 last.bus = lp->bus_num;
4259 last.irq = dev->irq;
4260 for (i=0; i<ETH_ALEN; i++) last.addr[i] = dev->dev_addr[i];
4267 ** List of board exceptions with correctly wired IRQs
4270 an_exception(struct de4x5_private *lp)
4272 if ((*(u_short *)lp->srom.sub_vendor_id == 0x00c0) &&
4273 (*(u_short *)lp->srom.sub_system_id == 0x95e0)) {
4284 srom_rd(u_long addr, u_char offset)
4286 sendto_srom(SROM_RD | SROM_SR, addr);
4288 srom_latch(SROM_RD | SROM_SR | DT_CS, addr);
4289 srom_command(SROM_RD | SROM_SR | DT_IN | DT_CS, addr);
4290 srom_address(SROM_RD | SROM_SR | DT_CS, addr, offset);
4292 return srom_data(SROM_RD | SROM_SR | DT_CS, addr);
4296 srom_latch(u_int command, u_long addr)
4298 sendto_srom(command, addr);
4299 sendto_srom(command | DT_CLK, addr);
4300 sendto_srom(command, addr);
4306 srom_command(u_int command, u_long addr)
4308 srom_latch(command, addr);
4309 srom_latch(command, addr);
4310 srom_latch((command & 0x0000ff00) | DT_CS, addr);
4316 srom_address(u_int command, u_long addr, u_char offset)
4321 for (i=0; i<6; i++, a <<= 1) {
4322 srom_latch(command | ((a & 0x80) ? DT_IN : 0), addr);
4326 i = (getfrom_srom(addr) >> 3) & 0x01;
4332 srom_data(u_int command, u_long addr)
4338 for (i=0; i<16; i++) {
4339 sendto_srom(command | DT_CLK, addr);
4340 tmp = getfrom_srom(addr);
4341 sendto_srom(command, addr);
4343 word = (word << 1) | ((tmp >> 3) & 0x01);
4346 sendto_srom(command & 0x0000ff00, addr);
4353 srom_busy(u_int command, u_long addr)
4355 sendto_srom((command & 0x0000ff00) | DT_CS, addr);
4357 while (!((getfrom_srom(addr) >> 3) & 0x01)) {
4361 sendto_srom(command & 0x0000ff00, addr);
4368 sendto_srom(u_int command, u_long addr)
4370 outl(command, addr);
4377 getfrom_srom(u_long addr)
4388 srom_infoleaf_info(struct net_device *dev)
4390 struct de4x5_private *lp = netdev_priv(dev);
4394 /* Find the infoleaf decoder function that matches this chipset */
4395 for (i=0; i<INFOLEAF_SIZE; i++) {
4396 if (lp->chipset == infoleaf_array[i].chipset) break;
4398 if (i == INFOLEAF_SIZE) {
4399 lp->useSROM = FALSE;
4400 printk("%s: Cannot find correct chipset for SROM decoding!\n",
4405 lp->infoleaf_fn = infoleaf_array[i].fn;
4407 /* Find the information offset that this function should use */
4408 count = *((u_char *)&lp->srom + 19);
4409 p = (u_char *)&lp->srom + 26;
4412 for (i=count; i; --i, p+=3) {
4413 if (lp->device == *p) break;
4416 lp->useSROM = FALSE;
4417 printk("%s: Cannot find correct PCI device [%d] for SROM decoding!\n",
4418 dev->name, lp->device);
4423 lp->infoleaf_offset = TWIDDLE(p+1);
4429 ** This routine loads any type 1 or 3 MII info into the mii device
4430 ** struct and executes any type 5 code to reset PHY devices for this
4432 ** The info for the MII devices will be valid since the index used
4433 ** will follow the discovery process from MII address 1-31 then 0.
4436 srom_init(struct net_device *dev)
4438 struct de4x5_private *lp = netdev_priv(dev);
4439 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4443 if (lp->chipset == DC21140) {
4444 lp->cache.gepc = (*p++ | GEP_CTRL);
4445 gep_wr(lp->cache.gepc, dev);
4451 /* Jump the infoblocks to find types */
4452 for (;count; --count) {
4455 } else if (*(p+1) == 5) {
4456 type5_infoblock(dev, 1, p);
4457 p += ((*p & BLOCK_LEN) + 1);
4458 } else if (*(p+1) == 4) {
4459 p += ((*p & BLOCK_LEN) + 1);
4460 } else if (*(p+1) == 3) {
4461 type3_infoblock(dev, 1, p);
4462 p += ((*p & BLOCK_LEN) + 1);
4463 } else if (*(p+1) == 2) {
4464 p += ((*p & BLOCK_LEN) + 1);
4465 } else if (*(p+1) == 1) {
4466 type1_infoblock(dev, 1, p);
4467 p += ((*p & BLOCK_LEN) + 1);
4469 p += ((*p & BLOCK_LEN) + 1);
4477 ** A generic routine that writes GEP control, data and reset information
4478 ** to the GEP register (21140) or csr15 GEP portion (2114[23]).
4481 srom_exec(struct net_device *dev, u_char *p)
4483 struct de4x5_private *lp = netdev_priv(dev);
4484 u_long iobase = dev->base_addr;
4485 u_char count = (p ? *p++ : 0);
4486 u_short *w = (u_short *)p;
4488 if (((lp->ibn != 1) && (lp->ibn != 3) && (lp->ibn != 5)) || !count) return;
4490 if (lp->chipset != DC21140) RESET_SIA;
4493 gep_wr(((lp->chipset==DC21140) && (lp->ibn!=5) ?
4494 *p++ : TWIDDLE(w++)), dev);
4495 mdelay(2); /* 2ms per action */
4498 if (lp->chipset != DC21140) {
4499 outl(lp->cache.csr14, DE4X5_STRR);
4500 outl(lp->cache.csr13, DE4X5_SICR);
4507 ** Basically this function is a NOP since it will never be called,
4508 ** unless I implement the DC21041 SROM functions. There's no need
4509 ** since the existing code will be satisfactory for all boards.
4512 dc21041_infoleaf(struct net_device *dev)
4514 return DE4X5_AUTOSENSE_MS;
4518 dc21140_infoleaf(struct net_device *dev)
4520 struct de4x5_private *lp = netdev_priv(dev);
4522 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4523 int next_tick = DE4X5_AUTOSENSE_MS;
4525 /* Read the connection type */
4529 lp->cache.gepc = (*p++ | GEP_CTRL);
4534 /* Recursively figure out the info blocks */
4536 next_tick = dc_infoblock[COMPACT](dev, count, p);
4538 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4541 if (lp->tcount == count) {
4543 if (lp->media != lp->c_media) {
4544 de4x5_dbg_media(dev);
4545 lp->c_media = lp->media;
4549 lp->tx_enable = FALSE;
4552 return next_tick & ~TIMER_CB;
4556 dc21142_infoleaf(struct net_device *dev)
4558 struct de4x5_private *lp = netdev_priv(dev);
4560 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4561 int next_tick = DE4X5_AUTOSENSE_MS;
4563 /* Read the connection type */
4569 /* Recursively figure out the info blocks */
4571 next_tick = dc_infoblock[COMPACT](dev, count, p);
4573 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4576 if (lp->tcount == count) {
4578 if (lp->media != lp->c_media) {
4579 de4x5_dbg_media(dev);
4580 lp->c_media = lp->media;
4584 lp->tx_enable = FALSE;
4587 return next_tick & ~TIMER_CB;
4591 dc21143_infoleaf(struct net_device *dev)
4593 struct de4x5_private *lp = netdev_priv(dev);
4595 u_char *p = (u_char *)&lp->srom + lp->infoleaf_offset;
4596 int next_tick = DE4X5_AUTOSENSE_MS;
4598 /* Read the connection type */
4604 /* Recursively figure out the info blocks */
4606 next_tick = dc_infoblock[COMPACT](dev, count, p);
4608 next_tick = dc_infoblock[*(p+1)](dev, count, p);
4610 if (lp->tcount == count) {
4612 if (lp->media != lp->c_media) {
4613 de4x5_dbg_media(dev);
4614 lp->c_media = lp->media;
4618 lp->tx_enable = FALSE;
4621 return next_tick & ~TIMER_CB;
4625 ** The compact infoblock is only designed for DC21140[A] chips, so
4626 ** we'll reuse the dc21140m_autoconf function. Non MII media only.
4629 compact_infoblock(struct net_device *dev, u_char count, u_char *p)
4631 struct de4x5_private *lp = netdev_priv(dev);
4634 /* Recursively figure out the info blocks */
4635 if (--count > lp->tcount) {
4636 if (*(p+COMPACT_LEN) < 128) {
4637 return dc_infoblock[COMPACT](dev, count, p+COMPACT_LEN);
4639 return dc_infoblock[*(p+COMPACT_LEN+1)](dev, count, p+COMPACT_LEN);
4643 if ((lp->media == INIT) && (lp->timeout < 0)) {
4646 gep_wr(lp->cache.gepc, dev);
4647 lp->infoblock_media = (*p++) & COMPACT_MC;
4648 lp->cache.gep = *p++;
4652 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4653 lp->defMedium = (flags & 0x40) ? -1 : 0;
4654 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4655 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4656 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4659 de4x5_switch_mac_port(dev);
4662 return dc21140m_autoconf(dev);
4666 ** This block describes non MII media for the DC21140[A] only.
4669 type0_infoblock(struct net_device *dev, u_char count, u_char *p)
4671 struct de4x5_private *lp = netdev_priv(dev);
4672 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4674 /* Recursively figure out the info blocks */
4675 if (--count > lp->tcount) {
4676 if (*(p+len) < 128) {
4677 return dc_infoblock[COMPACT](dev, count, p+len);
4679 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4683 if ((lp->media == INIT) && (lp->timeout < 0)) {
4686 gep_wr(lp->cache.gepc, dev);
4688 lp->infoblock_media = (*p++) & BLOCK0_MC;
4689 lp->cache.gep = *p++;
4693 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4694 lp->defMedium = (flags & 0x40) ? -1 : 0;
4695 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4696 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4697 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4700 de4x5_switch_mac_port(dev);
4703 return dc21140m_autoconf(dev);
4706 /* These functions are under construction! */
4709 type1_infoblock(struct net_device *dev, u_char count, u_char *p)
4711 struct de4x5_private *lp = netdev_priv(dev);
4712 u_char len = (*p & BLOCK_LEN)+1;
4714 /* Recursively figure out the info blocks */
4715 if (--count > lp->tcount) {
4716 if (*(p+len) < 128) {
4717 return dc_infoblock[COMPACT](dev, count, p+len);
4719 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4724 if (lp->state == INITIALISED) {
4727 lp->phy[lp->active].gep = (*p ? p : NULL); p += (*p + 1);
4728 lp->phy[lp->active].rst = (*p ? p : NULL); p += (*p + 1);
4729 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4730 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4731 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4732 lp->phy[lp->active].ttm = TWIDDLE(p);
4734 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4737 lp->infoblock_csr6 = OMR_MII_100;
4739 lp->infoblock_media = ANS;
4741 de4x5_switch_mac_port(dev);
4744 return dc21140m_autoconf(dev);
4748 type2_infoblock(struct net_device *dev, u_char count, u_char *p)
4750 struct de4x5_private *lp = netdev_priv(dev);
4751 u_char len = (*p & BLOCK_LEN)+1;
4753 /* Recursively figure out the info blocks */
4754 if (--count > lp->tcount) {
4755 if (*(p+len) < 128) {
4756 return dc_infoblock[COMPACT](dev, count, p+len);
4758 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4762 if ((lp->media == INIT) && (lp->timeout < 0)) {
4766 lp->infoblock_media = (*p) & MEDIA_CODE;
4768 if ((*p++) & EXT_FIELD) {
4769 lp->cache.csr13 = TWIDDLE(p); p += 2;
4770 lp->cache.csr14 = TWIDDLE(p); p += 2;
4771 lp->cache.csr15 = TWIDDLE(p); p += 2;
4773 lp->cache.csr13 = CSR13;
4774 lp->cache.csr14 = CSR14;
4775 lp->cache.csr15 = CSR15;
4777 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4778 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16);
4779 lp->infoblock_csr6 = OMR_SIA;
4782 de4x5_switch_mac_port(dev);
4785 return dc2114x_autoconf(dev);
4789 type3_infoblock(struct net_device *dev, u_char count, u_char *p)
4791 struct de4x5_private *lp = netdev_priv(dev);
4792 u_char len = (*p & BLOCK_LEN)+1;
4794 /* Recursively figure out the info blocks */
4795 if (--count > lp->tcount) {
4796 if (*(p+len) < 128) {
4797 return dc_infoblock[COMPACT](dev, count, p+len);
4799 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4804 if (lp->state == INITIALISED) {
4807 if (MOTO_SROM_BUG) lp->active = 0;
4808 lp->phy[lp->active].gep = (*p ? p : NULL); p += (2 * (*p) + 1);
4809 lp->phy[lp->active].rst = (*p ? p : NULL); p += (2 * (*p) + 1);
4810 lp->phy[lp->active].mc = TWIDDLE(p); p += 2;
4811 lp->phy[lp->active].ana = TWIDDLE(p); p += 2;
4812 lp->phy[lp->active].fdx = TWIDDLE(p); p += 2;
4813 lp->phy[lp->active].ttm = TWIDDLE(p); p += 2;
4814 lp->phy[lp->active].mci = *p;
4816 } else if ((lp->media == INIT) && (lp->timeout < 0)) {
4819 if (MOTO_SROM_BUG) lp->active = 0;
4820 lp->infoblock_csr6 = OMR_MII_100;
4822 lp->infoblock_media = ANS;
4824 de4x5_switch_mac_port(dev);
4827 return dc2114x_autoconf(dev);
4831 type4_infoblock(struct net_device *dev, u_char count, u_char *p)
4833 struct de4x5_private *lp = netdev_priv(dev);
4834 u_char flags, csr6, len = (*p & BLOCK_LEN)+1;
4836 /* Recursively figure out the info blocks */
4837 if (--count > lp->tcount) {
4838 if (*(p+len) < 128) {
4839 return dc_infoblock[COMPACT](dev, count, p+len);
4841 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4845 if ((lp->media == INIT) && (lp->timeout < 0)) {
4849 lp->infoblock_media = (*p++) & MEDIA_CODE;
4850 lp->cache.csr13 = CSR13; /* Hard coded defaults */
4851 lp->cache.csr14 = CSR14;
4852 lp->cache.csr15 = CSR15;
4853 lp->cache.gepc = ((s32)(TWIDDLE(p)) << 16); p += 2;
4854 lp->cache.gep = ((s32)(TWIDDLE(p)) << 16); p += 2;
4858 lp->asBitValid = (flags & 0x80) ? 0 : -1;
4859 lp->defMedium = (flags & 0x40) ? -1 : 0;
4860 lp->asBit = 1 << ((csr6 >> 1) & 0x07);
4861 lp->asPolarity = ((csr6 & 0x80) ? -1 : 0) & lp->asBit;
4862 lp->infoblock_csr6 = OMR_DEF | ((csr6 & 0x71) << 18);
4865 de4x5_switch_mac_port(dev);
4868 return dc2114x_autoconf(dev);
4872 ** This block type provides information for resetting external devices
4873 ** (chips) through the General Purpose Register.
4876 type5_infoblock(struct net_device *dev, u_char count, u_char *p)
4878 struct de4x5_private *lp = netdev_priv(dev);
4879 u_char len = (*p & BLOCK_LEN)+1;
4881 /* Recursively figure out the info blocks */
4882 if (--count > lp->tcount) {
4883 if (*(p+len) < 128) {
4884 return dc_infoblock[COMPACT](dev, count, p+len);
4886 return dc_infoblock[*(p+len+1)](dev, count, p+len);
4890 /* Must be initializing to run this code */
4891 if ((lp->state == INITIALISED) || (lp->media == INIT)) {
4894 srom_exec(dev, lp->rst);
4897 return DE4X5_AUTOSENSE_MS;
4905 mii_rd(u_char phyreg, u_char phyaddr, u_long ioaddr)
4907 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4908 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4909 mii_wdata(MII_STRD, 4, ioaddr); /* SFD and Read operation */
4910 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4911 mii_address(phyreg, ioaddr); /* PHY Register to read */
4912 mii_ta(MII_STRD, ioaddr); /* Turn around time - 2 MDC */
4914 return mii_rdata(ioaddr); /* Read data */
4918 mii_wr(int data, u_char phyreg, u_char phyaddr, u_long ioaddr)
4920 mii_wdata(MII_PREAMBLE, 2, ioaddr); /* Start of 34 bit preamble... */
4921 mii_wdata(MII_PREAMBLE, 32, ioaddr); /* ...continued */
4922 mii_wdata(MII_STWR, 4, ioaddr); /* SFD and Write operation */
4923 mii_address(phyaddr, ioaddr); /* PHY address to be accessed */
4924 mii_address(phyreg, ioaddr); /* PHY Register to write */
4925 mii_ta(MII_STWR, ioaddr); /* Turn around time - 2 MDC */
4926 data = mii_swap(data, 16); /* Swap data bit ordering */
4927 mii_wdata(data, 16, ioaddr); /* Write data */
4933 mii_rdata(u_long ioaddr)
4938 for (i=0; i<16; i++) {
4940 tmp |= getfrom_mii(MII_MRD | MII_RD, ioaddr);
4947 mii_wdata(int data, int len, u_long ioaddr)
4951 for (i=0; i<len; i++) {
4952 sendto_mii(MII_MWR | MII_WR, data, ioaddr);
4960 mii_address(u_char addr, u_long ioaddr)
4964 addr = mii_swap(addr, 5);
4965 for (i=0; i<5; i++) {
4966 sendto_mii(MII_MWR | MII_WR, addr, ioaddr);
4974 mii_ta(u_long rw, u_long ioaddr)
4976 if (rw == MII_STWR) {
4977 sendto_mii(MII_MWR | MII_WR, 1, ioaddr);
4978 sendto_mii(MII_MWR | MII_WR, 0, ioaddr);
4980 getfrom_mii(MII_MRD | MII_RD, ioaddr); /* Tri-state MDIO */
4987 mii_swap(int data, int len)
4991 for (i=0; i<len; i++) {
5001 sendto_mii(u32 command, int data, u_long ioaddr)
5005 j = (data & 1) << 17;
5006 outl(command | j, ioaddr);
5008 outl(command | MII_MDC | j, ioaddr);
5015 getfrom_mii(u32 command, u_long ioaddr)
5017 outl(command, ioaddr);
5019 outl(command | MII_MDC, ioaddr);
5022 return ((inl(ioaddr) >> 19) & 1);
5026 ** Here's 3 ways to calculate the OUI from the ID registers.
5029 mii_get_oui(u_char phyaddr, u_long ioaddr)
5036 int i, r2, r3, ret=0;*/
5039 /* Read r2 and r3 */
5040 r2 = mii_rd(MII_ID0, phyaddr, ioaddr);
5041 r3 = mii_rd(MII_ID1, phyaddr, ioaddr);
5042 /* SEEQ and Cypress way * /
5043 / * Shuffle r2 and r3 * /
5045 r3 = ((r3>>10)|(r2<<6))&0x0ff;
5046 r2 = ((r2>>2)&0x3fff);
5048 / * Bit reverse r3 * /
5055 / * Bit reverse r2 * /
5056 for (i=0;i<16;i++) {
5062 / * Swap r2 bytes * /
5064 a.breg[0]=a.breg[1];
5067 return ((a.reg<<8)|ret); */ /* SEEQ and Cypress way */
5068 /* return ((r2<<6)|(u_int)(r3>>10)); */ /* NATIONAL and BROADCOM way */
5069 return r2; /* (I did it) My way */
5073 ** The SROM spec forces us to search addresses [1-31 0]. Bummer.
5076 mii_get_phy(struct net_device *dev)
5078 struct de4x5_private *lp = netdev_priv(dev);
5079 u_long iobase = dev->base_addr;
5080 int i, j, k, n, limit=sizeof(phy_info)/sizeof(struct phy_table);
5086 /* Search the MII address space for possible PHY devices */
5087 for (n=0, lp->mii_cnt=0, i=1; !((i==1) && (n==1)); i=(i+1)%DE4X5_MAX_MII) {
5088 lp->phy[lp->active].addr = i;
5089 if (i==0) n++; /* Count cycles */
5090 while (de4x5_reset_phy(dev)<0) udelay(100);/* Wait for reset */
5091 id = mii_get_oui(i, DE4X5_MII);
5092 if ((id == 0) || (id == 65535)) continue; /* Valid ID? */
5093 for (j=0; j<limit; j++) { /* Search PHY table */
5094 if (id != phy_info[j].id) continue; /* ID match? */
5095 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5096 if (k < DE4X5_MAX_PHY) {
5097 memcpy((char *)&lp->phy[k],
5098 (char *)&phy_info[j], sizeof(struct phy_table));
5099 lp->phy[k].addr = i;
5103 goto purgatory; /* Stop the search */
5107 if ((j == limit) && (i < DE4X5_MAX_MII)) {
5108 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++);
5109 lp->phy[k].addr = i;
5111 lp->phy[k].spd.reg = GENERIC_REG; /* ANLPA register */
5112 lp->phy[k].spd.mask = GENERIC_MASK; /* 100Mb/s technologies */
5113 lp->phy[k].spd.value = GENERIC_VALUE; /* TX & T4, H/F Duplex */
5116 printk("%s: Using generic MII device control. If the board doesn't operate, \nplease mail the following dump to the author:\n", dev->name);
5118 de4x5_debug |= DEBUG_MII;
5119 de4x5_dbg_mii(dev, k);
5126 if (lp->phy[0].id) { /* Reset the PHY devices */
5127 for (k=0; lp->phy[k].id && (k < DE4X5_MAX_PHY); k++) { /*For each PHY*/
5128 mii_wr(MII_CR_RST, MII_CR, lp->phy[k].addr, DE4X5_MII);
5129 while (mii_rd(MII_CR, lp->phy[k].addr, DE4X5_MII) & MII_CR_RST);
5131 de4x5_dbg_mii(dev, k);
5134 if (!lp->mii_cnt) lp->useMII = FALSE;
5140 build_setup_frame(struct net_device *dev, int mode)
5142 struct de4x5_private *lp = netdev_priv(dev);
5144 char *pa = lp->setup_frame;
5146 /* Initialise the setup frame */
5148 memset(lp->setup_frame, 0, SETUP_FRAME_LEN);
5151 if (lp->setup_f == HASH_PERF) {
5152 for (pa=lp->setup_frame+IMPERF_PA_OFFSET, i=0; i<ETH_ALEN; i++) {
5153 *(pa + i) = dev->dev_addr[i]; /* Host address */
5154 if (i & 0x01) pa += 2;
5156 *(lp->setup_frame + (HASH_TABLE_LEN >> 3) - 3) = 0x80;
5158 for (i=0; i<ETH_ALEN; i++) { /* Host address */
5159 *(pa + (i&1)) = dev->dev_addr[i];
5160 if (i & 0x01) pa += 4;
5162 for (i=0; i<ETH_ALEN; i++) { /* Broadcast address */
5163 *(pa + (i&1)) = (char) 0xff;
5164 if (i & 0x01) pa += 4;
5168 return pa; /* Points to the next entry */
5172 enable_ast(struct net_device *dev, u32 time_out)
5174 timeout(dev, (void *)&de4x5_ast, (u_long)dev, time_out);
5180 disable_ast(struct net_device *dev)
5182 struct de4x5_private *lp = netdev_priv(dev);
5184 del_timer(&lp->timer);
5190 de4x5_switch_mac_port(struct net_device *dev)
5192 struct de4x5_private *lp = netdev_priv(dev);
5193 u_long iobase = dev->base_addr;
5198 /* Assert the OMR_PS bit in CSR6 */
5199 omr = (inl(DE4X5_OMR) & ~(OMR_PS | OMR_HBD | OMR_TTM | OMR_PCS | OMR_SCR |
5201 omr |= lp->infoblock_csr6;
5202 if (omr & OMR_PS) omr |= OMR_HBD;
5203 outl(omr, DE4X5_OMR);
5208 /* Restore the GEP - especially for COMPACT and Type 0 Infoblocks */
5209 if (lp->chipset == DC21140) {
5210 gep_wr(lp->cache.gepc, dev);
5211 gep_wr(lp->cache.gep, dev);
5212 } else if ((lp->chipset & ~0x0ff) == DC2114x) {
5213 reset_init_sia(dev, lp->cache.csr13, lp->cache.csr14, lp->cache.csr15);
5217 outl(omr, DE4X5_OMR);
5226 gep_wr(s32 data, struct net_device *dev)
5228 struct de4x5_private *lp = netdev_priv(dev);
5229 u_long iobase = dev->base_addr;
5231 if (lp->chipset == DC21140) {
5232 outl(data, DE4X5_GEP);
5233 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5234 outl((data<<16) | lp->cache.csr15, DE4X5_SIGR);
5241 gep_rd(struct net_device *dev)
5243 struct de4x5_private *lp = netdev_priv(dev);
5244 u_long iobase = dev->base_addr;
5246 if (lp->chipset == DC21140) {
5247 return inl(DE4X5_GEP);
5248 } else if ((lp->chipset & ~0x00ff) == DC2114x) {
5249 return (inl(DE4X5_SIGR) & 0x000fffff);
5256 timeout(struct net_device *dev, void (*fn)(u_long data), u_long data, u_long msec)
5258 struct de4x5_private *lp = netdev_priv(dev);
5261 /* First, cancel any pending timer events */
5262 del_timer(&lp->timer);
5264 /* Convert msec to ticks */
5265 dt = (msec * HZ) / 1000;
5269 init_timer(&lp->timer);
5270 lp->timer.expires = jiffies + dt;
5271 lp->timer.function = fn;
5272 lp->timer.data = data;
5273 add_timer(&lp->timer);
5279 yawn(struct net_device *dev, int state)
5281 struct de4x5_private *lp = netdev_priv(dev);
5282 u_long iobase = dev->base_addr;
5284 if ((lp->chipset == DC21040) || (lp->chipset == DC21140)) return;
5286 if(lp->bus == EISA) {
5289 outb(WAKEUP, PCI_CFPM);
5294 outb(SNOOZE, PCI_CFPM);
5298 outl(0, DE4X5_SICR);
5299 outb(SLEEP, PCI_CFPM);
5303 struct pci_dev *pdev = to_pci_dev (lp->gendev);
5306 pci_write_config_byte(pdev, PCI_CFDA_PSM, WAKEUP);
5311 pci_write_config_byte(pdev, PCI_CFDA_PSM, SNOOZE);
5315 outl(0, DE4X5_SICR);
5316 pci_write_config_byte(pdev, PCI_CFDA_PSM, SLEEP);
5325 de4x5_parse_params(struct net_device *dev)
5327 struct de4x5_private *lp = netdev_priv(dev);
5331 lp->params.autosense = AUTO;
5333 if (args == NULL) return;
5335 if ((p = strstr(args, dev->name))) {
5336 if (!(q = strstr(p+strlen(dev->name), "eth"))) q = p + strlen(p);
5340 if (strstr(p, "fdx") || strstr(p, "FDX")) lp->params.fdx = 1;
5342 if (strstr(p, "autosense") || strstr(p, "AUTOSENSE")) {
5343 if (strstr(p, "TP")) {
5344 lp->params.autosense = TP;
5345 } else if (strstr(p, "TP_NW")) {
5346 lp->params.autosense = TP_NW;
5347 } else if (strstr(p, "BNC")) {
5348 lp->params.autosense = BNC;
5349 } else if (strstr(p, "AUI")) {
5350 lp->params.autosense = AUI;
5351 } else if (strstr(p, "BNC_AUI")) {
5352 lp->params.autosense = BNC;
5353 } else if (strstr(p, "10Mb")) {
5354 lp->params.autosense = _10Mb;
5355 } else if (strstr(p, "100Mb")) {
5356 lp->params.autosense = _100Mb;
5357 } else if (strstr(p, "AUTO")) {
5358 lp->params.autosense = AUTO;
5368 de4x5_dbg_open(struct net_device *dev)
5370 struct de4x5_private *lp = netdev_priv(dev);
5373 if (de4x5_debug & DEBUG_OPEN) {
5374 printk("%s: de4x5 opening with irq %d\n",dev->name,dev->irq);
5375 printk("\tphysical address: ");
5377 printk("%2.2x:",(short)dev->dev_addr[i]);
5380 printk("Descriptor head addresses:\n");
5381 printk("\t0x%8.8lx 0x%8.8lx\n",(u_long)lp->rx_ring,(u_long)lp->tx_ring);
5382 printk("Descriptor addresses:\nRX: ");
5383 for (i=0;i<lp->rxRingSize-1;i++){
5385 printk("0x%8.8lx ",(u_long)&lp->rx_ring[i].status);
5388 printk("...0x%8.8lx\n",(u_long)&lp->rx_ring[i].status);
5390 for (i=0;i<lp->txRingSize-1;i++){
5392 printk("0x%8.8lx ", (u_long)&lp->tx_ring[i].status);
5395 printk("...0x%8.8lx\n", (u_long)&lp->tx_ring[i].status);
5396 printk("Descriptor buffers:\nRX: ");
5397 for (i=0;i<lp->rxRingSize-1;i++){
5399 printk("0x%8.8x ",le32_to_cpu(lp->rx_ring[i].buf));
5402 printk("...0x%8.8x\n",le32_to_cpu(lp->rx_ring[i].buf));
5404 for (i=0;i<lp->txRingSize-1;i++){
5406 printk("0x%8.8x ", le32_to_cpu(lp->tx_ring[i].buf));
5409 printk("...0x%8.8x\n", le32_to_cpu(lp->tx_ring[i].buf));
5410 printk("Ring size: \nRX: %d\nTX: %d\n",
5411 (short)lp->rxRingSize,
5412 (short)lp->txRingSize);
5419 de4x5_dbg_mii(struct net_device *dev, int k)
5421 struct de4x5_private *lp = netdev_priv(dev);
5422 u_long iobase = dev->base_addr;
5424 if (de4x5_debug & DEBUG_MII) {
5425 printk("\nMII device address: %d\n", lp->phy[k].addr);
5426 printk("MII CR: %x\n",mii_rd(MII_CR,lp->phy[k].addr,DE4X5_MII));
5427 printk("MII SR: %x\n",mii_rd(MII_SR,lp->phy[k].addr,DE4X5_MII));
5428 printk("MII ID0: %x\n",mii_rd(MII_ID0,lp->phy[k].addr,DE4X5_MII));
5429 printk("MII ID1: %x\n",mii_rd(MII_ID1,lp->phy[k].addr,DE4X5_MII));
5430 if (lp->phy[k].id != BROADCOM_T4) {
5431 printk("MII ANA: %x\n",mii_rd(0x04,lp->phy[k].addr,DE4X5_MII));
5432 printk("MII ANC: %x\n",mii_rd(0x05,lp->phy[k].addr,DE4X5_MII));
5434 printk("MII 16: %x\n",mii_rd(0x10,lp->phy[k].addr,DE4X5_MII));
5435 if (lp->phy[k].id != BROADCOM_T4) {
5436 printk("MII 17: %x\n",mii_rd(0x11,lp->phy[k].addr,DE4X5_MII));
5437 printk("MII 18: %x\n",mii_rd(0x12,lp->phy[k].addr,DE4X5_MII));
5439 printk("MII 20: %x\n",mii_rd(0x14,lp->phy[k].addr,DE4X5_MII));
5447 de4x5_dbg_media(struct net_device *dev)
5449 struct de4x5_private *lp = netdev_priv(dev);
5451 if (lp->media != lp->c_media) {
5452 if (de4x5_debug & DEBUG_MEDIA) {
5453 printk("%s: media is %s%s\n", dev->name,
5454 (lp->media == NC ? "unconnected, link down or incompatible connection" :
5455 (lp->media == TP ? "TP" :
5456 (lp->media == ANS ? "TP/Nway" :
5457 (lp->media == BNC ? "BNC" :
5458 (lp->media == AUI ? "AUI" :
5459 (lp->media == BNC_AUI ? "BNC/AUI" :
5460 (lp->media == EXT_SIA ? "EXT SIA" :
5461 (lp->media == _100Mb ? "100Mb/s" :
5462 (lp->media == _10Mb ? "10Mb/s" :
5464 ))))))))), (lp->fdx?" full duplex.":"."));
5466 lp->c_media = lp->media;
5473 de4x5_dbg_srom(struct de4x5_srom *p)
5477 if (de4x5_debug & DEBUG_SROM) {
5478 printk("Sub-system Vendor ID: %04x\n", *((u_short *)p->sub_vendor_id));
5479 printk("Sub-system ID: %04x\n", *((u_short *)p->sub_system_id));
5480 printk("ID Block CRC: %02x\n", (u_char)(p->id_block_crc));
5481 printk("SROM version: %02x\n", (u_char)(p->version));
5482 printk("# controllers: %02x\n", (u_char)(p->num_controllers));
5484 printk("Hardware Address: ");
5485 for (i=0;i<ETH_ALEN-1;i++) {
5486 printk("%02x:", (u_char)*(p->ieee_addr+i));
5488 printk("%02x\n", (u_char)*(p->ieee_addr+i));
5489 printk("CRC checksum: %04x\n", (u_short)(p->chksum));
5490 for (i=0; i<64; i++) {
5491 printk("%3d %04x\n", i<<1, (u_short)*((u_short *)p+i));
5499 de4x5_dbg_rx(struct sk_buff *skb, int len)
5503 if (de4x5_debug & DEBUG_RX) {
5504 printk("R: %02x:%02x:%02x:%02x:%02x:%02x <- %02x:%02x:%02x:%02x:%02x:%02x len/SAP:%02x%02x [%d]\n",
5505 (u_char)skb->data[0],
5506 (u_char)skb->data[1],
5507 (u_char)skb->data[2],
5508 (u_char)skb->data[3],
5509 (u_char)skb->data[4],
5510 (u_char)skb->data[5],
5511 (u_char)skb->data[6],
5512 (u_char)skb->data[7],
5513 (u_char)skb->data[8],
5514 (u_char)skb->data[9],
5515 (u_char)skb->data[10],
5516 (u_char)skb->data[11],
5517 (u_char)skb->data[12],
5518 (u_char)skb->data[13],
5520 for (j=0; len>0;j+=16, len-=16) {
5521 printk(" %03x: ",j);
5522 for (i=0; i<16 && i<len; i++) {
5523 printk("%02x ",(u_char)skb->data[i+j]);
5533 ** Perform IOCTL call functions here. Some are privileged operations and the
5534 ** effective uid is checked in those cases. In the normal course of events
5535 ** this function is only used for my testing.
5538 de4x5_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
5540 struct de4x5_private *lp = netdev_priv(dev);
5541 struct de4x5_ioctl *ioc = (struct de4x5_ioctl *) &rq->ifr_ifru;
5542 u_long iobase = dev->base_addr;
5543 int i, j, status = 0;
5553 case DE4X5_GET_HWADDR: /* Get the hardware address */
5554 ioc->len = ETH_ALEN;
5555 for (i=0; i<ETH_ALEN; i++) {
5556 tmp.addr[i] = dev->dev_addr[i];
5558 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5561 case DE4X5_SET_HWADDR: /* Set the hardware address */
5562 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5563 if (copy_from_user(tmp.addr, ioc->data, ETH_ALEN)) return -EFAULT;
5564 if (netif_queue_stopped(dev))
5566 netif_stop_queue(dev);
5567 for (i=0; i<ETH_ALEN; i++) {
5568 dev->dev_addr[i] = tmp.addr[i];
5570 build_setup_frame(dev, PHYS_ADDR_ONLY);
5571 /* Set up the descriptor and give ownership to the card */
5572 load_packet(dev, lp->setup_frame, TD_IC | PERFECT_F | TD_SET |
5573 SETUP_FRAME_LEN, (struct sk_buff *)1);
5574 lp->tx_new = (++lp->tx_new) % lp->txRingSize;
5575 outl(POLL_DEMAND, DE4X5_TPD); /* Start the TX */
5576 netif_wake_queue(dev); /* Unlock the TX ring */
5579 case DE4X5_SET_PROM: /* Set Promiscuous Mode */
5580 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5581 omr = inl(DE4X5_OMR);
5583 outl(omr, DE4X5_OMR);
5584 dev->flags |= IFF_PROMISC;
5587 case DE4X5_CLR_PROM: /* Clear Promiscuous Mode */
5588 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5589 omr = inl(DE4X5_OMR);
5591 outl(omr, DE4X5_OMR);
5592 dev->flags &= ~IFF_PROMISC;
5595 case DE4X5_SAY_BOO: /* Say "Boo!" to the kernel log file */
5596 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5597 printk("%s: Boo!\n", dev->name);
5600 case DE4X5_MCA_EN: /* Enable pass all multicast addressing */
5601 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5602 omr = inl(DE4X5_OMR);
5604 outl(omr, DE4X5_OMR);
5607 case DE4X5_GET_STATS: /* Get the driver statistics */
5609 struct pkt_stats statbuf;
5610 ioc->len = sizeof(statbuf);
5611 spin_lock_irqsave(&lp->lock, flags);
5612 memcpy(&statbuf, &lp->pktStats, ioc->len);
5613 spin_unlock_irqrestore(&lp->lock, flags);
5614 if (copy_to_user(ioc->data, &statbuf, ioc->len))
5618 case DE4X5_CLR_STATS: /* Zero out the driver statistics */
5619 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5620 spin_lock_irqsave(&lp->lock, flags);
5621 memset(&lp->pktStats, 0, sizeof(lp->pktStats));
5622 spin_unlock_irqrestore(&lp->lock, flags);
5625 case DE4X5_GET_OMR: /* Get the OMR Register contents */
5626 tmp.addr[0] = inl(DE4X5_OMR);
5627 if (copy_to_user(ioc->data, tmp.addr, 1)) return -EFAULT;
5630 case DE4X5_SET_OMR: /* Set the OMR Register contents */
5631 if (!capable(CAP_NET_ADMIN)) return -EPERM;
5632 if (copy_from_user(tmp.addr, ioc->data, 1)) return -EFAULT;
5633 outl(tmp.addr[0], DE4X5_OMR);
5636 case DE4X5_GET_REG: /* Get the DE4X5 Registers */
5638 tmp.lval[0] = inl(DE4X5_STS); j+=4;
5639 tmp.lval[1] = inl(DE4X5_BMR); j+=4;
5640 tmp.lval[2] = inl(DE4X5_IMR); j+=4;
5641 tmp.lval[3] = inl(DE4X5_OMR); j+=4;
5642 tmp.lval[4] = inl(DE4X5_SISR); j+=4;
5643 tmp.lval[5] = inl(DE4X5_SICR); j+=4;
5644 tmp.lval[6] = inl(DE4X5_STRR); j+=4;
5645 tmp.lval[7] = inl(DE4X5_SIGR); j+=4;
5647 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5650 #define DE4X5_DUMP 0x0f /* Dump the DE4X5 Status */
5654 tmp.addr[j++] = dev->irq;
5655 for (i=0; i<ETH_ALEN; i++) {
5656 tmp.addr[j++] = dev->dev_addr[i];
5658 tmp.addr[j++] = lp->rxRingSize;
5659 tmp.lval[j>>2] = (long)lp->rx_ring; j+=4;
5660 tmp.lval[j>>2] = (long)lp->tx_ring; j+=4;
5662 for (i=0;i<lp->rxRingSize-1;i++){
5664 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5667 tmp.lval[j>>2] = (long)&lp->rx_ring[i].status; j+=4;
5668 for (i=0;i<lp->txRingSize-1;i++){
5670 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5673 tmp.lval[j>>2] = (long)&lp->tx_ring[i].status; j+=4;
5675 for (i=0;i<lp->rxRingSize-1;i++){
5677 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5680 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->rx_ring[i].buf); j+=4;
5681 for (i=0;i<lp->txRingSize-1;i++){
5683 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5686 tmp.lval[j>>2] = (s32)le32_to_cpu(lp->tx_ring[i].buf); j+=4;
5688 for (i=0;i<lp->rxRingSize;i++){
5689 tmp.lval[j>>2] = le32_to_cpu(lp->rx_ring[i].status); j+=4;
5691 for (i=0;i<lp->txRingSize;i++){
5692 tmp.lval[j>>2] = le32_to_cpu(lp->tx_ring[i].status); j+=4;
5695 tmp.lval[j>>2] = inl(DE4X5_BMR); j+=4;
5696 tmp.lval[j>>2] = inl(DE4X5_TPD); j+=4;
5697 tmp.lval[j>>2] = inl(DE4X5_RPD); j+=4;
5698 tmp.lval[j>>2] = inl(DE4X5_RRBA); j+=4;
5699 tmp.lval[j>>2] = inl(DE4X5_TRBA); j+=4;
5700 tmp.lval[j>>2] = inl(DE4X5_STS); j+=4;
5701 tmp.lval[j>>2] = inl(DE4X5_OMR); j+=4;
5702 tmp.lval[j>>2] = inl(DE4X5_IMR); j+=4;
5703 tmp.lval[j>>2] = lp->chipset; j+=4;
5704 if (lp->chipset == DC21140) {
5705 tmp.lval[j>>2] = gep_rd(dev); j+=4;
5707 tmp.lval[j>>2] = inl(DE4X5_SISR); j+=4;
5708 tmp.lval[j>>2] = inl(DE4X5_SICR); j+=4;
5709 tmp.lval[j>>2] = inl(DE4X5_STRR); j+=4;
5710 tmp.lval[j>>2] = inl(DE4X5_SIGR); j+=4;
5712 tmp.lval[j>>2] = lp->phy[lp->active].id; j+=4;
5713 if (lp->phy[lp->active].id && (!lp->useSROM || lp->useMII)) {
5714 tmp.lval[j>>2] = lp->active; j+=4;
5715 tmp.lval[j>>2]=mii_rd(MII_CR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5716 tmp.lval[j>>2]=mii_rd(MII_SR,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5717 tmp.lval[j>>2]=mii_rd(MII_ID0,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5718 tmp.lval[j>>2]=mii_rd(MII_ID1,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5719 if (lp->phy[lp->active].id != BROADCOM_T4) {
5720 tmp.lval[j>>2]=mii_rd(MII_ANA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5721 tmp.lval[j>>2]=mii_rd(MII_ANLPA,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5723 tmp.lval[j>>2]=mii_rd(0x10,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5724 if (lp->phy[lp->active].id != BROADCOM_T4) {
5725 tmp.lval[j>>2]=mii_rd(0x11,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5726 tmp.lval[j>>2]=mii_rd(0x12,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5728 tmp.lval[j>>2]=mii_rd(0x14,lp->phy[lp->active].addr,DE4X5_MII); j+=4;
5732 tmp.addr[j++] = lp->txRingSize;
5733 tmp.addr[j++] = netif_queue_stopped(dev);
5736 if (copy_to_user(ioc->data, tmp.addr, ioc->len)) return -EFAULT;
5747 static int __init de4x5_module_init (void)
5752 err = pci_register_driver(&de4x5_pci_driver);
5755 err |= eisa_driver_register (&de4x5_eisa_driver);
5761 static void __exit de4x5_module_exit (void)
5764 pci_unregister_driver (&de4x5_pci_driver);
5767 eisa_driver_unregister (&de4x5_eisa_driver);
5771 module_init (de4x5_module_init);
5772 module_exit (de4x5_module_exit);