2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2007 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/if_vlan.h>
37 #include <linux/tcp.h>
38 #include <linux/workqueue.h>
39 #include <linux/prefetch.h>
40 #include <linux/dma-mapping.h>
42 #include <net/checksum.h>
45 #include <asm/system.h>
47 #include <asm/byteorder.h>
48 #include <asm/uaccess.h>
51 #include <asm/idprom.h>
55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
56 #define TG3_VLAN_TAG_USED 1
58 #define TG3_VLAN_TAG_USED 0
61 #define TG3_TSO_SUPPORT 1
65 #define DRV_MODULE_NAME "tg3"
66 #define PFX DRV_MODULE_NAME ": "
67 #define DRV_MODULE_VERSION "3.77"
68 #define DRV_MODULE_RELDATE "May 31, 2007"
70 #define TG3_DEF_MAC_MODE 0
71 #define TG3_DEF_RX_MODE 0
72 #define TG3_DEF_TX_MODE 0
73 #define TG3_DEF_MSG_ENABLE \
83 /* length of time before we decide the hardware is borked,
84 * and dev->tx_timeout() should be called to fix the problem
86 #define TG3_TX_TIMEOUT (5 * HZ)
88 /* hardware minimum and maximum for a single frame's data payload */
89 #define TG3_MIN_MTU 60
90 #define TG3_MAX_MTU(tp) \
91 ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
93 /* These numbers seem to be hard coded in the NIC firmware somehow.
94 * You can't change the ring sizes, but you can change where you place
95 * them in the NIC onboard memory.
97 #define TG3_RX_RING_SIZE 512
98 #define TG3_DEF_RX_RING_PENDING 200
99 #define TG3_RX_JUMBO_RING_SIZE 256
100 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
102 /* Do not place this n-ring entries value into the tp struct itself,
103 * we really want to expose these constants to GCC so that modulo et
104 * al. operations are done with shifts and masks instead of with
105 * hw multiply/modulo instructions. Another solution would be to
106 * replace things like '% foo' with '& (foo - 1)'.
108 #define TG3_RX_RCB_RING_SIZE(tp) \
109 ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
111 #define TG3_TX_RING_SIZE 512
112 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
114 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
117 TG3_RX_JUMBO_RING_SIZE)
118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
119 TG3_RX_RCB_RING_SIZE(tp))
120 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
122 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
124 #define RX_PKT_BUF_SZ (1536 + tp->rx_offset + 64)
125 #define RX_JUMBO_PKT_BUF_SZ (9046 + tp->rx_offset + 64)
127 /* minimum number of free TX descriptors required to wake up TX process */
128 #define TG3_TX_WAKEUP_THRESH(tp) ((tp)->tx_pending / 4)
130 /* number of ETHTOOL_GSTATS u64's */
131 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
133 #define TG3_NUM_TEST 6
135 static char version[] __devinitdata =
136 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
140 MODULE_LICENSE("GPL");
141 MODULE_VERSION(DRV_MODULE_VERSION);
143 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
144 module_param(tg3_debug, int, 0);
145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
147 static struct pci_device_id tg3_pci_tbl[] = {
148 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
149 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
150 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
151 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
152 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
153 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
154 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
155 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
156 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
157 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
158 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
159 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
160 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
161 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
162 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
163 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
164 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
165 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
166 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
167 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
168 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
169 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
170 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
171 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
172 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
173 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
174 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
175 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
176 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
177 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
201 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
202 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
203 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
204 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
205 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
206 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
207 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
213 static const struct {
214 const char string[ETH_GSTRING_LEN];
215 } ethtool_stats_keys[TG3_NUM_STATS] = {
218 { "rx_ucast_packets" },
219 { "rx_mcast_packets" },
220 { "rx_bcast_packets" },
222 { "rx_align_errors" },
223 { "rx_xon_pause_rcvd" },
224 { "rx_xoff_pause_rcvd" },
225 { "rx_mac_ctrl_rcvd" },
226 { "rx_xoff_entered" },
227 { "rx_frame_too_long_errors" },
229 { "rx_undersize_packets" },
230 { "rx_in_length_errors" },
231 { "rx_out_length_errors" },
232 { "rx_64_or_less_octet_packets" },
233 { "rx_65_to_127_octet_packets" },
234 { "rx_128_to_255_octet_packets" },
235 { "rx_256_to_511_octet_packets" },
236 { "rx_512_to_1023_octet_packets" },
237 { "rx_1024_to_1522_octet_packets" },
238 { "rx_1523_to_2047_octet_packets" },
239 { "rx_2048_to_4095_octet_packets" },
240 { "rx_4096_to_8191_octet_packets" },
241 { "rx_8192_to_9022_octet_packets" },
248 { "tx_flow_control" },
250 { "tx_single_collisions" },
251 { "tx_mult_collisions" },
253 { "tx_excessive_collisions" },
254 { "tx_late_collisions" },
255 { "tx_collide_2times" },
256 { "tx_collide_3times" },
257 { "tx_collide_4times" },
258 { "tx_collide_5times" },
259 { "tx_collide_6times" },
260 { "tx_collide_7times" },
261 { "tx_collide_8times" },
262 { "tx_collide_9times" },
263 { "tx_collide_10times" },
264 { "tx_collide_11times" },
265 { "tx_collide_12times" },
266 { "tx_collide_13times" },
267 { "tx_collide_14times" },
268 { "tx_collide_15times" },
269 { "tx_ucast_packets" },
270 { "tx_mcast_packets" },
271 { "tx_bcast_packets" },
272 { "tx_carrier_sense_errors" },
276 { "dma_writeq_full" },
277 { "dma_write_prioq_full" },
281 { "rx_threshold_hit" },
283 { "dma_readq_full" },
284 { "dma_read_prioq_full" },
285 { "tx_comp_queue_full" },
287 { "ring_set_send_prod_index" },
288 { "ring_status_update" },
290 { "nic_avoided_irqs" },
291 { "nic_tx_threshold_hit" }
294 static const struct {
295 const char string[ETH_GSTRING_LEN];
296 } ethtool_test_keys[TG3_NUM_TEST] = {
297 { "nvram test (online) " },
298 { "link test (online) " },
299 { "register test (offline)" },
300 { "memory test (offline)" },
301 { "loopback test (offline)" },
302 { "interrupt test (offline)" },
305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
307 writel(val, tp->regs + off);
310 static u32 tg3_read32(struct tg3 *tp, u32 off)
312 return (readl(tp->regs + off));
315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
319 spin_lock_irqsave(&tp->indirect_lock, flags);
320 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
321 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
322 spin_unlock_irqrestore(&tp->indirect_lock, flags);
325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
327 writel(val, tp->regs + off);
328 readl(tp->regs + off);
331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
336 spin_lock_irqsave(&tp->indirect_lock, flags);
337 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
338 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
339 spin_unlock_irqrestore(&tp->indirect_lock, flags);
343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
347 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
348 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
349 TG3_64BIT_REG_LOW, val);
352 if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
353 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
354 TG3_64BIT_REG_LOW, val);
358 spin_lock_irqsave(&tp->indirect_lock, flags);
359 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
360 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
361 spin_unlock_irqrestore(&tp->indirect_lock, flags);
363 /* In indirect mode when disabling interrupts, we also need
364 * to clear the interrupt bit in the GRC local ctrl register.
366 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
368 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
369 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
378 spin_lock_irqsave(&tp->indirect_lock, flags);
379 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
380 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
381 spin_unlock_irqrestore(&tp->indirect_lock, flags);
385 /* usec_wait specifies the wait time in usec when writing to certain registers
386 * where it is unsafe to read back the register without some delay.
387 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
388 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
392 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
393 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
394 /* Non-posted methods */
395 tp->write32(tp, off, val);
398 tg3_write32(tp, off, val);
403 /* Wait again after the read for the posted method to guarantee that
404 * the wait time is met.
410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
412 tp->write32_mbox(tp, off, val);
413 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
414 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
415 tp->read32_mbox(tp, off);
418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
420 void __iomem *mbox = tp->regs + off;
422 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
424 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
430 return (readl(tp->regs + off + GRCMBOX_BASE));
433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
435 writel(val, tp->regs + off + GRCMBOX_BASE);
438 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
439 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
440 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
441 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
442 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
444 #define tw32(reg,val) tp->write32(tp, reg, val)
445 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
447 #define tr32(reg) tp->read32(tp, reg)
449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
453 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
454 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
457 spin_lock_irqsave(&tp->indirect_lock, flags);
458 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
459 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
460 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
462 /* Always leave this as zero. */
463 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
465 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
466 tw32_f(TG3PCI_MEM_WIN_DATA, val);
468 /* Always leave this as zero. */
469 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
471 spin_unlock_irqrestore(&tp->indirect_lock, flags);
474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
478 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
479 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
484 spin_lock_irqsave(&tp->indirect_lock, flags);
485 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
486 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
487 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
489 /* Always leave this as zero. */
490 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
492 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
493 *val = tr32(TG3PCI_MEM_WIN_DATA);
495 /* Always leave this as zero. */
496 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
498 spin_unlock_irqrestore(&tp->indirect_lock, flags);
501 static void tg3_disable_ints(struct tg3 *tp)
503 tw32(TG3PCI_MISC_HOST_CTRL,
504 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
505 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
508 static inline void tg3_cond_int(struct tg3 *tp)
510 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
511 (tp->hw_status->status & SD_STATUS_UPDATED))
512 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
514 tw32(HOSTCC_MODE, tp->coalesce_mode |
515 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
518 static void tg3_enable_ints(struct tg3 *tp)
523 tw32(TG3PCI_MISC_HOST_CTRL,
524 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
525 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
526 (tp->last_tag << 24));
527 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
529 (tp->last_tag << 24));
533 static inline unsigned int tg3_has_work(struct tg3 *tp)
535 struct tg3_hw_status *sblk = tp->hw_status;
536 unsigned int work_exists = 0;
538 /* check for phy events */
539 if (!(tp->tg3_flags &
540 (TG3_FLAG_USE_LINKCHG_REG |
541 TG3_FLAG_POLL_SERDES))) {
542 if (sblk->status & SD_STATUS_LINK_CHG)
545 /* check for RX/TX work to do */
546 if (sblk->idx[0].tx_consumer != tp->tx_cons ||
547 sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
554 * similar to tg3_enable_ints, but it accurately determines whether there
555 * is new work pending and can return without flushing the PIO write
556 * which reenables interrupts
558 static void tg3_restart_ints(struct tg3 *tp)
560 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
564 /* When doing tagged status, this work check is unnecessary.
565 * The last_tag we write above tells the chip which piece of
566 * work we've completed.
568 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
570 tw32(HOSTCC_MODE, tp->coalesce_mode |
571 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
574 static inline void tg3_netif_stop(struct tg3 *tp)
576 tp->dev->trans_start = jiffies; /* prevent tx timeout */
577 netif_poll_disable(tp->dev);
578 netif_tx_disable(tp->dev);
581 static inline void tg3_netif_start(struct tg3 *tp)
583 netif_wake_queue(tp->dev);
584 /* NOTE: unconditional netif_wake_queue is only appropriate
585 * so long as all callers are assured to have free tx slots
586 * (such as after tg3_init_hw)
588 netif_poll_enable(tp->dev);
589 tp->hw_status->status |= SD_STATUS_UPDATED;
593 static void tg3_switch_clocks(struct tg3 *tp)
595 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
598 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
601 orig_clock_ctrl = clock_ctrl;
602 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
603 CLOCK_CTRL_CLKRUN_OENABLE |
605 tp->pci_clock_ctrl = clock_ctrl;
607 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
608 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
609 tw32_wait_f(TG3PCI_CLOCK_CTRL,
610 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
612 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
613 tw32_wait_f(TG3PCI_CLOCK_CTRL,
615 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
617 tw32_wait_f(TG3PCI_CLOCK_CTRL,
618 clock_ctrl | (CLOCK_CTRL_ALTCLK),
621 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
624 #define PHY_BUSY_LOOPS 5000
626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
632 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
634 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
640 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
641 MI_COM_PHY_ADDR_MASK);
642 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
643 MI_COM_REG_ADDR_MASK);
644 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
646 tw32_f(MAC_MI_COM, frame_val);
648 loops = PHY_BUSY_LOOPS;
651 frame_val = tr32(MAC_MI_COM);
653 if ((frame_val & MI_COM_BUSY) == 0) {
655 frame_val = tr32(MAC_MI_COM);
663 *val = frame_val & MI_COM_DATA_MASK;
667 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
668 tw32_f(MAC_MI_MODE, tp->mi_mode);
675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
682 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
685 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
687 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
691 frame_val = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
692 MI_COM_PHY_ADDR_MASK);
693 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
694 MI_COM_REG_ADDR_MASK);
695 frame_val |= (val & MI_COM_DATA_MASK);
696 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
698 tw32_f(MAC_MI_COM, frame_val);
700 loops = PHY_BUSY_LOOPS;
703 frame_val = tr32(MAC_MI_COM);
704 if ((frame_val & MI_COM_BUSY) == 0) {
706 frame_val = tr32(MAC_MI_COM);
716 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
717 tw32_f(MAC_MI_MODE, tp->mi_mode);
724 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
728 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
729 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
735 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &ephy)) {
736 tg3_writephy(tp, MII_TG3_EPHY_TEST,
737 ephy | MII_TG3_EPHY_SHADOW_EN);
738 if (!tg3_readphy(tp, MII_TG3_EPHYTST_MISCCTRL, &phy)) {
740 phy |= MII_TG3_EPHYTST_MISCCTRL_MDIX;
742 phy &= ~MII_TG3_EPHYTST_MISCCTRL_MDIX;
743 tg3_writephy(tp, MII_TG3_EPHYTST_MISCCTRL, phy);
745 tg3_writephy(tp, MII_TG3_EPHY_TEST, ephy);
748 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
749 MII_TG3_AUXCTL_SHDWSEL_MISC;
750 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
751 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
753 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
755 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
756 phy |= MII_TG3_AUXCTL_MISC_WREN;
757 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
762 static void tg3_phy_set_wirespeed(struct tg3 *tp)
766 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
769 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
770 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
771 tg3_writephy(tp, MII_TG3_AUX_CTRL,
772 (val | (1 << 15) | (1 << 4)));
775 static int tg3_bmcr_reset(struct tg3 *tp)
780 /* OK, reset it, and poll the BMCR_RESET bit until it
781 * clears or we time out.
783 phy_control = BMCR_RESET;
784 err = tg3_writephy(tp, MII_BMCR, phy_control);
790 err = tg3_readphy(tp, MII_BMCR, &phy_control);
794 if ((phy_control & BMCR_RESET) == 0) {
806 static int tg3_wait_macro_done(struct tg3 *tp)
813 if (!tg3_readphy(tp, 0x16, &tmp32)) {
814 if ((tmp32 & 0x1000) == 0)
824 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
826 static const u32 test_pat[4][6] = {
827 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
828 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
829 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
830 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
834 for (chan = 0; chan < 4; chan++) {
837 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
838 (chan * 0x2000) | 0x0200);
839 tg3_writephy(tp, 0x16, 0x0002);
841 for (i = 0; i < 6; i++)
842 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
845 tg3_writephy(tp, 0x16, 0x0202);
846 if (tg3_wait_macro_done(tp)) {
851 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
852 (chan * 0x2000) | 0x0200);
853 tg3_writephy(tp, 0x16, 0x0082);
854 if (tg3_wait_macro_done(tp)) {
859 tg3_writephy(tp, 0x16, 0x0802);
860 if (tg3_wait_macro_done(tp)) {
865 for (i = 0; i < 6; i += 2) {
868 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
869 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
870 tg3_wait_macro_done(tp)) {
876 if (low != test_pat[chan][i] ||
877 high != test_pat[chan][i+1]) {
878 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
879 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
880 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
890 static int tg3_phy_reset_chanpat(struct tg3 *tp)
894 for (chan = 0; chan < 4; chan++) {
897 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
898 (chan * 0x2000) | 0x0200);
899 tg3_writephy(tp, 0x16, 0x0002);
900 for (i = 0; i < 6; i++)
901 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
902 tg3_writephy(tp, 0x16, 0x0202);
903 if (tg3_wait_macro_done(tp))
910 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
912 u32 reg32, phy9_orig;
913 int retries, do_phy_reset, err;
919 err = tg3_bmcr_reset(tp);
925 /* Disable transmitter and interrupt. */
926 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
930 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
932 /* Set full-duplex, 1000 mbps. */
933 tg3_writephy(tp, MII_BMCR,
934 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
936 /* Set to master mode. */
937 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
940 tg3_writephy(tp, MII_TG3_CTRL,
941 (MII_TG3_CTRL_AS_MASTER |
942 MII_TG3_CTRL_ENABLE_AS_MASTER));
944 /* Enable SM_DSP_CLOCK and 6dB. */
945 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
947 /* Block the PHY control access. */
948 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
949 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
951 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
956 err = tg3_phy_reset_chanpat(tp);
960 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
961 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
963 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
964 tg3_writephy(tp, 0x16, 0x0000);
966 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
967 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
968 /* Set Extended packet length bit for jumbo frames */
969 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
975 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
977 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
979 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
986 static void tg3_link_report(struct tg3 *);
988 /* This will reset the tigon3 PHY if there is no valid
989 * link unless the FORCE argument is non-zero.
991 static int tg3_phy_reset(struct tg3 *tp)
996 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
999 val = tr32(GRC_MISC_CFG);
1000 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1003 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1004 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1008 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1009 netif_carrier_off(tp->dev);
1010 tg3_link_report(tp);
1013 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1014 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1016 err = tg3_phy_reset_5703_4_5(tp);
1022 err = tg3_bmcr_reset(tp);
1027 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1028 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1029 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1031 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1032 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1033 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1035 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1036 tg3_writephy(tp, 0x1c, 0x8d68);
1037 tg3_writephy(tp, 0x1c, 0x8d68);
1039 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1040 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1041 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1042 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1043 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1044 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1045 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1046 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1047 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1049 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1050 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1051 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1052 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1053 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1054 tg3_writephy(tp, MII_TG3_TEST1,
1055 MII_TG3_TEST1_TRIM_EN | 0x4);
1057 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1058 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1060 /* Set Extended packet length bit (bit 14) on all chips that */
1061 /* support jumbo frames */
1062 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1063 /* Cannot do read-modify-write on 5401 */
1064 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1065 } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1068 /* Set bit 14 with read-modify-write to preserve other bits */
1069 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1070 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1071 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1074 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1075 * jumbo frames transmission.
1077 if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1080 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1081 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1082 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1085 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1086 /* adjust output voltage */
1087 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1090 tg3_phy_toggle_automdix(tp, 1);
1091 tg3_phy_set_wirespeed(tp);
1095 static void tg3_frob_aux_power(struct tg3 *tp)
1097 struct tg3 *tp_peer = tp;
1099 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1102 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1103 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1104 struct net_device *dev_peer;
1106 dev_peer = pci_get_drvdata(tp->pdev_peer);
1107 /* remove_one() may have been run on the peer. */
1111 tp_peer = netdev_priv(dev_peer);
1114 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1115 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1116 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1117 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1118 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1119 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1120 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1121 (GRC_LCLCTRL_GPIO_OE0 |
1122 GRC_LCLCTRL_GPIO_OE1 |
1123 GRC_LCLCTRL_GPIO_OE2 |
1124 GRC_LCLCTRL_GPIO_OUTPUT0 |
1125 GRC_LCLCTRL_GPIO_OUTPUT1),
1129 u32 grc_local_ctrl = 0;
1131 if (tp_peer != tp &&
1132 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1135 /* Workaround to prevent overdrawing Amps. */
1136 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1138 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1139 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1140 grc_local_ctrl, 100);
1143 /* On 5753 and variants, GPIO2 cannot be used. */
1144 no_gpio2 = tp->nic_sram_data_cfg &
1145 NIC_SRAM_DATA_CFG_NO_GPIO2;
1147 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1148 GRC_LCLCTRL_GPIO_OE1 |
1149 GRC_LCLCTRL_GPIO_OE2 |
1150 GRC_LCLCTRL_GPIO_OUTPUT1 |
1151 GRC_LCLCTRL_GPIO_OUTPUT2;
1153 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1154 GRC_LCLCTRL_GPIO_OUTPUT2);
1156 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1157 grc_local_ctrl, 100);
1159 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1161 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1162 grc_local_ctrl, 100);
1165 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1166 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1167 grc_local_ctrl, 100);
1171 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1172 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1173 if (tp_peer != tp &&
1174 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1177 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1178 (GRC_LCLCTRL_GPIO_OE1 |
1179 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1181 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1182 GRC_LCLCTRL_GPIO_OE1, 100);
1184 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1185 (GRC_LCLCTRL_GPIO_OE1 |
1186 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1191 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1193 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1195 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
1196 if (speed != SPEED_10)
1198 } else if (speed == SPEED_10)
1204 static int tg3_setup_phy(struct tg3 *, int);
1206 #define RESET_KIND_SHUTDOWN 0
1207 #define RESET_KIND_INIT 1
1208 #define RESET_KIND_SUSPEND 2
1210 static void tg3_write_sig_post_reset(struct tg3 *, int);
1211 static int tg3_halt_cpu(struct tg3 *, u32);
1212 static int tg3_nvram_lock(struct tg3 *);
1213 static void tg3_nvram_unlock(struct tg3 *);
1215 static void tg3_power_down_phy(struct tg3 *tp)
1217 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1218 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1219 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1220 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1223 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1224 tw32(SG_DIG_CTRL, sg_dig_ctrl);
1225 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1230 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1234 val = tr32(GRC_MISC_CFG);
1235 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1239 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1240 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1241 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1244 /* The PHY should not be powered down on some chips because
1247 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1248 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1249 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1250 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1252 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1255 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1258 u16 power_control, power_caps;
1259 int pm = tp->pm_cap;
1261 /* Make sure register accesses (indirect or otherwise)
1262 * will function correctly.
1264 pci_write_config_dword(tp->pdev,
1265 TG3PCI_MISC_HOST_CTRL,
1266 tp->misc_host_ctrl);
1268 pci_read_config_word(tp->pdev,
1271 power_control |= PCI_PM_CTRL_PME_STATUS;
1272 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1276 pci_write_config_word(tp->pdev,
1279 udelay(100); /* Delay after power state change */
1281 /* Switch out of Vaux if it is a NIC */
1282 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1283 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1300 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1302 tp->dev->name, state);
1306 power_control |= PCI_PM_CTRL_PME_ENABLE;
1308 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1309 tw32(TG3PCI_MISC_HOST_CTRL,
1310 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1312 if (tp->link_config.phy_is_low_power == 0) {
1313 tp->link_config.phy_is_low_power = 1;
1314 tp->link_config.orig_speed = tp->link_config.speed;
1315 tp->link_config.orig_duplex = tp->link_config.duplex;
1316 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1319 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1320 tp->link_config.speed = SPEED_10;
1321 tp->link_config.duplex = DUPLEX_HALF;
1322 tp->link_config.autoneg = AUTONEG_ENABLE;
1323 tg3_setup_phy(tp, 0);
1326 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1329 val = tr32(GRC_VCPU_EXT_CTRL);
1330 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1331 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1335 for (i = 0; i < 200; i++) {
1336 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1337 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1342 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1343 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1344 WOL_DRV_STATE_SHUTDOWN |
1348 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1350 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1353 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1354 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1357 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1358 mac_mode = MAC_MODE_PORT_MODE_GMII;
1360 mac_mode = MAC_MODE_PORT_MODE_MII;
1362 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
1363 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1365 u32 speed = (tp->tg3_flags &
1366 TG3_FLAG_WOL_SPEED_100MB) ?
1367 SPEED_100 : SPEED_10;
1368 if (tg3_5700_link_polarity(tp, speed))
1369 mac_mode |= MAC_MODE_LINK_POLARITY;
1371 mac_mode &= ~MAC_MODE_LINK_POLARITY;
1374 mac_mode = MAC_MODE_PORT_MODE_TBI;
1377 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1378 tw32(MAC_LED_CTRL, tp->led_ctrl);
1380 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1381 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1382 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1384 tw32_f(MAC_MODE, mac_mode);
1387 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1391 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1392 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1393 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1396 base_val = tp->pci_clock_ctrl;
1397 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1398 CLOCK_CTRL_TXCLK_DISABLE);
1400 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1401 CLOCK_CTRL_PWRDOWN_PLL133, 40);
1402 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1403 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1405 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1406 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1407 u32 newbits1, newbits2;
1409 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1410 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1411 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1412 CLOCK_CTRL_TXCLK_DISABLE |
1414 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1415 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1416 newbits1 = CLOCK_CTRL_625_CORE;
1417 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1419 newbits1 = CLOCK_CTRL_ALTCLK;
1420 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1423 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1426 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1429 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1433 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1434 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1435 CLOCK_CTRL_TXCLK_DISABLE |
1436 CLOCK_CTRL_44MHZ_CORE);
1438 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1441 tw32_wait_f(TG3PCI_CLOCK_CTRL,
1442 tp->pci_clock_ctrl | newbits3, 40);
1446 if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1447 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1448 tg3_power_down_phy(tp);
1450 tg3_frob_aux_power(tp);
1452 /* Workaround for unstable PLL clock */
1453 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1454 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1455 u32 val = tr32(0x7d00);
1457 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1459 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1462 err = tg3_nvram_lock(tp);
1463 tg3_halt_cpu(tp, RX_CPU_BASE);
1465 tg3_nvram_unlock(tp);
1469 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1471 /* Finally, set the new power state. */
1472 pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1473 udelay(100); /* Delay after power state change */
1478 static void tg3_link_report(struct tg3 *tp)
1480 if (!netif_carrier_ok(tp->dev)) {
1481 if (netif_msg_link(tp))
1482 printk(KERN_INFO PFX "%s: Link is down.\n",
1484 } else if (netif_msg_link(tp)) {
1485 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1487 (tp->link_config.active_speed == SPEED_1000 ?
1489 (tp->link_config.active_speed == SPEED_100 ?
1491 (tp->link_config.active_duplex == DUPLEX_FULL ?
1494 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1497 (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1498 (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1502 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1504 u32 new_tg3_flags = 0;
1505 u32 old_rx_mode = tp->rx_mode;
1506 u32 old_tx_mode = tp->tx_mode;
1508 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1510 /* Convert 1000BaseX flow control bits to 1000BaseT
1511 * bits before resolving flow control.
1513 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1514 local_adv &= ~(ADVERTISE_PAUSE_CAP |
1515 ADVERTISE_PAUSE_ASYM);
1516 remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1518 if (local_adv & ADVERTISE_1000XPAUSE)
1519 local_adv |= ADVERTISE_PAUSE_CAP;
1520 if (local_adv & ADVERTISE_1000XPSE_ASYM)
1521 local_adv |= ADVERTISE_PAUSE_ASYM;
1522 if (remote_adv & LPA_1000XPAUSE)
1523 remote_adv |= LPA_PAUSE_CAP;
1524 if (remote_adv & LPA_1000XPAUSE_ASYM)
1525 remote_adv |= LPA_PAUSE_ASYM;
1528 if (local_adv & ADVERTISE_PAUSE_CAP) {
1529 if (local_adv & ADVERTISE_PAUSE_ASYM) {
1530 if (remote_adv & LPA_PAUSE_CAP)
1532 (TG3_FLAG_RX_PAUSE |
1534 else if (remote_adv & LPA_PAUSE_ASYM)
1536 (TG3_FLAG_RX_PAUSE);
1538 if (remote_adv & LPA_PAUSE_CAP)
1540 (TG3_FLAG_RX_PAUSE |
1543 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1544 if ((remote_adv & LPA_PAUSE_CAP) &&
1545 (remote_adv & LPA_PAUSE_ASYM))
1546 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1549 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1550 tp->tg3_flags |= new_tg3_flags;
1552 new_tg3_flags = tp->tg3_flags;
1555 if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1556 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1558 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1560 if (old_rx_mode != tp->rx_mode) {
1561 tw32_f(MAC_RX_MODE, tp->rx_mode);
1564 if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1565 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1567 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1569 if (old_tx_mode != tp->tx_mode) {
1570 tw32_f(MAC_TX_MODE, tp->tx_mode);
1574 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1576 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1577 case MII_TG3_AUX_STAT_10HALF:
1579 *duplex = DUPLEX_HALF;
1582 case MII_TG3_AUX_STAT_10FULL:
1584 *duplex = DUPLEX_FULL;
1587 case MII_TG3_AUX_STAT_100HALF:
1589 *duplex = DUPLEX_HALF;
1592 case MII_TG3_AUX_STAT_100FULL:
1594 *duplex = DUPLEX_FULL;
1597 case MII_TG3_AUX_STAT_1000HALF:
1598 *speed = SPEED_1000;
1599 *duplex = DUPLEX_HALF;
1602 case MII_TG3_AUX_STAT_1000FULL:
1603 *speed = SPEED_1000;
1604 *duplex = DUPLEX_FULL;
1608 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1609 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1611 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1615 *speed = SPEED_INVALID;
1616 *duplex = DUPLEX_INVALID;
1621 static void tg3_phy_copper_begin(struct tg3 *tp)
1626 if (tp->link_config.phy_is_low_power) {
1627 /* Entering low power mode. Disable gigabit and
1628 * 100baseT advertisements.
1630 tg3_writephy(tp, MII_TG3_CTRL, 0);
1632 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1633 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1634 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1635 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1637 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1638 } else if (tp->link_config.speed == SPEED_INVALID) {
1639 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1640 tp->link_config.advertising &=
1641 ~(ADVERTISED_1000baseT_Half |
1642 ADVERTISED_1000baseT_Full);
1644 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1645 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1646 new_adv |= ADVERTISE_10HALF;
1647 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1648 new_adv |= ADVERTISE_10FULL;
1649 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1650 new_adv |= ADVERTISE_100HALF;
1651 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1652 new_adv |= ADVERTISE_100FULL;
1653 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1655 if (tp->link_config.advertising &
1656 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1658 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1659 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1660 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1661 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1662 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1663 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1664 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1665 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1666 MII_TG3_CTRL_ENABLE_AS_MASTER);
1667 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1669 tg3_writephy(tp, MII_TG3_CTRL, 0);
1672 /* Asking for a specific link mode. */
1673 if (tp->link_config.speed == SPEED_1000) {
1674 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1675 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1677 if (tp->link_config.duplex == DUPLEX_FULL)
1678 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1680 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1681 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1682 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1683 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1684 MII_TG3_CTRL_ENABLE_AS_MASTER);
1685 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1687 tg3_writephy(tp, MII_TG3_CTRL, 0);
1689 new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1690 if (tp->link_config.speed == SPEED_100) {
1691 if (tp->link_config.duplex == DUPLEX_FULL)
1692 new_adv |= ADVERTISE_100FULL;
1694 new_adv |= ADVERTISE_100HALF;
1696 if (tp->link_config.duplex == DUPLEX_FULL)
1697 new_adv |= ADVERTISE_10FULL;
1699 new_adv |= ADVERTISE_10HALF;
1701 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1705 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1706 tp->link_config.speed != SPEED_INVALID) {
1707 u32 bmcr, orig_bmcr;
1709 tp->link_config.active_speed = tp->link_config.speed;
1710 tp->link_config.active_duplex = tp->link_config.duplex;
1713 switch (tp->link_config.speed) {
1719 bmcr |= BMCR_SPEED100;
1723 bmcr |= TG3_BMCR_SPEED1000;
1727 if (tp->link_config.duplex == DUPLEX_FULL)
1728 bmcr |= BMCR_FULLDPLX;
1730 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1731 (bmcr != orig_bmcr)) {
1732 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1733 for (i = 0; i < 1500; i++) {
1737 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1738 tg3_readphy(tp, MII_BMSR, &tmp))
1740 if (!(tmp & BMSR_LSTATUS)) {
1745 tg3_writephy(tp, MII_BMCR, bmcr);
1749 tg3_writephy(tp, MII_BMCR,
1750 BMCR_ANENABLE | BMCR_ANRESTART);
1754 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1758 /* Turn off tap power management. */
1759 /* Set Extended packet length bit */
1760 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1762 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1763 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1765 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1766 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1768 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1769 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1771 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1772 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1774 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1775 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1782 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1784 u32 adv_reg, all_mask = 0;
1786 if (mask & ADVERTISED_10baseT_Half)
1787 all_mask |= ADVERTISE_10HALF;
1788 if (mask & ADVERTISED_10baseT_Full)
1789 all_mask |= ADVERTISE_10FULL;
1790 if (mask & ADVERTISED_100baseT_Half)
1791 all_mask |= ADVERTISE_100HALF;
1792 if (mask & ADVERTISED_100baseT_Full)
1793 all_mask |= ADVERTISE_100FULL;
1795 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1798 if ((adv_reg & all_mask) != all_mask)
1800 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1804 if (mask & ADVERTISED_1000baseT_Half)
1805 all_mask |= ADVERTISE_1000HALF;
1806 if (mask & ADVERTISED_1000baseT_Full)
1807 all_mask |= ADVERTISE_1000FULL;
1809 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1812 if ((tg3_ctrl & all_mask) != all_mask)
1818 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1820 int current_link_up;
1829 (MAC_STATUS_SYNC_CHANGED |
1830 MAC_STATUS_CFG_CHANGED |
1831 MAC_STATUS_MI_COMPLETION |
1832 MAC_STATUS_LNKSTATE_CHANGED));
1835 tp->mi_mode = MAC_MI_MODE_BASE;
1836 tw32_f(MAC_MI_MODE, tp->mi_mode);
1839 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1841 /* Some third-party PHYs need to be reset on link going
1844 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1845 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1846 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1847 netif_carrier_ok(tp->dev)) {
1848 tg3_readphy(tp, MII_BMSR, &bmsr);
1849 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1850 !(bmsr & BMSR_LSTATUS))
1856 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1857 tg3_readphy(tp, MII_BMSR, &bmsr);
1858 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1859 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1862 if (!(bmsr & BMSR_LSTATUS)) {
1863 err = tg3_init_5401phy_dsp(tp);
1867 tg3_readphy(tp, MII_BMSR, &bmsr);
1868 for (i = 0; i < 1000; i++) {
1870 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1871 (bmsr & BMSR_LSTATUS)) {
1877 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1878 !(bmsr & BMSR_LSTATUS) &&
1879 tp->link_config.active_speed == SPEED_1000) {
1880 err = tg3_phy_reset(tp);
1882 err = tg3_init_5401phy_dsp(tp);
1887 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1888 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1889 /* 5701 {A0,B0} CRC bug workaround */
1890 tg3_writephy(tp, 0x15, 0x0a75);
1891 tg3_writephy(tp, 0x1c, 0x8c68);
1892 tg3_writephy(tp, 0x1c, 0x8d68);
1893 tg3_writephy(tp, 0x1c, 0x8c68);
1896 /* Clear pending interrupts... */
1897 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1898 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1900 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1901 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1902 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1903 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1905 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1906 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1907 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1908 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1909 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1911 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1914 current_link_up = 0;
1915 current_speed = SPEED_INVALID;
1916 current_duplex = DUPLEX_INVALID;
1918 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1921 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1922 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1923 if (!(val & (1 << 10))) {
1925 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1931 for (i = 0; i < 100; i++) {
1932 tg3_readphy(tp, MII_BMSR, &bmsr);
1933 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1934 (bmsr & BMSR_LSTATUS))
1939 if (bmsr & BMSR_LSTATUS) {
1942 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1943 for (i = 0; i < 2000; i++) {
1945 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1950 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1955 for (i = 0; i < 200; i++) {
1956 tg3_readphy(tp, MII_BMCR, &bmcr);
1957 if (tg3_readphy(tp, MII_BMCR, &bmcr))
1959 if (bmcr && bmcr != 0x7fff)
1964 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1965 if (bmcr & BMCR_ANENABLE) {
1966 current_link_up = 1;
1968 /* Force autoneg restart if we are exiting
1971 if (!tg3_copper_is_advertising_all(tp,
1972 tp->link_config.advertising))
1973 current_link_up = 0;
1975 current_link_up = 0;
1978 if (!(bmcr & BMCR_ANENABLE) &&
1979 tp->link_config.speed == current_speed &&
1980 tp->link_config.duplex == current_duplex) {
1981 current_link_up = 1;
1983 current_link_up = 0;
1987 tp->link_config.active_speed = current_speed;
1988 tp->link_config.active_duplex = current_duplex;
1991 if (current_link_up == 1 &&
1992 (tp->link_config.active_duplex == DUPLEX_FULL) &&
1993 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1994 u32 local_adv, remote_adv;
1996 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1998 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
2000 if (tg3_readphy(tp, MII_LPA, &remote_adv))
2003 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
2005 /* If we are not advertising full pause capability,
2006 * something is wrong. Bring the link down and reconfigure.
2008 if (local_adv != ADVERTISE_PAUSE_CAP) {
2009 current_link_up = 0;
2011 tg3_setup_flow_control(tp, local_adv, remote_adv);
2015 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
2018 tg3_phy_copper_begin(tp);
2020 tg3_readphy(tp, MII_BMSR, &tmp);
2021 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
2022 (tmp & BMSR_LSTATUS))
2023 current_link_up = 1;
2026 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
2027 if (current_link_up == 1) {
2028 if (tp->link_config.active_speed == SPEED_100 ||
2029 tp->link_config.active_speed == SPEED_10)
2030 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
2032 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2034 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2036 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2037 if (tp->link_config.active_duplex == DUPLEX_HALF)
2038 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2040 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
2041 if (current_link_up == 1 &&
2042 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
2043 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2045 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2048 /* ??? Without this setting Netgear GA302T PHY does not
2049 * ??? send/receive packets...
2051 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2052 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2053 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2054 tw32_f(MAC_MI_MODE, tp->mi_mode);
2058 tw32_f(MAC_MODE, tp->mac_mode);
2061 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2062 /* Polled via timer. */
2063 tw32_f(MAC_EVENT, 0);
2065 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2069 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2070 current_link_up == 1 &&
2071 tp->link_config.active_speed == SPEED_1000 &&
2072 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2073 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2076 (MAC_STATUS_SYNC_CHANGED |
2077 MAC_STATUS_CFG_CHANGED));
2080 NIC_SRAM_FIRMWARE_MBOX,
2081 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2084 if (current_link_up != netif_carrier_ok(tp->dev)) {
2085 if (current_link_up)
2086 netif_carrier_on(tp->dev);
2088 netif_carrier_off(tp->dev);
2089 tg3_link_report(tp);
2095 struct tg3_fiber_aneginfo {
2097 #define ANEG_STATE_UNKNOWN 0
2098 #define ANEG_STATE_AN_ENABLE 1
2099 #define ANEG_STATE_RESTART_INIT 2
2100 #define ANEG_STATE_RESTART 3
2101 #define ANEG_STATE_DISABLE_LINK_OK 4
2102 #define ANEG_STATE_ABILITY_DETECT_INIT 5
2103 #define ANEG_STATE_ABILITY_DETECT 6
2104 #define ANEG_STATE_ACK_DETECT_INIT 7
2105 #define ANEG_STATE_ACK_DETECT 8
2106 #define ANEG_STATE_COMPLETE_ACK_INIT 9
2107 #define ANEG_STATE_COMPLETE_ACK 10
2108 #define ANEG_STATE_IDLE_DETECT_INIT 11
2109 #define ANEG_STATE_IDLE_DETECT 12
2110 #define ANEG_STATE_LINK_OK 13
2111 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
2112 #define ANEG_STATE_NEXT_PAGE_WAIT 15
2115 #define MR_AN_ENABLE 0x00000001
2116 #define MR_RESTART_AN 0x00000002
2117 #define MR_AN_COMPLETE 0x00000004
2118 #define MR_PAGE_RX 0x00000008
2119 #define MR_NP_LOADED 0x00000010
2120 #define MR_TOGGLE_TX 0x00000020
2121 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
2122 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
2123 #define MR_LP_ADV_SYM_PAUSE 0x00000100
2124 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
2125 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2126 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2127 #define MR_LP_ADV_NEXT_PAGE 0x00001000
2128 #define MR_TOGGLE_RX 0x00002000
2129 #define MR_NP_RX 0x00004000
2131 #define MR_LINK_OK 0x80000000
2133 unsigned long link_time, cur_time;
2135 u32 ability_match_cfg;
2136 int ability_match_count;
2138 char ability_match, idle_match, ack_match;
2140 u32 txconfig, rxconfig;
2141 #define ANEG_CFG_NP 0x00000080
2142 #define ANEG_CFG_ACK 0x00000040
2143 #define ANEG_CFG_RF2 0x00000020
2144 #define ANEG_CFG_RF1 0x00000010
2145 #define ANEG_CFG_PS2 0x00000001
2146 #define ANEG_CFG_PS1 0x00008000
2147 #define ANEG_CFG_HD 0x00004000
2148 #define ANEG_CFG_FD 0x00002000
2149 #define ANEG_CFG_INVAL 0x00001f06
2154 #define ANEG_TIMER_ENAB 2
2155 #define ANEG_FAILED -1
2157 #define ANEG_STATE_SETTLE_TIME 10000
2159 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2160 struct tg3_fiber_aneginfo *ap)
2162 unsigned long delta;
2166 if (ap->state == ANEG_STATE_UNKNOWN) {
2170 ap->ability_match_cfg = 0;
2171 ap->ability_match_count = 0;
2172 ap->ability_match = 0;
2178 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2179 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2181 if (rx_cfg_reg != ap->ability_match_cfg) {
2182 ap->ability_match_cfg = rx_cfg_reg;
2183 ap->ability_match = 0;
2184 ap->ability_match_count = 0;
2186 if (++ap->ability_match_count > 1) {
2187 ap->ability_match = 1;
2188 ap->ability_match_cfg = rx_cfg_reg;
2191 if (rx_cfg_reg & ANEG_CFG_ACK)
2199 ap->ability_match_cfg = 0;
2200 ap->ability_match_count = 0;
2201 ap->ability_match = 0;
2207 ap->rxconfig = rx_cfg_reg;
2211 case ANEG_STATE_UNKNOWN:
2212 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2213 ap->state = ANEG_STATE_AN_ENABLE;
2216 case ANEG_STATE_AN_ENABLE:
2217 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2218 if (ap->flags & MR_AN_ENABLE) {
2221 ap->ability_match_cfg = 0;
2222 ap->ability_match_count = 0;
2223 ap->ability_match = 0;
2227 ap->state = ANEG_STATE_RESTART_INIT;
2229 ap->state = ANEG_STATE_DISABLE_LINK_OK;
2233 case ANEG_STATE_RESTART_INIT:
2234 ap->link_time = ap->cur_time;
2235 ap->flags &= ~(MR_NP_LOADED);
2237 tw32(MAC_TX_AUTO_NEG, 0);
2238 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2239 tw32_f(MAC_MODE, tp->mac_mode);
2242 ret = ANEG_TIMER_ENAB;
2243 ap->state = ANEG_STATE_RESTART;
2246 case ANEG_STATE_RESTART:
2247 delta = ap->cur_time - ap->link_time;
2248 if (delta > ANEG_STATE_SETTLE_TIME) {
2249 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2251 ret = ANEG_TIMER_ENAB;
2255 case ANEG_STATE_DISABLE_LINK_OK:
2259 case ANEG_STATE_ABILITY_DETECT_INIT:
2260 ap->flags &= ~(MR_TOGGLE_TX);
2261 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2262 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2263 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2264 tw32_f(MAC_MODE, tp->mac_mode);
2267 ap->state = ANEG_STATE_ABILITY_DETECT;
2270 case ANEG_STATE_ABILITY_DETECT:
2271 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2272 ap->state = ANEG_STATE_ACK_DETECT_INIT;
2276 case ANEG_STATE_ACK_DETECT_INIT:
2277 ap->txconfig |= ANEG_CFG_ACK;
2278 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2279 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2280 tw32_f(MAC_MODE, tp->mac_mode);
2283 ap->state = ANEG_STATE_ACK_DETECT;
2286 case ANEG_STATE_ACK_DETECT:
2287 if (ap->ack_match != 0) {
2288 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2289 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2290 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2292 ap->state = ANEG_STATE_AN_ENABLE;
2294 } else if (ap->ability_match != 0 &&
2295 ap->rxconfig == 0) {
2296 ap->state = ANEG_STATE_AN_ENABLE;
2300 case ANEG_STATE_COMPLETE_ACK_INIT:
2301 if (ap->rxconfig & ANEG_CFG_INVAL) {
2305 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2306 MR_LP_ADV_HALF_DUPLEX |
2307 MR_LP_ADV_SYM_PAUSE |
2308 MR_LP_ADV_ASYM_PAUSE |
2309 MR_LP_ADV_REMOTE_FAULT1 |
2310 MR_LP_ADV_REMOTE_FAULT2 |
2311 MR_LP_ADV_NEXT_PAGE |
2314 if (ap->rxconfig & ANEG_CFG_FD)
2315 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2316 if (ap->rxconfig & ANEG_CFG_HD)
2317 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2318 if (ap->rxconfig & ANEG_CFG_PS1)
2319 ap->flags |= MR_LP_ADV_SYM_PAUSE;
2320 if (ap->rxconfig & ANEG_CFG_PS2)
2321 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2322 if (ap->rxconfig & ANEG_CFG_RF1)
2323 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2324 if (ap->rxconfig & ANEG_CFG_RF2)
2325 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2326 if (ap->rxconfig & ANEG_CFG_NP)
2327 ap->flags |= MR_LP_ADV_NEXT_PAGE;
2329 ap->link_time = ap->cur_time;
2331 ap->flags ^= (MR_TOGGLE_TX);
2332 if (ap->rxconfig & 0x0008)
2333 ap->flags |= MR_TOGGLE_RX;
2334 if (ap->rxconfig & ANEG_CFG_NP)
2335 ap->flags |= MR_NP_RX;
2336 ap->flags |= MR_PAGE_RX;
2338 ap->state = ANEG_STATE_COMPLETE_ACK;
2339 ret = ANEG_TIMER_ENAB;
2342 case ANEG_STATE_COMPLETE_ACK:
2343 if (ap->ability_match != 0 &&
2344 ap->rxconfig == 0) {
2345 ap->state = ANEG_STATE_AN_ENABLE;
2348 delta = ap->cur_time - ap->link_time;
2349 if (delta > ANEG_STATE_SETTLE_TIME) {
2350 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2351 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2353 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2354 !(ap->flags & MR_NP_RX)) {
2355 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2363 case ANEG_STATE_IDLE_DETECT_INIT:
2364 ap->link_time = ap->cur_time;
2365 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2366 tw32_f(MAC_MODE, tp->mac_mode);
2369 ap->state = ANEG_STATE_IDLE_DETECT;
2370 ret = ANEG_TIMER_ENAB;
2373 case ANEG_STATE_IDLE_DETECT:
2374 if (ap->ability_match != 0 &&
2375 ap->rxconfig == 0) {
2376 ap->state = ANEG_STATE_AN_ENABLE;
2379 delta = ap->cur_time - ap->link_time;
2380 if (delta > ANEG_STATE_SETTLE_TIME) {
2381 /* XXX another gem from the Broadcom driver :( */
2382 ap->state = ANEG_STATE_LINK_OK;
2386 case ANEG_STATE_LINK_OK:
2387 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2391 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2392 /* ??? unimplemented */
2395 case ANEG_STATE_NEXT_PAGE_WAIT:
2396 /* ??? unimplemented */
2407 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2410 struct tg3_fiber_aneginfo aninfo;
2411 int status = ANEG_FAILED;
2415 tw32_f(MAC_TX_AUTO_NEG, 0);
2417 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2418 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2421 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2424 memset(&aninfo, 0, sizeof(aninfo));
2425 aninfo.flags |= MR_AN_ENABLE;
2426 aninfo.state = ANEG_STATE_UNKNOWN;
2427 aninfo.cur_time = 0;
2429 while (++tick < 195000) {
2430 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2431 if (status == ANEG_DONE || status == ANEG_FAILED)
2437 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2438 tw32_f(MAC_MODE, tp->mac_mode);
2441 *flags = aninfo.flags;
2443 if (status == ANEG_DONE &&
2444 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2445 MR_LP_ADV_FULL_DUPLEX)))
2451 static void tg3_init_bcm8002(struct tg3 *tp)
2453 u32 mac_status = tr32(MAC_STATUS);
2456 /* Reset when initting first time or we have a link. */
2457 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2458 !(mac_status & MAC_STATUS_PCS_SYNCED))
2461 /* Set PLL lock range. */
2462 tg3_writephy(tp, 0x16, 0x8007);
2465 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2467 /* Wait for reset to complete. */
2468 /* XXX schedule_timeout() ... */
2469 for (i = 0; i < 500; i++)
2472 /* Config mode; select PMA/Ch 1 regs. */
2473 tg3_writephy(tp, 0x10, 0x8411);
2475 /* Enable auto-lock and comdet, select txclk for tx. */
2476 tg3_writephy(tp, 0x11, 0x0a10);
2478 tg3_writephy(tp, 0x18, 0x00a0);
2479 tg3_writephy(tp, 0x16, 0x41ff);
2481 /* Assert and deassert POR. */
2482 tg3_writephy(tp, 0x13, 0x0400);
2484 tg3_writephy(tp, 0x13, 0x0000);
2486 tg3_writephy(tp, 0x11, 0x0a50);
2488 tg3_writephy(tp, 0x11, 0x0a10);
2490 /* Wait for signal to stabilize */
2491 /* XXX schedule_timeout() ... */
2492 for (i = 0; i < 15000; i++)
2495 /* Deselect the channel register so we can read the PHYID
2498 tg3_writephy(tp, 0x10, 0x8011);
2501 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2503 u32 sg_dig_ctrl, sg_dig_status;
2504 u32 serdes_cfg, expected_sg_dig_ctrl;
2505 int workaround, port_a;
2506 int current_link_up;
2509 expected_sg_dig_ctrl = 0;
2512 current_link_up = 0;
2514 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2515 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2517 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2520 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2521 /* preserve bits 20-23 for voltage regulator */
2522 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2525 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2527 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2528 if (sg_dig_ctrl & (1 << 31)) {
2530 u32 val = serdes_cfg;
2536 tw32_f(MAC_SERDES_CFG, val);
2538 tw32_f(SG_DIG_CTRL, 0x01388400);
2540 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2541 tg3_setup_flow_control(tp, 0, 0);
2542 current_link_up = 1;
2547 /* Want auto-negotiation. */
2548 expected_sg_dig_ctrl = 0x81388400;
2550 /* Pause capability */
2551 expected_sg_dig_ctrl |= (1 << 11);
2553 /* Asymettric pause */
2554 expected_sg_dig_ctrl |= (1 << 12);
2556 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2557 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2558 tp->serdes_counter &&
2559 ((mac_status & (MAC_STATUS_PCS_SYNCED |
2560 MAC_STATUS_RCVD_CFG)) ==
2561 MAC_STATUS_PCS_SYNCED)) {
2562 tp->serdes_counter--;
2563 current_link_up = 1;
2568 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2569 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2571 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2573 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2574 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2575 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2576 MAC_STATUS_SIGNAL_DET)) {
2577 sg_dig_status = tr32(SG_DIG_STATUS);
2578 mac_status = tr32(MAC_STATUS);
2580 if ((sg_dig_status & (1 << 1)) &&
2581 (mac_status & MAC_STATUS_PCS_SYNCED)) {
2582 u32 local_adv, remote_adv;
2584 local_adv = ADVERTISE_PAUSE_CAP;
2586 if (sg_dig_status & (1 << 19))
2587 remote_adv |= LPA_PAUSE_CAP;
2588 if (sg_dig_status & (1 << 20))
2589 remote_adv |= LPA_PAUSE_ASYM;
2591 tg3_setup_flow_control(tp, local_adv, remote_adv);
2592 current_link_up = 1;
2593 tp->serdes_counter = 0;
2594 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2595 } else if (!(sg_dig_status & (1 << 1))) {
2596 if (tp->serdes_counter)
2597 tp->serdes_counter--;
2600 u32 val = serdes_cfg;
2607 tw32_f(MAC_SERDES_CFG, val);
2610 tw32_f(SG_DIG_CTRL, 0x01388400);
2613 /* Link parallel detection - link is up */
2614 /* only if we have PCS_SYNC and not */
2615 /* receiving config code words */
2616 mac_status = tr32(MAC_STATUS);
2617 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2618 !(mac_status & MAC_STATUS_RCVD_CFG)) {
2619 tg3_setup_flow_control(tp, 0, 0);
2620 current_link_up = 1;
2622 TG3_FLG2_PARALLEL_DETECT;
2623 tp->serdes_counter =
2624 SERDES_PARALLEL_DET_TIMEOUT;
2626 goto restart_autoneg;
2630 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2631 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2635 return current_link_up;
2638 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2640 int current_link_up = 0;
2642 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
2645 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2649 if (fiber_autoneg(tp, &flags)) {
2650 u32 local_adv, remote_adv;
2652 local_adv = ADVERTISE_PAUSE_CAP;
2654 if (flags & MR_LP_ADV_SYM_PAUSE)
2655 remote_adv |= LPA_PAUSE_CAP;
2656 if (flags & MR_LP_ADV_ASYM_PAUSE)
2657 remote_adv |= LPA_PAUSE_ASYM;
2659 tg3_setup_flow_control(tp, local_adv, remote_adv);
2661 current_link_up = 1;
2663 for (i = 0; i < 30; i++) {
2666 (MAC_STATUS_SYNC_CHANGED |
2667 MAC_STATUS_CFG_CHANGED));
2669 if ((tr32(MAC_STATUS) &
2670 (MAC_STATUS_SYNC_CHANGED |
2671 MAC_STATUS_CFG_CHANGED)) == 0)
2675 mac_status = tr32(MAC_STATUS);
2676 if (current_link_up == 0 &&
2677 (mac_status & MAC_STATUS_PCS_SYNCED) &&
2678 !(mac_status & MAC_STATUS_RCVD_CFG))
2679 current_link_up = 1;
2681 /* Forcing 1000FD link up. */
2682 current_link_up = 1;
2684 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2687 tw32_f(MAC_MODE, tp->mac_mode);
2692 return current_link_up;
2695 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2698 u16 orig_active_speed;
2699 u8 orig_active_duplex;
2701 int current_link_up;
2705 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2706 TG3_FLAG_TX_PAUSE));
2707 orig_active_speed = tp->link_config.active_speed;
2708 orig_active_duplex = tp->link_config.active_duplex;
2710 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2711 netif_carrier_ok(tp->dev) &&
2712 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2713 mac_status = tr32(MAC_STATUS);
2714 mac_status &= (MAC_STATUS_PCS_SYNCED |
2715 MAC_STATUS_SIGNAL_DET |
2716 MAC_STATUS_CFG_CHANGED |
2717 MAC_STATUS_RCVD_CFG);
2718 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2719 MAC_STATUS_SIGNAL_DET)) {
2720 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2721 MAC_STATUS_CFG_CHANGED));
2726 tw32_f(MAC_TX_AUTO_NEG, 0);
2728 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2729 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2730 tw32_f(MAC_MODE, tp->mac_mode);
2733 if (tp->phy_id == PHY_ID_BCM8002)
2734 tg3_init_bcm8002(tp);
2736 /* Enable link change event even when serdes polling. */
2737 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2740 current_link_up = 0;
2741 mac_status = tr32(MAC_STATUS);
2743 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2744 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2746 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2748 tp->hw_status->status =
2749 (SD_STATUS_UPDATED |
2750 (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2752 for (i = 0; i < 100; i++) {
2753 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2754 MAC_STATUS_CFG_CHANGED));
2756 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2757 MAC_STATUS_CFG_CHANGED |
2758 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2762 mac_status = tr32(MAC_STATUS);
2763 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2764 current_link_up = 0;
2765 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2766 tp->serdes_counter == 0) {
2767 tw32_f(MAC_MODE, (tp->mac_mode |
2768 MAC_MODE_SEND_CONFIGS));
2770 tw32_f(MAC_MODE, tp->mac_mode);
2774 if (current_link_up == 1) {
2775 tp->link_config.active_speed = SPEED_1000;
2776 tp->link_config.active_duplex = DUPLEX_FULL;
2777 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2778 LED_CTRL_LNKLED_OVERRIDE |
2779 LED_CTRL_1000MBPS_ON));
2781 tp->link_config.active_speed = SPEED_INVALID;
2782 tp->link_config.active_duplex = DUPLEX_INVALID;
2783 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2784 LED_CTRL_LNKLED_OVERRIDE |
2785 LED_CTRL_TRAFFIC_OVERRIDE));
2788 if (current_link_up != netif_carrier_ok(tp->dev)) {
2789 if (current_link_up)
2790 netif_carrier_on(tp->dev);
2792 netif_carrier_off(tp->dev);
2793 tg3_link_report(tp);
2796 tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2798 if (orig_pause_cfg != now_pause_cfg ||
2799 orig_active_speed != tp->link_config.active_speed ||
2800 orig_active_duplex != tp->link_config.active_duplex)
2801 tg3_link_report(tp);
2807 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2809 int current_link_up, err = 0;
2814 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2815 tw32_f(MAC_MODE, tp->mac_mode);
2821 (MAC_STATUS_SYNC_CHANGED |
2822 MAC_STATUS_CFG_CHANGED |
2823 MAC_STATUS_MI_COMPLETION |
2824 MAC_STATUS_LNKSTATE_CHANGED));
2830 current_link_up = 0;
2831 current_speed = SPEED_INVALID;
2832 current_duplex = DUPLEX_INVALID;
2834 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2835 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2836 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2837 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2838 bmsr |= BMSR_LSTATUS;
2840 bmsr &= ~BMSR_LSTATUS;
2843 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2845 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2846 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2847 /* do nothing, just check for link up at the end */
2848 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2851 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2852 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2853 ADVERTISE_1000XPAUSE |
2854 ADVERTISE_1000XPSE_ASYM |
2857 /* Always advertise symmetric PAUSE just like copper */
2858 new_adv |= ADVERTISE_1000XPAUSE;
2860 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2861 new_adv |= ADVERTISE_1000XHALF;
2862 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2863 new_adv |= ADVERTISE_1000XFULL;
2865 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2866 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2867 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2868 tg3_writephy(tp, MII_BMCR, bmcr);
2870 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2871 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2872 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2879 bmcr &= ~BMCR_SPEED1000;
2880 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2882 if (tp->link_config.duplex == DUPLEX_FULL)
2883 new_bmcr |= BMCR_FULLDPLX;
2885 if (new_bmcr != bmcr) {
2886 /* BMCR_SPEED1000 is a reserved bit that needs
2887 * to be set on write.
2889 new_bmcr |= BMCR_SPEED1000;
2891 /* Force a linkdown */
2892 if (netif_carrier_ok(tp->dev)) {
2895 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2896 adv &= ~(ADVERTISE_1000XFULL |
2897 ADVERTISE_1000XHALF |
2899 tg3_writephy(tp, MII_ADVERTISE, adv);
2900 tg3_writephy(tp, MII_BMCR, bmcr |
2904 netif_carrier_off(tp->dev);
2906 tg3_writephy(tp, MII_BMCR, new_bmcr);
2908 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2909 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2910 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2912 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2913 bmsr |= BMSR_LSTATUS;
2915 bmsr &= ~BMSR_LSTATUS;
2917 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2921 if (bmsr & BMSR_LSTATUS) {
2922 current_speed = SPEED_1000;
2923 current_link_up = 1;
2924 if (bmcr & BMCR_FULLDPLX)
2925 current_duplex = DUPLEX_FULL;
2927 current_duplex = DUPLEX_HALF;
2929 if (bmcr & BMCR_ANENABLE) {
2930 u32 local_adv, remote_adv, common;
2932 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2933 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2934 common = local_adv & remote_adv;
2935 if (common & (ADVERTISE_1000XHALF |
2936 ADVERTISE_1000XFULL)) {
2937 if (common & ADVERTISE_1000XFULL)
2938 current_duplex = DUPLEX_FULL;
2940 current_duplex = DUPLEX_HALF;
2942 tg3_setup_flow_control(tp, local_adv,
2946 current_link_up = 0;
2950 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2951 if (tp->link_config.active_duplex == DUPLEX_HALF)
2952 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2954 tw32_f(MAC_MODE, tp->mac_mode);
2957 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2959 tp->link_config.active_speed = current_speed;
2960 tp->link_config.active_duplex = current_duplex;
2962 if (current_link_up != netif_carrier_ok(tp->dev)) {
2963 if (current_link_up)
2964 netif_carrier_on(tp->dev);
2966 netif_carrier_off(tp->dev);
2967 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2969 tg3_link_report(tp);
2974 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2976 if (tp->serdes_counter) {
2977 /* Give autoneg time to complete. */
2978 tp->serdes_counter--;
2981 if (!netif_carrier_ok(tp->dev) &&
2982 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2985 tg3_readphy(tp, MII_BMCR, &bmcr);
2986 if (bmcr & BMCR_ANENABLE) {
2989 /* Select shadow register 0x1f */
2990 tg3_writephy(tp, 0x1c, 0x7c00);
2991 tg3_readphy(tp, 0x1c, &phy1);
2993 /* Select expansion interrupt status register */
2994 tg3_writephy(tp, 0x17, 0x0f01);
2995 tg3_readphy(tp, 0x15, &phy2);
2996 tg3_readphy(tp, 0x15, &phy2);
2998 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2999 /* We have signal detect and not receiving
3000 * config code words, link is up by parallel
3004 bmcr &= ~BMCR_ANENABLE;
3005 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
3006 tg3_writephy(tp, MII_BMCR, bmcr);
3007 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
3011 else if (netif_carrier_ok(tp->dev) &&
3012 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
3013 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
3016 /* Select expansion interrupt status register */
3017 tg3_writephy(tp, 0x17, 0x0f01);
3018 tg3_readphy(tp, 0x15, &phy2);
3022 /* Config code words received, turn on autoneg. */
3023 tg3_readphy(tp, MII_BMCR, &bmcr);
3024 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
3026 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3032 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
3036 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
3037 err = tg3_setup_fiber_phy(tp, force_reset);
3038 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
3039 err = tg3_setup_fiber_mii_phy(tp, force_reset);
3041 err = tg3_setup_copper_phy(tp, force_reset);
3044 if (tp->link_config.active_speed == SPEED_1000 &&
3045 tp->link_config.active_duplex == DUPLEX_HALF)
3046 tw32(MAC_TX_LENGTHS,
3047 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3048 (6 << TX_LENGTHS_IPG_SHIFT) |
3049 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3051 tw32(MAC_TX_LENGTHS,
3052 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3053 (6 << TX_LENGTHS_IPG_SHIFT) |
3054 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3056 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3057 if (netif_carrier_ok(tp->dev)) {
3058 tw32(HOSTCC_STAT_COAL_TICKS,
3059 tp->coal.stats_block_coalesce_usecs);
3061 tw32(HOSTCC_STAT_COAL_TICKS, 0);
3065 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
3066 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
3067 if (!netif_carrier_ok(tp->dev))
3068 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
3071 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
3072 tw32(PCIE_PWR_MGMT_THRESH, val);
3078 /* This is called whenever we suspect that the system chipset is re-
3079 * ordering the sequence of MMIO to the tx send mailbox. The symptom
3080 * is bogus tx completions. We try to recover by setting the
3081 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3084 static void tg3_tx_recover(struct tg3 *tp)
3086 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3087 tp->write32_tx_mbox == tg3_write_indirect_mbox);
3089 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3090 "mapped I/O cycles to the network device, attempting to "
3091 "recover. Please report the problem to the driver maintainer "
3092 "and include system chipset information.\n", tp->dev->name);
3094 spin_lock(&tp->lock);
3095 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3096 spin_unlock(&tp->lock);
3099 static inline u32 tg3_tx_avail(struct tg3 *tp)
3102 return (tp->tx_pending -
3103 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3106 /* Tigon3 never reports partial packet sends. So we do not
3107 * need special logic to handle SKBs that have not had all
3108 * of their frags sent yet, like SunGEM does.
3110 static void tg3_tx(struct tg3 *tp)
3112 u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3113 u32 sw_idx = tp->tx_cons;
3115 while (sw_idx != hw_idx) {
3116 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3117 struct sk_buff *skb = ri->skb;
3120 if (unlikely(skb == NULL)) {
3125 pci_unmap_single(tp->pdev,
3126 pci_unmap_addr(ri, mapping),
3132 sw_idx = NEXT_TX(sw_idx);
3134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3135 ri = &tp->tx_buffers[sw_idx];
3136 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3139 pci_unmap_page(tp->pdev,
3140 pci_unmap_addr(ri, mapping),
3141 skb_shinfo(skb)->frags[i].size,
3144 sw_idx = NEXT_TX(sw_idx);
3149 if (unlikely(tx_bug)) {
3155 tp->tx_cons = sw_idx;
3157 /* Need to make the tx_cons update visible to tg3_start_xmit()
3158 * before checking for netif_queue_stopped(). Without the
3159 * memory barrier, there is a small possibility that tg3_start_xmit()
3160 * will miss it and cause the queue to be stopped forever.
3164 if (unlikely(netif_queue_stopped(tp->dev) &&
3165 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3166 netif_tx_lock(tp->dev);
3167 if (netif_queue_stopped(tp->dev) &&
3168 (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3169 netif_wake_queue(tp->dev);
3170 netif_tx_unlock(tp->dev);
3174 /* Returns size of skb allocated or < 0 on error.
3176 * We only need to fill in the address because the other members
3177 * of the RX descriptor are invariant, see tg3_init_rings.
3179 * Note the purposeful assymetry of cpu vs. chip accesses. For
3180 * posting buffers we only dirty the first cache line of the RX
3181 * descriptor (containing the address). Whereas for the RX status
3182 * buffers the cpu only reads the last cacheline of the RX descriptor
3183 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3185 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3186 int src_idx, u32 dest_idx_unmasked)
3188 struct tg3_rx_buffer_desc *desc;
3189 struct ring_info *map, *src_map;
3190 struct sk_buff *skb;
3192 int skb_size, dest_idx;
3195 switch (opaque_key) {
3196 case RXD_OPAQUE_RING_STD:
3197 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3198 desc = &tp->rx_std[dest_idx];
3199 map = &tp->rx_std_buffers[dest_idx];
3201 src_map = &tp->rx_std_buffers[src_idx];
3202 skb_size = tp->rx_pkt_buf_sz;
3205 case RXD_OPAQUE_RING_JUMBO:
3206 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3207 desc = &tp->rx_jumbo[dest_idx];
3208 map = &tp->rx_jumbo_buffers[dest_idx];
3210 src_map = &tp->rx_jumbo_buffers[src_idx];
3211 skb_size = RX_JUMBO_PKT_BUF_SZ;
3218 /* Do not overwrite any of the map or rp information
3219 * until we are sure we can commit to a new buffer.
3221 * Callers depend upon this behavior and assume that
3222 * we leave everything unchanged if we fail.
3224 skb = netdev_alloc_skb(tp->dev, skb_size);
3228 skb_reserve(skb, tp->rx_offset);
3230 mapping = pci_map_single(tp->pdev, skb->data,
3231 skb_size - tp->rx_offset,
3232 PCI_DMA_FROMDEVICE);
3235 pci_unmap_addr_set(map, mapping, mapping);
3237 if (src_map != NULL)
3238 src_map->skb = NULL;
3240 desc->addr_hi = ((u64)mapping >> 32);
3241 desc->addr_lo = ((u64)mapping & 0xffffffff);
3246 /* We only need to move over in the address because the other
3247 * members of the RX descriptor are invariant. See notes above
3248 * tg3_alloc_rx_skb for full details.
3250 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3251 int src_idx, u32 dest_idx_unmasked)
3253 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3254 struct ring_info *src_map, *dest_map;
3257 switch (opaque_key) {
3258 case RXD_OPAQUE_RING_STD:
3259 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3260 dest_desc = &tp->rx_std[dest_idx];
3261 dest_map = &tp->rx_std_buffers[dest_idx];
3262 src_desc = &tp->rx_std[src_idx];
3263 src_map = &tp->rx_std_buffers[src_idx];
3266 case RXD_OPAQUE_RING_JUMBO:
3267 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3268 dest_desc = &tp->rx_jumbo[dest_idx];
3269 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3270 src_desc = &tp->rx_jumbo[src_idx];
3271 src_map = &tp->rx_jumbo_buffers[src_idx];
3278 dest_map->skb = src_map->skb;
3279 pci_unmap_addr_set(dest_map, mapping,
3280 pci_unmap_addr(src_map, mapping));
3281 dest_desc->addr_hi = src_desc->addr_hi;
3282 dest_desc->addr_lo = src_desc->addr_lo;
3284 src_map->skb = NULL;
3287 #if TG3_VLAN_TAG_USED
3288 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3290 return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3294 /* The RX ring scheme is composed of multiple rings which post fresh
3295 * buffers to the chip, and one special ring the chip uses to report
3296 * status back to the host.
3298 * The special ring reports the status of received packets to the
3299 * host. The chip does not write into the original descriptor the
3300 * RX buffer was obtained from. The chip simply takes the original
3301 * descriptor as provided by the host, updates the status and length
3302 * field, then writes this into the next status ring entry.
3304 * Each ring the host uses to post buffers to the chip is described
3305 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
3306 * it is first placed into the on-chip ram. When the packet's length
3307 * is known, it walks down the TG3_BDINFO entries to select the ring.
3308 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3309 * which is within the range of the new packet's length is chosen.
3311 * The "separate ring for rx status" scheme may sound queer, but it makes
3312 * sense from a cache coherency perspective. If only the host writes
3313 * to the buffer post rings, and only the chip writes to the rx status
3314 * rings, then cache lines never move beyond shared-modified state.
3315 * If both the host and chip were to write into the same ring, cache line
3316 * eviction could occur since both entities want it in an exclusive state.
3318 static int tg3_rx(struct tg3 *tp, int budget)
3320 u32 work_mask, rx_std_posted = 0;
3321 u32 sw_idx = tp->rx_rcb_ptr;
3325 hw_idx = tp->hw_status->idx[0].rx_producer;
3327 * We need to order the read of hw_idx and the read of
3328 * the opaque cookie.
3333 while (sw_idx != hw_idx && budget > 0) {
3334 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3336 struct sk_buff *skb;
3337 dma_addr_t dma_addr;
3338 u32 opaque_key, desc_idx, *post_ptr;
3340 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3341 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3342 if (opaque_key == RXD_OPAQUE_RING_STD) {
3343 dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3345 skb = tp->rx_std_buffers[desc_idx].skb;
3346 post_ptr = &tp->rx_std_ptr;
3348 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3349 dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3351 skb = tp->rx_jumbo_buffers[desc_idx].skb;
3352 post_ptr = &tp->rx_jumbo_ptr;
3355 goto next_pkt_nopost;
3358 work_mask |= opaque_key;
3360 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3361 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3363 tg3_recycle_rx(tp, opaque_key,
3364 desc_idx, *post_ptr);
3366 /* Other statistics kept track of by card. */
3367 tp->net_stats.rx_dropped++;
3371 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3373 if (len > RX_COPY_THRESHOLD
3374 && tp->rx_offset == 2
3375 /* rx_offset != 2 iff this is a 5701 card running
3376 * in PCI-X mode [see tg3_get_invariants()] */
3380 skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3381 desc_idx, *post_ptr);
3385 pci_unmap_single(tp->pdev, dma_addr,
3386 skb_size - tp->rx_offset,
3387 PCI_DMA_FROMDEVICE);
3391 struct sk_buff *copy_skb;
3393 tg3_recycle_rx(tp, opaque_key,
3394 desc_idx, *post_ptr);
3396 copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3397 if (copy_skb == NULL)
3398 goto drop_it_no_recycle;
3400 skb_reserve(copy_skb, 2);
3401 skb_put(copy_skb, len);
3402 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3403 skb_copy_from_linear_data(skb, copy_skb->data, len);
3404 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3406 /* We'll reuse the original ring buffer. */
3410 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3411 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3412 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3413 >> RXD_TCPCSUM_SHIFT) == 0xffff))
3414 skb->ip_summed = CHECKSUM_UNNECESSARY;
3416 skb->ip_summed = CHECKSUM_NONE;
3418 skb->protocol = eth_type_trans(skb, tp->dev);
3419 #if TG3_VLAN_TAG_USED
3420 if (tp->vlgrp != NULL &&
3421 desc->type_flags & RXD_FLAG_VLAN) {
3422 tg3_vlan_rx(tp, skb,
3423 desc->err_vlan & RXD_VLAN_MASK);
3426 netif_receive_skb(skb);
3428 tp->dev->last_rx = jiffies;
3435 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3436 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3438 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3439 TG3_64BIT_REG_LOW, idx);
3440 work_mask &= ~RXD_OPAQUE_RING_STD;
3445 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3447 /* Refresh hw_idx to see if there is new work */
3448 if (sw_idx == hw_idx) {
3449 hw_idx = tp->hw_status->idx[0].rx_producer;
3454 /* ACK the status ring. */
3455 tp->rx_rcb_ptr = sw_idx;
3456 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3458 /* Refill RX ring(s). */
3459 if (work_mask & RXD_OPAQUE_RING_STD) {
3460 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3461 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3464 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3465 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3466 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3474 static int tg3_poll(struct net_device *netdev, int *budget)
3476 struct tg3 *tp = netdev_priv(netdev);
3477 struct tg3_hw_status *sblk = tp->hw_status;
3480 /* handle link change and other phy events */
3481 if (!(tp->tg3_flags &
3482 (TG3_FLAG_USE_LINKCHG_REG |
3483 TG3_FLAG_POLL_SERDES))) {
3484 if (sblk->status & SD_STATUS_LINK_CHG) {
3485 sblk->status = SD_STATUS_UPDATED |
3486 (sblk->status & ~SD_STATUS_LINK_CHG);
3487 spin_lock(&tp->lock);
3488 tg3_setup_phy(tp, 0);
3489 spin_unlock(&tp->lock);
3493 /* run TX completion thread */
3494 if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3496 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3497 netif_rx_complete(netdev);
3498 schedule_work(&tp->reset_task);
3503 /* run RX thread, within the bounds set by NAPI.
3504 * All RX "locking" is done by ensuring outside
3505 * code synchronizes with dev->poll()
3507 if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3508 int orig_budget = *budget;
3511 if (orig_budget > netdev->quota)
3512 orig_budget = netdev->quota;
3514 work_done = tg3_rx(tp, orig_budget);
3516 *budget -= work_done;
3517 netdev->quota -= work_done;
3520 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3521 tp->last_tag = sblk->status_tag;
3524 sblk->status &= ~SD_STATUS_UPDATED;
3526 /* if no more work, tell net stack and NIC we're done */
3527 done = !tg3_has_work(tp);
3529 netif_rx_complete(netdev);
3530 tg3_restart_ints(tp);
3533 return (done ? 0 : 1);
3536 static void tg3_irq_quiesce(struct tg3 *tp)
3538 BUG_ON(tp->irq_sync);
3543 synchronize_irq(tp->pdev->irq);
3546 static inline int tg3_irq_sync(struct tg3 *tp)
3548 return tp->irq_sync;
3551 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3552 * If irq_sync is non-zero, then the IRQ handler must be synchronized
3553 * with as well. Most of the time, this is not necessary except when
3554 * shutting down the device.
3556 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3558 spin_lock_bh(&tp->lock);
3560 tg3_irq_quiesce(tp);
3563 static inline void tg3_full_unlock(struct tg3 *tp)
3565 spin_unlock_bh(&tp->lock);
3568 /* One-shot MSI handler - Chip automatically disables interrupt
3569 * after sending MSI so driver doesn't have to do it.
3571 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3573 struct net_device *dev = dev_id;
3574 struct tg3 *tp = netdev_priv(dev);
3576 prefetch(tp->hw_status);
3577 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3579 if (likely(!tg3_irq_sync(tp)))
3580 netif_rx_schedule(dev); /* schedule NAPI poll */
3585 /* MSI ISR - No need to check for interrupt sharing and no need to
3586 * flush status block and interrupt mailbox. PCI ordering rules
3587 * guarantee that MSI will arrive after the status block.
3589 static irqreturn_t tg3_msi(int irq, void *dev_id)
3591 struct net_device *dev = dev_id;
3592 struct tg3 *tp = netdev_priv(dev);
3594 prefetch(tp->hw_status);
3595 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3597 * Writing any value to intr-mbox-0 clears PCI INTA# and
3598 * chip-internal interrupt pending events.
3599 * Writing non-zero to intr-mbox-0 additional tells the
3600 * NIC to stop sending us irqs, engaging "in-intr-handler"
3603 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3604 if (likely(!tg3_irq_sync(tp)))
3605 netif_rx_schedule(dev); /* schedule NAPI poll */
3607 return IRQ_RETVAL(1);
3610 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3612 struct net_device *dev = dev_id;
3613 struct tg3 *tp = netdev_priv(dev);
3614 struct tg3_hw_status *sblk = tp->hw_status;
3615 unsigned int handled = 1;
3617 /* In INTx mode, it is possible for the interrupt to arrive at
3618 * the CPU before the status block posted prior to the interrupt.
3619 * Reading the PCI State register will confirm whether the
3620 * interrupt is ours and will flush the status block.
3622 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
3623 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3624 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3631 * Writing any value to intr-mbox-0 clears PCI INTA# and
3632 * chip-internal interrupt pending events.
3633 * Writing non-zero to intr-mbox-0 additional tells the
3634 * NIC to stop sending us irqs, engaging "in-intr-handler"
3637 * Flush the mailbox to de-assert the IRQ immediately to prevent
3638 * spurious interrupts. The flush impacts performance but
3639 * excessive spurious interrupts can be worse in some cases.
3641 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3642 if (tg3_irq_sync(tp))
3644 sblk->status &= ~SD_STATUS_UPDATED;
3645 if (likely(tg3_has_work(tp))) {
3646 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3647 netif_rx_schedule(dev); /* schedule NAPI poll */
3649 /* No work, shared interrupt perhaps? re-enable
3650 * interrupts, and flush that PCI write
3652 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3656 return IRQ_RETVAL(handled);
3659 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3661 struct net_device *dev = dev_id;
3662 struct tg3 *tp = netdev_priv(dev);
3663 struct tg3_hw_status *sblk = tp->hw_status;
3664 unsigned int handled = 1;
3666 /* In INTx mode, it is possible for the interrupt to arrive at
3667 * the CPU before the status block posted prior to the interrupt.
3668 * Reading the PCI State register will confirm whether the
3669 * interrupt is ours and will flush the status block.
3671 if (unlikely(sblk->status_tag == tp->last_tag)) {
3672 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
3673 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3680 * writing any value to intr-mbox-0 clears PCI INTA# and
3681 * chip-internal interrupt pending events.
3682 * writing non-zero to intr-mbox-0 additional tells the
3683 * NIC to stop sending us irqs, engaging "in-intr-handler"
3686 * Flush the mailbox to de-assert the IRQ immediately to prevent
3687 * spurious interrupts. The flush impacts performance but
3688 * excessive spurious interrupts can be worse in some cases.
3690 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3691 if (tg3_irq_sync(tp))
3693 if (netif_rx_schedule_prep(dev)) {
3694 prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3695 /* Update last_tag to mark that this status has been
3696 * seen. Because interrupt may be shared, we may be
3697 * racing with tg3_poll(), so only update last_tag
3698 * if tg3_poll() is not scheduled.
3700 tp->last_tag = sblk->status_tag;
3701 __netif_rx_schedule(dev);
3704 return IRQ_RETVAL(handled);
3707 /* ISR for interrupt test */
3708 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3710 struct net_device *dev = dev_id;
3711 struct tg3 *tp = netdev_priv(dev);
3712 struct tg3_hw_status *sblk = tp->hw_status;
3714 if ((sblk->status & SD_STATUS_UPDATED) ||
3715 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3716 tg3_disable_ints(tp);
3717 return IRQ_RETVAL(1);
3719 return IRQ_RETVAL(0);
3722 static int tg3_init_hw(struct tg3 *, int);
3723 static int tg3_halt(struct tg3 *, int, int);
3725 /* Restart hardware after configuration changes, self-test, etc.
3726 * Invoked with tp->lock held.
3728 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3732 err = tg3_init_hw(tp, reset_phy);
3734 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3735 "aborting.\n", tp->dev->name);
3736 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3737 tg3_full_unlock(tp);
3738 del_timer_sync(&tp->timer);
3740 netif_poll_enable(tp->dev);
3742 tg3_full_lock(tp, 0);
3747 #ifdef CONFIG_NET_POLL_CONTROLLER
3748 static void tg3_poll_controller(struct net_device *dev)
3750 struct tg3 *tp = netdev_priv(dev);
3752 tg3_interrupt(tp->pdev->irq, dev);
3756 static void tg3_reset_task(struct work_struct *work)
3758 struct tg3 *tp = container_of(work, struct tg3, reset_task);
3759 unsigned int restart_timer;
3761 tg3_full_lock(tp, 0);
3763 if (!netif_running(tp->dev)) {
3764 tg3_full_unlock(tp);
3768 tg3_full_unlock(tp);
3772 tg3_full_lock(tp, 1);
3774 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3775 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3777 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3778 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3779 tp->write32_rx_mbox = tg3_write_flush_reg32;
3780 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3781 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3784 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3785 if (tg3_init_hw(tp, 1))
3788 tg3_netif_start(tp);
3791 mod_timer(&tp->timer, jiffies + 1);
3794 tg3_full_unlock(tp);
3797 static void tg3_dump_short_state(struct tg3 *tp)
3799 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3800 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3801 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3802 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3805 static void tg3_tx_timeout(struct net_device *dev)
3807 struct tg3 *tp = netdev_priv(dev);
3809 if (netif_msg_tx_err(tp)) {
3810 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3812 tg3_dump_short_state(tp);
3815 schedule_work(&tp->reset_task);
3818 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3819 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3821 u32 base = (u32) mapping & 0xffffffff;
3823 return ((base > 0xffffdcc0) &&
3824 (base + len + 8 < base));
3827 /* Test for DMA addresses > 40-bit */
3828 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3831 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3832 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3833 return (((u64) mapping + len) > DMA_40BIT_MASK);
3840 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3842 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3843 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3844 u32 last_plus_one, u32 *start,
3845 u32 base_flags, u32 mss)
3847 struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3848 dma_addr_t new_addr = 0;
3855 /* New SKB is guaranteed to be linear. */
3857 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3859 /* Make sure new skb does not cross any 4G boundaries.
3860 * Drop the packet if it does.
3862 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3864 dev_kfree_skb(new_skb);
3867 tg3_set_txd(tp, entry, new_addr, new_skb->len,
3868 base_flags, 1 | (mss << 1));
3869 *start = NEXT_TX(entry);
3873 /* Now clean up the sw ring entries. */
3875 while (entry != last_plus_one) {
3879 len = skb_headlen(skb);
3881 len = skb_shinfo(skb)->frags[i-1].size;
3882 pci_unmap_single(tp->pdev,
3883 pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3884 len, PCI_DMA_TODEVICE);
3886 tp->tx_buffers[entry].skb = new_skb;
3887 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3889 tp->tx_buffers[entry].skb = NULL;
3891 entry = NEXT_TX(entry);
3900 static void tg3_set_txd(struct tg3 *tp, int entry,
3901 dma_addr_t mapping, int len, u32 flags,
3904 struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3905 int is_end = (mss_and_is_end & 0x1);
3906 u32 mss = (mss_and_is_end >> 1);
3910 flags |= TXD_FLAG_END;
3911 if (flags & TXD_FLAG_VLAN) {
3912 vlan_tag = flags >> 16;
3915 vlan_tag |= (mss << TXD_MSS_SHIFT);
3917 txd->addr_hi = ((u64) mapping >> 32);
3918 txd->addr_lo = ((u64) mapping & 0xffffffff);
3919 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3920 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3923 /* hard_start_xmit for devices that don't have any bugs and
3924 * support TG3_FLG2_HW_TSO_2 only.
3926 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3928 struct tg3 *tp = netdev_priv(dev);
3930 u32 len, entry, base_flags, mss;
3932 len = skb_headlen(skb);
3934 /* We are running in BH disabled context with netif_tx_lock
3935 * and TX reclaim runs via tp->poll inside of a software
3936 * interrupt. Furthermore, IRQ processing runs lockless so we have
3937 * no IRQ context deadlocks to worry about either. Rejoice!
3939 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3940 if (!netif_queue_stopped(dev)) {
3941 netif_stop_queue(dev);
3943 /* This is a hard error, log it. */
3944 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3945 "queue awake!\n", dev->name);
3947 return NETDEV_TX_BUSY;
3950 entry = tp->tx_prod;
3953 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
3954 int tcp_opt_len, ip_tcp_len;
3956 if (skb_header_cloned(skb) &&
3957 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3962 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3963 mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3965 struct iphdr *iph = ip_hdr(skb);
3967 tcp_opt_len = tcp_optlen(skb);
3968 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
3971 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
3972 mss |= (ip_tcp_len + tcp_opt_len) << 9;
3975 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3976 TXD_FLAG_CPU_POST_DMA);
3978 tcp_hdr(skb)->check = 0;
3981 else if (skb->ip_summed == CHECKSUM_PARTIAL)
3982 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3983 #if TG3_VLAN_TAG_USED
3984 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3985 base_flags |= (TXD_FLAG_VLAN |
3986 (vlan_tx_tag_get(skb) << 16));
3989 /* Queue skb data, a.k.a. the main skb fragment. */
3990 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3992 tp->tx_buffers[entry].skb = skb;
3993 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3995 tg3_set_txd(tp, entry, mapping, len, base_flags,
3996 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3998 entry = NEXT_TX(entry);
4000 /* Now loop through additional data fragments, and queue them. */
4001 if (skb_shinfo(skb)->nr_frags > 0) {
4002 unsigned int i, last;
4004 last = skb_shinfo(skb)->nr_frags - 1;
4005 for (i = 0; i <= last; i++) {
4006 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4009 mapping = pci_map_page(tp->pdev,
4012 len, PCI_DMA_TODEVICE);
4014 tp->tx_buffers[entry].skb = NULL;
4015 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4017 tg3_set_txd(tp, entry, mapping, len,
4018 base_flags, (i == last) | (mss << 1));
4020 entry = NEXT_TX(entry);
4024 /* Packets are ready, update Tx producer idx local and on card. */
4025 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4027 tp->tx_prod = entry;
4028 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4029 netif_stop_queue(dev);
4030 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4031 netif_wake_queue(tp->dev);
4037 dev->trans_start = jiffies;
4039 return NETDEV_TX_OK;
4042 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
4044 /* Use GSO to workaround a rare TSO bug that may be triggered when the
4045 * TSO header is greater than 80 bytes.
4047 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
4049 struct sk_buff *segs, *nskb;
4051 /* Estimate the number of fragments in the worst case */
4052 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
4053 netif_stop_queue(tp->dev);
4054 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
4055 return NETDEV_TX_BUSY;
4057 netif_wake_queue(tp->dev);
4060 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4061 if (unlikely(IS_ERR(segs)))
4062 goto tg3_tso_bug_end;
4068 tg3_start_xmit_dma_bug(nskb, tp->dev);
4074 return NETDEV_TX_OK;
4077 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4078 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4080 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4082 struct tg3 *tp = netdev_priv(dev);
4084 u32 len, entry, base_flags, mss;
4085 int would_hit_hwbug;
4087 len = skb_headlen(skb);
4089 /* We are running in BH disabled context with netif_tx_lock
4090 * and TX reclaim runs via tp->poll inside of a software
4091 * interrupt. Furthermore, IRQ processing runs lockless so we have
4092 * no IRQ context deadlocks to worry about either. Rejoice!
4094 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4095 if (!netif_queue_stopped(dev)) {
4096 netif_stop_queue(dev);
4098 /* This is a hard error, log it. */
4099 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4100 "queue awake!\n", dev->name);
4102 return NETDEV_TX_BUSY;
4105 entry = tp->tx_prod;
4107 if (skb->ip_summed == CHECKSUM_PARTIAL)
4108 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4110 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
4112 int tcp_opt_len, ip_tcp_len, hdr_len;
4114 if (skb_header_cloned(skb) &&
4115 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4120 tcp_opt_len = tcp_optlen(skb);
4121 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
4123 hdr_len = ip_tcp_len + tcp_opt_len;
4124 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4125 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4126 return (tg3_tso_bug(tp, skb));
4128 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4129 TXD_FLAG_CPU_POST_DMA);
4133 iph->tot_len = htons(mss + hdr_len);
4134 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4135 tcp_hdr(skb)->check = 0;
4136 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4138 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4143 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4144 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4145 if (tcp_opt_len || iph->ihl > 5) {
4148 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4149 mss |= (tsflags << 11);
4152 if (tcp_opt_len || iph->ihl > 5) {
4155 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
4156 base_flags |= tsflags << 12;
4160 #if TG3_VLAN_TAG_USED
4161 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4162 base_flags |= (TXD_FLAG_VLAN |
4163 (vlan_tx_tag_get(skb) << 16));
4166 /* Queue skb data, a.k.a. the main skb fragment. */
4167 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4169 tp->tx_buffers[entry].skb = skb;
4170 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4172 would_hit_hwbug = 0;
4174 if (tg3_4g_overflow_test(mapping, len))
4175 would_hit_hwbug = 1;
4177 tg3_set_txd(tp, entry, mapping, len, base_flags,
4178 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4180 entry = NEXT_TX(entry);
4182 /* Now loop through additional data fragments, and queue them. */
4183 if (skb_shinfo(skb)->nr_frags > 0) {
4184 unsigned int i, last;
4186 last = skb_shinfo(skb)->nr_frags - 1;
4187 for (i = 0; i <= last; i++) {
4188 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4191 mapping = pci_map_page(tp->pdev,
4194 len, PCI_DMA_TODEVICE);
4196 tp->tx_buffers[entry].skb = NULL;
4197 pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4199 if (tg3_4g_overflow_test(mapping, len))
4200 would_hit_hwbug = 1;
4202 if (tg3_40bit_overflow_test(tp, mapping, len))
4203 would_hit_hwbug = 1;
4205 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4206 tg3_set_txd(tp, entry, mapping, len,
4207 base_flags, (i == last)|(mss << 1));
4209 tg3_set_txd(tp, entry, mapping, len,
4210 base_flags, (i == last));
4212 entry = NEXT_TX(entry);
4216 if (would_hit_hwbug) {
4217 u32 last_plus_one = entry;
4220 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4221 start &= (TG3_TX_RING_SIZE - 1);
4223 /* If the workaround fails due to memory/mapping
4224 * failure, silently drop this packet.
4226 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4227 &start, base_flags, mss))
4233 /* Packets are ready, update Tx producer idx local and on card. */
4234 tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4236 tp->tx_prod = entry;
4237 if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4238 netif_stop_queue(dev);
4239 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4240 netif_wake_queue(tp->dev);
4246 dev->trans_start = jiffies;
4248 return NETDEV_TX_OK;
4251 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4256 if (new_mtu > ETH_DATA_LEN) {
4257 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4258 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4259 ethtool_op_set_tso(dev, 0);
4262 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4264 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4265 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4266 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4270 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4272 struct tg3 *tp = netdev_priv(dev);
4275 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4278 if (!netif_running(dev)) {
4279 /* We'll just catch it later when the
4282 tg3_set_mtu(dev, tp, new_mtu);
4288 tg3_full_lock(tp, 1);
4290 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4292 tg3_set_mtu(dev, tp, new_mtu);
4294 err = tg3_restart_hw(tp, 0);
4297 tg3_netif_start(tp);
4299 tg3_full_unlock(tp);
4304 /* Free up pending packets in all rx/tx rings.
4306 * The chip has been shut down and the driver detached from
4307 * the networking, so no interrupts or new tx packets will
4308 * end up in the driver. tp->{tx,}lock is not held and we are not
4309 * in an interrupt context and thus may sleep.
4311 static void tg3_free_rings(struct tg3 *tp)
4313 struct ring_info *rxp;
4316 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4317 rxp = &tp->rx_std_buffers[i];
4319 if (rxp->skb == NULL)
4321 pci_unmap_single(tp->pdev,
4322 pci_unmap_addr(rxp, mapping),
4323 tp->rx_pkt_buf_sz - tp->rx_offset,
4324 PCI_DMA_FROMDEVICE);
4325 dev_kfree_skb_any(rxp->skb);
4329 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4330 rxp = &tp->rx_jumbo_buffers[i];
4332 if (rxp->skb == NULL)
4334 pci_unmap_single(tp->pdev,
4335 pci_unmap_addr(rxp, mapping),
4336 RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4337 PCI_DMA_FROMDEVICE);
4338 dev_kfree_skb_any(rxp->skb);
4342 for (i = 0; i < TG3_TX_RING_SIZE; ) {
4343 struct tx_ring_info *txp;
4344 struct sk_buff *skb;
4347 txp = &tp->tx_buffers[i];
4355 pci_unmap_single(tp->pdev,
4356 pci_unmap_addr(txp, mapping),
4363 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4364 txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4365 pci_unmap_page(tp->pdev,
4366 pci_unmap_addr(txp, mapping),
4367 skb_shinfo(skb)->frags[j].size,
4372 dev_kfree_skb_any(skb);
4376 /* Initialize tx/rx rings for packet processing.
4378 * The chip has been shut down and the driver detached from
4379 * the networking, so no interrupts or new tx packets will
4380 * end up in the driver. tp->{tx,}lock are held and thus
4383 static int tg3_init_rings(struct tg3 *tp)
4387 /* Free up all the SKBs. */
4390 /* Zero out all descriptors. */
4391 memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4392 memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4393 memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4394 memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4396 tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4397 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4398 (tp->dev->mtu > ETH_DATA_LEN))
4399 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4401 /* Initialize invariants of the rings, we only set this
4402 * stuff once. This works because the card does not
4403 * write into the rx buffer posting rings.
4405 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4406 struct tg3_rx_buffer_desc *rxd;
4408 rxd = &tp->rx_std[i];
4409 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4411 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4412 rxd->opaque = (RXD_OPAQUE_RING_STD |
4413 (i << RXD_OPAQUE_INDEX_SHIFT));
4416 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4417 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4418 struct tg3_rx_buffer_desc *rxd;
4420 rxd = &tp->rx_jumbo[i];
4421 rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4423 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4425 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4426 (i << RXD_OPAQUE_INDEX_SHIFT));
4430 /* Now allocate fresh SKBs for each rx ring. */
4431 for (i = 0; i < tp->rx_pending; i++) {
4432 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4433 printk(KERN_WARNING PFX
4434 "%s: Using a smaller RX standard ring, "
4435 "only %d out of %d buffers were allocated "
4437 tp->dev->name, i, tp->rx_pending);
4445 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4446 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4447 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4449 printk(KERN_WARNING PFX
4450 "%s: Using a smaller RX jumbo ring, "
4451 "only %d out of %d buffers were "
4452 "allocated successfully.\n",
4453 tp->dev->name, i, tp->rx_jumbo_pending);
4458 tp->rx_jumbo_pending = i;
4467 * Must not be invoked with interrupt sources disabled and
4468 * the hardware shutdown down.
4470 static void tg3_free_consistent(struct tg3 *tp)
4472 kfree(tp->rx_std_buffers);
4473 tp->rx_std_buffers = NULL;
4475 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4476 tp->rx_std, tp->rx_std_mapping);
4480 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4481 tp->rx_jumbo, tp->rx_jumbo_mapping);
4482 tp->rx_jumbo = NULL;
4485 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4486 tp->rx_rcb, tp->rx_rcb_mapping);
4490 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4491 tp->tx_ring, tp->tx_desc_mapping);
4494 if (tp->hw_status) {
4495 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4496 tp->hw_status, tp->status_mapping);
4497 tp->hw_status = NULL;
4500 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4501 tp->hw_stats, tp->stats_mapping);
4502 tp->hw_stats = NULL;
4507 * Must not be invoked with interrupt sources disabled and
4508 * the hardware shutdown down. Can sleep.
4510 static int tg3_alloc_consistent(struct tg3 *tp)
4512 tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4514 TG3_RX_JUMBO_RING_SIZE)) +
4515 (sizeof(struct tx_ring_info) *
4518 if (!tp->rx_std_buffers)
4521 tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4522 tp->tx_buffers = (struct tx_ring_info *)
4523 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4525 tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4526 &tp->rx_std_mapping);
4530 tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4531 &tp->rx_jumbo_mapping);
4536 tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4537 &tp->rx_rcb_mapping);
4541 tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4542 &tp->tx_desc_mapping);
4546 tp->hw_status = pci_alloc_consistent(tp->pdev,
4548 &tp->status_mapping);
4552 tp->hw_stats = pci_alloc_consistent(tp->pdev,
4553 sizeof(struct tg3_hw_stats),
4554 &tp->stats_mapping);
4558 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4559 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4564 tg3_free_consistent(tp);
4568 #define MAX_WAIT_CNT 1000
4570 /* To stop a block, clear the enable bit and poll till it
4571 * clears. tp->lock is held.
4573 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4578 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4585 /* We can't enable/disable these bits of the
4586 * 5705/5750, just say success.
4599 for (i = 0; i < MAX_WAIT_CNT; i++) {
4602 if ((val & enable_bit) == 0)
4606 if (i == MAX_WAIT_CNT && !silent) {
4607 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4608 "ofs=%lx enable_bit=%x\n",
4616 /* tp->lock is held. */
4617 static int tg3_abort_hw(struct tg3 *tp, int silent)
4621 tg3_disable_ints(tp);
4623 tp->rx_mode &= ~RX_MODE_ENABLE;
4624 tw32_f(MAC_RX_MODE, tp->rx_mode);
4627 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4628 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4629 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4630 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4631 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4632 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4634 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4635 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4636 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4637 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4638 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4639 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4640 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4642 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4643 tw32_f(MAC_MODE, tp->mac_mode);
4646 tp->tx_mode &= ~TX_MODE_ENABLE;
4647 tw32_f(MAC_TX_MODE, tp->tx_mode);
4649 for (i = 0; i < MAX_WAIT_CNT; i++) {
4651 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4654 if (i >= MAX_WAIT_CNT) {
4655 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4656 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4657 tp->dev->name, tr32(MAC_TX_MODE));
4661 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4662 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4663 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4665 tw32(FTQ_RESET, 0xffffffff);
4666 tw32(FTQ_RESET, 0x00000000);
4668 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4669 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4672 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4674 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4679 /* tp->lock is held. */
4680 static int tg3_nvram_lock(struct tg3 *tp)
4682 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4685 if (tp->nvram_lock_cnt == 0) {
4686 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4687 for (i = 0; i < 8000; i++) {
4688 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4693 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4697 tp->nvram_lock_cnt++;
4702 /* tp->lock is held. */
4703 static void tg3_nvram_unlock(struct tg3 *tp)
4705 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4706 if (tp->nvram_lock_cnt > 0)
4707 tp->nvram_lock_cnt--;
4708 if (tp->nvram_lock_cnt == 0)
4709 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4713 /* tp->lock is held. */
4714 static void tg3_enable_nvram_access(struct tg3 *tp)
4716 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4717 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4718 u32 nvaccess = tr32(NVRAM_ACCESS);
4720 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4724 /* tp->lock is held. */
4725 static void tg3_disable_nvram_access(struct tg3 *tp)
4727 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4728 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4729 u32 nvaccess = tr32(NVRAM_ACCESS);
4731 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4735 /* tp->lock is held. */
4736 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4738 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4739 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4741 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4743 case RESET_KIND_INIT:
4744 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4748 case RESET_KIND_SHUTDOWN:
4749 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4753 case RESET_KIND_SUSPEND:
4754 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4764 /* tp->lock is held. */
4765 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4767 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4769 case RESET_KIND_INIT:
4770 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4771 DRV_STATE_START_DONE);
4774 case RESET_KIND_SHUTDOWN:
4775 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4776 DRV_STATE_UNLOAD_DONE);
4785 /* tp->lock is held. */
4786 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4788 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4790 case RESET_KIND_INIT:
4791 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4795 case RESET_KIND_SHUTDOWN:
4796 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4800 case RESET_KIND_SUSPEND:
4801 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4811 static int tg3_poll_fw(struct tg3 *tp)
4816 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4817 /* Wait up to 20ms for init done. */
4818 for (i = 0; i < 200; i++) {
4819 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4826 /* Wait for firmware initialization to complete. */
4827 for (i = 0; i < 100000; i++) {
4828 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4829 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4834 /* Chip might not be fitted with firmware. Some Sun onboard
4835 * parts are configured like that. So don't signal the timeout
4836 * of the above loop as an error, but do report the lack of
4837 * running firmware once.
4840 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4841 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4843 printk(KERN_INFO PFX "%s: No firmware running.\n",
4850 static void tg3_stop_fw(struct tg3 *);
4852 /* tp->lock is held. */
4853 static int tg3_chip_reset(struct tg3 *tp)
4856 void (*write_op)(struct tg3 *, u32, u32);
4861 /* No matching tg3_nvram_unlock() after this because
4862 * chip reset below will undo the nvram lock.
4864 tp->nvram_lock_cnt = 0;
4866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4868 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4869 tw32(GRC_FASTBOOT_PC, 0);
4872 * We must avoid the readl() that normally takes place.
4873 * It locks machines, causes machine checks, and other
4874 * fun things. So, temporarily disable the 5701
4875 * hardware workaround, while we do the reset.
4877 write_op = tp->write32;
4878 if (write_op == tg3_write_flush_reg32)
4879 tp->write32 = tg3_write32;
4881 /* Prevent the irq handler from reading or writing PCI registers
4882 * during chip reset when the memory enable bit in the PCI command
4883 * register may be cleared. The chip does not generate interrupt
4884 * at this time, but the irq handler may still be called due to irq
4885 * sharing or irqpoll.
4887 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
4888 if (tp->hw_status) {
4889 tp->hw_status->status = 0;
4890 tp->hw_status->status_tag = 0;
4894 synchronize_irq(tp->pdev->irq);
4897 val = GRC_MISC_CFG_CORECLK_RESET;
4899 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4900 if (tr32(0x7e2c) == 0x60) {
4903 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4904 tw32(GRC_MISC_CFG, (1 << 29));
4909 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4910 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4911 tw32(GRC_VCPU_EXT_CTRL,
4912 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4915 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4916 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4917 tw32(GRC_MISC_CFG, val);
4919 /* restore 5701 hardware bug workaround write method */
4920 tp->write32 = write_op;
4922 /* Unfortunately, we have to delay before the PCI read back.
4923 * Some 575X chips even will not respond to a PCI cfg access
4924 * when the reset command is given to the chip.
4926 * How do these hardware designers expect things to work
4927 * properly if the PCI write is posted for a long period
4928 * of time? It is always necessary to have some method by
4929 * which a register read back can occur to push the write
4930 * out which does the reset.
4932 * For most tg3 variants the trick below was working.
4937 /* Flush PCI posted writes. The normal MMIO registers
4938 * are inaccessible at this time so this is the only
4939 * way to make this reliably (actually, this is no longer
4940 * the case, see above). I tried to use indirect
4941 * register read/write but this upset some 5701 variants.
4943 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4947 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4948 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4952 /* Wait for link training to complete. */
4953 for (i = 0; i < 5000; i++)
4956 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4957 pci_write_config_dword(tp->pdev, 0xc4,
4958 cfg_val | (1 << 15));
4960 /* Set PCIE max payload size and clear error status. */
4961 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4964 /* Re-enable indirect register accesses. */
4965 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4966 tp->misc_host_ctrl);
4968 /* Set MAX PCI retry to zero. */
4969 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4970 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4971 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4972 val |= PCISTATE_RETRY_SAME_DMA;
4973 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4975 pci_restore_state(tp->pdev);
4977 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
4979 /* Make sure PCI-X relaxed ordering bit is clear. */
4980 pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4981 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4982 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4984 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4987 /* Chip reset on 5780 will reset MSI enable bit,
4988 * so need to restore it.
4990 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4993 pci_read_config_word(tp->pdev,
4994 tp->msi_cap + PCI_MSI_FLAGS,
4996 pci_write_config_word(tp->pdev,
4997 tp->msi_cap + PCI_MSI_FLAGS,
4998 ctrl | PCI_MSI_FLAGS_ENABLE);
4999 val = tr32(MSGINT_MODE);
5000 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
5003 val = tr32(MEMARB_MODE);
5004 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
5007 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
5009 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
5011 tw32(0x5000, 0x400);
5014 tw32(GRC_MODE, tp->grc_mode);
5016 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5017 u32 val = tr32(0xc4);
5019 tw32(0xc4, val | (1 << 15));
5022 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
5023 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5024 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
5025 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
5026 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
5027 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5030 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
5031 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
5032 tw32_f(MAC_MODE, tp->mac_mode);
5033 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5034 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
5035 tw32_f(MAC_MODE, tp->mac_mode);
5037 tw32_f(MAC_MODE, 0);
5040 err = tg3_poll_fw(tp);
5044 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5045 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5046 u32 val = tr32(0x7c00);
5048 tw32(0x7c00, val | (1 << 25));
5051 /* Reprobe ASF enable state. */
5052 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
5053 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
5054 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
5055 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
5058 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
5059 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
5060 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
5061 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
5062 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
5069 /* tp->lock is held. */
5070 static void tg3_stop_fw(struct tg3 *tp)
5072 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5076 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5077 val = tr32(GRC_RX_CPU_EVENT);
5079 tw32(GRC_RX_CPU_EVENT, val);
5081 /* Wait for RX cpu to ACK the event. */
5082 for (i = 0; i < 100; i++) {
5083 if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5090 /* tp->lock is held. */
5091 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5097 tg3_write_sig_pre_reset(tp, kind);
5099 tg3_abort_hw(tp, silent);
5100 err = tg3_chip_reset(tp);
5102 tg3_write_sig_legacy(tp, kind);
5103 tg3_write_sig_post_reset(tp, kind);
5111 #define TG3_FW_RELEASE_MAJOR 0x0
5112 #define TG3_FW_RELASE_MINOR 0x0
5113 #define TG3_FW_RELEASE_FIX 0x0
5114 #define TG3_FW_START_ADDR 0x08000000
5115 #define TG3_FW_TEXT_ADDR 0x08000000
5116 #define TG3_FW_TEXT_LEN 0x9c0
5117 #define TG3_FW_RODATA_ADDR 0x080009c0
5118 #define TG3_FW_RODATA_LEN 0x60
5119 #define TG3_FW_DATA_ADDR 0x08000a40
5120 #define TG3_FW_DATA_LEN 0x20
5121 #define TG3_FW_SBSS_ADDR 0x08000a60
5122 #define TG3_FW_SBSS_LEN 0xc
5123 #define TG3_FW_BSS_ADDR 0x08000a70
5124 #define TG3_FW_BSS_LEN 0x10
5126 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5127 0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5128 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5129 0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5130 0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5131 0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5132 0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5133 0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5134 0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5135 0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5136 0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5137 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5138 0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5139 0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5140 0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5141 0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5142 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5143 0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5144 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5145 0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5146 0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5147 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5148 0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5149 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5150 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5151 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5153 0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5154 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5155 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5156 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5157 0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5158 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5159 0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5160 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5161 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5162 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5163 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5164 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5165 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5166 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5167 0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5168 0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5169 0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5170 0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5171 0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5172 0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5173 0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5174 0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5175 0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5176 0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5177 0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5178 0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5179 0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5180 0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5181 0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5182 0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5183 0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5184 0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5185 0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5186 0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5187 0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5188 0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5189 0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5190 0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5191 0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5192 0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5193 0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5194 0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5195 0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5196 0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5197 0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5198 0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5199 0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5200 0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5201 0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5202 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5203 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5204 0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5205 0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5206 0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5207 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5208 0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5209 0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5210 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5211 0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5212 0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5213 0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5214 0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5215 0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5216 0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5217 0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5220 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5221 0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5222 0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5223 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5224 0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5228 #if 0 /* All zeros, don't eat up space with it. */
5229 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5230 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5231 0x00000000, 0x00000000, 0x00000000, 0x00000000
5235 #define RX_CPU_SCRATCH_BASE 0x30000
5236 #define RX_CPU_SCRATCH_SIZE 0x04000
5237 #define TX_CPU_SCRATCH_BASE 0x34000
5238 #define TX_CPU_SCRATCH_SIZE 0x04000
5240 /* tp->lock is held. */
5241 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5245 BUG_ON(offset == TX_CPU_BASE &&
5246 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5248 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5249 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5251 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5254 if (offset == RX_CPU_BASE) {
5255 for (i = 0; i < 10000; i++) {
5256 tw32(offset + CPU_STATE, 0xffffffff);
5257 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5258 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5262 tw32(offset + CPU_STATE, 0xffffffff);
5263 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
5266 for (i = 0; i < 10000; i++) {
5267 tw32(offset + CPU_STATE, 0xffffffff);
5268 tw32(offset + CPU_MODE, CPU_MODE_HALT);
5269 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5275 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5278 (offset == RX_CPU_BASE ? "RX" : "TX"));
5282 /* Clear firmware's nvram arbitration. */
5283 if (tp->tg3_flags & TG3_FLAG_NVRAM)
5284 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5289 unsigned int text_base;
5290 unsigned int text_len;
5291 const u32 *text_data;
5292 unsigned int rodata_base;
5293 unsigned int rodata_len;
5294 const u32 *rodata_data;
5295 unsigned int data_base;
5296 unsigned int data_len;
5297 const u32 *data_data;
5300 /* tp->lock is held. */
5301 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5302 int cpu_scratch_size, struct fw_info *info)
5304 int err, lock_err, i;
5305 void (*write_op)(struct tg3 *, u32, u32);
5307 if (cpu_base == TX_CPU_BASE &&
5308 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5309 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5310 "TX cpu firmware on %s which is 5705.\n",
5315 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5316 write_op = tg3_write_mem;
5318 write_op = tg3_write_indirect_reg32;
5320 /* It is possible that bootcode is still loading at this point.
5321 * Get the nvram lock first before halting the cpu.
5323 lock_err = tg3_nvram_lock(tp);
5324 err = tg3_halt_cpu(tp, cpu_base);
5326 tg3_nvram_unlock(tp);
5330 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5331 write_op(tp, cpu_scratch_base + i, 0);
5332 tw32(cpu_base + CPU_STATE, 0xffffffff);
5333 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5334 for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5335 write_op(tp, (cpu_scratch_base +
5336 (info->text_base & 0xffff) +
5339 info->text_data[i] : 0));
5340 for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5341 write_op(tp, (cpu_scratch_base +
5342 (info->rodata_base & 0xffff) +
5344 (info->rodata_data ?
5345 info->rodata_data[i] : 0));
5346 for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5347 write_op(tp, (cpu_scratch_base +
5348 (info->data_base & 0xffff) +
5351 info->data_data[i] : 0));
5359 /* tp->lock is held. */
5360 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5362 struct fw_info info;
5365 info.text_base = TG3_FW_TEXT_ADDR;
5366 info.text_len = TG3_FW_TEXT_LEN;
5367 info.text_data = &tg3FwText[0];
5368 info.rodata_base = TG3_FW_RODATA_ADDR;
5369 info.rodata_len = TG3_FW_RODATA_LEN;
5370 info.rodata_data = &tg3FwRodata[0];
5371 info.data_base = TG3_FW_DATA_ADDR;
5372 info.data_len = TG3_FW_DATA_LEN;
5373 info.data_data = NULL;
5375 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5376 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5381 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5382 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5387 /* Now startup only the RX cpu. */
5388 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5389 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5391 for (i = 0; i < 5; i++) {
5392 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5394 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5395 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
5396 tw32_f(RX_CPU_BASE + CPU_PC, TG3_FW_TEXT_ADDR);
5400 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5401 "to set RX CPU PC, is %08x should be %08x\n",
5402 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5406 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5407 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
5413 #define TG3_TSO_FW_RELEASE_MAJOR 0x1
5414 #define TG3_TSO_FW_RELASE_MINOR 0x6
5415 #define TG3_TSO_FW_RELEASE_FIX 0x0
5416 #define TG3_TSO_FW_START_ADDR 0x08000000
5417 #define TG3_TSO_FW_TEXT_ADDR 0x08000000
5418 #define TG3_TSO_FW_TEXT_LEN 0x1aa0
5419 #define TG3_TSO_FW_RODATA_ADDR 0x08001aa0
5420 #define TG3_TSO_FW_RODATA_LEN 0x60
5421 #define TG3_TSO_FW_DATA_ADDR 0x08001b20
5422 #define TG3_TSO_FW_DATA_LEN 0x30
5423 #define TG3_TSO_FW_SBSS_ADDR 0x08001b50
5424 #define TG3_TSO_FW_SBSS_LEN 0x2c
5425 #define TG3_TSO_FW_BSS_ADDR 0x08001b80
5426 #define TG3_TSO_FW_BSS_LEN 0x894
5428 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5429 0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5430 0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5431 0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5432 0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5433 0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5434 0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5435 0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5436 0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5437 0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5438 0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5439 0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5440 0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5441 0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5442 0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5443 0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5444 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5445 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5446 0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5447 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5448 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5449 0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5450 0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5451 0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5452 0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5453 0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5454 0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5455 0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5456 0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5457 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5458 0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5459 0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5460 0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5461 0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5462 0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5463 0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5464 0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5465 0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5466 0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5467 0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5468 0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5469 0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5470 0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5471 0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5472 0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5473 0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5474 0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5475 0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5476 0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5477 0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5478 0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5479 0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5480 0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5481 0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5482 0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5483 0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5484 0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5485 0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5486 0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5487 0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5488 0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5489 0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5490 0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5491 0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5492 0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5493 0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5494 0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5495 0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5496 0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5497 0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5498 0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5499 0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5500 0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5501 0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5502 0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5503 0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5504 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5505 0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5506 0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5507 0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5508 0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5509 0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5510 0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5511 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5512 0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5513 0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5514 0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5515 0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5516 0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5517 0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5518 0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5519 0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5520 0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5521 0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5522 0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5523 0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5524 0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5525 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5526 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5527 0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5528 0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5529 0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5530 0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5531 0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5532 0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5533 0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5534 0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5535 0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5536 0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5537 0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5538 0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5539 0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5540 0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5541 0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5542 0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5543 0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5544 0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5545 0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5546 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5547 0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5548 0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5549 0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5550 0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5551 0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5552 0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5553 0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5554 0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5555 0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5556 0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5557 0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5558 0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5559 0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5560 0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5561 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5562 0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5563 0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5564 0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5565 0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5566 0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5567 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5568 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5569 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5570 0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5571 0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5572 0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5573 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5574 0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5575 0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5576 0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5577 0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5578 0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5579 0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5580 0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5581 0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5582 0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5583 0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5584 0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5585 0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5586 0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5587 0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5588 0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5589 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5590 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5591 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5592 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5593 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5594 0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5595 0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5596 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5597 0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5598 0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5599 0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5600 0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5601 0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5602 0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5603 0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5604 0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5605 0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5606 0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5607 0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5608 0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5609 0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5610 0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5611 0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5612 0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5613 0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5614 0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5615 0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5616 0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5617 0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5618 0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5619 0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5620 0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5621 0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5622 0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5623 0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5624 0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5625 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5626 0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5627 0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5628 0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5629 0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5630 0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5631 0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5632 0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5633 0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5634 0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5635 0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5636 0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5637 0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5638 0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5639 0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5640 0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5641 0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5642 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5643 0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5644 0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5645 0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5646 0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5647 0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5648 0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5649 0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5650 0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5651 0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5652 0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5653 0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5654 0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5655 0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5656 0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5657 0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5658 0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5659 0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5660 0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5661 0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5662 0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5663 0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5664 0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5665 0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5666 0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5667 0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5668 0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5669 0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5670 0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5671 0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5672 0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5673 0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5674 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5675 0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5676 0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5677 0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5678 0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5679 0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5680 0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5681 0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5682 0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5683 0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5684 0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5685 0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5686 0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5687 0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5688 0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5689 0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5690 0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5691 0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5692 0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5693 0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5694 0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5695 0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5696 0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5697 0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5698 0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5699 0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5700 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5701 0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5702 0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5703 0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5704 0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5705 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5706 0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5707 0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5708 0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5709 0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5710 0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5711 0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5712 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5715 static const u32 tg3TsoFwRodata[] = {
5716 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5717 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5718 0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5719 0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5723 static const u32 tg3TsoFwData[] = {
5724 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5725 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5729 /* 5705 needs a special version of the TSO firmware. */
5730 #define TG3_TSO5_FW_RELEASE_MAJOR 0x1
5731 #define TG3_TSO5_FW_RELASE_MINOR 0x2
5732 #define TG3_TSO5_FW_RELEASE_FIX 0x0
5733 #define TG3_TSO5_FW_START_ADDR 0x00010000
5734 #define TG3_TSO5_FW_TEXT_ADDR 0x00010000
5735 #define TG3_TSO5_FW_TEXT_LEN 0xe90
5736 #define TG3_TSO5_FW_RODATA_ADDR 0x00010e90
5737 #define TG3_TSO5_FW_RODATA_LEN 0x50
5738 #define TG3_TSO5_FW_DATA_ADDR 0x00010f00
5739 #define TG3_TSO5_FW_DATA_LEN 0x20
5740 #define TG3_TSO5_FW_SBSS_ADDR 0x00010f20
5741 #define TG3_TSO5_FW_SBSS_LEN 0x28
5742 #define TG3_TSO5_FW_BSS_ADDR 0x00010f50
5743 #define TG3_TSO5_FW_BSS_LEN 0x88
5745 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5746 0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5747 0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5748 0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5749 0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5750 0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5751 0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5752 0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5753 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5754 0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5755 0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5756 0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5757 0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5758 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5759 0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5760 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5761 0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5762 0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5763 0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5764 0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5765 0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5766 0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5767 0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5768 0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5769 0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5770 0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5771 0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5772 0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5773 0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5774 0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5775 0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5776 0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5777 0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5778 0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5779 0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5780 0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5781 0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5782 0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5783 0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5784 0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5785 0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5786 0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5787 0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5788 0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5789 0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5790 0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5791 0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5792 0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5793 0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5794 0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5795 0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5796 0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5797 0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5798 0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5799 0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5800 0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5801 0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5802 0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5803 0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5804 0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5805 0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5806 0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5807 0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5808 0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5809 0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5810 0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5811 0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5812 0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5813 0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5814 0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5815 0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5816 0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5817 0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5818 0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5819 0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5820 0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5821 0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5822 0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5823 0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5824 0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5825 0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5826 0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5827 0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5828 0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5829 0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5830 0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5831 0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5832 0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5833 0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5834 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5835 0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5836 0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5837 0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5838 0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5839 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5840 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5841 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5842 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5843 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5844 0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5845 0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5846 0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5847 0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5848 0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5849 0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5850 0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5851 0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5852 0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5853 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5854 0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5855 0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5856 0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5857 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5858 0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5859 0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5860 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5861 0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5862 0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5863 0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5864 0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5865 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5866 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5867 0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5868 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5869 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5870 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5871 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5872 0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5873 0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5874 0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5875 0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5876 0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5877 0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5878 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5879 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5880 0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5881 0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5882 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5883 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5884 0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5885 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5886 0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5887 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5888 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5889 0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5890 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5891 0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5892 0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5893 0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5894 0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5895 0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5896 0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5897 0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5898 0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5899 0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5900 0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5901 0x00000000, 0x00000000, 0x00000000,
5904 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5905 0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5906 0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5907 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5908 0x00000000, 0x00000000, 0x00000000,
5911 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5912 0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5913 0x00000000, 0x00000000, 0x00000000,
5916 /* tp->lock is held. */
5917 static int tg3_load_tso_firmware(struct tg3 *tp)
5919 struct fw_info info;
5920 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5923 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5926 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5927 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5928 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5929 info.text_data = &tg3Tso5FwText[0];
5930 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5931 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5932 info.rodata_data = &tg3Tso5FwRodata[0];
5933 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5934 info.data_len = TG3_TSO5_FW_DATA_LEN;
5935 info.data_data = &tg3Tso5FwData[0];
5936 cpu_base = RX_CPU_BASE;
5937 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5938 cpu_scratch_size = (info.text_len +
5941 TG3_TSO5_FW_SBSS_LEN +
5942 TG3_TSO5_FW_BSS_LEN);
5944 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5945 info.text_len = TG3_TSO_FW_TEXT_LEN;
5946 info.text_data = &tg3TsoFwText[0];
5947 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5948 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5949 info.rodata_data = &tg3TsoFwRodata[0];
5950 info.data_base = TG3_TSO_FW_DATA_ADDR;
5951 info.data_len = TG3_TSO_FW_DATA_LEN;
5952 info.data_data = &tg3TsoFwData[0];
5953 cpu_base = TX_CPU_BASE;
5954 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5955 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5958 err = tg3_load_firmware_cpu(tp, cpu_base,
5959 cpu_scratch_base, cpu_scratch_size,
5964 /* Now startup the cpu. */
5965 tw32(cpu_base + CPU_STATE, 0xffffffff);
5966 tw32_f(cpu_base + CPU_PC, info.text_base);
5968 for (i = 0; i < 5; i++) {
5969 if (tr32(cpu_base + CPU_PC) == info.text_base)
5971 tw32(cpu_base + CPU_STATE, 0xffffffff);
5972 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
5973 tw32_f(cpu_base + CPU_PC, info.text_base);
5977 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5978 "to set CPU PC, is %08x should be %08x\n",
5979 tp->dev->name, tr32(cpu_base + CPU_PC),
5983 tw32(cpu_base + CPU_STATE, 0xffffffff);
5984 tw32_f(cpu_base + CPU_MODE, 0x00000000);
5989 /* tp->lock is held. */
5990 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
5992 u32 addr_high, addr_low;
5995 addr_high = ((tp->dev->dev_addr[0] << 8) |
5996 tp->dev->dev_addr[1]);
5997 addr_low = ((tp->dev->dev_addr[2] << 24) |
5998 (tp->dev->dev_addr[3] << 16) |
5999 (tp->dev->dev_addr[4] << 8) |
6000 (tp->dev->dev_addr[5] << 0));
6001 for (i = 0; i < 4; i++) {
6002 if (i == 1 && skip_mac_1)
6004 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
6005 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
6008 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
6009 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6010 for (i = 0; i < 12; i++) {
6011 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
6012 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
6016 addr_high = (tp->dev->dev_addr[0] +
6017 tp->dev->dev_addr[1] +
6018 tp->dev->dev_addr[2] +
6019 tp->dev->dev_addr[3] +
6020 tp->dev->dev_addr[4] +
6021 tp->dev->dev_addr[5]) &
6022 TX_BACKOFF_SEED_MASK;
6023 tw32(MAC_TX_BACKOFF_SEED, addr_high);
6026 static int tg3_set_mac_addr(struct net_device *dev, void *p)
6028 struct tg3 *tp = netdev_priv(dev);
6029 struct sockaddr *addr = p;
6030 int err = 0, skip_mac_1 = 0;
6032 if (!is_valid_ether_addr(addr->sa_data))
6035 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
6037 if (!netif_running(dev))
6040 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6041 u32 addr0_high, addr0_low, addr1_high, addr1_low;
6043 addr0_high = tr32(MAC_ADDR_0_HIGH);
6044 addr0_low = tr32(MAC_ADDR_0_LOW);
6045 addr1_high = tr32(MAC_ADDR_1_HIGH);
6046 addr1_low = tr32(MAC_ADDR_1_LOW);
6048 /* Skip MAC addr 1 if ASF is using it. */
6049 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
6050 !(addr1_high == 0 && addr1_low == 0))
6053 spin_lock_bh(&tp->lock);
6054 __tg3_set_mac_addr(tp, skip_mac_1);
6055 spin_unlock_bh(&tp->lock);
6060 /* tp->lock is held. */
6061 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
6062 dma_addr_t mapping, u32 maxlen_flags,
6066 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
6067 ((u64) mapping >> 32));
6069 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
6070 ((u64) mapping & 0xffffffff));
6072 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
6075 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6077 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6081 static void __tg3_set_rx_mode(struct net_device *);
6082 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6084 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6085 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6086 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6087 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6088 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6089 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6090 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6092 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6093 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6094 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6095 u32 val = ec->stats_block_coalesce_usecs;
6097 if (!netif_carrier_ok(tp->dev))
6100 tw32(HOSTCC_STAT_COAL_TICKS, val);
6104 /* tp->lock is held. */
6105 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6107 u32 val, rdmac_mode;
6110 tg3_disable_ints(tp);
6114 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6116 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6117 tg3_abort_hw(tp, 1);
6123 err = tg3_chip_reset(tp);
6127 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6129 /* This works around an issue with Athlon chipsets on
6130 * B3 tigon3 silicon. This bit has no effect on any
6131 * other revision. But do not set this on PCI Express
6134 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6135 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6136 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6138 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6139 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6140 val = tr32(TG3PCI_PCISTATE);
6141 val |= PCISTATE_RETRY_SAME_DMA;
6142 tw32(TG3PCI_PCISTATE, val);
6145 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6146 /* Enable some hw fixes. */
6147 val = tr32(TG3PCI_MSI_DATA);
6148 val |= (1 << 26) | (1 << 28) | (1 << 29);
6149 tw32(TG3PCI_MSI_DATA, val);
6152 /* Descriptor ring init may make accesses to the
6153 * NIC SRAM area to setup the TX descriptors, so we
6154 * can only do this after the hardware has been
6155 * successfully reset.
6157 err = tg3_init_rings(tp);
6161 /* This value is determined during the probe time DMA
6162 * engine test, tg3_test_dma.
6164 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6166 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6167 GRC_MODE_4X_NIC_SEND_RINGS |
6168 GRC_MODE_NO_TX_PHDR_CSUM |
6169 GRC_MODE_NO_RX_PHDR_CSUM);
6170 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6172 /* Pseudo-header checksum is done by hardware logic and not
6173 * the offload processers, so make the chip do the pseudo-
6174 * header checksums on receive. For transmit it is more
6175 * convenient to do the pseudo-header checksum in software
6176 * as Linux does that on transmit for us in all cases.
6178 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6182 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6184 /* Setup the timer prescalar register. Clock is always 66Mhz. */
6185 val = tr32(GRC_MISC_CFG);
6187 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6188 tw32(GRC_MISC_CFG, val);
6190 /* Initialize MBUF/DESC pool. */
6191 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6193 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6194 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6195 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6196 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6198 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6199 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6200 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6202 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6205 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6206 TG3_TSO5_FW_RODATA_LEN +
6207 TG3_TSO5_FW_DATA_LEN +
6208 TG3_TSO5_FW_SBSS_LEN +
6209 TG3_TSO5_FW_BSS_LEN);
6210 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6211 tw32(BUFMGR_MB_POOL_ADDR,
6212 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6213 tw32(BUFMGR_MB_POOL_SIZE,
6214 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6217 if (tp->dev->mtu <= ETH_DATA_LEN) {
6218 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6219 tp->bufmgr_config.mbuf_read_dma_low_water);
6220 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6221 tp->bufmgr_config.mbuf_mac_rx_low_water);
6222 tw32(BUFMGR_MB_HIGH_WATER,
6223 tp->bufmgr_config.mbuf_high_water);
6225 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6226 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6227 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6228 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6229 tw32(BUFMGR_MB_HIGH_WATER,
6230 tp->bufmgr_config.mbuf_high_water_jumbo);
6232 tw32(BUFMGR_DMA_LOW_WATER,
6233 tp->bufmgr_config.dma_low_water);
6234 tw32(BUFMGR_DMA_HIGH_WATER,
6235 tp->bufmgr_config.dma_high_water);
6237 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6238 for (i = 0; i < 2000; i++) {
6239 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6244 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6249 /* Setup replenish threshold. */
6250 val = tp->rx_pending / 8;
6253 else if (val > tp->rx_std_max_post)
6254 val = tp->rx_std_max_post;
6255 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6256 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6257 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6259 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6260 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6263 tw32(RCVBDI_STD_THRESH, val);
6265 /* Initialize TG3_BDINFO's at:
6266 * RCVDBDI_STD_BD: standard eth size rx ring
6267 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
6268 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
6271 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
6272 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
6273 * ring attribute flags
6274 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
6276 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6277 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6279 * The size of each ring is fixed in the firmware, but the location is
6282 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6283 ((u64) tp->rx_std_mapping >> 32));
6284 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6285 ((u64) tp->rx_std_mapping & 0xffffffff));
6286 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6287 NIC_SRAM_RX_BUFFER_DESC);
6289 /* Don't even try to program the JUMBO/MINI buffer descriptor
6292 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6293 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6294 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6296 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6297 RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6299 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6300 BDINFO_FLAGS_DISABLED);
6302 /* Setup replenish threshold. */
6303 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6305 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6306 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6307 ((u64) tp->rx_jumbo_mapping >> 32));
6308 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6309 ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6310 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6311 RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6312 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6313 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6315 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6316 BDINFO_FLAGS_DISABLED);
6321 /* There is only one send ring on 5705/5750, no need to explicitly
6322 * disable the others.
6324 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6325 /* Clear out send RCB ring in SRAM. */
6326 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6327 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6328 BDINFO_FLAGS_DISABLED);
6333 tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6334 tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6336 tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6337 tp->tx_desc_mapping,
6338 (TG3_TX_RING_SIZE <<
6339 BDINFO_FLAGS_MAXLEN_SHIFT),
6340 NIC_SRAM_TX_BUFFER_DESC);
6342 /* There is only one receive return ring on 5705/5750, no need
6343 * to explicitly disable the others.
6345 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6346 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6347 i += TG3_BDINFO_SIZE) {
6348 tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6349 BDINFO_FLAGS_DISABLED);
6354 tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6356 tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6358 (TG3_RX_RCB_RING_SIZE(tp) <<
6359 BDINFO_FLAGS_MAXLEN_SHIFT),
6362 tp->rx_std_ptr = tp->rx_pending;
6363 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6366 tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6367 tp->rx_jumbo_pending : 0;
6368 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6371 /* Initialize MAC address and backoff seed. */
6372 __tg3_set_mac_addr(tp, 0);
6374 /* MTU + ethernet header + FCS + optional VLAN tag */
6375 tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6377 /* The slot time is changed by tg3_setup_phy if we
6378 * run at gigabit with half duplex.
6380 tw32(MAC_TX_LENGTHS,
6381 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6382 (6 << TX_LENGTHS_IPG_SHIFT) |
6383 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6385 /* Receive rules. */
6386 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6387 tw32(RCVLPC_CONFIG, 0x0181);
6389 /* Calculate RDMAC_MODE setting early, we need it to determine
6390 * the RCVLPC_STATE_ENABLE mask.
6392 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6393 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6394 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6395 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6396 RDMAC_MODE_LNGREAD_ENAB);
6398 /* If statement applies to 5705 and 5750 PCI devices only */
6399 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6400 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6401 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6402 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6403 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6404 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6405 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6406 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6407 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6411 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6412 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6414 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6415 rdmac_mode |= (1 << 27);
6417 /* Receive/send statistics. */
6418 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6419 val = tr32(RCVLPC_STATS_ENABLE);
6420 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6421 tw32(RCVLPC_STATS_ENABLE, val);
6422 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6423 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6424 val = tr32(RCVLPC_STATS_ENABLE);
6425 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6426 tw32(RCVLPC_STATS_ENABLE, val);
6428 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6430 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6431 tw32(SNDDATAI_STATSENAB, 0xffffff);
6432 tw32(SNDDATAI_STATSCTRL,
6433 (SNDDATAI_SCTRL_ENABLE |
6434 SNDDATAI_SCTRL_FASTUPD));
6436 /* Setup host coalescing engine. */
6437 tw32(HOSTCC_MODE, 0);
6438 for (i = 0; i < 2000; i++) {
6439 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6444 __tg3_set_coalesce(tp, &tp->coal);
6446 /* set status block DMA address */
6447 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6448 ((u64) tp->status_mapping >> 32));
6449 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6450 ((u64) tp->status_mapping & 0xffffffff));
6452 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6453 /* Status/statistics block address. See tg3_timer,
6454 * the tg3_periodic_fetch_stats call there, and
6455 * tg3_get_stats to see how this works for 5705/5750 chips.
6457 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6458 ((u64) tp->stats_mapping >> 32));
6459 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6460 ((u64) tp->stats_mapping & 0xffffffff));
6461 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6462 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6465 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6467 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6468 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6469 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6470 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6472 /* Clear statistics/status block in chip, and status block in ram. */
6473 for (i = NIC_SRAM_STATS_BLK;
6474 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6476 tg3_write_mem(tp, i, 0);
6479 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6481 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6482 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6483 /* reset to prevent losing 1st rx packet intermittently */
6484 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6488 tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6489 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6490 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6491 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6492 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
6493 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
6494 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6497 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6498 * If TG3_FLG2_IS_NIC is zero, we should read the
6499 * register to preserve the GPIO settings for LOMs. The GPIOs,
6500 * whether used as inputs or outputs, are set by boot code after
6503 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6506 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6507 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6508 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6510 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6511 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6512 GRC_LCLCTRL_GPIO_OUTPUT3;
6514 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6515 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6517 tp->grc_local_ctrl &= ~gpio_mask;
6518 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6520 /* GPIO1 must be driven high for eeprom write protect */
6521 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6522 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6523 GRC_LCLCTRL_GPIO_OUTPUT1);
6525 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6528 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6531 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6532 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6536 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6537 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6538 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6539 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6540 WDMAC_MODE_LNGREAD_ENAB);
6542 /* If statement applies to 5705 and 5750 PCI devices only */
6543 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6544 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6545 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6546 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6547 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6548 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6550 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6551 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6552 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6553 val |= WDMAC_MODE_RX_ACCEL;
6557 /* Enable host coalescing bug fix */
6558 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6559 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6562 tw32_f(WDMAC_MODE, val);
6565 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6566 val = tr32(TG3PCI_X_CAPS);
6567 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6568 val &= ~PCIX_CAPS_BURST_MASK;
6569 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6570 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6571 val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6572 val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6574 tw32(TG3PCI_X_CAPS, val);
6577 tw32_f(RDMAC_MODE, rdmac_mode);
6580 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6581 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6582 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6583 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6584 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6585 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6586 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6587 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6588 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6589 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6590 tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6591 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6593 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6594 err = tg3_load_5701_a0_firmware_fix(tp);
6599 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6600 err = tg3_load_tso_firmware(tp);
6605 tp->tx_mode = TX_MODE_ENABLE;
6606 tw32_f(MAC_TX_MODE, tp->tx_mode);
6609 tp->rx_mode = RX_MODE_ENABLE;
6610 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6611 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6613 tw32_f(MAC_RX_MODE, tp->rx_mode);
6616 if (tp->link_config.phy_is_low_power) {
6617 tp->link_config.phy_is_low_power = 0;
6618 tp->link_config.speed = tp->link_config.orig_speed;
6619 tp->link_config.duplex = tp->link_config.orig_duplex;
6620 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6623 tp->mi_mode = MAC_MI_MODE_BASE;
6624 tw32_f(MAC_MI_MODE, tp->mi_mode);
6627 tw32(MAC_LED_CTRL, tp->led_ctrl);
6629 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6630 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6631 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6634 tw32_f(MAC_RX_MODE, tp->rx_mode);
6637 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6638 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6639 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6640 /* Set drive transmission level to 1.2V */
6641 /* only if the signal pre-emphasis bit is not set */
6642 val = tr32(MAC_SERDES_CFG);
6645 tw32(MAC_SERDES_CFG, val);
6647 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6648 tw32(MAC_SERDES_CFG, 0x616000);
6651 /* Prevent chip from dropping frames when flow control
6654 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6656 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6657 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6658 /* Use hardware link auto-negotiation */
6659 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6662 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6663 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6666 tmp = tr32(SERDES_RX_CTRL);
6667 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6668 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6669 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6670 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6673 err = tg3_setup_phy(tp, 0);
6677 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6678 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6681 /* Clear CRC stats. */
6682 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6683 tg3_writephy(tp, MII_TG3_TEST1,
6684 tmp | MII_TG3_TEST1_CRC_EN);
6685 tg3_readphy(tp, 0x14, &tmp);
6689 __tg3_set_rx_mode(tp->dev);
6691 /* Initialize receive rules. */
6692 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
6693 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6694 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
6695 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6697 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6698 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6702 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6706 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
6708 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
6710 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
6712 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
6714 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
6716 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
6718 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
6720 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
6722 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
6724 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
6726 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
6728 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
6730 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
6732 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
6740 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6745 /* Called at device open time to get the chip ready for
6746 * packet processing. Invoked with tp->lock held.
6748 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6752 /* Force the chip into D0. */
6753 err = tg3_set_power_state(tp, PCI_D0);
6757 tg3_switch_clocks(tp);
6759 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6761 err = tg3_reset_hw(tp, reset_phy);
6767 #define TG3_STAT_ADD32(PSTAT, REG) \
6768 do { u32 __val = tr32(REG); \
6769 (PSTAT)->low += __val; \
6770 if ((PSTAT)->low < __val) \
6771 (PSTAT)->high += 1; \
6774 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6776 struct tg3_hw_stats *sp = tp->hw_stats;
6778 if (!netif_carrier_ok(tp->dev))
6781 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6782 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6783 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6784 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6785 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6786 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6787 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6788 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6789 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6790 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6791 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6792 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6793 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6795 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6796 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6797 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6798 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6799 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6800 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6801 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6802 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6803 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6804 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6805 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6806 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6807 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6808 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6810 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6811 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6812 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6815 static void tg3_timer(unsigned long __opaque)
6817 struct tg3 *tp = (struct tg3 *) __opaque;
6822 spin_lock(&tp->lock);
6824 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6825 /* All of this garbage is because when using non-tagged
6826 * IRQ status the mailbox/status_block protocol the chip
6827 * uses with the cpu is race prone.
6829 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6830 tw32(GRC_LOCAL_CTRL,
6831 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6833 tw32(HOSTCC_MODE, tp->coalesce_mode |
6834 (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6837 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6838 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6839 spin_unlock(&tp->lock);
6840 schedule_work(&tp->reset_task);
6845 /* This part only runs once per second. */
6846 if (!--tp->timer_counter) {
6847 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6848 tg3_periodic_fetch_stats(tp);
6850 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6854 mac_stat = tr32(MAC_STATUS);
6857 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6858 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6860 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6864 tg3_setup_phy(tp, 0);
6865 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6866 u32 mac_stat = tr32(MAC_STATUS);
6869 if (netif_carrier_ok(tp->dev) &&
6870 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6873 if (! netif_carrier_ok(tp->dev) &&
6874 (mac_stat & (MAC_STATUS_PCS_SYNCED |
6875 MAC_STATUS_SIGNAL_DET))) {
6879 if (!tp->serdes_counter) {
6882 ~MAC_MODE_PORT_MODE_MASK));
6884 tw32_f(MAC_MODE, tp->mac_mode);
6887 tg3_setup_phy(tp, 0);
6889 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6890 tg3_serdes_parallel_detect(tp);
6892 tp->timer_counter = tp->timer_multiplier;
6895 /* Heartbeat is only sent once every 2 seconds.
6897 * The heartbeat is to tell the ASF firmware that the host
6898 * driver is still alive. In the event that the OS crashes,
6899 * ASF needs to reset the hardware to free up the FIFO space
6900 * that may be filled with rx packets destined for the host.
6901 * If the FIFO is full, ASF will no longer function properly.
6903 * Unintended resets have been reported on real time kernels
6904 * where the timer doesn't run on time. Netpoll will also have
6907 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6908 * to check the ring condition when the heartbeat is expiring
6909 * before doing the reset. This will prevent most unintended
6912 if (!--tp->asf_counter) {
6913 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6916 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6917 FWCMD_NICDRV_ALIVE3);
6918 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6919 /* 5 seconds timeout */
6920 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6921 val = tr32(GRC_RX_CPU_EVENT);
6923 tw32(GRC_RX_CPU_EVENT, val);
6925 tp->asf_counter = tp->asf_multiplier;
6928 spin_unlock(&tp->lock);
6931 tp->timer.expires = jiffies + tp->timer_offset;
6932 add_timer(&tp->timer);
6935 static int tg3_request_irq(struct tg3 *tp)
6938 unsigned long flags;
6939 struct net_device *dev = tp->dev;
6941 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6943 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6945 flags = IRQF_SAMPLE_RANDOM;
6948 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6949 fn = tg3_interrupt_tagged;
6950 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6952 return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6955 static int tg3_test_interrupt(struct tg3 *tp)
6957 struct net_device *dev = tp->dev;
6958 int err, i, intr_ok = 0;
6960 if (!netif_running(dev))
6963 tg3_disable_ints(tp);
6965 free_irq(tp->pdev->irq, dev);
6967 err = request_irq(tp->pdev->irq, tg3_test_isr,
6968 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6972 tp->hw_status->status &= ~SD_STATUS_UPDATED;
6973 tg3_enable_ints(tp);
6975 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6978 for (i = 0; i < 5; i++) {
6979 u32 int_mbox, misc_host_ctrl;
6981 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6983 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6985 if ((int_mbox != 0) ||
6986 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6994 tg3_disable_ints(tp);
6996 free_irq(tp->pdev->irq, dev);
6998 err = tg3_request_irq(tp);
7009 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
7010 * successfully restored
7012 static int tg3_test_msi(struct tg3 *tp)
7014 struct net_device *dev = tp->dev;
7018 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
7021 /* Turn off SERR reporting in case MSI terminates with Master
7024 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
7025 pci_write_config_word(tp->pdev, PCI_COMMAND,
7026 pci_cmd & ~PCI_COMMAND_SERR);
7028 err = tg3_test_interrupt(tp);
7030 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
7035 /* other failures */
7039 /* MSI test failed, go back to INTx mode */
7040 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
7041 "switching to INTx mode. Please report this failure to "
7042 "the PCI maintainer and include system chipset information.\n",
7045 free_irq(tp->pdev->irq, dev);
7046 pci_disable_msi(tp->pdev);
7048 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7050 err = tg3_request_irq(tp);
7054 /* Need to reset the chip because the MSI cycle may have terminated
7055 * with Master Abort.
7057 tg3_full_lock(tp, 1);
7059 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7060 err = tg3_init_hw(tp, 1);
7062 tg3_full_unlock(tp);
7065 free_irq(tp->pdev->irq, dev);
7070 static int tg3_open(struct net_device *dev)
7072 struct tg3 *tp = netdev_priv(dev);
7075 netif_carrier_off(tp->dev);
7077 tg3_full_lock(tp, 0);
7079 err = tg3_set_power_state(tp, PCI_D0);
7081 tg3_full_unlock(tp);
7085 tg3_disable_ints(tp);
7086 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7088 tg3_full_unlock(tp);
7090 /* The placement of this call is tied
7091 * to the setup and use of Host TX descriptors.
7093 err = tg3_alloc_consistent(tp);
7097 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) {
7098 /* All MSI supporting chips should support tagged
7099 * status. Assert that this is the case.
7101 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7102 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7103 "Not using MSI.\n", tp->dev->name);
7104 } else if (pci_enable_msi(tp->pdev) == 0) {
7107 msi_mode = tr32(MSGINT_MODE);
7108 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7109 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7112 err = tg3_request_irq(tp);
7115 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7116 pci_disable_msi(tp->pdev);
7117 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7119 tg3_free_consistent(tp);
7123 tg3_full_lock(tp, 0);
7125 err = tg3_init_hw(tp, 1);
7127 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7130 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7131 tp->timer_offset = HZ;
7133 tp->timer_offset = HZ / 10;
7135 BUG_ON(tp->timer_offset > HZ);
7136 tp->timer_counter = tp->timer_multiplier =
7137 (HZ / tp->timer_offset);
7138 tp->asf_counter = tp->asf_multiplier =
7139 ((HZ / tp->timer_offset) * 2);
7141 init_timer(&tp->timer);
7142 tp->timer.expires = jiffies + tp->timer_offset;
7143 tp->timer.data = (unsigned long) tp;
7144 tp->timer.function = tg3_timer;
7147 tg3_full_unlock(tp);
7150 free_irq(tp->pdev->irq, dev);
7151 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7152 pci_disable_msi(tp->pdev);
7153 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7155 tg3_free_consistent(tp);
7159 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7160 err = tg3_test_msi(tp);
7163 tg3_full_lock(tp, 0);
7165 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7166 pci_disable_msi(tp->pdev);
7167 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7169 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7171 tg3_free_consistent(tp);
7173 tg3_full_unlock(tp);
7178 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7179 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7180 u32 val = tr32(PCIE_TRANSACTION_CFG);
7182 tw32(PCIE_TRANSACTION_CFG,
7183 val | PCIE_TRANS_CFG_1SHOT_MSI);
7188 tg3_full_lock(tp, 0);
7190 add_timer(&tp->timer);
7191 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7192 tg3_enable_ints(tp);
7194 tg3_full_unlock(tp);
7196 netif_start_queue(dev);
7202 /*static*/ void tg3_dump_state(struct tg3 *tp)
7204 u32 val32, val32_2, val32_3, val32_4, val32_5;
7208 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7209 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7210 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7214 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7215 tr32(MAC_MODE), tr32(MAC_STATUS));
7216 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7217 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7218 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7219 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7220 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7221 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7223 /* Send data initiator control block */
7224 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7225 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7226 printk(" SNDDATAI_STATSCTRL[%08x]\n",
7227 tr32(SNDDATAI_STATSCTRL));
7229 /* Send data completion control block */
7230 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7232 /* Send BD ring selector block */
7233 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7234 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7236 /* Send BD initiator control block */
7237 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7238 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7240 /* Send BD completion control block */
7241 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7243 /* Receive list placement control block */
7244 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7245 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7246 printk(" RCVLPC_STATSCTRL[%08x]\n",
7247 tr32(RCVLPC_STATSCTRL));
7249 /* Receive data and receive BD initiator control block */
7250 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7251 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7253 /* Receive data completion control block */
7254 printk("DEBUG: RCVDCC_MODE[%08x]\n",
7257 /* Receive BD initiator control block */
7258 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7259 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7261 /* Receive BD completion control block */
7262 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7263 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7265 /* Receive list selector control block */
7266 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7267 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7269 /* Mbuf cluster free block */
7270 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7271 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7273 /* Host coalescing control block */
7274 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7275 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7276 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7277 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7278 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7279 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7280 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7281 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7282 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7283 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7284 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7285 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7287 /* Memory arbiter control block */
7288 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7289 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7291 /* Buffer manager control block */
7292 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7293 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7294 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7295 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7296 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7297 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7298 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7299 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7301 /* Read DMA control block */
7302 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7303 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7305 /* Write DMA control block */
7306 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7307 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7309 /* DMA completion block */
7310 printk("DEBUG: DMAC_MODE[%08x]\n",
7314 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7315 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7316 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7317 tr32(GRC_LOCAL_CTRL));
7320 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7321 tr32(RCVDBDI_JUMBO_BD + 0x0),
7322 tr32(RCVDBDI_JUMBO_BD + 0x4),
7323 tr32(RCVDBDI_JUMBO_BD + 0x8),
7324 tr32(RCVDBDI_JUMBO_BD + 0xc));
7325 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7326 tr32(RCVDBDI_STD_BD + 0x0),
7327 tr32(RCVDBDI_STD_BD + 0x4),
7328 tr32(RCVDBDI_STD_BD + 0x8),
7329 tr32(RCVDBDI_STD_BD + 0xc));
7330 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7331 tr32(RCVDBDI_MINI_BD + 0x0),
7332 tr32(RCVDBDI_MINI_BD + 0x4),
7333 tr32(RCVDBDI_MINI_BD + 0x8),
7334 tr32(RCVDBDI_MINI_BD + 0xc));
7336 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7337 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7338 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7339 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7340 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7341 val32, val32_2, val32_3, val32_4);
7343 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7344 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7345 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7346 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7347 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7348 val32, val32_2, val32_3, val32_4);
7350 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7351 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7352 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7353 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7354 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7355 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7356 val32, val32_2, val32_3, val32_4, val32_5);
7358 /* SW status block */
7359 printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7360 tp->hw_status->status,
7361 tp->hw_status->status_tag,
7362 tp->hw_status->rx_jumbo_consumer,
7363 tp->hw_status->rx_consumer,
7364 tp->hw_status->rx_mini_consumer,
7365 tp->hw_status->idx[0].rx_producer,
7366 tp->hw_status->idx[0].tx_consumer);
7368 /* SW statistics block */
7369 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7370 ((u32 *)tp->hw_stats)[0],
7371 ((u32 *)tp->hw_stats)[1],
7372 ((u32 *)tp->hw_stats)[2],
7373 ((u32 *)tp->hw_stats)[3]);
7376 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7377 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7378 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7379 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7380 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7382 /* NIC side send descriptors. */
7383 for (i = 0; i < 6; i++) {
7386 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7387 + (i * sizeof(struct tg3_tx_buffer_desc));
7388 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7390 readl(txd + 0x0), readl(txd + 0x4),
7391 readl(txd + 0x8), readl(txd + 0xc));
7394 /* NIC side RX descriptors. */
7395 for (i = 0; i < 6; i++) {
7398 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7399 + (i * sizeof(struct tg3_rx_buffer_desc));
7400 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7402 readl(rxd + 0x0), readl(rxd + 0x4),
7403 readl(rxd + 0x8), readl(rxd + 0xc));
7404 rxd += (4 * sizeof(u32));
7405 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7407 readl(rxd + 0x0), readl(rxd + 0x4),
7408 readl(rxd + 0x8), readl(rxd + 0xc));
7411 for (i = 0; i < 6; i++) {
7414 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7415 + (i * sizeof(struct tg3_rx_buffer_desc));
7416 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7418 readl(rxd + 0x0), readl(rxd + 0x4),
7419 readl(rxd + 0x8), readl(rxd + 0xc));
7420 rxd += (4 * sizeof(u32));
7421 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7423 readl(rxd + 0x0), readl(rxd + 0x4),
7424 readl(rxd + 0x8), readl(rxd + 0xc));
7429 static struct net_device_stats *tg3_get_stats(struct net_device *);
7430 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7432 static int tg3_close(struct net_device *dev)
7434 struct tg3 *tp = netdev_priv(dev);
7436 cancel_work_sync(&tp->reset_task);
7438 netif_stop_queue(dev);
7440 del_timer_sync(&tp->timer);
7442 tg3_full_lock(tp, 1);
7447 tg3_disable_ints(tp);
7449 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7451 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7453 tg3_full_unlock(tp);
7455 free_irq(tp->pdev->irq, dev);
7456 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7457 pci_disable_msi(tp->pdev);
7458 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7461 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7462 sizeof(tp->net_stats_prev));
7463 memcpy(&tp->estats_prev, tg3_get_estats(tp),
7464 sizeof(tp->estats_prev));
7466 tg3_free_consistent(tp);
7468 tg3_set_power_state(tp, PCI_D3hot);
7470 netif_carrier_off(tp->dev);
7475 static inline unsigned long get_stat64(tg3_stat64_t *val)
7479 #if (BITS_PER_LONG == 32)
7482 ret = ((u64)val->high << 32) | ((u64)val->low);
7487 static unsigned long calc_crc_errors(struct tg3 *tp)
7489 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7491 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7492 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7493 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7496 spin_lock_bh(&tp->lock);
7497 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7498 tg3_writephy(tp, MII_TG3_TEST1,
7499 val | MII_TG3_TEST1_CRC_EN);
7500 tg3_readphy(tp, 0x14, &val);
7503 spin_unlock_bh(&tp->lock);
7505 tp->phy_crc_errors += val;
7507 return tp->phy_crc_errors;
7510 return get_stat64(&hw_stats->rx_fcs_errors);
7513 #define ESTAT_ADD(member) \
7514 estats->member = old_estats->member + \
7515 get_stat64(&hw_stats->member)
7517 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7519 struct tg3_ethtool_stats *estats = &tp->estats;
7520 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7521 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7526 ESTAT_ADD(rx_octets);
7527 ESTAT_ADD(rx_fragments);
7528 ESTAT_ADD(rx_ucast_packets);
7529 ESTAT_ADD(rx_mcast_packets);
7530 ESTAT_ADD(rx_bcast_packets);
7531 ESTAT_ADD(rx_fcs_errors);
7532 ESTAT_ADD(rx_align_errors);
7533 ESTAT_ADD(rx_xon_pause_rcvd);
7534 ESTAT_ADD(rx_xoff_pause_rcvd);
7535 ESTAT_ADD(rx_mac_ctrl_rcvd);
7536 ESTAT_ADD(rx_xoff_entered);
7537 ESTAT_ADD(rx_frame_too_long_errors);
7538 ESTAT_ADD(rx_jabbers);
7539 ESTAT_ADD(rx_undersize_packets);
7540 ESTAT_ADD(rx_in_length_errors);
7541 ESTAT_ADD(rx_out_length_errors);
7542 ESTAT_ADD(rx_64_or_less_octet_packets);
7543 ESTAT_ADD(rx_65_to_127_octet_packets);
7544 ESTAT_ADD(rx_128_to_255_octet_packets);
7545 ESTAT_ADD(rx_256_to_511_octet_packets);
7546 ESTAT_ADD(rx_512_to_1023_octet_packets);
7547 ESTAT_ADD(rx_1024_to_1522_octet_packets);
7548 ESTAT_ADD(rx_1523_to_2047_octet_packets);
7549 ESTAT_ADD(rx_2048_to_4095_octet_packets);
7550 ESTAT_ADD(rx_4096_to_8191_octet_packets);
7551 ESTAT_ADD(rx_8192_to_9022_octet_packets);
7553 ESTAT_ADD(tx_octets);
7554 ESTAT_ADD(tx_collisions);
7555 ESTAT_ADD(tx_xon_sent);
7556 ESTAT_ADD(tx_xoff_sent);
7557 ESTAT_ADD(tx_flow_control);
7558 ESTAT_ADD(tx_mac_errors);
7559 ESTAT_ADD(tx_single_collisions);
7560 ESTAT_ADD(tx_mult_collisions);
7561 ESTAT_ADD(tx_deferred);
7562 ESTAT_ADD(tx_excessive_collisions);
7563 ESTAT_ADD(tx_late_collisions);
7564 ESTAT_ADD(tx_collide_2times);
7565 ESTAT_ADD(tx_collide_3times);
7566 ESTAT_ADD(tx_collide_4times);
7567 ESTAT_ADD(tx_collide_5times);
7568 ESTAT_ADD(tx_collide_6times);
7569 ESTAT_ADD(tx_collide_7times);
7570 ESTAT_ADD(tx_collide_8times);
7571 ESTAT_ADD(tx_collide_9times);
7572 ESTAT_ADD(tx_collide_10times);
7573 ESTAT_ADD(tx_collide_11times);
7574 ESTAT_ADD(tx_collide_12times);
7575 ESTAT_ADD(tx_collide_13times);
7576 ESTAT_ADD(tx_collide_14times);
7577 ESTAT_ADD(tx_collide_15times);
7578 ESTAT_ADD(tx_ucast_packets);
7579 ESTAT_ADD(tx_mcast_packets);
7580 ESTAT_ADD(tx_bcast_packets);
7581 ESTAT_ADD(tx_carrier_sense_errors);
7582 ESTAT_ADD(tx_discards);
7583 ESTAT_ADD(tx_errors);
7585 ESTAT_ADD(dma_writeq_full);
7586 ESTAT_ADD(dma_write_prioq_full);
7587 ESTAT_ADD(rxbds_empty);
7588 ESTAT_ADD(rx_discards);
7589 ESTAT_ADD(rx_errors);
7590 ESTAT_ADD(rx_threshold_hit);
7592 ESTAT_ADD(dma_readq_full);
7593 ESTAT_ADD(dma_read_prioq_full);
7594 ESTAT_ADD(tx_comp_queue_full);
7596 ESTAT_ADD(ring_set_send_prod_index);
7597 ESTAT_ADD(ring_status_update);
7598 ESTAT_ADD(nic_irqs);
7599 ESTAT_ADD(nic_avoided_irqs);
7600 ESTAT_ADD(nic_tx_threshold_hit);
7605 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7607 struct tg3 *tp = netdev_priv(dev);
7608 struct net_device_stats *stats = &tp->net_stats;
7609 struct net_device_stats *old_stats = &tp->net_stats_prev;
7610 struct tg3_hw_stats *hw_stats = tp->hw_stats;
7615 stats->rx_packets = old_stats->rx_packets +
7616 get_stat64(&hw_stats->rx_ucast_packets) +
7617 get_stat64(&hw_stats->rx_mcast_packets) +
7618 get_stat64(&hw_stats->rx_bcast_packets);
7620 stats->tx_packets = old_stats->tx_packets +
7621 get_stat64(&hw_stats->tx_ucast_packets) +
7622 get_stat64(&hw_stats->tx_mcast_packets) +
7623 get_stat64(&hw_stats->tx_bcast_packets);
7625 stats->rx_bytes = old_stats->rx_bytes +
7626 get_stat64(&hw_stats->rx_octets);
7627 stats->tx_bytes = old_stats->tx_bytes +
7628 get_stat64(&hw_stats->tx_octets);
7630 stats->rx_errors = old_stats->rx_errors +
7631 get_stat64(&hw_stats->rx_errors);
7632 stats->tx_errors = old_stats->tx_errors +
7633 get_stat64(&hw_stats->tx_errors) +
7634 get_stat64(&hw_stats->tx_mac_errors) +
7635 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7636 get_stat64(&hw_stats->tx_discards);
7638 stats->multicast = old_stats->multicast +
7639 get_stat64(&hw_stats->rx_mcast_packets);
7640 stats->collisions = old_stats->collisions +
7641 get_stat64(&hw_stats->tx_collisions);
7643 stats->rx_length_errors = old_stats->rx_length_errors +
7644 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7645 get_stat64(&hw_stats->rx_undersize_packets);
7647 stats->rx_over_errors = old_stats->rx_over_errors +
7648 get_stat64(&hw_stats->rxbds_empty);
7649 stats->rx_frame_errors = old_stats->rx_frame_errors +
7650 get_stat64(&hw_stats->rx_align_errors);
7651 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7652 get_stat64(&hw_stats->tx_discards);
7653 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7654 get_stat64(&hw_stats->tx_carrier_sense_errors);
7656 stats->rx_crc_errors = old_stats->rx_crc_errors +
7657 calc_crc_errors(tp);
7659 stats->rx_missed_errors = old_stats->rx_missed_errors +
7660 get_stat64(&hw_stats->rx_discards);
7665 static inline u32 calc_crc(unsigned char *buf, int len)
7673 for (j = 0; j < len; j++) {
7676 for (k = 0; k < 8; k++) {
7690 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7692 /* accept or reject all multicast frames */
7693 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7694 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7695 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7696 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7699 static void __tg3_set_rx_mode(struct net_device *dev)
7701 struct tg3 *tp = netdev_priv(dev);
7704 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7705 RX_MODE_KEEP_VLAN_TAG);
7707 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7710 #if TG3_VLAN_TAG_USED
7712 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7713 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7715 /* By definition, VLAN is disabled always in this
7718 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7719 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7722 if (dev->flags & IFF_PROMISC) {
7723 /* Promiscuous mode. */
7724 rx_mode |= RX_MODE_PROMISC;
7725 } else if (dev->flags & IFF_ALLMULTI) {
7726 /* Accept all multicast. */
7727 tg3_set_multi (tp, 1);
7728 } else if (dev->mc_count < 1) {
7729 /* Reject all multicast. */
7730 tg3_set_multi (tp, 0);
7732 /* Accept one or more multicast(s). */
7733 struct dev_mc_list *mclist;
7735 u32 mc_filter[4] = { 0, };
7740 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7741 i++, mclist = mclist->next) {
7743 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7745 regidx = (bit & 0x60) >> 5;
7747 mc_filter[regidx] |= (1 << bit);
7750 tw32(MAC_HASH_REG_0, mc_filter[0]);
7751 tw32(MAC_HASH_REG_1, mc_filter[1]);
7752 tw32(MAC_HASH_REG_2, mc_filter[2]);
7753 tw32(MAC_HASH_REG_3, mc_filter[3]);
7756 if (rx_mode != tp->rx_mode) {
7757 tp->rx_mode = rx_mode;
7758 tw32_f(MAC_RX_MODE, rx_mode);
7763 static void tg3_set_rx_mode(struct net_device *dev)
7765 struct tg3 *tp = netdev_priv(dev);
7767 if (!netif_running(dev))
7770 tg3_full_lock(tp, 0);
7771 __tg3_set_rx_mode(dev);
7772 tg3_full_unlock(tp);
7775 #define TG3_REGDUMP_LEN (32 * 1024)
7777 static int tg3_get_regs_len(struct net_device *dev)
7779 return TG3_REGDUMP_LEN;
7782 static void tg3_get_regs(struct net_device *dev,
7783 struct ethtool_regs *regs, void *_p)
7786 struct tg3 *tp = netdev_priv(dev);
7792 memset(p, 0, TG3_REGDUMP_LEN);
7794 if (tp->link_config.phy_is_low_power)
7797 tg3_full_lock(tp, 0);
7799 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
7800 #define GET_REG32_LOOP(base,len) \
7801 do { p = (u32 *)(orig_p + (base)); \
7802 for (i = 0; i < len; i += 4) \
7803 __GET_REG32((base) + i); \
7805 #define GET_REG32_1(reg) \
7806 do { p = (u32 *)(orig_p + (reg)); \
7807 __GET_REG32((reg)); \
7810 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7811 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7812 GET_REG32_LOOP(MAC_MODE, 0x4f0);
7813 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7814 GET_REG32_1(SNDDATAC_MODE);
7815 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7816 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7817 GET_REG32_1(SNDBDC_MODE);
7818 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7819 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7820 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7821 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7822 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7823 GET_REG32_1(RCVDCC_MODE);
7824 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7825 GET_REG32_LOOP(RCVCC_MODE, 0x14);
7826 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7827 GET_REG32_1(MBFREE_MODE);
7828 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7829 GET_REG32_LOOP(MEMARB_MODE, 0x10);
7830 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7831 GET_REG32_LOOP(RDMAC_MODE, 0x08);
7832 GET_REG32_LOOP(WDMAC_MODE, 0x08);
7833 GET_REG32_1(RX_CPU_MODE);
7834 GET_REG32_1(RX_CPU_STATE);
7835 GET_REG32_1(RX_CPU_PGMCTR);
7836 GET_REG32_1(RX_CPU_HWBKPT);
7837 GET_REG32_1(TX_CPU_MODE);
7838 GET_REG32_1(TX_CPU_STATE);
7839 GET_REG32_1(TX_CPU_PGMCTR);
7840 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7841 GET_REG32_LOOP(FTQ_RESET, 0x120);
7842 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7843 GET_REG32_1(DMAC_MODE);
7844 GET_REG32_LOOP(GRC_MODE, 0x4c);
7845 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7846 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7849 #undef GET_REG32_LOOP
7852 tg3_full_unlock(tp);
7855 static int tg3_get_eeprom_len(struct net_device *dev)
7857 struct tg3 *tp = netdev_priv(dev);
7859 return tp->nvram_size;
7862 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7863 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7865 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7867 struct tg3 *tp = netdev_priv(dev);
7870 u32 i, offset, len, val, b_offset, b_count;
7872 if (tp->link_config.phy_is_low_power)
7875 offset = eeprom->offset;
7879 eeprom->magic = TG3_EEPROM_MAGIC;
7882 /* adjustments to start on required 4 byte boundary */
7883 b_offset = offset & 3;
7884 b_count = 4 - b_offset;
7885 if (b_count > len) {
7886 /* i.e. offset=1 len=2 */
7889 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7892 val = cpu_to_le32(val);
7893 memcpy(data, ((char*)&val) + b_offset, b_count);
7896 eeprom->len += b_count;
7899 /* read bytes upto the last 4 byte boundary */
7900 pd = &data[eeprom->len];
7901 for (i = 0; i < (len - (len & 3)); i += 4) {
7902 ret = tg3_nvram_read(tp, offset + i, &val);
7907 val = cpu_to_le32(val);
7908 memcpy(pd + i, &val, 4);
7913 /* read last bytes not ending on 4 byte boundary */
7914 pd = &data[eeprom->len];
7916 b_offset = offset + len - b_count;
7917 ret = tg3_nvram_read(tp, b_offset, &val);
7920 val = cpu_to_le32(val);
7921 memcpy(pd, ((char*)&val), b_count);
7922 eeprom->len += b_count;
7927 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7929 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7931 struct tg3 *tp = netdev_priv(dev);
7933 u32 offset, len, b_offset, odd_len, start, end;
7936 if (tp->link_config.phy_is_low_power)
7939 if (eeprom->magic != TG3_EEPROM_MAGIC)
7942 offset = eeprom->offset;
7945 if ((b_offset = (offset & 3))) {
7946 /* adjustments to start on required 4 byte boundary */
7947 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7950 start = cpu_to_le32(start);
7959 /* adjustments to end on required 4 byte boundary */
7961 len = (len + 3) & ~3;
7962 ret = tg3_nvram_read(tp, offset+len-4, &end);
7965 end = cpu_to_le32(end);
7969 if (b_offset || odd_len) {
7970 buf = kmalloc(len, GFP_KERNEL);
7974 memcpy(buf, &start, 4);
7976 memcpy(buf+len-4, &end, 4);
7977 memcpy(buf + b_offset, data, eeprom->len);
7980 ret = tg3_nvram_write_block(tp, offset, len, buf);
7988 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7990 struct tg3 *tp = netdev_priv(dev);
7992 cmd->supported = (SUPPORTED_Autoneg);
7994 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7995 cmd->supported |= (SUPPORTED_1000baseT_Half |
7996 SUPPORTED_1000baseT_Full);
7998 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7999 cmd->supported |= (SUPPORTED_100baseT_Half |
8000 SUPPORTED_100baseT_Full |
8001 SUPPORTED_10baseT_Half |
8002 SUPPORTED_10baseT_Full |
8004 cmd->port = PORT_TP;
8006 cmd->supported |= SUPPORTED_FIBRE;
8007 cmd->port = PORT_FIBRE;
8010 cmd->advertising = tp->link_config.advertising;
8011 if (netif_running(dev)) {
8012 cmd->speed = tp->link_config.active_speed;
8013 cmd->duplex = tp->link_config.active_duplex;
8015 cmd->phy_address = PHY_ADDR;
8016 cmd->transceiver = 0;
8017 cmd->autoneg = tp->link_config.autoneg;
8023 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
8025 struct tg3 *tp = netdev_priv(dev);
8027 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
8028 /* These are the only valid advertisement bits allowed. */
8029 if (cmd->autoneg == AUTONEG_ENABLE &&
8030 (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
8031 ADVERTISED_1000baseT_Full |
8032 ADVERTISED_Autoneg |
8035 /* Fiber can only do SPEED_1000. */
8036 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8037 (cmd->speed != SPEED_1000))
8039 /* Copper cannot force SPEED_1000. */
8040 } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
8041 (cmd->speed == SPEED_1000))
8043 else if ((cmd->speed == SPEED_1000) &&
8044 (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
8047 tg3_full_lock(tp, 0);
8049 tp->link_config.autoneg = cmd->autoneg;
8050 if (cmd->autoneg == AUTONEG_ENABLE) {
8051 tp->link_config.advertising = cmd->advertising;
8052 tp->link_config.speed = SPEED_INVALID;
8053 tp->link_config.duplex = DUPLEX_INVALID;
8055 tp->link_config.advertising = 0;
8056 tp->link_config.speed = cmd->speed;
8057 tp->link_config.duplex = cmd->duplex;
8060 tp->link_config.orig_speed = tp->link_config.speed;
8061 tp->link_config.orig_duplex = tp->link_config.duplex;
8062 tp->link_config.orig_autoneg = tp->link_config.autoneg;
8064 if (netif_running(dev))
8065 tg3_setup_phy(tp, 1);
8067 tg3_full_unlock(tp);
8072 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8074 struct tg3 *tp = netdev_priv(dev);
8076 strcpy(info->driver, DRV_MODULE_NAME);
8077 strcpy(info->version, DRV_MODULE_VERSION);
8078 strcpy(info->fw_version, tp->fw_ver);
8079 strcpy(info->bus_info, pci_name(tp->pdev));
8082 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8084 struct tg3 *tp = netdev_priv(dev);
8086 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8087 wol->supported = WAKE_MAGIC;
8091 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8092 wol->wolopts = WAKE_MAGIC;
8093 memset(&wol->sopass, 0, sizeof(wol->sopass));
8096 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8098 struct tg3 *tp = netdev_priv(dev);
8100 if (wol->wolopts & ~WAKE_MAGIC)
8102 if ((wol->wolopts & WAKE_MAGIC) &&
8103 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8106 spin_lock_bh(&tp->lock);
8107 if (wol->wolopts & WAKE_MAGIC)
8108 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8110 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8111 spin_unlock_bh(&tp->lock);
8116 static u32 tg3_get_msglevel(struct net_device *dev)
8118 struct tg3 *tp = netdev_priv(dev);
8119 return tp->msg_enable;
8122 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8124 struct tg3 *tp = netdev_priv(dev);
8125 tp->msg_enable = value;
8128 static int tg3_set_tso(struct net_device *dev, u32 value)
8130 struct tg3 *tp = netdev_priv(dev);
8132 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8137 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8138 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8140 dev->features |= NETIF_F_TSO6;
8142 dev->features &= ~NETIF_F_TSO6;
8144 return ethtool_op_set_tso(dev, value);
8147 static int tg3_nway_reset(struct net_device *dev)
8149 struct tg3 *tp = netdev_priv(dev);
8153 if (!netif_running(dev))
8156 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8159 spin_lock_bh(&tp->lock);
8161 tg3_readphy(tp, MII_BMCR, &bmcr);
8162 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8163 ((bmcr & BMCR_ANENABLE) ||
8164 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8165 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8169 spin_unlock_bh(&tp->lock);
8174 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8176 struct tg3 *tp = netdev_priv(dev);
8178 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8179 ering->rx_mini_max_pending = 0;
8180 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8181 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8183 ering->rx_jumbo_max_pending = 0;
8185 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8187 ering->rx_pending = tp->rx_pending;
8188 ering->rx_mini_pending = 0;
8189 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8190 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8192 ering->rx_jumbo_pending = 0;
8194 ering->tx_pending = tp->tx_pending;
8197 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8199 struct tg3 *tp = netdev_priv(dev);
8200 int irq_sync = 0, err = 0;
8202 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8203 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8204 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8205 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8206 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8207 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8210 if (netif_running(dev)) {
8215 tg3_full_lock(tp, irq_sync);
8217 tp->rx_pending = ering->rx_pending;
8219 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8220 tp->rx_pending > 63)
8221 tp->rx_pending = 63;
8222 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8223 tp->tx_pending = ering->tx_pending;
8225 if (netif_running(dev)) {
8226 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8227 err = tg3_restart_hw(tp, 1);
8229 tg3_netif_start(tp);
8232 tg3_full_unlock(tp);
8237 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8239 struct tg3 *tp = netdev_priv(dev);
8241 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8242 epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8243 epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8246 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8248 struct tg3 *tp = netdev_priv(dev);
8249 int irq_sync = 0, err = 0;
8251 if (netif_running(dev)) {
8256 tg3_full_lock(tp, irq_sync);
8258 if (epause->autoneg)
8259 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8261 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8262 if (epause->rx_pause)
8263 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8265 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8266 if (epause->tx_pause)
8267 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8269 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8271 if (netif_running(dev)) {
8272 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8273 err = tg3_restart_hw(tp, 1);
8275 tg3_netif_start(tp);
8278 tg3_full_unlock(tp);
8283 static u32 tg3_get_rx_csum(struct net_device *dev)
8285 struct tg3 *tp = netdev_priv(dev);
8286 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8289 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8291 struct tg3 *tp = netdev_priv(dev);
8293 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8299 spin_lock_bh(&tp->lock);
8301 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8303 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8304 spin_unlock_bh(&tp->lock);
8309 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8311 struct tg3 *tp = netdev_priv(dev);
8313 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8319 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8320 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8321 ethtool_op_set_tx_hw_csum(dev, data);
8323 ethtool_op_set_tx_csum(dev, data);
8328 static int tg3_get_stats_count (struct net_device *dev)
8330 return TG3_NUM_STATS;
8333 static int tg3_get_test_count (struct net_device *dev)
8335 return TG3_NUM_TEST;
8338 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8340 switch (stringset) {
8342 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
8345 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
8348 WARN_ON(1); /* we need a WARN() */
8353 static int tg3_phys_id(struct net_device *dev, u32 data)
8355 struct tg3 *tp = netdev_priv(dev);
8358 if (!netif_running(tp->dev))
8364 for (i = 0; i < (data * 2); i++) {
8366 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8367 LED_CTRL_1000MBPS_ON |
8368 LED_CTRL_100MBPS_ON |
8369 LED_CTRL_10MBPS_ON |
8370 LED_CTRL_TRAFFIC_OVERRIDE |
8371 LED_CTRL_TRAFFIC_BLINK |
8372 LED_CTRL_TRAFFIC_LED);
8375 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8376 LED_CTRL_TRAFFIC_OVERRIDE);
8378 if (msleep_interruptible(500))
8381 tw32(MAC_LED_CTRL, tp->led_ctrl);
8385 static void tg3_get_ethtool_stats (struct net_device *dev,
8386 struct ethtool_stats *estats, u64 *tmp_stats)
8388 struct tg3 *tp = netdev_priv(dev);
8389 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8392 #define NVRAM_TEST_SIZE 0x100
8393 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8394 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8395 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8397 static int tg3_test_nvram(struct tg3 *tp)
8399 u32 *buf, csum, magic;
8400 int i, j, err = 0, size;
8402 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8405 if (magic == TG3_EEPROM_MAGIC)
8406 size = NVRAM_TEST_SIZE;
8407 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8408 if ((magic & 0xe00000) == 0x200000)
8409 size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8412 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8413 size = NVRAM_SELFBOOT_HW_SIZE;
8417 buf = kmalloc(size, GFP_KERNEL);
8422 for (i = 0, j = 0; i < size; i += 4, j++) {
8425 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8427 buf[j] = cpu_to_le32(val);
8432 /* Selfboot format */
8433 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8434 TG3_EEPROM_MAGIC_FW) {
8435 u8 *buf8 = (u8 *) buf, csum8 = 0;
8437 for (i = 0; i < size; i++)
8449 if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8450 TG3_EEPROM_MAGIC_HW) {
8451 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8452 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8453 u8 *buf8 = (u8 *) buf;
8456 /* Separate the parity bits and the data bytes. */
8457 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8458 if ((i == 0) || (i == 8)) {
8462 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8463 parity[k++] = buf8[i] & msk;
8470 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8471 parity[k++] = buf8[i] & msk;
8474 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8475 parity[k++] = buf8[i] & msk;
8478 data[j++] = buf8[i];
8482 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8483 u8 hw8 = hweight8(data[i]);
8485 if ((hw8 & 0x1) && parity[i])
8487 else if (!(hw8 & 0x1) && !parity[i])
8494 /* Bootstrap checksum at offset 0x10 */
8495 csum = calc_crc((unsigned char *) buf, 0x10);
8496 if(csum != cpu_to_le32(buf[0x10/4]))
8499 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8500 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8501 if (csum != cpu_to_le32(buf[0xfc/4]))
8511 #define TG3_SERDES_TIMEOUT_SEC 2
8512 #define TG3_COPPER_TIMEOUT_SEC 6
8514 static int tg3_test_link(struct tg3 *tp)
8518 if (!netif_running(tp->dev))
8521 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8522 max = TG3_SERDES_TIMEOUT_SEC;
8524 max = TG3_COPPER_TIMEOUT_SEC;
8526 for (i = 0; i < max; i++) {
8527 if (netif_carrier_ok(tp->dev))
8530 if (msleep_interruptible(1000))
8537 /* Only test the commonly used registers */
8538 static int tg3_test_registers(struct tg3 *tp)
8540 int i, is_5705, is_5750;
8541 u32 offset, read_mask, write_mask, val, save_val, read_val;
8545 #define TG3_FL_5705 0x1
8546 #define TG3_FL_NOT_5705 0x2
8547 #define TG3_FL_NOT_5788 0x4
8548 #define TG3_FL_NOT_5750 0x8
8552 /* MAC Control Registers */
8553 { MAC_MODE, TG3_FL_NOT_5705,
8554 0x00000000, 0x00ef6f8c },
8555 { MAC_MODE, TG3_FL_5705,
8556 0x00000000, 0x01ef6b8c },
8557 { MAC_STATUS, TG3_FL_NOT_5705,
8558 0x03800107, 0x00000000 },
8559 { MAC_STATUS, TG3_FL_5705,
8560 0x03800100, 0x00000000 },
8561 { MAC_ADDR_0_HIGH, 0x0000,
8562 0x00000000, 0x0000ffff },
8563 { MAC_ADDR_0_LOW, 0x0000,
8564 0x00000000, 0xffffffff },
8565 { MAC_RX_MTU_SIZE, 0x0000,
8566 0x00000000, 0x0000ffff },
8567 { MAC_TX_MODE, 0x0000,
8568 0x00000000, 0x00000070 },
8569 { MAC_TX_LENGTHS, 0x0000,
8570 0x00000000, 0x00003fff },
8571 { MAC_RX_MODE, TG3_FL_NOT_5705,
8572 0x00000000, 0x000007fc },
8573 { MAC_RX_MODE, TG3_FL_5705,
8574 0x00000000, 0x000007dc },
8575 { MAC_HASH_REG_0, 0x0000,
8576 0x00000000, 0xffffffff },
8577 { MAC_HASH_REG_1, 0x0000,
8578 0x00000000, 0xffffffff },
8579 { MAC_HASH_REG_2, 0x0000,
8580 0x00000000, 0xffffffff },
8581 { MAC_HASH_REG_3, 0x0000,
8582 0x00000000, 0xffffffff },
8584 /* Receive Data and Receive BD Initiator Control Registers. */
8585 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8586 0x00000000, 0xffffffff },
8587 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8588 0x00000000, 0xffffffff },
8589 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8590 0x00000000, 0x00000003 },
8591 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8592 0x00000000, 0xffffffff },
8593 { RCVDBDI_STD_BD+0, 0x0000,
8594 0x00000000, 0xffffffff },
8595 { RCVDBDI_STD_BD+4, 0x0000,
8596 0x00000000, 0xffffffff },
8597 { RCVDBDI_STD_BD+8, 0x0000,
8598 0x00000000, 0xffff0002 },
8599 { RCVDBDI_STD_BD+0xc, 0x0000,
8600 0x00000000, 0xffffffff },
8602 /* Receive BD Initiator Control Registers. */
8603 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8604 0x00000000, 0xffffffff },
8605 { RCVBDI_STD_THRESH, TG3_FL_5705,
8606 0x00000000, 0x000003ff },
8607 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8608 0x00000000, 0xffffffff },
8610 /* Host Coalescing Control Registers. */
8611 { HOSTCC_MODE, TG3_FL_NOT_5705,
8612 0x00000000, 0x00000004 },
8613 { HOSTCC_MODE, TG3_FL_5705,
8614 0x00000000, 0x000000f6 },
8615 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8616 0x00000000, 0xffffffff },
8617 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8618 0x00000000, 0x000003ff },
8619 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8620 0x00000000, 0xffffffff },
8621 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8622 0x00000000, 0x000003ff },
8623 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8624 0x00000000, 0xffffffff },
8625 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8626 0x00000000, 0x000000ff },
8627 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8628 0x00000000, 0xffffffff },
8629 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8630 0x00000000, 0x000000ff },
8631 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8632 0x00000000, 0xffffffff },
8633 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8634 0x00000000, 0xffffffff },
8635 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8636 0x00000000, 0xffffffff },
8637 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8638 0x00000000, 0x000000ff },
8639 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8640 0x00000000, 0xffffffff },
8641 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8642 0x00000000, 0x000000ff },
8643 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8644 0x00000000, 0xffffffff },
8645 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8646 0x00000000, 0xffffffff },
8647 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8648 0x00000000, 0xffffffff },
8649 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8650 0x00000000, 0xffffffff },
8651 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8652 0x00000000, 0xffffffff },
8653 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8654 0xffffffff, 0x00000000 },
8655 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8656 0xffffffff, 0x00000000 },
8658 /* Buffer Manager Control Registers. */
8659 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8660 0x00000000, 0x007fff80 },
8661 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8662 0x00000000, 0x007fffff },
8663 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8664 0x00000000, 0x0000003f },
8665 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8666 0x00000000, 0x000001ff },
8667 { BUFMGR_MB_HIGH_WATER, 0x0000,
8668 0x00000000, 0x000001ff },
8669 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8670 0xffffffff, 0x00000000 },
8671 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8672 0xffffffff, 0x00000000 },
8674 /* Mailbox Registers */
8675 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8676 0x00000000, 0x000001ff },
8677 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8678 0x00000000, 0x000001ff },
8679 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8680 0x00000000, 0x000007ff },
8681 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8682 0x00000000, 0x000001ff },
8684 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8687 is_5705 = is_5750 = 0;
8688 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8690 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8694 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8695 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8698 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8701 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8702 (reg_tbl[i].flags & TG3_FL_NOT_5788))
8705 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8708 offset = (u32) reg_tbl[i].offset;
8709 read_mask = reg_tbl[i].read_mask;
8710 write_mask = reg_tbl[i].write_mask;
8712 /* Save the original register content */
8713 save_val = tr32(offset);
8715 /* Determine the read-only value. */
8716 read_val = save_val & read_mask;
8718 /* Write zero to the register, then make sure the read-only bits
8719 * are not changed and the read/write bits are all zeros.
8725 /* Test the read-only and read/write bits. */
8726 if (((val & read_mask) != read_val) || (val & write_mask))
8729 /* Write ones to all the bits defined by RdMask and WrMask, then
8730 * make sure the read-only bits are not changed and the
8731 * read/write bits are all ones.
8733 tw32(offset, read_mask | write_mask);
8737 /* Test the read-only bits. */
8738 if ((val & read_mask) != read_val)
8741 /* Test the read/write bits. */
8742 if ((val & write_mask) != write_mask)
8745 tw32(offset, save_val);
8751 if (netif_msg_hw(tp))
8752 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8754 tw32(offset, save_val);
8758 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8760 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8764 for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8765 for (j = 0; j < len; j += 4) {
8768 tg3_write_mem(tp, offset + j, test_pattern[i]);
8769 tg3_read_mem(tp, offset + j, &val);
8770 if (val != test_pattern[i])
8777 static int tg3_test_memory(struct tg3 *tp)
8779 static struct mem_entry {
8782 } mem_tbl_570x[] = {
8783 { 0x00000000, 0x00b50},
8784 { 0x00002000, 0x1c000},
8785 { 0xffffffff, 0x00000}
8786 }, mem_tbl_5705[] = {
8787 { 0x00000100, 0x0000c},
8788 { 0x00000200, 0x00008},
8789 { 0x00004000, 0x00800},
8790 { 0x00006000, 0x01000},
8791 { 0x00008000, 0x02000},
8792 { 0x00010000, 0x0e000},
8793 { 0xffffffff, 0x00000}
8794 }, mem_tbl_5755[] = {
8795 { 0x00000200, 0x00008},
8796 { 0x00004000, 0x00800},
8797 { 0x00006000, 0x00800},
8798 { 0x00008000, 0x02000},
8799 { 0x00010000, 0x0c000},
8800 { 0xffffffff, 0x00000}
8801 }, mem_tbl_5906[] = {
8802 { 0x00000200, 0x00008},
8803 { 0x00004000, 0x00400},
8804 { 0x00006000, 0x00400},
8805 { 0x00008000, 0x01000},
8806 { 0x00010000, 0x01000},
8807 { 0xffffffff, 0x00000}
8809 struct mem_entry *mem_tbl;
8813 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8814 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8815 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8816 mem_tbl = mem_tbl_5755;
8817 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8818 mem_tbl = mem_tbl_5906;
8820 mem_tbl = mem_tbl_5705;
8822 mem_tbl = mem_tbl_570x;
8824 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8825 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8826 mem_tbl[i].len)) != 0)
8833 #define TG3_MAC_LOOPBACK 0
8834 #define TG3_PHY_LOOPBACK 1
8836 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8838 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8840 struct sk_buff *skb, *rx_skb;
8843 int num_pkts, tx_len, rx_len, i, err;
8844 struct tg3_rx_buffer_desc *desc;
8846 if (loopback_mode == TG3_MAC_LOOPBACK) {
8847 /* HW errata - mac loopback fails in some cases on 5780.
8848 * Normal traffic and PHY loopback are not affected by
8851 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8854 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8855 MAC_MODE_PORT_INT_LPBACK;
8856 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8857 mac_mode |= MAC_MODE_LINK_POLARITY;
8858 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8859 mac_mode |= MAC_MODE_PORT_MODE_MII;
8861 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8862 tw32(MAC_MODE, mac_mode);
8863 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8866 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8869 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8872 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8873 phytest | MII_TG3_EPHY_SHADOW_EN);
8874 if (!tg3_readphy(tp, 0x1b, &phy))
8875 tg3_writephy(tp, 0x1b, phy & ~0x20);
8876 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8878 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8880 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8882 tg3_phy_toggle_automdix(tp, 0);
8884 tg3_writephy(tp, MII_BMCR, val);
8887 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
8888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8889 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8890 mac_mode |= MAC_MODE_PORT_MODE_MII;
8892 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8894 /* reset to prevent losing 1st rx packet intermittently */
8895 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8896 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8898 tw32_f(MAC_RX_MODE, tp->rx_mode);
8900 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
8901 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8902 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8903 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
8904 mac_mode |= MAC_MODE_LINK_POLARITY;
8905 tg3_writephy(tp, MII_TG3_EXT_CTRL,
8906 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8908 tw32(MAC_MODE, mac_mode);
8916 skb = netdev_alloc_skb(tp->dev, tx_len);
8920 tx_data = skb_put(skb, tx_len);
8921 memcpy(tx_data, tp->dev->dev_addr, 6);
8922 memset(tx_data + 6, 0x0, 8);
8924 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8926 for (i = 14; i < tx_len; i++)
8927 tx_data[i] = (u8) (i & 0xff);
8929 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8931 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8936 rx_start_idx = tp->hw_status->idx[0].rx_producer;
8940 tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8945 tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8947 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8951 /* 250 usec to allow enough time on some 10/100 Mbps devices. */
8952 for (i = 0; i < 25; i++) {
8953 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8958 tx_idx = tp->hw_status->idx[0].tx_consumer;
8959 rx_idx = tp->hw_status->idx[0].rx_producer;
8960 if ((tx_idx == tp->tx_prod) &&
8961 (rx_idx == (rx_start_idx + num_pkts)))
8965 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8968 if (tx_idx != tp->tx_prod)
8971 if (rx_idx != rx_start_idx + num_pkts)
8974 desc = &tp->rx_rcb[rx_start_idx];
8975 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8976 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8977 if (opaque_key != RXD_OPAQUE_RING_STD)
8980 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8981 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8984 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8985 if (rx_len != tx_len)
8988 rx_skb = tp->rx_std_buffers[desc_idx].skb;
8990 map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8991 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8993 for (i = 14; i < tx_len; i++) {
8994 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8999 /* tg3_free_rings will unmap and free the rx_skb */
9004 #define TG3_MAC_LOOPBACK_FAILED 1
9005 #define TG3_PHY_LOOPBACK_FAILED 2
9006 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
9007 TG3_PHY_LOOPBACK_FAILED)
9009 static int tg3_test_loopback(struct tg3 *tp)
9013 if (!netif_running(tp->dev))
9014 return TG3_LOOPBACK_FAILED;
9016 err = tg3_reset_hw(tp, 1);
9018 return TG3_LOOPBACK_FAILED;
9020 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
9021 err |= TG3_MAC_LOOPBACK_FAILED;
9022 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9023 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
9024 err |= TG3_PHY_LOOPBACK_FAILED;
9030 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
9033 struct tg3 *tp = netdev_priv(dev);
9035 if (tp->link_config.phy_is_low_power)
9036 tg3_set_power_state(tp, PCI_D0);
9038 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
9040 if (tg3_test_nvram(tp) != 0) {
9041 etest->flags |= ETH_TEST_FL_FAILED;
9044 if (tg3_test_link(tp) != 0) {
9045 etest->flags |= ETH_TEST_FL_FAILED;
9048 if (etest->flags & ETH_TEST_FL_OFFLINE) {
9049 int err, irq_sync = 0;
9051 if (netif_running(dev)) {
9056 tg3_full_lock(tp, irq_sync);
9058 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
9059 err = tg3_nvram_lock(tp);
9060 tg3_halt_cpu(tp, RX_CPU_BASE);
9061 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
9062 tg3_halt_cpu(tp, TX_CPU_BASE);
9064 tg3_nvram_unlock(tp);
9066 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
9069 if (tg3_test_registers(tp) != 0) {
9070 etest->flags |= ETH_TEST_FL_FAILED;
9073 if (tg3_test_memory(tp) != 0) {
9074 etest->flags |= ETH_TEST_FL_FAILED;
9077 if ((data[4] = tg3_test_loopback(tp)) != 0)
9078 etest->flags |= ETH_TEST_FL_FAILED;
9080 tg3_full_unlock(tp);
9082 if (tg3_test_interrupt(tp) != 0) {
9083 etest->flags |= ETH_TEST_FL_FAILED;
9087 tg3_full_lock(tp, 0);
9089 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9090 if (netif_running(dev)) {
9091 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9092 if (!tg3_restart_hw(tp, 1))
9093 tg3_netif_start(tp);
9096 tg3_full_unlock(tp);
9098 if (tp->link_config.phy_is_low_power)
9099 tg3_set_power_state(tp, PCI_D3hot);
9103 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9105 struct mii_ioctl_data *data = if_mii(ifr);
9106 struct tg3 *tp = netdev_priv(dev);
9111 data->phy_id = PHY_ADDR;
9117 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9118 break; /* We have no PHY */
9120 if (tp->link_config.phy_is_low_power)
9123 spin_lock_bh(&tp->lock);
9124 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9125 spin_unlock_bh(&tp->lock);
9127 data->val_out = mii_regval;
9133 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9134 break; /* We have no PHY */
9136 if (!capable(CAP_NET_ADMIN))
9139 if (tp->link_config.phy_is_low_power)
9142 spin_lock_bh(&tp->lock);
9143 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9144 spin_unlock_bh(&tp->lock);
9155 #if TG3_VLAN_TAG_USED
9156 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9158 struct tg3 *tp = netdev_priv(dev);
9160 if (netif_running(dev))
9163 tg3_full_lock(tp, 0);
9167 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9168 __tg3_set_rx_mode(dev);
9170 if (netif_running(dev))
9171 tg3_netif_start(tp);
9173 tg3_full_unlock(tp);
9177 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9179 struct tg3 *tp = netdev_priv(dev);
9181 memcpy(ec, &tp->coal, sizeof(*ec));
9185 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9187 struct tg3 *tp = netdev_priv(dev);
9188 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9189 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9191 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9192 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9193 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9194 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9195 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9198 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9199 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9200 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9201 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9202 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9203 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9204 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9205 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9206 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9207 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9210 /* No rx interrupts will be generated if both are zero */
9211 if ((ec->rx_coalesce_usecs == 0) &&
9212 (ec->rx_max_coalesced_frames == 0))
9215 /* No tx interrupts will be generated if both are zero */
9216 if ((ec->tx_coalesce_usecs == 0) &&
9217 (ec->tx_max_coalesced_frames == 0))
9220 /* Only copy relevant parameters, ignore all others. */
9221 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9222 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9223 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9224 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9225 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9226 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9227 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9228 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9229 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9231 if (netif_running(dev)) {
9232 tg3_full_lock(tp, 0);
9233 __tg3_set_coalesce(tp, &tp->coal);
9234 tg3_full_unlock(tp);
9239 static const struct ethtool_ops tg3_ethtool_ops = {
9240 .get_settings = tg3_get_settings,
9241 .set_settings = tg3_set_settings,
9242 .get_drvinfo = tg3_get_drvinfo,
9243 .get_regs_len = tg3_get_regs_len,
9244 .get_regs = tg3_get_regs,
9245 .get_wol = tg3_get_wol,
9246 .set_wol = tg3_set_wol,
9247 .get_msglevel = tg3_get_msglevel,
9248 .set_msglevel = tg3_set_msglevel,
9249 .nway_reset = tg3_nway_reset,
9250 .get_link = ethtool_op_get_link,
9251 .get_eeprom_len = tg3_get_eeprom_len,
9252 .get_eeprom = tg3_get_eeprom,
9253 .set_eeprom = tg3_set_eeprom,
9254 .get_ringparam = tg3_get_ringparam,
9255 .set_ringparam = tg3_set_ringparam,
9256 .get_pauseparam = tg3_get_pauseparam,
9257 .set_pauseparam = tg3_set_pauseparam,
9258 .get_rx_csum = tg3_get_rx_csum,
9259 .set_rx_csum = tg3_set_rx_csum,
9260 .get_tx_csum = ethtool_op_get_tx_csum,
9261 .set_tx_csum = tg3_set_tx_csum,
9262 .get_sg = ethtool_op_get_sg,
9263 .set_sg = ethtool_op_set_sg,
9264 .get_tso = ethtool_op_get_tso,
9265 .set_tso = tg3_set_tso,
9266 .self_test_count = tg3_get_test_count,
9267 .self_test = tg3_self_test,
9268 .get_strings = tg3_get_strings,
9269 .phys_id = tg3_phys_id,
9270 .get_stats_count = tg3_get_stats_count,
9271 .get_ethtool_stats = tg3_get_ethtool_stats,
9272 .get_coalesce = tg3_get_coalesce,
9273 .set_coalesce = tg3_set_coalesce,
9274 .get_perm_addr = ethtool_op_get_perm_addr,
9277 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9279 u32 cursize, val, magic;
9281 tp->nvram_size = EEPROM_CHIP_SIZE;
9283 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9286 if ((magic != TG3_EEPROM_MAGIC) &&
9287 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9288 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9292 * Size the chip by reading offsets at increasing powers of two.
9293 * When we encounter our validation signature, we know the addressing
9294 * has wrapped around, and thus have our chip size.
9298 while (cursize < tp->nvram_size) {
9299 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9308 tp->nvram_size = cursize;
9311 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9315 if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9318 /* Selfboot format */
9319 if (val != TG3_EEPROM_MAGIC) {
9320 tg3_get_eeprom_size(tp);
9324 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9326 tp->nvram_size = (val >> 16) * 1024;
9330 tp->nvram_size = 0x80000;
9333 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9337 nvcfg1 = tr32(NVRAM_CFG1);
9338 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9339 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9342 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9343 tw32(NVRAM_CFG1, nvcfg1);
9346 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9347 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9348 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9349 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9350 tp->nvram_jedecnum = JEDEC_ATMEL;
9351 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9352 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9354 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9355 tp->nvram_jedecnum = JEDEC_ATMEL;
9356 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9358 case FLASH_VENDOR_ATMEL_EEPROM:
9359 tp->nvram_jedecnum = JEDEC_ATMEL;
9360 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9361 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9363 case FLASH_VENDOR_ST:
9364 tp->nvram_jedecnum = JEDEC_ST;
9365 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9368 case FLASH_VENDOR_SAIFUN:
9369 tp->nvram_jedecnum = JEDEC_SAIFUN;
9370 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9372 case FLASH_VENDOR_SST_SMALL:
9373 case FLASH_VENDOR_SST_LARGE:
9374 tp->nvram_jedecnum = JEDEC_SST;
9375 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9380 tp->nvram_jedecnum = JEDEC_ATMEL;
9381 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9382 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9386 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9390 nvcfg1 = tr32(NVRAM_CFG1);
9392 /* NVRAM protection for TPM */
9393 if (nvcfg1 & (1 << 27))
9394 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9396 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9397 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9398 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9399 tp->nvram_jedecnum = JEDEC_ATMEL;
9400 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9402 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9403 tp->nvram_jedecnum = JEDEC_ATMEL;
9404 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9405 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9407 case FLASH_5752VENDOR_ST_M45PE10:
9408 case FLASH_5752VENDOR_ST_M45PE20:
9409 case FLASH_5752VENDOR_ST_M45PE40:
9410 tp->nvram_jedecnum = JEDEC_ST;
9411 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9412 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9416 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9417 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9418 case FLASH_5752PAGE_SIZE_256:
9419 tp->nvram_pagesize = 256;
9421 case FLASH_5752PAGE_SIZE_512:
9422 tp->nvram_pagesize = 512;
9424 case FLASH_5752PAGE_SIZE_1K:
9425 tp->nvram_pagesize = 1024;
9427 case FLASH_5752PAGE_SIZE_2K:
9428 tp->nvram_pagesize = 2048;
9430 case FLASH_5752PAGE_SIZE_4K:
9431 tp->nvram_pagesize = 4096;
9433 case FLASH_5752PAGE_SIZE_264:
9434 tp->nvram_pagesize = 264;
9439 /* For eeprom, set pagesize to maximum eeprom size */
9440 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9442 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9443 tw32(NVRAM_CFG1, nvcfg1);
9447 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9449 u32 nvcfg1, protect = 0;
9451 nvcfg1 = tr32(NVRAM_CFG1);
9453 /* NVRAM protection for TPM */
9454 if (nvcfg1 & (1 << 27)) {
9455 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9459 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
9461 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9462 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9463 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9464 tp->nvram_jedecnum = JEDEC_ATMEL;
9465 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9466 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9467 tp->nvram_pagesize = 264;
9468 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1)
9469 tp->nvram_size = (protect ? 0x3e200 : 0x80000);
9470 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
9471 tp->nvram_size = (protect ? 0x1f200 : 0x40000);
9473 tp->nvram_size = (protect ? 0x1f200 : 0x20000);
9475 case FLASH_5752VENDOR_ST_M45PE10:
9476 case FLASH_5752VENDOR_ST_M45PE20:
9477 case FLASH_5752VENDOR_ST_M45PE40:
9478 tp->nvram_jedecnum = JEDEC_ST;
9479 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9480 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9481 tp->nvram_pagesize = 256;
9482 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
9483 tp->nvram_size = (protect ? 0x10000 : 0x20000);
9484 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
9485 tp->nvram_size = (protect ? 0x10000 : 0x40000);
9487 tp->nvram_size = (protect ? 0x20000 : 0x80000);
9492 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9496 nvcfg1 = tr32(NVRAM_CFG1);
9498 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9499 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9500 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9501 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9502 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9503 tp->nvram_jedecnum = JEDEC_ATMEL;
9504 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9505 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9507 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9508 tw32(NVRAM_CFG1, nvcfg1);
9510 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9511 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9512 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9513 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9514 tp->nvram_jedecnum = JEDEC_ATMEL;
9515 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9516 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9517 tp->nvram_pagesize = 264;
9519 case FLASH_5752VENDOR_ST_M45PE10:
9520 case FLASH_5752VENDOR_ST_M45PE20:
9521 case FLASH_5752VENDOR_ST_M45PE40:
9522 tp->nvram_jedecnum = JEDEC_ST;
9523 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9524 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9525 tp->nvram_pagesize = 256;
9530 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9532 tp->nvram_jedecnum = JEDEC_ATMEL;
9533 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9534 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9537 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9538 static void __devinit tg3_nvram_init(struct tg3 *tp)
9540 tw32_f(GRC_EEPROM_ADDR,
9541 (EEPROM_ADDR_FSM_RESET |
9542 (EEPROM_DEFAULT_CLOCK_PERIOD <<
9543 EEPROM_ADDR_CLKPERD_SHIFT)));
9547 /* Enable seeprom accesses. */
9548 tw32_f(GRC_LOCAL_CTRL,
9549 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9552 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9553 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9554 tp->tg3_flags |= TG3_FLAG_NVRAM;
9556 if (tg3_nvram_lock(tp)) {
9557 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9558 "tg3_nvram_init failed.\n", tp->dev->name);
9561 tg3_enable_nvram_access(tp);
9565 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9566 tg3_get_5752_nvram_info(tp);
9567 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9568 tg3_get_5755_nvram_info(tp);
9569 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9570 tg3_get_5787_nvram_info(tp);
9571 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9572 tg3_get_5906_nvram_info(tp);
9574 tg3_get_nvram_info(tp);
9576 if (tp->nvram_size == 0)
9577 tg3_get_nvram_size(tp);
9579 tg3_disable_nvram_access(tp);
9580 tg3_nvram_unlock(tp);
9583 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9585 tg3_get_eeprom_size(tp);
9589 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9590 u32 offset, u32 *val)
9595 if (offset > EEPROM_ADDR_ADDR_MASK ||
9599 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9600 EEPROM_ADDR_DEVID_MASK |
9602 tw32(GRC_EEPROM_ADDR,
9604 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9605 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9606 EEPROM_ADDR_ADDR_MASK) |
9607 EEPROM_ADDR_READ | EEPROM_ADDR_START);
9609 for (i = 0; i < 1000; i++) {
9610 tmp = tr32(GRC_EEPROM_ADDR);
9612 if (tmp & EEPROM_ADDR_COMPLETE)
9616 if (!(tmp & EEPROM_ADDR_COMPLETE))
9619 *val = tr32(GRC_EEPROM_DATA);
9623 #define NVRAM_CMD_TIMEOUT 10000
9625 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9629 tw32(NVRAM_CMD, nvram_cmd);
9630 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9632 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9637 if (i == NVRAM_CMD_TIMEOUT) {
9643 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9645 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9646 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9647 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9648 (tp->nvram_jedecnum == JEDEC_ATMEL))
9650 addr = ((addr / tp->nvram_pagesize) <<
9651 ATMEL_AT45DB0X1B_PAGE_POS) +
9652 (addr % tp->nvram_pagesize);
9657 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9659 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9660 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9661 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9662 (tp->nvram_jedecnum == JEDEC_ATMEL))
9664 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9665 tp->nvram_pagesize) +
9666 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9671 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9675 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9676 return tg3_nvram_read_using_eeprom(tp, offset, val);
9678 offset = tg3_nvram_phys_addr(tp, offset);
9680 if (offset > NVRAM_ADDR_MSK)
9683 ret = tg3_nvram_lock(tp);
9687 tg3_enable_nvram_access(tp);
9689 tw32(NVRAM_ADDR, offset);
9690 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9691 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9694 *val = swab32(tr32(NVRAM_RDDATA));
9696 tg3_disable_nvram_access(tp);
9698 tg3_nvram_unlock(tp);
9703 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9708 err = tg3_nvram_read(tp, offset, &tmp);
9713 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9714 u32 offset, u32 len, u8 *buf)
9719 for (i = 0; i < len; i += 4) {
9724 memcpy(&data, buf + i, 4);
9726 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9728 val = tr32(GRC_EEPROM_ADDR);
9729 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9731 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9733 tw32(GRC_EEPROM_ADDR, val |
9734 (0 << EEPROM_ADDR_DEVID_SHIFT) |
9735 (addr & EEPROM_ADDR_ADDR_MASK) |
9739 for (j = 0; j < 1000; j++) {
9740 val = tr32(GRC_EEPROM_ADDR);
9742 if (val & EEPROM_ADDR_COMPLETE)
9746 if (!(val & EEPROM_ADDR_COMPLETE)) {
9755 /* offset and length are dword aligned */
9756 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9760 u32 pagesize = tp->nvram_pagesize;
9761 u32 pagemask = pagesize - 1;
9765 tmp = kmalloc(pagesize, GFP_KERNEL);
9771 u32 phy_addr, page_off, size;
9773 phy_addr = offset & ~pagemask;
9775 for (j = 0; j < pagesize; j += 4) {
9776 if ((ret = tg3_nvram_read(tp, phy_addr + j,
9777 (u32 *) (tmp + j))))
9783 page_off = offset & pagemask;
9790 memcpy(tmp + page_off, buf, size);
9792 offset = offset + (pagesize - page_off);
9794 tg3_enable_nvram_access(tp);
9797 * Before we can erase the flash page, we need
9798 * to issue a special "write enable" command.
9800 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9802 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9805 /* Erase the target page */
9806 tw32(NVRAM_ADDR, phy_addr);
9808 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9809 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9811 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9814 /* Issue another write enable to start the write. */
9815 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9817 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9820 for (j = 0; j < pagesize; j += 4) {
9823 data = *((u32 *) (tmp + j));
9824 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9826 tw32(NVRAM_ADDR, phy_addr + j);
9828 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9832 nvram_cmd |= NVRAM_CMD_FIRST;
9833 else if (j == (pagesize - 4))
9834 nvram_cmd |= NVRAM_CMD_LAST;
9836 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9843 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9844 tg3_nvram_exec_cmd(tp, nvram_cmd);
9851 /* offset and length are dword aligned */
9852 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9857 for (i = 0; i < len; i += 4, offset += 4) {
9858 u32 data, page_off, phy_addr, nvram_cmd;
9860 memcpy(&data, buf + i, 4);
9861 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9863 page_off = offset % tp->nvram_pagesize;
9865 phy_addr = tg3_nvram_phys_addr(tp, offset);
9867 tw32(NVRAM_ADDR, phy_addr);
9869 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9871 if ((page_off == 0) || (i == 0))
9872 nvram_cmd |= NVRAM_CMD_FIRST;
9873 if (page_off == (tp->nvram_pagesize - 4))
9874 nvram_cmd |= NVRAM_CMD_LAST;
9877 nvram_cmd |= NVRAM_CMD_LAST;
9879 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9880 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9881 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9882 (tp->nvram_jedecnum == JEDEC_ST) &&
9883 (nvram_cmd & NVRAM_CMD_FIRST)) {
9885 if ((ret = tg3_nvram_exec_cmd(tp,
9886 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9891 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9892 /* We always do complete word writes to eeprom. */
9893 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9896 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9902 /* offset and length are dword aligned */
9903 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9907 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9908 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9909 ~GRC_LCLCTRL_GPIO_OUTPUT1);
9913 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9914 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9919 ret = tg3_nvram_lock(tp);
9923 tg3_enable_nvram_access(tp);
9924 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9925 !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9926 tw32(NVRAM_WRITE1, 0x406);
9928 grc_mode = tr32(GRC_MODE);
9929 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9931 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9932 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9934 ret = tg3_nvram_write_block_buffered(tp, offset, len,
9938 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9942 grc_mode = tr32(GRC_MODE);
9943 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9945 tg3_disable_nvram_access(tp);
9946 tg3_nvram_unlock(tp);
9949 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9950 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9957 struct subsys_tbl_ent {
9958 u16 subsys_vendor, subsys_devid;
9962 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9963 /* Broadcom boards. */
9964 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9965 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9966 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9967 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
9968 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9969 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9970 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
9971 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9972 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9973 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9974 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9977 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9978 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9979 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
9980 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9981 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9984 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9985 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9986 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9987 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9989 /* Compaq boards. */
9990 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9991 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9992 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
9993 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9994 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9997 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
10000 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
10004 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
10005 if ((subsys_id_to_phy_id[i].subsys_vendor ==
10006 tp->pdev->subsystem_vendor) &&
10007 (subsys_id_to_phy_id[i].subsys_devid ==
10008 tp->pdev->subsystem_device))
10009 return &subsys_id_to_phy_id[i];
10014 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10019 /* On some early chips the SRAM cannot be accessed in D3hot state,
10020 * so need make sure we're in D0.
10022 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
10023 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
10024 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
10027 /* Make sure register accesses (indirect or otherwise)
10028 * will function correctly.
10030 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10031 tp->misc_host_ctrl);
10033 /* The memory arbiter has to be enabled in order for SRAM accesses
10034 * to succeed. Normally on powerup the tg3 chip firmware will make
10035 * sure it is enabled, but other entities such as system netboot
10036 * code might disable it.
10038 val = tr32(MEMARB_MODE);
10039 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
10041 tp->phy_id = PHY_ID_INVALID;
10042 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10044 /* Assume an onboard device and WOL capable by default. */
10045 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10048 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
10049 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10050 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10052 if (tr32(VCPU_CFGSHDW) & VCPU_CFGSHDW_ASPM_DBNC)
10053 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10057 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
10058 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
10059 u32 nic_cfg, led_cfg;
10060 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
10061 int eeprom_phy_serdes = 0;
10063 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10064 tp->nic_sram_data_cfg = nic_cfg;
10066 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10067 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10068 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10069 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10070 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10071 (ver > 0) && (ver < 0x100))
10072 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10074 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10075 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10076 eeprom_phy_serdes = 1;
10078 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10079 if (nic_phy_id != 0) {
10080 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10081 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10083 eeprom_phy_id = (id1 >> 16) << 10;
10084 eeprom_phy_id |= (id2 & 0xfc00) << 16;
10085 eeprom_phy_id |= (id2 & 0x03ff) << 0;
10089 tp->phy_id = eeprom_phy_id;
10090 if (eeprom_phy_serdes) {
10091 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10092 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10094 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10097 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10098 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10099 SHASTA_EXT_LED_MODE_MASK);
10101 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10105 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10106 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10109 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10110 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10113 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10114 tp->led_ctrl = LED_CTRL_MODE_MAC;
10116 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10117 * read on some older 5700/5701 bootcode.
10119 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10121 GET_ASIC_REV(tp->pci_chip_rev_id) ==
10123 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10127 case SHASTA_EXT_LED_SHARED:
10128 tp->led_ctrl = LED_CTRL_MODE_SHARED;
10129 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10130 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10131 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10132 LED_CTRL_MODE_PHY_2);
10135 case SHASTA_EXT_LED_MAC:
10136 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10139 case SHASTA_EXT_LED_COMBO:
10140 tp->led_ctrl = LED_CTRL_MODE_COMBO;
10141 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10142 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10143 LED_CTRL_MODE_PHY_2);
10148 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10149 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10150 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10151 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10153 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10154 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10155 if ((tp->pdev->subsystem_vendor ==
10156 PCI_VENDOR_ID_ARIMA) &&
10157 (tp->pdev->subsystem_device == 0x205a ||
10158 tp->pdev->subsystem_device == 0x2063))
10159 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10161 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10162 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10165 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10166 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10167 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10168 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10170 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10171 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10172 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10174 if (cfg2 & (1 << 17))
10175 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10177 /* serdes signal pre-emphasis in register 0x590 set by */
10178 /* bootcode if bit 18 is set */
10179 if (cfg2 & (1 << 18))
10180 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10182 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10185 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
10186 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
10187 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
10192 static int __devinit tg3_phy_probe(struct tg3 *tp)
10194 u32 hw_phy_id_1, hw_phy_id_2;
10195 u32 hw_phy_id, hw_phy_id_masked;
10198 /* Reading the PHY ID register can conflict with ASF
10199 * firwmare access to the PHY hardware.
10202 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10203 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10205 /* Now read the physical PHY_ID from the chip and verify
10206 * that it is sane. If it doesn't look good, we fall back
10207 * to either the hard-coded table based PHY_ID and failing
10208 * that the value found in the eeprom area.
10210 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10211 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10213 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
10214 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10215 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
10217 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10220 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10221 tp->phy_id = hw_phy_id;
10222 if (hw_phy_id_masked == PHY_ID_BCM8002)
10223 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10225 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10227 if (tp->phy_id != PHY_ID_INVALID) {
10228 /* Do nothing, phy ID already set up in
10229 * tg3_get_eeprom_hw_cfg().
10232 struct subsys_tbl_ent *p;
10234 /* No eeprom signature? Try the hardcoded
10235 * subsys device table.
10237 p = lookup_by_subsys(tp);
10241 tp->phy_id = p->phy_id;
10243 tp->phy_id == PHY_ID_BCM8002)
10244 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10248 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10249 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10250 u32 bmsr, adv_reg, tg3_ctrl, mask;
10252 tg3_readphy(tp, MII_BMSR, &bmsr);
10253 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10254 (bmsr & BMSR_LSTATUS))
10255 goto skip_phy_reset;
10257 err = tg3_phy_reset(tp);
10261 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10262 ADVERTISE_100HALF | ADVERTISE_100FULL |
10263 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10265 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10266 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10267 MII_TG3_CTRL_ADV_1000_FULL);
10268 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10269 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10270 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10271 MII_TG3_CTRL_ENABLE_AS_MASTER);
10274 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10275 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10276 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10277 if (!tg3_copper_is_advertising_all(tp, mask)) {
10278 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10280 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10281 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10283 tg3_writephy(tp, MII_BMCR,
10284 BMCR_ANENABLE | BMCR_ANRESTART);
10286 tg3_phy_set_wirespeed(tp);
10288 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10289 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10290 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10294 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10295 err = tg3_init_5401phy_dsp(tp);
10300 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10301 err = tg3_init_5401phy_dsp(tp);
10304 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10305 tp->link_config.advertising =
10306 (ADVERTISED_1000baseT_Half |
10307 ADVERTISED_1000baseT_Full |
10308 ADVERTISED_Autoneg |
10310 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10311 tp->link_config.advertising &=
10312 ~(ADVERTISED_1000baseT_Half |
10313 ADVERTISED_1000baseT_Full);
10318 static void __devinit tg3_read_partno(struct tg3 *tp)
10320 unsigned char vpd_data[256];
10324 if (tg3_nvram_read_swab(tp, 0x0, &magic))
10325 goto out_not_found;
10327 if (magic == TG3_EEPROM_MAGIC) {
10328 for (i = 0; i < 256; i += 4) {
10331 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10332 goto out_not_found;
10334 vpd_data[i + 0] = ((tmp >> 0) & 0xff);
10335 vpd_data[i + 1] = ((tmp >> 8) & 0xff);
10336 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10337 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10342 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10343 for (i = 0; i < 256; i += 4) {
10347 pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10349 while (j++ < 100) {
10350 pci_read_config_word(tp->pdev, vpd_cap +
10351 PCI_VPD_ADDR, &tmp16);
10352 if (tmp16 & 0x8000)
10356 if (!(tmp16 & 0x8000))
10357 goto out_not_found;
10359 pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10361 tmp = cpu_to_le32(tmp);
10362 memcpy(&vpd_data[i], &tmp, 4);
10366 /* Now parse and find the part number. */
10367 for (i = 0; i < 254; ) {
10368 unsigned char val = vpd_data[i];
10369 unsigned int block_end;
10371 if (val == 0x82 || val == 0x91) {
10374 (vpd_data[i + 2] << 8)));
10379 goto out_not_found;
10381 block_end = (i + 3 +
10383 (vpd_data[i + 2] << 8)));
10386 if (block_end > 256)
10387 goto out_not_found;
10389 while (i < (block_end - 2)) {
10390 if (vpd_data[i + 0] == 'P' &&
10391 vpd_data[i + 1] == 'N') {
10392 int partno_len = vpd_data[i + 2];
10395 if (partno_len > 24 || (partno_len + i) > 256)
10396 goto out_not_found;
10398 memcpy(tp->board_part_number,
10399 &vpd_data[i], partno_len);
10404 i += 3 + vpd_data[i + 2];
10407 /* Part number not found. */
10408 goto out_not_found;
10412 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10413 strcpy(tp->board_part_number, "BCM95906");
10415 strcpy(tp->board_part_number, "none");
10418 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10420 u32 val, offset, start;
10422 if (tg3_nvram_read_swab(tp, 0, &val))
10425 if (val != TG3_EEPROM_MAGIC)
10428 if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10429 tg3_nvram_read_swab(tp, 0x4, &start))
10432 offset = tg3_nvram_logical_addr(tp, offset);
10433 if (tg3_nvram_read_swab(tp, offset, &val))
10436 if ((val & 0xfc000000) == 0x0c000000) {
10437 u32 ver_offset, addr;
10440 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10441 tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10447 addr = offset + ver_offset - start;
10448 for (i = 0; i < 16; i += 4) {
10449 if (tg3_nvram_read(tp, addr + i, &val))
10452 val = cpu_to_le32(val);
10453 memcpy(tp->fw_ver + i, &val, 4);
10458 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
10460 static int __devinit tg3_get_invariants(struct tg3 *tp)
10462 static struct pci_device_id write_reorder_chipsets[] = {
10463 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10464 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10465 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10466 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10467 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10468 PCI_DEVICE_ID_VIA_8385_0) },
10472 u32 cacheline_sz_reg;
10473 u32 pci_state_reg, grc_misc_cfg;
10478 /* Force memory write invalidate off. If we leave it on,
10479 * then on 5700_BX chips we have to enable a workaround.
10480 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10481 * to match the cacheline size. The Broadcom driver have this
10482 * workaround but turns MWI off all the times so never uses
10483 * it. This seems to suggest that the workaround is insufficient.
10485 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10486 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10487 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10489 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10490 * has the register indirect write enable bit set before
10491 * we try to access any of the MMIO registers. It is also
10492 * critical that the PCI-X hw workaround situation is decided
10493 * before that as well.
10495 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10498 tp->pci_chip_rev_id = (misc_ctrl_reg >>
10499 MISC_HOST_CTRL_CHIPREV_SHIFT);
10501 /* Wrong chip ID in 5752 A0. This code can be removed later
10502 * as A0 is not in production.
10504 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10505 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10507 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10508 * we need to disable memory and use config. cycles
10509 * only to access all registers. The 5702/03 chips
10510 * can mistakenly decode the special cycles from the
10511 * ICH chipsets as memory write cycles, causing corruption
10512 * of register and memory space. Only certain ICH bridges
10513 * will drive special cycles with non-zero data during the
10514 * address phase which can fall within the 5703's address
10515 * range. This is not an ICH bug as the PCI spec allows
10516 * non-zero address during special cycles. However, only
10517 * these ICH bridges are known to drive non-zero addresses
10518 * during special cycles.
10520 * Since special cycles do not cross PCI bridges, we only
10521 * enable this workaround if the 5703 is on the secondary
10522 * bus of these ICH bridges.
10524 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10525 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10526 static struct tg3_dev_id {
10530 } ich_chipsets[] = {
10531 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10533 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10535 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10537 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10541 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10542 struct pci_dev *bridge = NULL;
10544 while (pci_id->vendor != 0) {
10545 bridge = pci_get_device(pci_id->vendor, pci_id->device,
10551 if (pci_id->rev != PCI_ANY_ID) {
10554 pci_read_config_byte(bridge, PCI_REVISION_ID,
10556 if (rev > pci_id->rev)
10559 if (bridge->subordinate &&
10560 (bridge->subordinate->number ==
10561 tp->pdev->bus->number)) {
10563 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10564 pci_dev_put(bridge);
10570 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10571 * DMA addresses > 40-bit. This bridge may have other additional
10572 * 57xx devices behind it in some 4-port NIC designs for example.
10573 * Any tg3 device found behind the bridge will also need the 40-bit
10576 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10577 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10578 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10579 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10580 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10583 struct pci_dev *bridge = NULL;
10586 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10587 PCI_DEVICE_ID_SERVERWORKS_EPB,
10589 if (bridge && bridge->subordinate &&
10590 (bridge->subordinate->number <=
10591 tp->pdev->bus->number) &&
10592 (bridge->subordinate->subordinate >=
10593 tp->pdev->bus->number)) {
10594 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10595 pci_dev_put(bridge);
10601 /* Initialize misc host control in PCI block. */
10602 tp->misc_host_ctrl |= (misc_ctrl_reg &
10603 MISC_HOST_CTRL_CHIPREV);
10604 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10605 tp->misc_host_ctrl);
10607 pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10608 &cacheline_sz_reg);
10610 tp->pci_cacheline_sz = (cacheline_sz_reg >> 0) & 0xff;
10611 tp->pci_lat_timer = (cacheline_sz_reg >> 8) & 0xff;
10612 tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
10613 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
10615 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10616 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10617 tp->pdev_peer = tg3_find_peer(tp);
10619 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10620 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10621 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10622 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10623 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10624 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10625 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10627 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10628 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10629 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10631 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10632 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
10633 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
10634 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
10635 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
10636 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
10637 tp->pdev_peer == tp->pdev))
10638 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
10640 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10641 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10642 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10643 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10644 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10646 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10647 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10649 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10650 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10654 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10655 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10656 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10657 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10658 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10659 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10660 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10662 pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10663 if (pcie_cap != 0) {
10664 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10665 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10668 pci_read_config_word(tp->pdev,
10669 pcie_cap + PCI_EXP_LNKCTL,
10671 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10672 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10676 /* If we have an AMD 762 or VIA K8T800 chipset, write
10677 * reordering to the mailbox registers done by the host
10678 * controller can cause major troubles. We read back from
10679 * every mailbox register write to force the writes to be
10680 * posted to the chip in order.
10682 if (pci_dev_present(write_reorder_chipsets) &&
10683 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10684 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10686 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10687 tp->pci_lat_timer < 64) {
10688 tp->pci_lat_timer = 64;
10690 cacheline_sz_reg = ((tp->pci_cacheline_sz & 0xff) << 0);
10691 cacheline_sz_reg |= ((tp->pci_lat_timer & 0xff) << 8);
10692 cacheline_sz_reg |= ((tp->pci_hdr_type & 0xff) << 16);
10693 cacheline_sz_reg |= ((tp->pci_bist & 0xff) << 24);
10695 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10699 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10702 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10703 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10705 /* If this is a 5700 BX chipset, and we are in PCI-X
10706 * mode, enable register write workaround.
10708 * The workaround is to use indirect register accesses
10709 * for all chip writes not to mailbox registers.
10711 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10715 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10717 /* The chip can have it's power management PCI config
10718 * space registers clobbered due to this bug.
10719 * So explicitly force the chip into D0 here.
10721 pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10723 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10724 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10725 pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10728 /* Also, force SERR#/PERR# in PCI command. */
10729 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10730 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10731 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10735 /* 5700 BX chips need to have their TX producer index mailboxes
10736 * written twice to workaround a bug.
10738 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10739 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10741 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10742 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10743 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10744 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10746 /* Chip-specific fixup from Broadcom driver */
10747 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10748 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10749 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10750 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10753 /* Default fast path register access methods */
10754 tp->read32 = tg3_read32;
10755 tp->write32 = tg3_write32;
10756 tp->read32_mbox = tg3_read32;
10757 tp->write32_mbox = tg3_write32;
10758 tp->write32_tx_mbox = tg3_write32;
10759 tp->write32_rx_mbox = tg3_write32;
10761 /* Various workaround register access methods */
10762 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10763 tp->write32 = tg3_write_indirect_reg32;
10764 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10765 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10766 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
10768 * Back to back register writes can cause problems on these
10769 * chips, the workaround is to read back all reg writes
10770 * except those to mailbox regs.
10772 * See tg3_write_indirect_reg32().
10774 tp->write32 = tg3_write_flush_reg32;
10778 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10779 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10780 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10781 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10782 tp->write32_rx_mbox = tg3_write_flush_reg32;
10785 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10786 tp->read32 = tg3_read_indirect_reg32;
10787 tp->write32 = tg3_write_indirect_reg32;
10788 tp->read32_mbox = tg3_read_indirect_mbox;
10789 tp->write32_mbox = tg3_write_indirect_mbox;
10790 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10791 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10796 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10797 pci_cmd &= ~PCI_COMMAND_MEMORY;
10798 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10800 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10801 tp->read32_mbox = tg3_read32_mbox_5906;
10802 tp->write32_mbox = tg3_write32_mbox_5906;
10803 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10804 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10807 if (tp->write32 == tg3_write_indirect_reg32 ||
10808 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10809 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10810 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10811 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10813 /* Get eeprom hw config before calling tg3_set_power_state().
10814 * In particular, the TG3_FLG2_IS_NIC flag must be
10815 * determined before calling tg3_set_power_state() so that
10816 * we know whether or not to switch out of Vaux power.
10817 * When the flag is set, it means that GPIO1 is used for eeprom
10818 * write protect and also implies that it is a LOM where GPIOs
10819 * are not used to switch power.
10821 tg3_get_eeprom_hw_cfg(tp);
10823 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10824 * GPIO1 driven high will bring 5700's external PHY out of reset.
10825 * It is also used as eeprom write protect on LOMs.
10827 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10828 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10829 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10830 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10831 GRC_LCLCTRL_GPIO_OUTPUT1);
10832 /* Unused GPIO3 must be driven as output on 5752 because there
10833 * are no pull-up resistors on unused GPIO pins.
10835 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10836 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10838 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10839 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10841 /* Force the chip into D0. */
10842 err = tg3_set_power_state(tp, PCI_D0);
10844 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10845 pci_name(tp->pdev));
10849 /* 5700 B0 chips do not support checksumming correctly due
10850 * to hardware bugs.
10852 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10853 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10855 /* Derive initial jumbo mode from MTU assigned in
10856 * ether_setup() via the alloc_etherdev() call
10858 if (tp->dev->mtu > ETH_DATA_LEN &&
10859 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10860 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10862 /* Determine WakeOnLan speed to use. */
10863 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10864 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10865 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10866 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10867 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10869 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10872 /* A few boards don't want Ethernet@WireSpeed phy feature */
10873 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10874 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10875 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10876 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10877 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10878 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10879 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10881 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10882 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10883 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10884 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10885 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10887 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10888 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10889 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10890 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10891 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10892 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10893 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10894 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10895 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10896 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10899 tp->coalesce_mode = 0;
10900 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10901 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10902 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10904 /* Initialize MAC MI mode, polling disabled. */
10905 tw32_f(MAC_MI_MODE, tp->mi_mode);
10908 /* Initialize data/descriptor byte/word swapping. */
10909 val = tr32(GRC_MODE);
10910 val &= GRC_MODE_HOST_STACKUP;
10911 tw32(GRC_MODE, val | tp->grc_mode);
10913 tg3_switch_clocks(tp);
10915 /* Clear this out for sanity. */
10916 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10918 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10920 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10921 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10922 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10924 if (chiprevid == CHIPREV_ID_5701_A0 ||
10925 chiprevid == CHIPREV_ID_5701_B0 ||
10926 chiprevid == CHIPREV_ID_5701_B2 ||
10927 chiprevid == CHIPREV_ID_5701_B5) {
10928 void __iomem *sram_base;
10930 /* Write some dummy words into the SRAM status block
10931 * area, see if it reads back correctly. If the return
10932 * value is bad, force enable the PCIX workaround.
10934 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10936 writel(0x00000000, sram_base);
10937 writel(0x00000000, sram_base + 4);
10938 writel(0xffffffff, sram_base + 4);
10939 if (readl(sram_base) != 0x00000000)
10940 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10945 tg3_nvram_init(tp);
10947 grc_misc_cfg = tr32(GRC_MISC_CFG);
10948 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10950 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10951 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10952 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10953 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10955 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10956 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10957 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10958 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10959 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10960 HOSTCC_MODE_CLRTICK_TXBD);
10962 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10963 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10964 tp->misc_host_ctrl);
10967 /* these are limited to 10/100 only */
10968 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10969 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10970 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10971 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10972 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10973 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10974 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10975 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10976 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10977 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10978 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10979 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10980 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10982 err = tg3_phy_probe(tp);
10984 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10985 pci_name(tp->pdev), err);
10986 /* ... but do not return immediately ... */
10989 tg3_read_partno(tp);
10990 tg3_read_fw_ver(tp);
10992 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10993 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10995 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10996 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10998 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
11001 /* 5700 {AX,BX} chips have a broken status block link
11002 * change bit implementation, so we must use the
11003 * status register in those cases.
11005 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
11006 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
11008 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
11010 /* The led_ctrl is set during tg3_phy_probe, here we might
11011 * have to force the link status polling mechanism based
11012 * upon subsystem IDs.
11014 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
11015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11016 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
11017 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
11018 TG3_FLAG_USE_LINKCHG_REG);
11021 /* For all SERDES we poll the MAC status register. */
11022 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11023 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
11025 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
11027 /* All chips before 5787 can get confused if TX buffers
11028 * straddle the 4GB address boundary in some cases.
11030 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11032 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11033 tp->dev->hard_start_xmit = tg3_start_xmit;
11035 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
11038 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
11039 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
11042 tp->rx_std_max_post = TG3_RX_RING_SIZE;
11044 /* Increment the rx prod index on the rx std ring by at most
11045 * 8 for these chips to workaround hw errata.
11047 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
11048 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
11049 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11050 tp->rx_std_max_post = 8;
11052 /* By default, disable wake-on-lan. User can change this
11053 * using ETHTOOL_SWOL.
11055 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
11057 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
11058 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
11059 PCIE_PWR_MGMT_L1_THRESH_MSK;
11064 #ifdef CONFIG_SPARC
11065 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
11067 struct net_device *dev = tp->dev;
11068 struct pci_dev *pdev = tp->pdev;
11069 struct device_node *dp = pci_device_to_OF_node(pdev);
11070 const unsigned char *addr;
11073 addr = of_get_property(dp, "local-mac-address", &len);
11074 if (addr && len == 6) {
11075 memcpy(dev->dev_addr, addr, 6);
11076 memcpy(dev->perm_addr, dev->dev_addr, 6);
11082 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11084 struct net_device *dev = tp->dev;
11086 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11087 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11092 static int __devinit tg3_get_device_address(struct tg3 *tp)
11094 struct net_device *dev = tp->dev;
11095 u32 hi, lo, mac_offset;
11098 #ifdef CONFIG_SPARC
11099 if (!tg3_get_macaddr_sparc(tp))
11104 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11105 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11106 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11108 if (tg3_nvram_lock(tp))
11109 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11111 tg3_nvram_unlock(tp);
11113 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11116 /* First try to get it from MAC address mailbox. */
11117 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11118 if ((hi >> 16) == 0x484b) {
11119 dev->dev_addr[0] = (hi >> 8) & 0xff;
11120 dev->dev_addr[1] = (hi >> 0) & 0xff;
11122 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11123 dev->dev_addr[2] = (lo >> 24) & 0xff;
11124 dev->dev_addr[3] = (lo >> 16) & 0xff;
11125 dev->dev_addr[4] = (lo >> 8) & 0xff;
11126 dev->dev_addr[5] = (lo >> 0) & 0xff;
11128 /* Some old bootcode may report a 0 MAC address in SRAM */
11129 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11132 /* Next, try NVRAM. */
11133 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11134 !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11135 dev->dev_addr[0] = ((hi >> 16) & 0xff);
11136 dev->dev_addr[1] = ((hi >> 24) & 0xff);
11137 dev->dev_addr[2] = ((lo >> 0) & 0xff);
11138 dev->dev_addr[3] = ((lo >> 8) & 0xff);
11139 dev->dev_addr[4] = ((lo >> 16) & 0xff);
11140 dev->dev_addr[5] = ((lo >> 24) & 0xff);
11142 /* Finally just fetch it out of the MAC control regs. */
11144 hi = tr32(MAC_ADDR_0_HIGH);
11145 lo = tr32(MAC_ADDR_0_LOW);
11147 dev->dev_addr[5] = lo & 0xff;
11148 dev->dev_addr[4] = (lo >> 8) & 0xff;
11149 dev->dev_addr[3] = (lo >> 16) & 0xff;
11150 dev->dev_addr[2] = (lo >> 24) & 0xff;
11151 dev->dev_addr[1] = hi & 0xff;
11152 dev->dev_addr[0] = (hi >> 8) & 0xff;
11156 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11157 #ifdef CONFIG_SPARC64
11158 if (!tg3_get_default_macaddr_sparc(tp))
11163 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11167 #define BOUNDARY_SINGLE_CACHELINE 1
11168 #define BOUNDARY_MULTI_CACHELINE 2
11170 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11172 int cacheline_size;
11176 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11178 cacheline_size = 1024;
11180 cacheline_size = (int) byte * 4;
11182 /* On 5703 and later chips, the boundary bits have no
11185 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11186 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11187 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11190 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11191 goal = BOUNDARY_MULTI_CACHELINE;
11193 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11194 goal = BOUNDARY_SINGLE_CACHELINE;
11203 /* PCI controllers on most RISC systems tend to disconnect
11204 * when a device tries to burst across a cache-line boundary.
11205 * Therefore, letting tg3 do so just wastes PCI bandwidth.
11207 * Unfortunately, for PCI-E there are only limited
11208 * write-side controls for this, and thus for reads
11209 * we will still get the disconnects. We'll also waste
11210 * these PCI cycles for both read and write for chips
11211 * other than 5700 and 5701 which do not implement the
11214 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11215 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11216 switch (cacheline_size) {
11221 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11222 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11223 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11225 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11226 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11231 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11232 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11236 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11237 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11240 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11241 switch (cacheline_size) {
11245 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11246 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11247 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11253 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11254 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11258 switch (cacheline_size) {
11260 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11261 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11262 DMA_RWCTRL_WRITE_BNDRY_16);
11267 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11268 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11269 DMA_RWCTRL_WRITE_BNDRY_32);
11274 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11275 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11276 DMA_RWCTRL_WRITE_BNDRY_64);
11281 if (goal == BOUNDARY_SINGLE_CACHELINE) {
11282 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11283 DMA_RWCTRL_WRITE_BNDRY_128);
11288 val |= (DMA_RWCTRL_READ_BNDRY_256 |
11289 DMA_RWCTRL_WRITE_BNDRY_256);
11292 val |= (DMA_RWCTRL_READ_BNDRY_512 |
11293 DMA_RWCTRL_WRITE_BNDRY_512);
11297 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11298 DMA_RWCTRL_WRITE_BNDRY_1024);
11307 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11309 struct tg3_internal_buffer_desc test_desc;
11310 u32 sram_dma_descs;
11313 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11315 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11316 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11317 tw32(RDMAC_STATUS, 0);
11318 tw32(WDMAC_STATUS, 0);
11320 tw32(BUFMGR_MODE, 0);
11321 tw32(FTQ_RESET, 0);
11323 test_desc.addr_hi = ((u64) buf_dma) >> 32;
11324 test_desc.addr_lo = buf_dma & 0xffffffff;
11325 test_desc.nic_mbuf = 0x00002100;
11326 test_desc.len = size;
11329 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11330 * the *second* time the tg3 driver was getting loaded after an
11333 * Broadcom tells me:
11334 * ...the DMA engine is connected to the GRC block and a DMA
11335 * reset may affect the GRC block in some unpredictable way...
11336 * The behavior of resets to individual blocks has not been tested.
11338 * Broadcom noted the GRC reset will also reset all sub-components.
11341 test_desc.cqid_sqid = (13 << 8) | 2;
11343 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11346 test_desc.cqid_sqid = (16 << 8) | 7;
11348 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11351 test_desc.flags = 0x00000005;
11353 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11356 val = *(((u32 *)&test_desc) + i);
11357 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11358 sram_dma_descs + (i * sizeof(u32)));
11359 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11361 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11364 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11366 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11370 for (i = 0; i < 40; i++) {
11374 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11376 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11377 if ((val & 0xffff) == sram_dma_descs) {
11388 #define TEST_BUFFER_SIZE 0x2000
11390 static int __devinit tg3_test_dma(struct tg3 *tp)
11392 dma_addr_t buf_dma;
11393 u32 *buf, saved_dma_rwctrl;
11396 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11402 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11403 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11405 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11407 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11408 /* DMA read watermark not used on PCIE */
11409 tp->dma_rwctrl |= 0x00180000;
11410 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11412 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11413 tp->dma_rwctrl |= 0x003f0000;
11415 tp->dma_rwctrl |= 0x003f000f;
11417 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11418 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11419 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11420 u32 read_water = 0x7;
11422 /* If the 5704 is behind the EPB bridge, we can
11423 * do the less restrictive ONE_DMA workaround for
11424 * better performance.
11426 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11427 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11428 tp->dma_rwctrl |= 0x8000;
11429 else if (ccval == 0x6 || ccval == 0x7)
11430 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11432 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11434 /* Set bit 23 to enable PCIX hw bug fix */
11436 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11437 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11439 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11440 /* 5780 always in PCIX mode */
11441 tp->dma_rwctrl |= 0x00144000;
11442 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11443 /* 5714 always in PCIX mode */
11444 tp->dma_rwctrl |= 0x00148000;
11446 tp->dma_rwctrl |= 0x001b000f;
11450 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11451 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11452 tp->dma_rwctrl &= 0xfffffff0;
11454 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11456 /* Remove this if it causes problems for some boards. */
11457 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11459 /* On 5700/5701 chips, we need to set this bit.
11460 * Otherwise the chip will issue cacheline transactions
11461 * to streamable DMA memory with not all the byte
11462 * enables turned on. This is an error on several
11463 * RISC PCI controllers, in particular sparc64.
11465 * On 5703/5704 chips, this bit has been reassigned
11466 * a different meaning. In particular, it is used
11467 * on those chips to enable a PCI-X workaround.
11469 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11472 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11475 /* Unneeded, already done by tg3_get_invariants. */
11476 tg3_switch_clocks(tp);
11480 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11481 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11484 /* It is best to perform DMA test with maximum write burst size
11485 * to expose the 5700/5701 write DMA bug.
11487 saved_dma_rwctrl = tp->dma_rwctrl;
11488 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11489 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11494 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11497 /* Send the buffer to the chip. */
11498 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11500 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11505 /* validate data reached card RAM correctly. */
11506 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11508 tg3_read_mem(tp, 0x2100 + (i*4), &val);
11509 if (le32_to_cpu(val) != p[i]) {
11510 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
11511 /* ret = -ENODEV here? */
11516 /* Now read it back. */
11517 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11519 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11525 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11529 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11530 DMA_RWCTRL_WRITE_BNDRY_16) {
11531 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11532 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11533 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11536 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11542 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11548 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11549 DMA_RWCTRL_WRITE_BNDRY_16) {
11550 static struct pci_device_id dma_wait_state_chipsets[] = {
11551 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11552 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11556 /* DMA test passed without adjusting DMA boundary,
11557 * now look for chipsets that are known to expose the
11558 * DMA bug without failing the test.
11560 if (pci_dev_present(dma_wait_state_chipsets)) {
11561 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11562 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11565 /* Safe to use the calculated DMA boundary. */
11566 tp->dma_rwctrl = saved_dma_rwctrl;
11568 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11572 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11577 static void __devinit tg3_init_link_config(struct tg3 *tp)
11579 tp->link_config.advertising =
11580 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11581 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11582 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11583 ADVERTISED_Autoneg | ADVERTISED_MII);
11584 tp->link_config.speed = SPEED_INVALID;
11585 tp->link_config.duplex = DUPLEX_INVALID;
11586 tp->link_config.autoneg = AUTONEG_ENABLE;
11587 tp->link_config.active_speed = SPEED_INVALID;
11588 tp->link_config.active_duplex = DUPLEX_INVALID;
11589 tp->link_config.phy_is_low_power = 0;
11590 tp->link_config.orig_speed = SPEED_INVALID;
11591 tp->link_config.orig_duplex = DUPLEX_INVALID;
11592 tp->link_config.orig_autoneg = AUTONEG_INVALID;
11595 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11597 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11598 tp->bufmgr_config.mbuf_read_dma_low_water =
11599 DEFAULT_MB_RDMA_LOW_WATER_5705;
11600 tp->bufmgr_config.mbuf_mac_rx_low_water =
11601 DEFAULT_MB_MACRX_LOW_WATER_5705;
11602 tp->bufmgr_config.mbuf_high_water =
11603 DEFAULT_MB_HIGH_WATER_5705;
11604 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11605 tp->bufmgr_config.mbuf_mac_rx_low_water =
11606 DEFAULT_MB_MACRX_LOW_WATER_5906;
11607 tp->bufmgr_config.mbuf_high_water =
11608 DEFAULT_MB_HIGH_WATER_5906;
11611 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11612 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11613 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11614 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11615 tp->bufmgr_config.mbuf_high_water_jumbo =
11616 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11618 tp->bufmgr_config.mbuf_read_dma_low_water =
11619 DEFAULT_MB_RDMA_LOW_WATER;
11620 tp->bufmgr_config.mbuf_mac_rx_low_water =
11621 DEFAULT_MB_MACRX_LOW_WATER;
11622 tp->bufmgr_config.mbuf_high_water =
11623 DEFAULT_MB_HIGH_WATER;
11625 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11626 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11627 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11628 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11629 tp->bufmgr_config.mbuf_high_water_jumbo =
11630 DEFAULT_MB_HIGH_WATER_JUMBO;
11633 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11634 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11637 static char * __devinit tg3_phy_string(struct tg3 *tp)
11639 switch (tp->phy_id & PHY_ID_MASK) {
11640 case PHY_ID_BCM5400: return "5400";
11641 case PHY_ID_BCM5401: return "5401";
11642 case PHY_ID_BCM5411: return "5411";
11643 case PHY_ID_BCM5701: return "5701";
11644 case PHY_ID_BCM5703: return "5703";
11645 case PHY_ID_BCM5704: return "5704";
11646 case PHY_ID_BCM5705: return "5705";
11647 case PHY_ID_BCM5750: return "5750";
11648 case PHY_ID_BCM5752: return "5752";
11649 case PHY_ID_BCM5714: return "5714";
11650 case PHY_ID_BCM5780: return "5780";
11651 case PHY_ID_BCM5755: return "5755";
11652 case PHY_ID_BCM5787: return "5787";
11653 case PHY_ID_BCM5756: return "5722/5756";
11654 case PHY_ID_BCM5906: return "5906";
11655 case PHY_ID_BCM8002: return "8002/serdes";
11656 case 0: return "serdes";
11657 default: return "unknown";
11661 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11663 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11664 strcpy(str, "PCI Express");
11666 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11667 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11669 strcpy(str, "PCIX:");
11671 if ((clock_ctrl == 7) ||
11672 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11673 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11674 strcat(str, "133MHz");
11675 else if (clock_ctrl == 0)
11676 strcat(str, "33MHz");
11677 else if (clock_ctrl == 2)
11678 strcat(str, "50MHz");
11679 else if (clock_ctrl == 4)
11680 strcat(str, "66MHz");
11681 else if (clock_ctrl == 6)
11682 strcat(str, "100MHz");
11684 strcpy(str, "PCI:");
11685 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11686 strcat(str, "66MHz");
11688 strcat(str, "33MHz");
11690 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11691 strcat(str, ":32-bit");
11693 strcat(str, ":64-bit");
11697 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11699 struct pci_dev *peer;
11700 unsigned int func, devnr = tp->pdev->devfn & ~7;
11702 for (func = 0; func < 8; func++) {
11703 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11704 if (peer && peer != tp->pdev)
11708 /* 5704 can be configured in single-port mode, set peer to
11709 * tp->pdev in that case.
11717 * We don't need to keep the refcount elevated; there's no way
11718 * to remove one half of this device without removing the other
11725 static void __devinit tg3_init_coal(struct tg3 *tp)
11727 struct ethtool_coalesce *ec = &tp->coal;
11729 memset(ec, 0, sizeof(*ec));
11730 ec->cmd = ETHTOOL_GCOALESCE;
11731 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11732 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11733 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11734 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11735 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11736 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11737 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11738 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11739 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11741 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11742 HOSTCC_MODE_CLRTICK_TXBD)) {
11743 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11744 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11745 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11746 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11749 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11750 ec->rx_coalesce_usecs_irq = 0;
11751 ec->tx_coalesce_usecs_irq = 0;
11752 ec->stats_block_coalesce_usecs = 0;
11756 static int __devinit tg3_init_one(struct pci_dev *pdev,
11757 const struct pci_device_id *ent)
11759 static int tg3_version_printed = 0;
11760 unsigned long tg3reg_base, tg3reg_len;
11761 struct net_device *dev;
11763 int i, err, pm_cap;
11765 u64 dma_mask, persist_dma_mask;
11767 if (tg3_version_printed++ == 0)
11768 printk(KERN_INFO "%s", version);
11770 err = pci_enable_device(pdev);
11772 printk(KERN_ERR PFX "Cannot enable PCI device, "
11777 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11778 printk(KERN_ERR PFX "Cannot find proper PCI device "
11779 "base address, aborting.\n");
11781 goto err_out_disable_pdev;
11784 err = pci_request_regions(pdev, DRV_MODULE_NAME);
11786 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11788 goto err_out_disable_pdev;
11791 pci_set_master(pdev);
11793 /* Find power-management capability. */
11794 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11796 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11799 goto err_out_free_res;
11802 tg3reg_base = pci_resource_start(pdev, 0);
11803 tg3reg_len = pci_resource_len(pdev, 0);
11805 dev = alloc_etherdev(sizeof(*tp));
11807 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11809 goto err_out_free_res;
11812 SET_MODULE_OWNER(dev);
11813 SET_NETDEV_DEV(dev, &pdev->dev);
11815 #if TG3_VLAN_TAG_USED
11816 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11817 dev->vlan_rx_register = tg3_vlan_rx_register;
11820 tp = netdev_priv(dev);
11823 tp->pm_cap = pm_cap;
11824 tp->mac_mode = TG3_DEF_MAC_MODE;
11825 tp->rx_mode = TG3_DEF_RX_MODE;
11826 tp->tx_mode = TG3_DEF_TX_MODE;
11827 tp->mi_mode = MAC_MI_MODE_BASE;
11829 tp->msg_enable = tg3_debug;
11831 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11833 /* The word/byte swap controls here control register access byte
11834 * swapping. DMA data byte swapping is controlled in the GRC_MODE
11837 tp->misc_host_ctrl =
11838 MISC_HOST_CTRL_MASK_PCI_INT |
11839 MISC_HOST_CTRL_WORD_SWAP |
11840 MISC_HOST_CTRL_INDIR_ACCESS |
11841 MISC_HOST_CTRL_PCISTATE_RW;
11843 /* The NONFRM (non-frame) byte/word swap controls take effect
11844 * on descriptor entries, anything which isn't packet data.
11846 * The StrongARM chips on the board (one for tx, one for rx)
11847 * are running in big-endian mode.
11849 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11850 GRC_MODE_WSWAP_NONFRM_DATA);
11851 #ifdef __BIG_ENDIAN
11852 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11854 spin_lock_init(&tp->lock);
11855 spin_lock_init(&tp->indirect_lock);
11856 INIT_WORK(&tp->reset_task, tg3_reset_task);
11858 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11859 if (tp->regs == 0UL) {
11860 printk(KERN_ERR PFX "Cannot map device registers, "
11863 goto err_out_free_dev;
11866 tg3_init_link_config(tp);
11868 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11869 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11870 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11872 dev->open = tg3_open;
11873 dev->stop = tg3_close;
11874 dev->get_stats = tg3_get_stats;
11875 dev->set_multicast_list = tg3_set_rx_mode;
11876 dev->set_mac_address = tg3_set_mac_addr;
11877 dev->do_ioctl = tg3_ioctl;
11878 dev->tx_timeout = tg3_tx_timeout;
11879 dev->poll = tg3_poll;
11880 dev->ethtool_ops = &tg3_ethtool_ops;
11882 dev->watchdog_timeo = TG3_TX_TIMEOUT;
11883 dev->change_mtu = tg3_change_mtu;
11884 dev->irq = pdev->irq;
11885 #ifdef CONFIG_NET_POLL_CONTROLLER
11886 dev->poll_controller = tg3_poll_controller;
11889 err = tg3_get_invariants(tp);
11891 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11893 goto err_out_iounmap;
11896 /* The EPB bridge inside 5714, 5715, and 5780 and any
11897 * device behind the EPB cannot support DMA addresses > 40-bit.
11898 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11899 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11900 * do DMA address check in tg3_start_xmit().
11902 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11903 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11904 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11905 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11906 #ifdef CONFIG_HIGHMEM
11907 dma_mask = DMA_64BIT_MASK;
11910 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11912 /* Configure DMA attributes. */
11913 if (dma_mask > DMA_32BIT_MASK) {
11914 err = pci_set_dma_mask(pdev, dma_mask);
11916 dev->features |= NETIF_F_HIGHDMA;
11917 err = pci_set_consistent_dma_mask(pdev,
11920 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11921 "DMA for consistent allocations\n");
11922 goto err_out_iounmap;
11926 if (err || dma_mask == DMA_32BIT_MASK) {
11927 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11929 printk(KERN_ERR PFX "No usable DMA configuration, "
11931 goto err_out_iounmap;
11935 tg3_init_bufmgr_config(tp);
11937 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11938 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11940 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11941 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11942 tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11943 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11944 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11945 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11947 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11950 /* TSO is on by default on chips that support hardware TSO.
11951 * Firmware TSO on older chips gives lower performance, so it
11952 * is off by default, but can be enabled using ethtool.
11954 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11955 dev->features |= NETIF_F_TSO;
11956 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11957 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11958 dev->features |= NETIF_F_TSO6;
11962 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11963 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11964 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11965 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11966 tp->rx_pending = 63;
11969 err = tg3_get_device_address(tp);
11971 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11973 goto err_out_iounmap;
11977 * Reset chip in case UNDI or EFI driver did not shutdown
11978 * DMA self test will enable WDMAC and we'll see (spurious)
11979 * pending DMA on the PCI bus at that point.
11981 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11982 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11983 pci_save_state(tp->pdev);
11984 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11985 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11988 err = tg3_test_dma(tp);
11990 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11991 goto err_out_iounmap;
11994 /* Tigon3 can do ipv4 only... and some chips have buggy
11997 if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11998 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
11999 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
12000 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
12001 dev->features |= NETIF_F_IPV6_CSUM;
12003 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
12005 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
12007 /* flow control autonegotiation is default behavior */
12008 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
12012 /* Now that we have fully setup the chip, save away a snapshot
12013 * of the PCI config space. We need to restore this after
12014 * GRC_MISC_CFG core clock resets and some resume events.
12016 pci_save_state(tp->pdev);
12018 pci_set_drvdata(pdev, dev);
12020 err = register_netdev(dev);
12022 printk(KERN_ERR PFX "Cannot register net device, "
12024 goto err_out_iounmap;
12027 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
12029 tp->board_part_number,
12030 tp->pci_chip_rev_id,
12031 tg3_phy_string(tp),
12032 tg3_bus_string(tp, str),
12033 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
12034 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
12035 "10/100/1000Base-T")));
12037 for (i = 0; i < 6; i++)
12038 printk("%2.2x%c", dev->dev_addr[i],
12039 i == 5 ? '\n' : ':');
12041 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
12042 "MIirq[%d] ASF[%d] WireSpeed[%d] TSOcap[%d]\n",
12044 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
12045 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
12046 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
12047 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
12048 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
12049 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
12050 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
12051 dev->name, tp->dma_rwctrl,
12052 (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
12053 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
12067 pci_release_regions(pdev);
12069 err_out_disable_pdev:
12070 pci_disable_device(pdev);
12071 pci_set_drvdata(pdev, NULL);
12075 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12077 struct net_device *dev = pci_get_drvdata(pdev);
12080 struct tg3 *tp = netdev_priv(dev);
12082 flush_scheduled_work();
12083 unregister_netdev(dev);
12089 pci_release_regions(pdev);
12090 pci_disable_device(pdev);
12091 pci_set_drvdata(pdev, NULL);
12095 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12097 struct net_device *dev = pci_get_drvdata(pdev);
12098 struct tg3 *tp = netdev_priv(dev);
12101 if (!netif_running(dev))
12104 flush_scheduled_work();
12105 tg3_netif_stop(tp);
12107 del_timer_sync(&tp->timer);
12109 tg3_full_lock(tp, 1);
12110 tg3_disable_ints(tp);
12111 tg3_full_unlock(tp);
12113 netif_device_detach(dev);
12115 tg3_full_lock(tp, 0);
12116 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12117 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12118 tg3_full_unlock(tp);
12120 /* Save MSI address and data for resume. */
12121 pci_save_state(pdev);
12123 err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12125 tg3_full_lock(tp, 0);
12127 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12128 if (tg3_restart_hw(tp, 1))
12131 tp->timer.expires = jiffies + tp->timer_offset;
12132 add_timer(&tp->timer);
12134 netif_device_attach(dev);
12135 tg3_netif_start(tp);
12138 tg3_full_unlock(tp);
12144 static int tg3_resume(struct pci_dev *pdev)
12146 struct net_device *dev = pci_get_drvdata(pdev);
12147 struct tg3 *tp = netdev_priv(dev);
12150 if (!netif_running(dev))
12153 pci_restore_state(tp->pdev);
12155 err = tg3_set_power_state(tp, PCI_D0);
12159 netif_device_attach(dev);
12161 tg3_full_lock(tp, 0);
12163 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12164 err = tg3_restart_hw(tp, 1);
12168 tp->timer.expires = jiffies + tp->timer_offset;
12169 add_timer(&tp->timer);
12171 tg3_netif_start(tp);
12174 tg3_full_unlock(tp);
12179 static struct pci_driver tg3_driver = {
12180 .name = DRV_MODULE_NAME,
12181 .id_table = tg3_pci_tbl,
12182 .probe = tg3_init_one,
12183 .remove = __devexit_p(tg3_remove_one),
12184 .suspend = tg3_suspend,
12185 .resume = tg3_resume
12188 static int __init tg3_init(void)
12190 return pci_register_driver(&tg3_driver);
12193 static void __exit tg3_cleanup(void)
12195 pci_unregister_driver(&tg3_driver);
12198 module_init(tg3_init);
12199 module_exit(tg3_cleanup);