err.no Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18 #include <linux/config.h>
  19
  20 #include <linux/module.h>
  21 #include <linux/moduleparam.h>
  22 #include <linux/kernel.h>
  23 #include <linux/types.h>
  24 #include <linux/compiler.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #ifdef NETIF_F_TSO
  62 #define TG3_TSO_SUPPORT 1
  63 #else
  64 #define TG3_TSO_SUPPORT 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.45"
  72 #define DRV_MODULE_RELDATE      "Dec 13, 2005"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define TX_BUFFS_AVAIL(TP)                                              \
 127         ((TP)->tx_pending -                                             \
 128          (((TP)->tx_prod - (TP)->tx_cons) & (TG3_TX_RING_SIZE - 1)))
 129 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 130
 131 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 132 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 133
 134 /* minimum number of free TX descriptors required to wake up TX process */
 135 #define TG3_TX_WAKEUP_THRESH            (TG3_TX_RING_SIZE / 4)
 136
 137 /* number of ETHTOOL_GSTATS u64's */
 138 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 139
 140 #define TG3_NUM_TEST            6
 141
 142 static char version[] __devinitdata =
 143         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 144
 145 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 146 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 147 MODULE_LICENSE("GPL");
 148 MODULE_VERSION(DRV_MODULE_VERSION);
 149
 150 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 151 module_param(tg3_debug, int, 0);
 152 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 153
 154 static struct pci_device_id tg3_pci_tbl[] = {
 155         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700,
 156           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 157         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701,
 158           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 159         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702,
 160           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 161         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703,
 162           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 163         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704,
 164           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 165         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE,
 166           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 167         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705,
 168           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 169         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2,
 170           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 171         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M,
 172           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 173         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2,
 174           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 175         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X,
 176           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 177         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X,
 178           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 179         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S,
 180           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 181         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3,
 182           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 183         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3,
 184           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 185         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782,
 186           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 187         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788,
 188           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 189         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789,
 190           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 191         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901,
 192           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 193         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2,
 194           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 195         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2,
 196           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 197         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F,
 198           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 199         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720,
 200           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 201         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721,
 202           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 203         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750,
 204           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 205         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751,
 206           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 207         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M,
 208           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 209         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M,
 210           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 211         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
 212           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 213         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
 214           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 215         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M,
 216           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 217         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
 218           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 219         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
 220           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 221         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
 222           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 223         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714,
 224           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 225         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715,
 226           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 227         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
 228           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 229         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
 230           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 231         { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
 232           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 233         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
 234           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 235         { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX,
 236           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 237         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000,
 238           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 239         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001,
 240           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 241         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003,
 242           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 243         { PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100,
 244           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 245         { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3,
 246           PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
 247         { 0, }
 248 };
 249
 250 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 251
 252 static struct {
 253         const char string[ETH_GSTRING_LEN];
 254 } ethtool_stats_keys[TG3_NUM_STATS] = {
 255         { "rx_octets" },
 256         { "rx_fragments" },
 257         { "rx_ucast_packets" },
 258         { "rx_mcast_packets" },
 259         { "rx_bcast_packets" },
 260         { "rx_fcs_errors" },
 261         { "rx_align_errors" },
 262         { "rx_xon_pause_rcvd" },
 263         { "rx_xoff_pause_rcvd" },
 264         { "rx_mac_ctrl_rcvd" },
 265         { "rx_xoff_entered" },
 266         { "rx_frame_too_long_errors" },
 267         { "rx_jabbers" },
 268         { "rx_undersize_packets" },
 269         { "rx_in_length_errors" },
 270         { "rx_out_length_errors" },
 271         { "rx_64_or_less_octet_packets" },
 272         { "rx_65_to_127_octet_packets" },
 273         { "rx_128_to_255_octet_packets" },
 274         { "rx_256_to_511_octet_packets" },
 275         { "rx_512_to_1023_octet_packets" },
 276         { "rx_1024_to_1522_octet_packets" },
 277         { "rx_1523_to_2047_octet_packets" },
 278         { "rx_2048_to_4095_octet_packets" },
 279         { "rx_4096_to_8191_octet_packets" },
 280         { "rx_8192_to_9022_octet_packets" },
 281
 282         { "tx_octets" },
 283         { "tx_collisions" },
 284
 285         { "tx_xon_sent" },
 286         { "tx_xoff_sent" },
 287         { "tx_flow_control" },
 288         { "tx_mac_errors" },
 289         { "tx_single_collisions" },
 290         { "tx_mult_collisions" },
 291         { "tx_deferred" },
 292         { "tx_excessive_collisions" },
 293         { "tx_late_collisions" },
 294         { "tx_collide_2times" },
 295         { "tx_collide_3times" },
 296         { "tx_collide_4times" },
 297         { "tx_collide_5times" },
 298         { "tx_collide_6times" },
 299         { "tx_collide_7times" },
 300         { "tx_collide_8times" },
 301         { "tx_collide_9times" },
 302         { "tx_collide_10times" },
 303         { "tx_collide_11times" },
 304         { "tx_collide_12times" },
 305         { "tx_collide_13times" },
 306         { "tx_collide_14times" },
 307         { "tx_collide_15times" },
 308         { "tx_ucast_packets" },
 309         { "tx_mcast_packets" },
 310         { "tx_bcast_packets" },
 311         { "tx_carrier_sense_errors" },
 312         { "tx_discards" },
 313         { "tx_errors" },
 314
 315         { "dma_writeq_full" },
 316         { "dma_write_prioq_full" },
 317         { "rxbds_empty" },
 318         { "rx_discards" },
 319         { "rx_errors" },
 320         { "rx_threshold_hit" },
 321
 322         { "dma_readq_full" },
 323         { "dma_read_prioq_full" },
 324         { "tx_comp_queue_full" },
 325
 326         { "ring_set_send_prod_index" },
 327         { "ring_status_update" },
 328         { "nic_irqs" },
 329         { "nic_avoided_irqs" },
 330         { "nic_tx_threshold_hit" }
 331 };
 332
 333 static struct {
 334         const char string[ETH_GSTRING_LEN];
 335 } ethtool_test_keys[TG3_NUM_TEST] = {
 336         { "nvram test     (online) " },
 337         { "link test      (online) " },
 338         { "register test  (offline)" },
 339         { "memory test    (offline)" },
 340         { "loopback test  (offline)" },
 341         { "interrupt test (offline)" },
 342 };
 343
 344 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 345 {
 346         unsigned long flags;
 347
 348         spin_lock_irqsave(&tp->indirect_lock, flags);
 349         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 350         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 351         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 352 }
 353
 354 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 355 {
 356         writel(val, tp->regs + off);
 357         readl(tp->regs + off);
 358 }
 359
 360 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 361 {
 362         unsigned long flags;
 363         u32 val;
 364
 365         spin_lock_irqsave(&tp->indirect_lock, flags);
 366         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 367         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 368         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 369         return val;
 370 }
 371
 372 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 373 {
 374         unsigned long flags;
 375
 376         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 377                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 378                                        TG3_64BIT_REG_LOW, val);
 379                 return;
 380         }
 381         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 382                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 383                                        TG3_64BIT_REG_LOW, val);
 384                 return;
 385         }
 386
 387         spin_lock_irqsave(&tp->indirect_lock, flags);
 388         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 389         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 390         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 391
 392         /* In indirect mode when disabling interrupts, we also need
 393          * to clear the interrupt bit in the GRC local ctrl register.
 394          */
 395         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 396             (val == 0x1)) {
 397                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 398                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 399         }
 400 }
 401
 402 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 403 {
 404         unsigned long flags;
 405         u32 val;
 406
 407         spin_lock_irqsave(&tp->indirect_lock, flags);
 408         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 409         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 410         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 411         return val;
 412 }
 413
 414 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val)
 415 {
 416         tp->write32(tp, off, val);
 417         if (!(tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) &&
 418             !(tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG) &&
 419             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 420                 tp->read32(tp, off);    /* flush */
 421 }
 422
 423 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 424 {
 425         tp->write32_mbox(tp, off, val);
 426         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 427             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 428                 tp->read32_mbox(tp, off);
 429 }
 430
 431 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 432 {
 433         void __iomem *mbox = tp->regs + off;
 434         writel(val, mbox);
 435         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 436                 writel(val, mbox);
 437         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 438                 readl(mbox);
 439 }
 440
 441 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 442 {
 443         writel(val, tp->regs + off);
 444 }
 445
 446 static u32 tg3_read32(struct tg3 *tp, u32 off)
 447 {
 448         return (readl(tp->regs + off));
 449 }
 450
 451 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 452 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 453 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 454 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 455 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 456
 457 #define tw32(reg,val)           tp->write32(tp, reg, val)
 458 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val))
 459 #define tr32(reg)               tp->read32(tp, reg)
 460
 461 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 462 {
 463         unsigned long flags;
 464
 465         spin_lock_irqsave(&tp->indirect_lock, flags);
 466         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 467         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 468
 469         /* Always leave this as zero. */
 470         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 472 }
 473
 474 static void tg3_write_mem_fast(struct tg3 *tp, u32 off, u32 val)
 475 {
 476         /* If no workaround is needed, write to mem space directly */
 477         if (tp->write32 != tg3_write_indirect_reg32)
 478                 tw32(NIC_SRAM_WIN_BASE + off, val);
 479         else
 480                 tg3_write_mem(tp, off, val);
 481 }
 482
 483 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 484 {
 485         unsigned long flags;
 486
 487         spin_lock_irqsave(&tp->indirect_lock, flags);
 488         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 489         pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 490
 491         /* Always leave this as zero. */
 492         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 493         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 494 }
 495
 496 static void tg3_disable_ints(struct tg3 *tp)
 497 {
 498         tw32(TG3PCI_MISC_HOST_CTRL,
 499              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 500         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 501 }
 502
 503 static inline void tg3_cond_int(struct tg3 *tp)
 504 {
 505         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 506             (tp->hw_status->status & SD_STATUS_UPDATED))
 507                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 508 }
 509
 510 static void tg3_enable_ints(struct tg3 *tp)
 511 {
 512         tp->irq_sync = 0;
 513         wmb();
 514
 515         tw32(TG3PCI_MISC_HOST_CTRL,
 516              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 517         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 518                        (tp->last_tag << 24));
 519         tg3_cond_int(tp);
 520 }
 521
 522 static inline unsigned int tg3_has_work(struct tg3 *tp)
 523 {
 524         struct tg3_hw_status *sblk = tp->hw_status;
 525         unsigned int work_exists = 0;
 526
 527         /* check for phy events */
 528         if (!(tp->tg3_flags &
 529               (TG3_FLAG_USE_LINKCHG_REG |
 530                TG3_FLAG_POLL_SERDES))) {
 531                 if (sblk->status & SD_STATUS_LINK_CHG)
 532                         work_exists = 1;
 533         }
 534         /* check for RX/TX work to do */
 535         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 536             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 537                 work_exists = 1;
 538
 539         return work_exists;
 540 }
 541
 542 /* tg3_restart_ints
 543  *  similar to tg3_enable_ints, but it accurately determines whether there
 544  *  is new work pending and can return without flushing the PIO write
 545  *  which reenables interrupts
 546  */
 547 static void tg3_restart_ints(struct tg3 *tp)
 548 {
 549         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 550                      tp->last_tag << 24);
 551         mmiowb();
 552
 553         /* When doing tagged status, this work check is unnecessary.
 554          * The last_tag we write above tells the chip which piece of
 555          * work we've completed.
 556          */
 557         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 558             tg3_has_work(tp))
 559                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 560                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 561 }
 562
 563 static inline void tg3_netif_stop(struct tg3 *tp)
 564 {
 565         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 566         netif_poll_disable(tp->dev);
 567         netif_tx_disable(tp->dev);
 568 }
 569
 570 static inline void tg3_netif_start(struct tg3 *tp)
 571 {
 572         netif_wake_queue(tp->dev);
 573         /* NOTE: unconditional netif_wake_queue is only appropriate
 574          * so long as all callers are assured to have free tx slots
 575          * (such as after tg3_init_hw)
 576          */
 577         netif_poll_enable(tp->dev);
 578         tp->hw_status->status |= SD_STATUS_UPDATED;
 579         tg3_enable_ints(tp);
 580 }
 581
 582 static void tg3_switch_clocks(struct tg3 *tp)
 583 {
 584         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 585         u32 orig_clock_ctrl;
 586
 587         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 588                 return;
 589
 590         orig_clock_ctrl = clock_ctrl;
 591         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 592                        CLOCK_CTRL_CLKRUN_OENABLE |
 593                        0x1f);
 594         tp->pci_clock_ctrl = clock_ctrl;
 595
 596         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 597                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 598                         tw32_f(TG3PCI_CLOCK_CTRL,
 599                                clock_ctrl | CLOCK_CTRL_625_CORE);
 600                         udelay(40);
 601                 }
 602         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 603                 tw32_f(TG3PCI_CLOCK_CTRL,
 604                      clock_ctrl |
 605                      (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
 606                 udelay(40);
 607                 tw32_f(TG3PCI_CLOCK_CTRL,
 608                      clock_ctrl | (CLOCK_CTRL_ALTCLK));
 609                 udelay(40);
 610         }
 611         tw32_f(TG3PCI_CLOCK_CTRL, clock_ctrl);
 612         udelay(40);
 613 }
 614
 615 #define PHY_BUSY_LOOPS  5000
 616
 617 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 618 {
 619         u32 frame_val;
 620         unsigned int loops;
 621         int ret;
 622
 623         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 624                 tw32_f(MAC_MI_MODE,
 625                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 626                 udelay(80);
 627         }
 628
 629         *val = 0x0;
 630
 631         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 632                       MI_COM_PHY_ADDR_MASK);
 633         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 634                       MI_COM_REG_ADDR_MASK);
 635         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 636
 637         tw32_f(MAC_MI_COM, frame_val);
 638
 639         loops = PHY_BUSY_LOOPS;
 640         while (loops != 0) {
 641                 udelay(10);
 642                 frame_val = tr32(MAC_MI_COM);
 643
 644                 if ((frame_val & MI_COM_BUSY) == 0) {
 645                         udelay(5);
 646                         frame_val = tr32(MAC_MI_COM);
 647                         break;
 648                 }
 649                 loops -= 1;
 650         }
 651
 652         ret = -EBUSY;
 653         if (loops != 0) {
 654                 *val = frame_val & MI_COM_DATA_MASK;
 655                 ret = 0;
 656         }
 657
 658         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 659                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 660                 udelay(80);
 661         }
 662
 663         return ret;
 664 }
 665
 666 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 667 {
 668         u32 frame_val;
 669         unsigned int loops;
 670         int ret;
 671
 672         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 673                 tw32_f(MAC_MI_MODE,
 674                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 675                 udelay(80);
 676         }
 677
 678         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 679                       MI_COM_PHY_ADDR_MASK);
 680         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 681                       MI_COM_REG_ADDR_MASK);
 682         frame_val |= (val & MI_COM_DATA_MASK);
 683         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 684
 685         tw32_f(MAC_MI_COM, frame_val);
 686
 687         loops = PHY_BUSY_LOOPS;
 688         while (loops != 0) {
 689                 udelay(10);
 690                 frame_val = tr32(MAC_MI_COM);
 691                 if ((frame_val & MI_COM_BUSY) == 0) {
 692                         udelay(5);
 693                         frame_val = tr32(MAC_MI_COM);
 694                         break;
 695                 }
 696                 loops -= 1;
 697         }
 698
 699         ret = -EBUSY;
 700         if (loops != 0)
 701                 ret = 0;
 702
 703         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 704                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 705                 udelay(80);
 706         }
 707
 708         return ret;
 709 }
 710
 711 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 712 {
 713         u32 val;
 714
 715         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 716                 return;
 717
 718         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 719             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 720                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 721                              (val | (1 << 15) | (1 << 4)));
 722 }
 723
 724 static int tg3_bmcr_reset(struct tg3 *tp)
 725 {
 726         u32 phy_control;
 727         int limit, err;
 728
 729         /* OK, reset it, and poll the BMCR_RESET bit until it
 730          * clears or we time out.
 731          */
 732         phy_control = BMCR_RESET;
 733         err = tg3_writephy(tp, MII_BMCR, phy_control);
 734         if (err != 0)
 735                 return -EBUSY;
 736
 737         limit = 5000;
 738         while (limit--) {
 739                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 740                 if (err != 0)
 741                         return -EBUSY;
 742
 743                 if ((phy_control & BMCR_RESET) == 0) {
 744                         udelay(40);
 745                         break;
 746                 }
 747                 udelay(10);
 748         }
 749         if (limit <= 0)
 750                 return -EBUSY;
 751
 752         return 0;
 753 }
 754
 755 static int tg3_wait_macro_done(struct tg3 *tp)
 756 {
 757         int limit = 100;
 758
 759         while (limit--) {
 760                 u32 tmp32;
 761
 762                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 763                         if ((tmp32 & 0x1000) == 0)
 764                                 break;
 765                 }
 766         }
 767         if (limit <= 0)
 768                 return -EBUSY;
 769
 770         return 0;
 771 }
 772
 773 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 774 {
 775         static const u32 test_pat[4][6] = {
 776         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 777         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 778         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 779         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 780         };
 781         int chan;
 782
 783         for (chan = 0; chan < 4; chan++) {
 784                 int i;
 785
 786                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 787                              (chan * 0x2000) | 0x0200);
 788                 tg3_writephy(tp, 0x16, 0x0002);
 789
 790                 for (i = 0; i < 6; i++)
 791                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 792                                      test_pat[chan][i]);
 793
 794                 tg3_writephy(tp, 0x16, 0x0202);
 795                 if (tg3_wait_macro_done(tp)) {
 796                         *resetp = 1;
 797                         return -EBUSY;
 798                 }
 799
 800                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 801                              (chan * 0x2000) | 0x0200);
 802                 tg3_writephy(tp, 0x16, 0x0082);
 803                 if (tg3_wait_macro_done(tp)) {
 804                         *resetp = 1;
 805                         return -EBUSY;
 806                 }
 807
 808                 tg3_writephy(tp, 0x16, 0x0802);
 809                 if (tg3_wait_macro_done(tp)) {
 810                         *resetp = 1;
 811                         return -EBUSY;
 812                 }
 813
 814                 for (i = 0; i < 6; i += 2) {
 815                         u32 low, high;
 816
 817                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 818                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 819                             tg3_wait_macro_done(tp)) {
 820                                 *resetp = 1;
 821                                 return -EBUSY;
 822                         }
 823                         low &= 0x7fff;
 824                         high &= 0x000f;
 825                         if (low != test_pat[chan][i] ||
 826                             high != test_pat[chan][i+1]) {
 827                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 828                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 829                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 830
 831                                 return -EBUSY;
 832                         }
 833                 }
 834         }
 835
 836         return 0;
 837 }
 838
 839 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 840 {
 841         int chan;
 842
 843         for (chan = 0; chan < 4; chan++) {
 844                 int i;
 845
 846                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 847                              (chan * 0x2000) | 0x0200);
 848                 tg3_writephy(tp, 0x16, 0x0002);
 849                 for (i = 0; i < 6; i++)
 850                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 851                 tg3_writephy(tp, 0x16, 0x0202);
 852                 if (tg3_wait_macro_done(tp))
 853                         return -EBUSY;
 854         }
 855
 856         return 0;
 857 }
 858
 859 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 860 {
 861         u32 reg32, phy9_orig;
 862         int retries, do_phy_reset, err;
 863
 864         retries = 10;
 865         do_phy_reset = 1;
 866         do {
 867                 if (do_phy_reset) {
 868                         err = tg3_bmcr_reset(tp);
 869                         if (err)
 870                                 return err;
 871                         do_phy_reset = 0;
 872                 }
 873
 874                 /* Disable transmitter and interrupt.  */
 875                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 876                         continue;
 877
 878                 reg32 |= 0x3000;
 879                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 880
 881                 /* Set full-duplex, 1000 mbps.  */
 882                 tg3_writephy(tp, MII_BMCR,
 883                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 884
 885                 /* Set to master mode.  */
 886                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 887                         continue;
 888
 889                 tg3_writephy(tp, MII_TG3_CTRL,
 890                              (MII_TG3_CTRL_AS_MASTER |
 891                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 892
 893                 /* Enable SM_DSP_CLOCK and 6dB.  */
 894                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 895
 896                 /* Block the PHY control access.  */
 897                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 898                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 899
 900                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 901                 if (!err)
 902                         break;
 903         } while (--retries);
 904
 905         err = tg3_phy_reset_chanpat(tp);
 906         if (err)
 907                 return err;
 908
 909         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 910         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 911
 912         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 913         tg3_writephy(tp, 0x16, 0x0000);
 914
 915         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 916             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 917                 /* Set Extended packet length bit for jumbo frames */
 918                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 919         }
 920         else {
 921                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 922         }
 923
 924         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 925
 926         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 927                 reg32 &= ~0x3000;
 928                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 929         } else if (!err)
 930                 err = -EBUSY;
 931
 932         return err;
 933 }
 934
 935 /* This will reset the tigon3 PHY if there is no valid
 936  * link unless the FORCE argument is non-zero.
 937  */
 938 static int tg3_phy_reset(struct tg3 *tp)
 939 {
 940         u32 phy_status;
 941         int err;
 942
 943         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 944         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 945         if (err != 0)
 946                 return -EBUSY;
 947
 948         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 949             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 950             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 951                 err = tg3_phy_reset_5703_4_5(tp);
 952                 if (err)
 953                         return err;
 954                 goto out;
 955         }
 956
 957         err = tg3_bmcr_reset(tp);
 958         if (err)
 959                 return err;
 960
 961 out:
 962         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 963                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 964                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 965                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 966                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 967                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 968                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 969         }
 970         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 971                 tg3_writephy(tp, 0x1c, 0x8d68);
 972                 tg3_writephy(tp, 0x1c, 0x8d68);
 973         }
 974         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 975                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 976                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 977                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
 978                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 979                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
 980                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
 981                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
 982                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 983         }
 984         /* Set Extended packet length bit (bit 14) on all chips that */
 985         /* support jumbo frames */
 986         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
 987                 /* Cannot do read-modify-write on 5401 */
 988                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
 989         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
 990                 u32 phy_reg;
 991
 992                 /* Set bit 14 with read-modify-write to preserve other bits */
 993                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
 994                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
 995                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
 996         }
 997
 998         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
 999          * jumbo frames transmission.
1000          */
1001         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1002                 u32 phy_reg;
1003
1004                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1005                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1006                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1007         }
1008
1009         tg3_phy_set_wirespeed(tp);
1010         return 0;
1011 }
1012
1013 static void tg3_frob_aux_power(struct tg3 *tp)
1014 {
1015         struct tg3 *tp_peer = tp;
1016
1017         if ((tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) != 0)
1018                 return;
1019
1020         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1021             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1022                 struct net_device *dev_peer;
1023
1024                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1025                 if (!dev_peer)
1026                         BUG();
1027                 tp_peer = netdev_priv(dev_peer);
1028         }
1029
1030         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1031             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1032             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1033             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1034                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1035                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1036                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1037                              (GRC_LCLCTRL_GPIO_OE0 |
1038                               GRC_LCLCTRL_GPIO_OE1 |
1039                               GRC_LCLCTRL_GPIO_OE2 |
1040                               GRC_LCLCTRL_GPIO_OUTPUT0 |
1041                               GRC_LCLCTRL_GPIO_OUTPUT1));
1042                         udelay(100);
1043                 } else {
1044                         u32 no_gpio2;
1045                         u32 grc_local_ctrl;
1046
1047                         if (tp_peer != tp &&
1048                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1049                                 return;
1050
1051                         /* On 5753 and variants, GPIO2 cannot be used. */
1052                         no_gpio2 = tp->nic_sram_data_cfg &
1053                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1054
1055                         grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1056                                          GRC_LCLCTRL_GPIO_OE1 |
1057                                          GRC_LCLCTRL_GPIO_OE2 |
1058                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1059                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1060                         if (no_gpio2) {
1061                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1062                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1063                         }
1064                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1065                                                 grc_local_ctrl);
1066                         udelay(100);
1067
1068                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1069
1070                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1071                                                 grc_local_ctrl);
1072                         udelay(100);
1073
1074                         if (!no_gpio2) {
1075                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1076                                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1077                                        grc_local_ctrl);
1078                                 udelay(100);
1079                         }
1080                 }
1081         } else {
1082                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1083                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1084                         if (tp_peer != tp &&
1085                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1086                                 return;
1087
1088                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1089                              (GRC_LCLCTRL_GPIO_OE1 |
1090                               GRC_LCLCTRL_GPIO_OUTPUT1));
1091                         udelay(100);
1092
1093                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1094                              (GRC_LCLCTRL_GPIO_OE1));
1095                         udelay(100);
1096
1097                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1098                              (GRC_LCLCTRL_GPIO_OE1 |
1099                               GRC_LCLCTRL_GPIO_OUTPUT1));
1100                         udelay(100);
1101                 }
1102         }
1103 }
1104
1105 static int tg3_setup_phy(struct tg3 *, int);
1106
1107 #define RESET_KIND_SHUTDOWN     0
1108 #define RESET_KIND_INIT         1
1109 #define RESET_KIND_SUSPEND      2
1110
1111 static void tg3_write_sig_post_reset(struct tg3 *, int);
1112 static int tg3_halt_cpu(struct tg3 *, u32);
1113 static int tg3_nvram_lock(struct tg3 *);
1114 static void tg3_nvram_unlock(struct tg3 *);
1115
1116 static int tg3_set_power_state(struct tg3 *tp, int state)
1117 {
1118         u32 misc_host_ctrl;
1119         u16 power_control, power_caps;
1120         int pm = tp->pm_cap;
1121
1122         /* Make sure register accesses (indirect or otherwise)
1123          * will function correctly.
1124          */
1125         pci_write_config_dword(tp->pdev,
1126                                TG3PCI_MISC_HOST_CTRL,
1127                                tp->misc_host_ctrl);
1128
1129         pci_read_config_word(tp->pdev,
1130                              pm + PCI_PM_CTRL,
1131                              &power_control);
1132         power_control |= PCI_PM_CTRL_PME_STATUS;
1133         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1134         switch (state) {
1135         case 0:
1136                 power_control |= 0;
1137                 pci_write_config_word(tp->pdev,
1138                                       pm + PCI_PM_CTRL,
1139                                       power_control);
1140                 udelay(100);    /* Delay after power state change */
1141
1142                 /* Switch out of Vaux if it is not a LOM */
1143                 if (!(tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)) {
1144                         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
1145                         udelay(100);
1146                 }
1147
1148                 return 0;
1149
1150         case 1:
1151                 power_control |= 1;
1152                 break;
1153
1154         case 2:
1155                 power_control |= 2;
1156                 break;
1157
1158         case 3:
1159                 power_control |= 3;
1160                 break;
1161
1162         default:
1163                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1164                        "requested.\n",
1165                        tp->dev->name, state);
1166                 return -EINVAL;
1167         };
1168
1169         power_control |= PCI_PM_CTRL_PME_ENABLE;
1170
1171         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1172         tw32(TG3PCI_MISC_HOST_CTRL,
1173              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1174
1175         if (tp->link_config.phy_is_low_power == 0) {
1176                 tp->link_config.phy_is_low_power = 1;
1177                 tp->link_config.orig_speed = tp->link_config.speed;
1178                 tp->link_config.orig_duplex = tp->link_config.duplex;
1179                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1180         }
1181
1182         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1183                 tp->link_config.speed = SPEED_10;
1184                 tp->link_config.duplex = DUPLEX_HALF;
1185                 tp->link_config.autoneg = AUTONEG_ENABLE;
1186                 tg3_setup_phy(tp, 0);
1187         }
1188
1189         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1190                 int i;
1191                 u32 val;
1192
1193                 for (i = 0; i < 200; i++) {
1194                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1195                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1196                                 break;
1197                         msleep(1);
1198                 }
1199         }
1200         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1201                                              WOL_DRV_STATE_SHUTDOWN |
1202                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1203
1204         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1205
1206         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1207                 u32 mac_mode;
1208
1209                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1210                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1211                         udelay(40);
1212
1213                         mac_mode = MAC_MODE_PORT_MODE_MII;
1214
1215                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1216                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1217                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1218                 } else {
1219                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1220                 }
1221
1222                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1223                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1224
1225                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1226                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1227                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1228
1229                 tw32_f(MAC_MODE, mac_mode);
1230                 udelay(100);
1231
1232                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1233                 udelay(10);
1234         }
1235
1236         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1237             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1238              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1239                 u32 base_val;
1240
1241                 base_val = tp->pci_clock_ctrl;
1242                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1243                              CLOCK_CTRL_TXCLK_DISABLE);
1244
1245                 tw32_f(TG3PCI_CLOCK_CTRL, base_val |
1246                      CLOCK_CTRL_ALTCLK |
1247                      CLOCK_CTRL_PWRDOWN_PLL133);
1248                 udelay(40);
1249         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1250                 /* do nothing */
1251         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1252                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1253                 u32 newbits1, newbits2;
1254
1255                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1256                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1257                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1258                                     CLOCK_CTRL_TXCLK_DISABLE |
1259                                     CLOCK_CTRL_ALTCLK);
1260                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1261                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1262                         newbits1 = CLOCK_CTRL_625_CORE;
1263                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1264                 } else {
1265                         newbits1 = CLOCK_CTRL_ALTCLK;
1266                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1267                 }
1268
1269                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1);
1270                 udelay(40);
1271
1272                 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2);
1273                 udelay(40);
1274
1275                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1276                         u32 newbits3;
1277
1278                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1279                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1280                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1281                                             CLOCK_CTRL_TXCLK_DISABLE |
1282                                             CLOCK_CTRL_44MHZ_CORE);
1283                         } else {
1284                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1285                         }
1286
1287                         tw32_f(TG3PCI_CLOCK_CTRL,
1288                                          tp->pci_clock_ctrl | newbits3);
1289                         udelay(40);
1290                 }
1291         }
1292
1293         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1294             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1295                 /* Turn off the PHY */
1296                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1297                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1298                                      MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1299                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1300                         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1301                 }
1302         }
1303
1304         tg3_frob_aux_power(tp);
1305
1306         /* Workaround for unstable PLL clock */
1307         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1308             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1309                 u32 val = tr32(0x7d00);
1310
1311                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1312                 tw32(0x7d00, val);
1313                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1314                         tg3_nvram_lock(tp);
1315                         tg3_halt_cpu(tp, RX_CPU_BASE);
1316                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR0);
1317                         tg3_nvram_unlock(tp);
1318                 }
1319         }
1320
1321         /* Finally, set the new power state. */
1322         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1323         udelay(100);    /* Delay after power state change */
1324
1325         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1326
1327         return 0;
1328 }
1329
1330 static void tg3_link_report(struct tg3 *tp)
1331 {
1332         if (!netif_carrier_ok(tp->dev)) {
1333                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1334         } else {
1335                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1336                        tp->dev->name,
1337                        (tp->link_config.active_speed == SPEED_1000 ?
1338                         1000 :
1339                         (tp->link_config.active_speed == SPEED_100 ?
1340                          100 : 10)),
1341                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1342                         "full" : "half"));
1343
1344                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1345                        "%s for RX.\n",
1346                        tp->dev->name,
1347                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1348                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1349         }
1350 }
1351
1352 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1353 {
1354         u32 new_tg3_flags = 0;
1355         u32 old_rx_mode = tp->rx_mode;
1356         u32 old_tx_mode = tp->tx_mode;
1357
1358         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1359
1360                 /* Convert 1000BaseX flow control bits to 1000BaseT
1361                  * bits before resolving flow control.
1362                  */
1363                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1364                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1365                                        ADVERTISE_PAUSE_ASYM);
1366                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1367
1368                         if (local_adv & ADVERTISE_1000XPAUSE)
1369                                 local_adv |= ADVERTISE_PAUSE_CAP;
1370                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1371                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1372                         if (remote_adv & LPA_1000XPAUSE)
1373                                 remote_adv |= LPA_PAUSE_CAP;
1374                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1375                                 remote_adv |= LPA_PAUSE_ASYM;
1376                 }
1377
1378                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1379                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1380                                 if (remote_adv & LPA_PAUSE_CAP)
1381                                         new_tg3_flags |=
1382                                                 (TG3_FLAG_RX_PAUSE |
1383                                                 TG3_FLAG_TX_PAUSE);
1384                                 else if (remote_adv & LPA_PAUSE_ASYM)
1385                                         new_tg3_flags |=
1386                                                 (TG3_FLAG_RX_PAUSE);
1387                         } else {
1388                                 if (remote_adv & LPA_PAUSE_CAP)
1389                                         new_tg3_flags |=
1390                                                 (TG3_FLAG_RX_PAUSE |
1391                                                 TG3_FLAG_TX_PAUSE);
1392                         }
1393                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1394                         if ((remote_adv & LPA_PAUSE_CAP) &&
1395                         (remote_adv & LPA_PAUSE_ASYM))
1396                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1397                 }
1398
1399                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1400                 tp->tg3_flags |= new_tg3_flags;
1401         } else {
1402                 new_tg3_flags = tp->tg3_flags;
1403         }
1404
1405         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1406                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1407         else
1408                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1409
1410         if (old_rx_mode != tp->rx_mode) {
1411                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1412         }
1413
1414         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1415                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1416         else
1417                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1418
1419         if (old_tx_mode != tp->tx_mode) {
1420                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1421         }
1422 }
1423
1424 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1425 {
1426         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1427         case MII_TG3_AUX_STAT_10HALF:
1428                 *speed = SPEED_10;
1429                 *duplex = DUPLEX_HALF;
1430                 break;
1431
1432         case MII_TG3_AUX_STAT_10FULL:
1433                 *speed = SPEED_10;
1434                 *duplex = DUPLEX_FULL;
1435                 break;
1436
1437         case MII_TG3_AUX_STAT_100HALF:
1438                 *speed = SPEED_100;
1439                 *duplex = DUPLEX_HALF;
1440                 break;
1441
1442         case MII_TG3_AUX_STAT_100FULL:
1443                 *speed = SPEED_100;
1444                 *duplex = DUPLEX_FULL;
1445                 break;
1446
1447         case MII_TG3_AUX_STAT_1000HALF:
1448                 *speed = SPEED_1000;
1449                 *duplex = DUPLEX_HALF;
1450                 break;
1451
1452         case MII_TG3_AUX_STAT_1000FULL:
1453                 *speed = SPEED_1000;
1454                 *duplex = DUPLEX_FULL;
1455                 break;
1456
1457         default:
1458                 *speed = SPEED_INVALID;
1459                 *duplex = DUPLEX_INVALID;
1460                 break;
1461         };
1462 }
1463
1464 static void tg3_phy_copper_begin(struct tg3 *tp)
1465 {
1466         u32 new_adv;
1467         int i;
1468
1469         if (tp->link_config.phy_is_low_power) {
1470                 /* Entering low power mode.  Disable gigabit and
1471                  * 100baseT advertisements.
1472                  */
1473                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1474
1475                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1476                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1477                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1478                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1479
1480                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1481         } else if (tp->link_config.speed == SPEED_INVALID) {
1482                 tp->link_config.advertising =
1483                         (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
1484                          ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
1485                          ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
1486                          ADVERTISED_Autoneg | ADVERTISED_MII);
1487
1488                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1489                         tp->link_config.advertising &=
1490                                 ~(ADVERTISED_1000baseT_Half |
1491                                   ADVERTISED_1000baseT_Full);
1492
1493                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1494                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1495                         new_adv |= ADVERTISE_10HALF;
1496                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1497                         new_adv |= ADVERTISE_10FULL;
1498                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1499                         new_adv |= ADVERTISE_100HALF;
1500                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1501                         new_adv |= ADVERTISE_100FULL;
1502                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1503
1504                 if (tp->link_config.advertising &
1505                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1506                         new_adv = 0;
1507                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1508                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1509                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1510                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1511                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1512                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1513                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1514                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1515                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1516                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1517                 } else {
1518                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1519                 }
1520         } else {
1521                 /* Asking for a specific link mode. */
1522                 if (tp->link_config.speed == SPEED_1000) {
1523                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1524                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1525
1526                         if (tp->link_config.duplex == DUPLEX_FULL)
1527                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1528                         else
1529                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1530                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1531                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1532                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1533                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1534                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1535                 } else {
1536                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1537
1538                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1539                         if (tp->link_config.speed == SPEED_100) {
1540                                 if (tp->link_config.duplex == DUPLEX_FULL)
1541                                         new_adv |= ADVERTISE_100FULL;
1542                                 else
1543                                         new_adv |= ADVERTISE_100HALF;
1544                         } else {
1545                                 if (tp->link_config.duplex == DUPLEX_FULL)
1546                                         new_adv |= ADVERTISE_10FULL;
1547                                 else
1548                                         new_adv |= ADVERTISE_10HALF;
1549                         }
1550                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1551                 }
1552         }
1553
1554         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1555             tp->link_config.speed != SPEED_INVALID) {
1556                 u32 bmcr, orig_bmcr;
1557
1558                 tp->link_config.active_speed = tp->link_config.speed;
1559                 tp->link_config.active_duplex = tp->link_config.duplex;
1560
1561                 bmcr = 0;
1562                 switch (tp->link_config.speed) {
1563                 default:
1564                 case SPEED_10:
1565                         break;
1566
1567                 case SPEED_100:
1568                         bmcr |= BMCR_SPEED100;
1569                         break;
1570
1571                 case SPEED_1000:
1572                         bmcr |= TG3_BMCR_SPEED1000;
1573                         break;
1574                 };
1575
1576                 if (tp->link_config.duplex == DUPLEX_FULL)
1577                         bmcr |= BMCR_FULLDPLX;
1578
1579                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1580                     (bmcr != orig_bmcr)) {
1581                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1582                         for (i = 0; i < 1500; i++) {
1583                                 u32 tmp;
1584
1585                                 udelay(10);
1586                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1587                                     tg3_readphy(tp, MII_BMSR, &tmp))
1588                                         continue;
1589                                 if (!(tmp & BMSR_LSTATUS)) {
1590                                         udelay(40);
1591                                         break;
1592                                 }
1593                         }
1594                         tg3_writephy(tp, MII_BMCR, bmcr);
1595                         udelay(40);
1596                 }
1597         } else {
1598                 tg3_writephy(tp, MII_BMCR,
1599                              BMCR_ANENABLE | BMCR_ANRESTART);
1600         }
1601 }
1602
1603 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1604 {
1605         int err;
1606
1607         /* Turn off tap power management. */
1608         /* Set Extended packet length bit */
1609         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1610
1611         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1612         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1613
1614         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1615         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1616
1617         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1618         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1619
1620         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1621         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1622
1623         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1624         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1625
1626         udelay(40);
1627
1628         return err;
1629 }
1630
1631 static int tg3_copper_is_advertising_all(struct tg3 *tp)
1632 {
1633         u32 adv_reg, all_mask;
1634
1635         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1636                 return 0;
1637
1638         all_mask = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1639                     ADVERTISE_100HALF | ADVERTISE_100FULL);
1640         if ((adv_reg & all_mask) != all_mask)
1641                 return 0;
1642         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1643                 u32 tg3_ctrl;
1644
1645                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1646                         return 0;
1647
1648                 all_mask = (MII_TG3_CTRL_ADV_1000_HALF |
1649                             MII_TG3_CTRL_ADV_1000_FULL);
1650                 if ((tg3_ctrl & all_mask) != all_mask)
1651                         return 0;
1652         }
1653         return 1;
1654 }
1655
1656 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1657 {
1658         int current_link_up;
1659         u32 bmsr, dummy;
1660         u16 current_speed;
1661         u8 current_duplex;
1662         int i, err;
1663
1664         tw32(MAC_EVENT, 0);
1665
1666         tw32_f(MAC_STATUS,
1667              (MAC_STATUS_SYNC_CHANGED |
1668               MAC_STATUS_CFG_CHANGED |
1669               MAC_STATUS_MI_COMPLETION |
1670               MAC_STATUS_LNKSTATE_CHANGED));
1671         udelay(40);
1672
1673         tp->mi_mode = MAC_MI_MODE_BASE;
1674         tw32_f(MAC_MI_MODE, tp->mi_mode);
1675         udelay(80);
1676
1677         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1678
1679         /* Some third-party PHYs need to be reset on link going
1680          * down.
1681          */
1682         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1683              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1684              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1685             netif_carrier_ok(tp->dev)) {
1686                 tg3_readphy(tp, MII_BMSR, &bmsr);
1687                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1688                     !(bmsr & BMSR_LSTATUS))
1689                         force_reset = 1;
1690         }
1691         if (force_reset)
1692                 tg3_phy_reset(tp);
1693
1694         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1695                 tg3_readphy(tp, MII_BMSR, &bmsr);
1696                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1697                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1698                         bmsr = 0;
1699
1700                 if (!(bmsr & BMSR_LSTATUS)) {
1701                         err = tg3_init_5401phy_dsp(tp);
1702                         if (err)
1703                                 return err;
1704
1705                         tg3_readphy(tp, MII_BMSR, &bmsr);
1706                         for (i = 0; i < 1000; i++) {
1707                                 udelay(10);
1708                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1709                                     (bmsr & BMSR_LSTATUS)) {
1710                                         udelay(40);
1711                                         break;
1712                                 }
1713                         }
1714
1715                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1716                             !(bmsr & BMSR_LSTATUS) &&
1717                             tp->link_config.active_speed == SPEED_1000) {
1718                                 err = tg3_phy_reset(tp);
1719                                 if (!err)
1720                                         err = tg3_init_5401phy_dsp(tp);
1721                                 if (err)
1722                                         return err;
1723                         }
1724                 }
1725         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1726                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1727                 /* 5701 {A0,B0} CRC bug workaround */
1728                 tg3_writephy(tp, 0x15, 0x0a75);
1729                 tg3_writephy(tp, 0x1c, 0x8c68);
1730                 tg3_writephy(tp, 0x1c, 0x8d68);
1731                 tg3_writephy(tp, 0x1c, 0x8c68);
1732         }
1733
1734         /* Clear pending interrupts... */
1735         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1736         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1737
1738         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1739                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1740         else
1741                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1742
1743         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1744             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1745                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1746                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1747                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1748                 else
1749                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1750         }
1751
1752         current_link_up = 0;
1753         current_speed = SPEED_INVALID;
1754         current_duplex = DUPLEX_INVALID;
1755
1756         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1757                 u32 val;
1758
1759                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1760                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1761                 if (!(val & (1 << 10))) {
1762                         val |= (1 << 10);
1763                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1764                         goto relink;
1765                 }
1766         }
1767
1768         bmsr = 0;
1769         for (i = 0; i < 100; i++) {
1770                 tg3_readphy(tp, MII_BMSR, &bmsr);
1771                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1772                     (bmsr & BMSR_LSTATUS))
1773                         break;
1774                 udelay(40);
1775         }
1776
1777         if (bmsr & BMSR_LSTATUS) {
1778                 u32 aux_stat, bmcr;
1779
1780                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1781                 for (i = 0; i < 2000; i++) {
1782                         udelay(10);
1783                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1784                             aux_stat)
1785                                 break;
1786                 }
1787
1788                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1789                                              &current_speed,
1790                                              &current_duplex);
1791
1792                 bmcr = 0;
1793                 for (i = 0; i < 200; i++) {
1794                         tg3_readphy(tp, MII_BMCR, &bmcr);
1795                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1796                                 continue;
1797                         if (bmcr && bmcr != 0x7fff)
1798                                 break;
1799                         udelay(10);
1800                 }
1801
1802                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1803                         if (bmcr & BMCR_ANENABLE) {
1804                                 current_link_up = 1;
1805
1806                                 /* Force autoneg restart if we are exiting
1807                                  * low power mode.
1808                                  */
1809                                 if (!tg3_copper_is_advertising_all(tp))
1810                                         current_link_up = 0;
1811                         } else {
1812                                 current_link_up = 0;
1813                         }
1814                 } else {
1815                         if (!(bmcr & BMCR_ANENABLE) &&
1816                             tp->link_config.speed == current_speed &&
1817                             tp->link_config.duplex == current_duplex) {
1818                                 current_link_up = 1;
1819                         } else {
1820                                 current_link_up = 0;
1821                         }
1822                 }
1823
1824                 tp->link_config.active_speed = current_speed;
1825                 tp->link_config.active_duplex = current_duplex;
1826         }
1827
1828         if (current_link_up == 1 &&
1829             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1830             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1831                 u32 local_adv, remote_adv;
1832
1833                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1834                         local_adv = 0;
1835                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1836
1837                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1838                         remote_adv = 0;
1839
1840                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1841
1842                 /* If we are not advertising full pause capability,
1843                  * something is wrong.  Bring the link down and reconfigure.
1844                  */
1845                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1846                         current_link_up = 0;
1847                 } else {
1848                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1849                 }
1850         }
1851 relink:
1852         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1853                 u32 tmp;
1854
1855                 tg3_phy_copper_begin(tp);
1856
1857                 tg3_readphy(tp, MII_BMSR, &tmp);
1858                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1859                     (tmp & BMSR_LSTATUS))
1860                         current_link_up = 1;
1861         }
1862
1863         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1864         if (current_link_up == 1) {
1865                 if (tp->link_config.active_speed == SPEED_100 ||
1866                     tp->link_config.active_speed == SPEED_10)
1867                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1868                 else
1869                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1870         } else
1871                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1872
1873         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1874         if (tp->link_config.active_duplex == DUPLEX_HALF)
1875                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1876
1877         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1878         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1879                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1880                     (current_link_up == 1 &&
1881                      tp->link_config.active_speed == SPEED_10))
1882                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1883         } else {
1884                 if (current_link_up == 1)
1885                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1886         }
1887
1888         /* ??? Without this setting Netgear GA302T PHY does not
1889          * ??? send/receive packets...
1890          */
1891         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1892             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1893                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1894                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1895                 udelay(80);
1896         }
1897
1898         tw32_f(MAC_MODE, tp->mac_mode);
1899         udelay(40);
1900
1901         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1902                 /* Polled via timer. */
1903                 tw32_f(MAC_EVENT, 0);
1904         } else {
1905                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1906         }
1907         udelay(40);
1908
1909         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1910             current_link_up == 1 &&
1911             tp->link_config.active_speed == SPEED_1000 &&
1912             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1913              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1914                 udelay(120);
1915                 tw32_f(MAC_STATUS,
1916                      (MAC_STATUS_SYNC_CHANGED |
1917                       MAC_STATUS_CFG_CHANGED));
1918                 udelay(40);
1919                 tg3_write_mem(tp,
1920                               NIC_SRAM_FIRMWARE_MBOX,
1921                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1922         }
1923
1924         if (current_link_up != netif_carrier_ok(tp->dev)) {
1925                 if (current_link_up)
1926                         netif_carrier_on(tp->dev);
1927                 else
1928                         netif_carrier_off(tp->dev);
1929                 tg3_link_report(tp);
1930         }
1931
1932         return 0;
1933 }
1934
1935 struct tg3_fiber_aneginfo {
1936         int state;
1937 #define ANEG_STATE_UNKNOWN              0
1938 #define ANEG_STATE_AN_ENABLE            1
1939 #define ANEG_STATE_RESTART_INIT         2
1940 #define ANEG_STATE_RESTART              3
1941 #define ANEG_STATE_DISABLE_LINK_OK      4
1942 #define ANEG_STATE_ABILITY_DETECT_INIT  5
1943 #define ANEG_STATE_ABILITY_DETECT       6
1944 #define ANEG_STATE_ACK_DETECT_INIT      7
1945 #define ANEG_STATE_ACK_DETECT           8
1946 #define ANEG_STATE_COMPLETE_ACK_INIT    9
1947 #define ANEG_STATE_COMPLETE_ACK         10
1948 #define ANEG_STATE_IDLE_DETECT_INIT     11
1949 #define ANEG_STATE_IDLE_DETECT          12
1950 #define ANEG_STATE_LINK_OK              13
1951 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
1952 #define ANEG_STATE_NEXT_PAGE_WAIT       15
1953
1954         u32 flags;
1955 #define MR_AN_ENABLE            0x00000001
1956 #define MR_RESTART_AN           0x00000002
1957 #define MR_AN_COMPLETE          0x00000004
1958 #define MR_PAGE_RX              0x00000008
1959 #define MR_NP_LOADED            0x00000010
1960 #define MR_TOGGLE_TX            0x00000020
1961 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
1962 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
1963 #define MR_LP_ADV_SYM_PAUSE     0x00000100
1964 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
1965 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
1966 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
1967 #define MR_LP_ADV_NEXT_PAGE     0x00001000
1968 #define MR_TOGGLE_RX            0x00002000
1969 #define MR_NP_RX                0x00004000
1970
1971 #define MR_LINK_OK              0x80000000
1972
1973         unsigned long link_time, cur_time;
1974
1975         u32 ability_match_cfg;
1976         int ability_match_count;
1977
1978         char ability_match, idle_match, ack_match;
1979
1980         u32 txconfig, rxconfig;
1981 #define ANEG_CFG_NP             0x00000080
1982 #define ANEG_CFG_ACK            0x00000040
1983 #define ANEG_CFG_RF2            0x00000020
1984 #define ANEG_CFG_RF1            0x00000010
1985 #define ANEG_CFG_PS2            0x00000001
1986 #define ANEG_CFG_PS1            0x00008000
1987 #define ANEG_CFG_HD             0x00004000
1988 #define ANEG_CFG_FD             0x00002000
1989 #define ANEG_CFG_INVAL          0x00001f06
1990
1991 };
1992 #define ANEG_OK         0
1993 #define ANEG_DONE       1
1994 #define ANEG_TIMER_ENAB 2
1995 #define ANEG_FAILED     -1
1996
1997 #define ANEG_STATE_SETTLE_TIME  10000
1998
1999 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2000                                    struct tg3_fiber_aneginfo *ap)
2001 {
2002         unsigned long delta;
2003         u32 rx_cfg_reg;
2004         int ret;
2005
2006         if (ap->state == ANEG_STATE_UNKNOWN) {
2007                 ap->rxconfig = 0;
2008                 ap->link_time = 0;
2009                 ap->cur_time = 0;
2010                 ap->ability_match_cfg = 0;
2011                 ap->ability_match_count = 0;
2012                 ap->ability_match = 0;
2013                 ap->idle_match = 0;
2014                 ap->ack_match = 0;
2015         }
2016         ap->cur_time++;
2017
2018         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2019                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2020
2021                 if (rx_cfg_reg != ap->ability_match_cfg) {
2022                         ap->ability_match_cfg = rx_cfg_reg;
2023                         ap->ability_match = 0;
2024                         ap->ability_match_count = 0;
2025                 } else {
2026                         if (++ap->ability_match_count > 1) {
2027                                 ap->ability_match = 1;
2028                                 ap->ability_match_cfg = rx_cfg_reg;
2029                         }
2030                 }
2031                 if (rx_cfg_reg & ANEG_CFG_ACK)
2032                         ap->ack_match = 1;
2033                 else
2034                         ap->ack_match = 0;
2035
2036                 ap->idle_match = 0;
2037         } else {
2038                 ap->idle_match = 1;
2039                 ap->ability_match_cfg = 0;
2040                 ap->ability_match_count = 0;
2041                 ap->ability_match = 0;
2042                 ap->ack_match = 0;
2043
2044                 rx_cfg_reg = 0;
2045         }
2046
2047         ap->rxconfig = rx_cfg_reg;
2048         ret = ANEG_OK;
2049
2050         switch(ap->state) {
2051         case ANEG_STATE_UNKNOWN:
2052                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2053                         ap->state = ANEG_STATE_AN_ENABLE;
2054
2055                 /* fallthru */
2056         case ANEG_STATE_AN_ENABLE:
2057                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2058                 if (ap->flags & MR_AN_ENABLE) {
2059                         ap->link_time = 0;
2060                         ap->cur_time = 0;
2061                         ap->ability_match_cfg = 0;
2062                         ap->ability_match_count = 0;
2063                         ap->ability_match = 0;
2064                         ap->idle_match = 0;
2065                         ap->ack_match = 0;
2066
2067                         ap->state = ANEG_STATE_RESTART_INIT;
2068                 } else {
2069                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2070                 }
2071                 break;
2072
2073         case ANEG_STATE_RESTART_INIT:
2074                 ap->link_time = ap->cur_time;
2075                 ap->flags &= ~(MR_NP_LOADED);
2076                 ap->txconfig = 0;
2077                 tw32(MAC_TX_AUTO_NEG, 0);
2078                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2079                 tw32_f(MAC_MODE, tp->mac_mode);
2080                 udelay(40);
2081
2082                 ret = ANEG_TIMER_ENAB;
2083                 ap->state = ANEG_STATE_RESTART;
2084
2085                 /* fallthru */
2086         case ANEG_STATE_RESTART:
2087                 delta = ap->cur_time - ap->link_time;
2088                 if (delta > ANEG_STATE_SETTLE_TIME) {
2089                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2090                 } else {
2091                         ret = ANEG_TIMER_ENAB;
2092                 }
2093                 break;
2094
2095         case ANEG_STATE_DISABLE_LINK_OK:
2096                 ret = ANEG_DONE;
2097                 break;
2098
2099         case ANEG_STATE_ABILITY_DETECT_INIT:
2100                 ap->flags &= ~(MR_TOGGLE_TX);
2101                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2102                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2103                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2104                 tw32_f(MAC_MODE, tp->mac_mode);
2105                 udelay(40);
2106
2107                 ap->state = ANEG_STATE_ABILITY_DETECT;
2108                 break;
2109
2110         case ANEG_STATE_ABILITY_DETECT:
2111                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2112                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2113                 }
2114                 break;
2115
2116         case ANEG_STATE_ACK_DETECT_INIT:
2117                 ap->txconfig |= ANEG_CFG_ACK;
2118                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2119                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2120                 tw32_f(MAC_MODE, tp->mac_mode);
2121                 udelay(40);
2122
2123                 ap->state = ANEG_STATE_ACK_DETECT;
2124
2125                 /* fallthru */
2126         case ANEG_STATE_ACK_DETECT:
2127                 if (ap->ack_match != 0) {
2128                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2129                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2130                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2131                         } else {
2132                                 ap->state = ANEG_STATE_AN_ENABLE;
2133                         }
2134                 } else if (ap->ability_match != 0 &&
2135                            ap->rxconfig == 0) {
2136                         ap->state = ANEG_STATE_AN_ENABLE;
2137                 }
2138                 break;
2139
2140         case ANEG_STATE_COMPLETE_ACK_INIT:
2141                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2142                         ret = ANEG_FAILED;
2143                         break;
2144                 }
2145                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2146                                MR_LP_ADV_HALF_DUPLEX |
2147                                MR_LP_ADV_SYM_PAUSE |
2148                                MR_LP_ADV_ASYM_PAUSE |
2149                                MR_LP_ADV_REMOTE_FAULT1 |
2150                                MR_LP_ADV_REMOTE_FAULT2 |
2151                                MR_LP_ADV_NEXT_PAGE |
2152                                MR_TOGGLE_RX |
2153                                MR_NP_RX);
2154                 if (ap->rxconfig & ANEG_CFG_FD)
2155                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2156                 if (ap->rxconfig & ANEG_CFG_HD)
2157                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2158                 if (ap->rxconfig & ANEG_CFG_PS1)
2159                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2160                 if (ap->rxconfig & ANEG_CFG_PS2)
2161                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2162                 if (ap->rxconfig & ANEG_CFG_RF1)
2163                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2164                 if (ap->rxconfig & ANEG_CFG_RF2)
2165                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2166                 if (ap->rxconfig & ANEG_CFG_NP)
2167                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2168
2169                 ap->link_time = ap->cur_time;
2170
2171                 ap->flags ^= (MR_TOGGLE_TX);
2172                 if (ap->rxconfig & 0x0008)
2173                         ap->flags |= MR_TOGGLE_RX;
2174                 if (ap->rxconfig & ANEG_CFG_NP)
2175                         ap->flags |= MR_NP_RX;
2176                 ap->flags |= MR_PAGE_RX;
2177
2178                 ap->state = ANEG_STATE_COMPLETE_ACK;
2179                 ret = ANEG_TIMER_ENAB;
2180                 break;
2181
2182         case ANEG_STATE_COMPLETE_ACK:
2183                 if (ap->ability_match != 0 &&
2184                     ap->rxconfig == 0) {
2185                         ap->state = ANEG_STATE_AN_ENABLE;
2186                         break;
2187                 }
2188                 delta = ap->cur_time - ap->link_time;
2189                 if (delta > ANEG_STATE_SETTLE_TIME) {
2190                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2191                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2192                         } else {
2193                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2194                                     !(ap->flags & MR_NP_RX)) {
2195                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2196                                 } else {
2197                                         ret = ANEG_FAILED;
2198                                 }
2199                         }
2200                 }
2201                 break;
2202
2203         case ANEG_STATE_IDLE_DETECT_INIT:
2204                 ap->link_time = ap->cur_time;
2205                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2206                 tw32_f(MAC_MODE, tp->mac_mode);
2207                 udelay(40);
2208
2209                 ap->state = ANEG_STATE_IDLE_DETECT;
2210                 ret = ANEG_TIMER_ENAB;
2211                 break;
2212
2213         case ANEG_STATE_IDLE_DETECT:
2214                 if (ap->ability_match != 0 &&
2215                     ap->rxconfig == 0) {
2216                         ap->state = ANEG_STATE_AN_ENABLE;
2217                         break;
2218                 }
2219                 delta = ap->cur_time - ap->link_time;
2220                 if (delta > ANEG_STATE_SETTLE_TIME) {
2221                         /* XXX another gem from the Broadcom driver :( */
2222                         ap->state = ANEG_STATE_LINK_OK;
2223                 }
2224                 break;
2225
2226         case ANEG_STATE_LINK_OK:
2227                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2228                 ret = ANEG_DONE;
2229                 break;
2230
2231         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2232                 /* ??? unimplemented */
2233                 break;
2234
2235         case ANEG_STATE_NEXT_PAGE_WAIT:
2236                 /* ??? unimplemented */
2237                 break;
2238
2239         default:
2240                 ret = ANEG_FAILED;
2241                 break;
2242         };
2243
2244         return ret;
2245 }
2246
2247 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2248 {
2249         int res = 0;
2250         struct tg3_fiber_aneginfo aninfo;
2251         int status = ANEG_FAILED;
2252         unsigned int tick;
2253         u32 tmp;
2254
2255         tw32_f(MAC_TX_AUTO_NEG, 0);
2256
2257         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2258         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2259         udelay(40);
2260
2261         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2262         udelay(40);
2263
2264         memset(&aninfo, 0, sizeof(aninfo));
2265         aninfo.flags |= MR_AN_ENABLE;
2266         aninfo.state = ANEG_STATE_UNKNOWN;
2267         aninfo.cur_time = 0;
2268         tick = 0;
2269         while (++tick < 195000) {
2270                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2271                 if (status == ANEG_DONE || status == ANEG_FAILED)
2272                         break;
2273
2274                 udelay(1);
2275         }
2276
2277         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2278         tw32_f(MAC_MODE, tp->mac_mode);
2279         udelay(40);
2280
2281         *flags = aninfo.flags;
2282
2283         if (status == ANEG_DONE &&
2284             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2285                              MR_LP_ADV_FULL_DUPLEX)))
2286                 res = 1;
2287
2288         return res;
2289 }
2290
2291 static void tg3_init_bcm8002(struct tg3 *tp)
2292 {
2293         u32 mac_status = tr32(MAC_STATUS);
2294         int i;
2295
2296         /* Reset when initting first time or we have a link. */
2297         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2298             !(mac_status & MAC_STATUS_PCS_SYNCED))
2299                 return;
2300
2301         /* Set PLL lock range. */
2302         tg3_writephy(tp, 0x16, 0x8007);
2303
2304         /* SW reset */
2305         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2306
2307         /* Wait for reset to complete. */
2308         /* XXX schedule_timeout() ... */
2309         for (i = 0; i < 500; i++)
2310                 udelay(10);
2311
2312         /* Config mode; select PMA/Ch 1 regs. */
2313         tg3_writephy(tp, 0x10, 0x8411);
2314
2315         /* Enable auto-lock and comdet, select txclk for tx. */
2316         tg3_writephy(tp, 0x11, 0x0a10);
2317
2318         tg3_writephy(tp, 0x18, 0x00a0);
2319         tg3_writephy(tp, 0x16, 0x41ff);
2320
2321         /* Assert and deassert POR. */
2322         tg3_writephy(tp, 0x13, 0x0400);
2323         udelay(40);
2324         tg3_writephy(tp, 0x13, 0x0000);
2325
2326         tg3_writephy(tp, 0x11, 0x0a50);
2327         udelay(40);
2328         tg3_writephy(tp, 0x11, 0x0a10);
2329
2330         /* Wait for signal to stabilize */
2331         /* XXX schedule_timeout() ... */
2332         for (i = 0; i < 15000; i++)
2333                 udelay(10);
2334
2335         /* Deselect the channel register so we can read the PHYID
2336          * later.
2337          */
2338         tg3_writephy(tp, 0x10, 0x8011);
2339 }
2340
2341 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2342 {
2343         u32 sg_dig_ctrl, sg_dig_status;
2344         u32 serdes_cfg, expected_sg_dig_ctrl;
2345         int workaround, port_a;
2346         int current_link_up;
2347
2348         serdes_cfg = 0;
2349         expected_sg_dig_ctrl = 0;
2350         workaround = 0;
2351         port_a = 1;
2352         current_link_up = 0;
2353
2354         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2355             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2356                 workaround = 1;
2357                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2358                         port_a = 0;
2359
2360                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2361                 /* preserve bits 20-23 for voltage regulator */
2362                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2363         }
2364
2365         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2366
2367         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2368                 if (sg_dig_ctrl & (1 << 31)) {
2369                         if (workaround) {
2370                                 u32 val = serdes_cfg;
2371
2372                                 if (port_a)
2373                                         val |= 0xc010000;
2374                                 else
2375                                         val |= 0x4010000;
2376                                 tw32_f(MAC_SERDES_CFG, val);
2377                         }
2378                         tw32_f(SG_DIG_CTRL, 0x01388400);
2379                 }
2380                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2381                         tg3_setup_flow_control(tp, 0, 0);
2382                         current_link_up = 1;
2383                 }
2384                 goto out;
2385         }
2386
2387         /* Want auto-negotiation.  */
2388         expected_sg_dig_ctrl = 0x81388400;
2389
2390         /* Pause capability */
2391         expected_sg_dig_ctrl |= (1 << 11);
2392
2393         /* Asymettric pause */
2394         expected_sg_dig_ctrl |= (1 << 12);
2395
2396         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2397                 if (workaround)
2398                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2399                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2400                 udelay(5);
2401                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2402
2403                 tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2404         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2405                                  MAC_STATUS_SIGNAL_DET)) {
2406                 int i;
2407
2408                 /* Giver time to negotiate (~200ms) */
2409                 for (i = 0; i < 40000; i++) {
2410                         sg_dig_status = tr32(SG_DIG_STATUS);
2411                         if (sg_dig_status & (0x3))
2412                                 break;
2413                         udelay(5);
2414                 }
2415                 mac_status = tr32(MAC_STATUS);
2416
2417                 if ((sg_dig_status & (1 << 1)) &&
2418                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2419                         u32 local_adv, remote_adv;
2420
2421                         local_adv = ADVERTISE_PAUSE_CAP;
2422                         remote_adv = 0;
2423                         if (sg_dig_status & (1 << 19))
2424                                 remote_adv |= LPA_PAUSE_CAP;
2425                         if (sg_dig_status & (1 << 20))
2426                                 remote_adv |= LPA_PAUSE_ASYM;
2427
2428                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2429                         current_link_up = 1;
2430                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2431                 } else if (!(sg_dig_status & (1 << 1))) {
2432                         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED)
2433                                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2434                         else {
2435                                 if (workaround) {
2436                                         u32 val = serdes_cfg;
2437
2438                                         if (port_a)
2439                                                 val |= 0xc010000;
2440                                         else
2441                                                 val |= 0x4010000;
2442
2443                                         tw32_f(MAC_SERDES_CFG, val);
2444                                 }
2445
2446                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2447                                 udelay(40);
2448
2449                                 /* Link parallel detection - link is up */
2450                                 /* only if we have PCS_SYNC and not */
2451                                 /* receiving config code words */
2452                                 mac_status = tr32(MAC_STATUS);
2453                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2454                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2455                                         tg3_setup_flow_control(tp, 0, 0);
2456                                         current_link_up = 1;
2457                                 }
2458                         }
2459                 }
2460         }
2461
2462 out:
2463         return current_link_up;
2464 }
2465
2466 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2467 {
2468         int current_link_up = 0;
2469
2470         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2471                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2472                 goto out;
2473         }
2474
2475         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2476                 u32 flags;
2477                 int i;
2478
2479                 if (fiber_autoneg(tp, &flags)) {
2480                         u32 local_adv, remote_adv;
2481
2482                         local_adv = ADVERTISE_PAUSE_CAP;
2483                         remote_adv = 0;
2484                         if (flags & MR_LP_ADV_SYM_PAUSE)
2485                                 remote_adv |= LPA_PAUSE_CAP;
2486                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2487                                 remote_adv |= LPA_PAUSE_ASYM;
2488
2489                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2490
2491                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2492                         current_link_up = 1;
2493                 }
2494                 for (i = 0; i < 30; i++) {
2495                         udelay(20);
2496                         tw32_f(MAC_STATUS,
2497                                (MAC_STATUS_SYNC_CHANGED |
2498                                 MAC_STATUS_CFG_CHANGED));
2499                         udelay(40);
2500                         if ((tr32(MAC_STATUS) &
2501                              (MAC_STATUS_SYNC_CHANGED |
2502                               MAC_STATUS_CFG_CHANGED)) == 0)
2503                                 break;
2504                 }
2505
2506                 mac_status = tr32(MAC_STATUS);
2507                 if (current_link_up == 0 &&
2508                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2509                     !(mac_status & MAC_STATUS_RCVD_CFG))
2510                         current_link_up = 1;
2511         } else {
2512                 /* Forcing 1000FD link up. */
2513                 current_link_up = 1;
2514                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2515
2516                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2517                 udelay(40);
2518         }
2519
2520 out:
2521         return current_link_up;
2522 }
2523
2524 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2525 {
2526         u32 orig_pause_cfg;
2527         u16 orig_active_speed;
2528         u8 orig_active_duplex;
2529         u32 mac_status;
2530         int current_link_up;
2531         int i;
2532
2533         orig_pause_cfg =
2534                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2535                                   TG3_FLAG_TX_PAUSE));
2536         orig_active_speed = tp->link_config.active_speed;
2537         orig_active_duplex = tp->link_config.active_duplex;
2538
2539         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2540             netif_carrier_ok(tp->dev) &&
2541             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2542                 mac_status = tr32(MAC_STATUS);
2543                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2544                                MAC_STATUS_SIGNAL_DET |
2545                                MAC_STATUS_CFG_CHANGED |
2546                                MAC_STATUS_RCVD_CFG);
2547                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2548                                    MAC_STATUS_SIGNAL_DET)) {
2549                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2550                                             MAC_STATUS_CFG_CHANGED));
2551                         return 0;
2552                 }
2553         }
2554
2555         tw32_f(MAC_TX_AUTO_NEG, 0);
2556
2557         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2558         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2559         tw32_f(MAC_MODE, tp->mac_mode);
2560         udelay(40);
2561
2562         if (tp->phy_id == PHY_ID_BCM8002)
2563                 tg3_init_bcm8002(tp);
2564
2565         /* Enable link change event even when serdes polling.  */
2566         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2567         udelay(40);
2568
2569         current_link_up = 0;
2570         mac_status = tr32(MAC_STATUS);
2571
2572         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2573                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2574         else
2575                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2576
2577         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2578         tw32_f(MAC_MODE, tp->mac_mode);
2579         udelay(40);
2580
2581         tp->hw_status->status =
2582                 (SD_STATUS_UPDATED |
2583                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2584
2585         for (i = 0; i < 100; i++) {
2586                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2587                                     MAC_STATUS_CFG_CHANGED));
2588                 udelay(5);
2589                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2590                                          MAC_STATUS_CFG_CHANGED)) == 0)
2591                         break;
2592         }
2593
2594         mac_status = tr32(MAC_STATUS);
2595         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2596                 current_link_up = 0;
2597                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2598                         tw32_f(MAC_MODE, (tp->mac_mode |
2599                                           MAC_MODE_SEND_CONFIGS));
2600                         udelay(1);
2601                         tw32_f(MAC_MODE, tp->mac_mode);
2602                 }
2603         }
2604
2605         if (current_link_up == 1) {
2606                 tp->link_config.active_speed = SPEED_1000;
2607                 tp->link_config.active_duplex = DUPLEX_FULL;
2608                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2609                                     LED_CTRL_LNKLED_OVERRIDE |
2610                                     LED_CTRL_1000MBPS_ON));
2611         } else {
2612                 tp->link_config.active_speed = SPEED_INVALID;
2613                 tp->link_config.active_duplex = DUPLEX_INVALID;
2614                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2615                                     LED_CTRL_LNKLED_OVERRIDE |
2616                                     LED_CTRL_TRAFFIC_OVERRIDE));
2617         }
2618
2619         if (current_link_up != netif_carrier_ok(tp->dev)) {
2620                 if (current_link_up)
2621                         netif_carrier_on(tp->dev);
2622                 else
2623                         netif_carrier_off(tp->dev);
2624                 tg3_link_report(tp);
2625         } else {
2626                 u32 now_pause_cfg =
2627                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2628                                          TG3_FLAG_TX_PAUSE);
2629                 if (orig_pause_cfg != now_pause_cfg ||
2630                     orig_active_speed != tp->link_config.active_speed ||
2631                     orig_active_duplex != tp->link_config.active_duplex)
2632                         tg3_link_report(tp);
2633         }
2634
2635         return 0;
2636 }
2637
2638 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2639 {
2640         int current_link_up, err = 0;
2641         u32 bmsr, bmcr;
2642         u16 current_speed;
2643         u8 current_duplex;
2644
2645         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2646         tw32_f(MAC_MODE, tp->mac_mode);
2647         udelay(40);
2648
2649         tw32(MAC_EVENT, 0);
2650
2651         tw32_f(MAC_STATUS,
2652              (MAC_STATUS_SYNC_CHANGED |
2653               MAC_STATUS_CFG_CHANGED |
2654               MAC_STATUS_MI_COMPLETION |
2655               MAC_STATUS_LNKSTATE_CHANGED));
2656         udelay(40);
2657
2658         if (force_reset)
2659                 tg3_phy_reset(tp);
2660
2661         current_link_up = 0;
2662         current_speed = SPEED_INVALID;
2663         current_duplex = DUPLEX_INVALID;
2664
2665         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2666         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2667
2668         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2669
2670         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2671             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2672                 /* do nothing, just check for link up at the end */
2673         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2674                 u32 adv, new_adv;
2675
2676                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2677                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2678                                   ADVERTISE_1000XPAUSE |
2679                                   ADVERTISE_1000XPSE_ASYM |
2680                                   ADVERTISE_SLCT);
2681
2682                 /* Always advertise symmetric PAUSE just like copper */
2683                 new_adv |= ADVERTISE_1000XPAUSE;
2684
2685                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2686                         new_adv |= ADVERTISE_1000XHALF;
2687                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2688                         new_adv |= ADVERTISE_1000XFULL;
2689
2690                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2691                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2692                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2693                         tg3_writephy(tp, MII_BMCR, bmcr);
2694
2695                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2696                         tp->tg3_flags2 |= TG3_FLG2_PHY_JUST_INITTED;
2697                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2698
2699                         return err;
2700                 }
2701         } else {
2702                 u32 new_bmcr;
2703
2704                 bmcr &= ~BMCR_SPEED1000;
2705                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2706
2707                 if (tp->link_config.duplex == DUPLEX_FULL)
2708                         new_bmcr |= BMCR_FULLDPLX;
2709
2710                 if (new_bmcr != bmcr) {
2711                         /* BMCR_SPEED1000 is a reserved bit that needs
2712                          * to be set on write.
2713                          */
2714                         new_bmcr |= BMCR_SPEED1000;
2715
2716                         /* Force a linkdown */
2717                         if (netif_carrier_ok(tp->dev)) {
2718                                 u32 adv;
2719
2720                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2721                                 adv &= ~(ADVERTISE_1000XFULL |
2722                                          ADVERTISE_1000XHALF |
2723                                          ADVERTISE_SLCT);
2724                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2725                                 tg3_writephy(tp, MII_BMCR, bmcr |
2726                                                            BMCR_ANRESTART |
2727                                                            BMCR_ANENABLE);
2728                                 udelay(10);
2729                                 netif_carrier_off(tp->dev);
2730                         }
2731                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2732                         bmcr = new_bmcr;
2733                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2734                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2735                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2736                 }
2737         }
2738
2739         if (bmsr & BMSR_LSTATUS) {
2740                 current_speed = SPEED_1000;
2741                 current_link_up = 1;
2742                 if (bmcr & BMCR_FULLDPLX)
2743                         current_duplex = DUPLEX_FULL;
2744                 else
2745                         current_duplex = DUPLEX_HALF;
2746
2747                 if (bmcr & BMCR_ANENABLE) {
2748                         u32 local_adv, remote_adv, common;
2749
2750                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2751                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2752                         common = local_adv & remote_adv;
2753                         if (common & (ADVERTISE_1000XHALF |
2754                                       ADVERTISE_1000XFULL)) {
2755                                 if (common & ADVERTISE_1000XFULL)
2756                                         current_duplex = DUPLEX_FULL;
2757                                 else
2758                                         current_duplex = DUPLEX_HALF;
2759
2760                                 tg3_setup_flow_control(tp, local_adv,
2761                                                        remote_adv);
2762                         }
2763                         else
2764                                 current_link_up = 0;
2765                 }
2766         }
2767
2768         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2769         if (tp->link_config.active_duplex == DUPLEX_HALF)
2770                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2771
2772         tw32_f(MAC_MODE, tp->mac_mode);
2773         udelay(40);
2774
2775         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2776
2777         tp->link_config.active_speed = current_speed;
2778         tp->link_config.active_duplex = current_duplex;
2779
2780         if (current_link_up != netif_carrier_ok(tp->dev)) {
2781                 if (current_link_up)
2782                         netif_carrier_on(tp->dev);
2783                 else {
2784                         netif_carrier_off(tp->dev);
2785                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2786                 }
2787                 tg3_link_report(tp);
2788         }
2789         return err;
2790 }
2791
2792 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2793 {
2794         if (tp->tg3_flags2 & TG3_FLG2_PHY_JUST_INITTED) {
2795                 /* Give autoneg time to complete. */
2796                 tp->tg3_flags2 &= ~TG3_FLG2_PHY_JUST_INITTED;
2797                 return;
2798         }
2799         if (!netif_carrier_ok(tp->dev) &&
2800             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2801                 u32 bmcr;
2802
2803                 tg3_readphy(tp, MII_BMCR, &bmcr);
2804                 if (bmcr & BMCR_ANENABLE) {
2805                         u32 phy1, phy2;
2806
2807                         /* Select shadow register 0x1f */
2808                         tg3_writephy(tp, 0x1c, 0x7c00);
2809                         tg3_readphy(tp, 0x1c, &phy1);
2810
2811                         /* Select expansion interrupt status register */
2812                         tg3_writephy(tp, 0x17, 0x0f01);
2813                         tg3_readphy(tp, 0x15, &phy2);
2814                         tg3_readphy(tp, 0x15, &phy2);
2815
2816                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2817                                 /* We have signal detect and not receiving
2818                                  * config code words, link is up by parallel
2819                                  * detection.
2820                                  */
2821
2822                                 bmcr &= ~BMCR_ANENABLE;
2823                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2824                                 tg3_writephy(tp, MII_BMCR, bmcr);
2825                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2826                         }
2827                 }
2828         }
2829         else if (netif_carrier_ok(tp->dev) &&
2830                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2831                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2832                 u32 phy2;
2833
2834                 /* Select expansion interrupt status register */
2835                 tg3_writephy(tp, 0x17, 0x0f01);
2836                 tg3_readphy(tp, 0x15, &phy2);
2837                 if (phy2 & 0x20) {
2838                         u32 bmcr;
2839
2840                         /* Config code words received, turn on autoneg. */
2841                         tg3_readphy(tp, MII_BMCR, &bmcr);
2842                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2843
2844                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2845
2846                 }
2847         }
2848 }
2849
2850 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2851 {
2852         int err;
2853
2854         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2855                 err = tg3_setup_fiber_phy(tp, force_reset);
2856         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2857                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2858         } else {
2859                 err = tg3_setup_copper_phy(tp, force_reset);
2860         }
2861
2862         if (tp->link_config.active_speed == SPEED_1000 &&
2863             tp->link_config.active_duplex == DUPLEX_HALF)
2864                 tw32(MAC_TX_LENGTHS,
2865                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2866                       (6 << TX_LENGTHS_IPG_SHIFT) |
2867                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2868         else
2869                 tw32(MAC_TX_LENGTHS,
2870                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2871                       (6 << TX_LENGTHS_IPG_SHIFT) |
2872                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2873
2874         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2875                 if (netif_carrier_ok(tp->dev)) {
2876                         tw32(HOSTCC_STAT_COAL_TICKS,
2877                              tp->coal.stats_block_coalesce_usecs);
2878                 } else {
2879                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2880                 }
2881         }
2882
2883         return err;
2884 }
2885
2886 /* Tigon3 never reports partial packet sends.  So we do not
2887  * need special logic to handle SKBs that have not had all
2888  * of their frags sent yet, like SunGEM does.
2889  */
2890 static void tg3_tx(struct tg3 *tp)
2891 {
2892         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
2893         u32 sw_idx = tp->tx_cons;
2894
2895         while (sw_idx != hw_idx) {
2896                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
2897                 struct sk_buff *skb = ri->skb;
2898                 int i;
2899
2900                 if (unlikely(skb == NULL))
2901                         BUG();
2902
2903                 pci_unmap_single(tp->pdev,
2904                                  pci_unmap_addr(ri, mapping),
2905                                  skb_headlen(skb),
2906                                  PCI_DMA_TODEVICE);
2907
2908                 ri->skb = NULL;
2909
2910                 sw_idx = NEXT_TX(sw_idx);
2911
2912                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2913                         if (unlikely(sw_idx == hw_idx))
2914                                 BUG();
2915
2916                         ri = &tp->tx_buffers[sw_idx];
2917                         if (unlikely(ri->skb != NULL))
2918                                 BUG();
2919
2920                         pci_unmap_page(tp->pdev,
2921                                        pci_unmap_addr(ri, mapping),
2922                                        skb_shinfo(skb)->frags[i].size,
2923                                        PCI_DMA_TODEVICE);
2924
2925                         sw_idx = NEXT_TX(sw_idx);
2926                 }
2927
2928                 dev_kfree_skb(skb);
2929         }
2930
2931         tp->tx_cons = sw_idx;
2932
2933         if (unlikely(netif_queue_stopped(tp->dev))) {
2934                 spin_lock(&tp->tx_lock);
2935                 if (netif_queue_stopped(tp->dev) &&
2936                     (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH))
2937                         netif_wake_queue(tp->dev);
2938                 spin_unlock(&tp->tx_lock);
2939         }
2940 }
2941
2942 /* Returns size of skb allocated or < 0 on error.
2943  *
2944  * We only need to fill in the address because the other members
2945  * of the RX descriptor are invariant, see tg3_init_rings.
2946  *
2947  * Note the purposeful assymetry of cpu vs. chip accesses.  For
2948  * posting buffers we only dirty the first cache line of the RX
2949  * descriptor (containing the address).  Whereas for the RX status
2950  * buffers the cpu only reads the last cacheline of the RX descriptor
2951  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
2952  */
2953 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
2954                             int src_idx, u32 dest_idx_unmasked)
2955 {
2956         struct tg3_rx_buffer_desc *desc;
2957         struct ring_info *map, *src_map;
2958         struct sk_buff *skb;
2959         dma_addr_t mapping;
2960         int skb_size, dest_idx;
2961
2962         src_map = NULL;
2963         switch (opaque_key) {
2964         case RXD_OPAQUE_RING_STD:
2965                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
2966                 desc = &tp->rx_std[dest_idx];
2967                 map = &tp->rx_std_buffers[dest_idx];
2968                 if (src_idx >= 0)
2969                         src_map = &tp->rx_std_buffers[src_idx];
2970                 skb_size = tp->rx_pkt_buf_sz;
2971                 break;
2972
2973         case RXD_OPAQUE_RING_JUMBO:
2974                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
2975                 desc = &tp->rx_jumbo[dest_idx];
2976                 map = &tp->rx_jumbo_buffers[dest_idx];
2977                 if (src_idx >= 0)
2978                         src_map = &tp->rx_jumbo_buffers[src_idx];
2979                 skb_size = RX_JUMBO_PKT_BUF_SZ;
2980                 break;
2981
2982         default:
2983                 return -EINVAL;
2984         };
2985
2986         /* Do not overwrite any of the map or rp information
2987          * until we are sure we can commit to a new buffer.
2988          *
2989          * Callers depend upon this behavior and assume that
2990          * we leave everything unchanged if we fail.
2991          */
2992         skb = dev_alloc_skb(skb_size);
2993         if (skb == NULL)
2994                 return -ENOMEM;
2995
2996         skb->dev = tp->dev;
2997         skb_reserve(skb, tp->rx_offset);
2998
2999         mapping = pci_map_single(tp->pdev, skb->data,
3000                                  skb_size - tp->rx_offset,
3001                                  PCI_DMA_FROMDEVICE);
3002
3003         map->skb = skb;
3004         pci_unmap_addr_set(map, mapping, mapping);
3005
3006         if (src_map != NULL)
3007                 src_map->skb = NULL;
3008
3009         desc->addr_hi = ((u64)mapping >> 32);
3010         desc->addr_lo = ((u64)mapping & 0xffffffff);
3011
3012         return skb_size;
3013 }
3014
3015 /* We only need to move over in the address because the other
3016  * members of the RX descriptor are invariant.  See notes above
3017  * tg3_alloc_rx_skb for full details.
3018  */
3019 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3020                            int src_idx, u32 dest_idx_unmasked)
3021 {
3022         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3023         struct ring_info *src_map, *dest_map;
3024         int dest_idx;
3025
3026         switch (opaque_key) {
3027         case RXD_OPAQUE_RING_STD:
3028                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3029                 dest_desc = &tp->rx_std[dest_idx];
3030                 dest_map = &tp->rx_std_buffers[dest_idx];
3031                 src_desc = &tp->rx_std[src_idx];
3032                 src_map = &tp->rx_std_buffers[src_idx];
3033                 break;
3034
3035         case RXD_OPAQUE_RING_JUMBO:
3036                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3037                 dest_desc = &tp->rx_jumbo[dest_idx];
3038                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3039                 src_desc = &tp->rx_jumbo[src_idx];
3040                 src_map = &tp->rx_jumbo_buffers[src_idx];
3041                 break;
3042
3043         default:
3044                 return;
3045         };
3046
3047         dest_map->skb = src_map->skb;
3048         pci_unmap_addr_set(dest_map, mapping,
3049                            pci_unmap_addr(src_map, mapping));
3050         dest_desc->addr_hi = src_desc->addr_hi;
3051         dest_desc->addr_lo = src_desc->addr_lo;
3052
3053         src_map->skb = NULL;
3054 }
3055
3056 #if TG3_VLAN_TAG_USED
3057 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3058 {
3059         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3060 }
3061 #endif
3062
3063 /* The RX ring scheme is composed of multiple rings which post fresh
3064  * buffers to the chip, and one special ring the chip uses to report
3065  * status back to the host.
3066  *
3067  * The special ring reports the status of received packets to the
3068  * host.  The chip does not write into the original descriptor the
3069  * RX buffer was obtained from.  The chip simply takes the original
3070  * descriptor as provided by the host, updates the status and length
3071  * field, then writes this into the next status ring entry.
3072  *
3073  * Each ring the host uses to post buffers to the chip is described
3074  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3075  * it is first placed into the on-chip ram.  When the packet's length
3076  * is known, it walks down the TG3_BDINFO entries to select the ring.
3077  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3078  * which is within the range of the new packet's length is chosen.
3079  *
3080  * The "separate ring for rx status" scheme may sound queer, but it makes
3081  * sense from a cache coherency perspective.  If only the host writes
3082  * to the buffer post rings, and only the chip writes to the rx status
3083  * rings, then cache lines never move beyond shared-modified state.
3084  * If both the host and chip were to write into the same ring, cache line
3085  * eviction could occur since both entities want it in an exclusive state.
3086  */
3087 static int tg3_rx(struct tg3 *tp, int budget)
3088 {
3089         u32 work_mask;
3090         u32 sw_idx = tp->rx_rcb_ptr;
3091         u16 hw_idx;
3092         int received;
3093
3094         hw_idx = tp->hw_status->idx[0].rx_producer;
3095         /*
3096          * We need to order the read of hw_idx and the read of
3097          * the opaque cookie.
3098          */
3099         rmb();
3100         work_mask = 0;
3101         received = 0;
3102         while (sw_idx != hw_idx && budget > 0) {
3103                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3104                 unsigned int len;
3105                 struct sk_buff *skb;
3106                 dma_addr_t dma_addr;
3107                 u32 opaque_key, desc_idx, *post_ptr;
3108
3109                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3110                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3111                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3112                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3113                                                   mapping);
3114                         skb = tp->rx_std_buffers[desc_idx].skb;
3115                         post_ptr = &tp->rx_std_ptr;
3116                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3117                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3118                                                   mapping);
3119                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3120                         post_ptr = &tp->rx_jumbo_ptr;
3121                 }
3122                 else {
3123                         goto next_pkt_nopost;
3124                 }
3125
3126                 work_mask |= opaque_key;
3127
3128                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3129                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3130                 drop_it:
3131                         tg3_recycle_rx(tp, opaque_key,
3132                                        desc_idx, *post_ptr);
3133                 drop_it_no_recycle:
3134                         /* Other statistics kept track of by card. */
3135                         tp->net_stats.rx_dropped++;
3136                         goto next_pkt;
3137                 }
3138
3139                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3140
3141                 if (len > RX_COPY_THRESHOLD
3142                         && tp->rx_offset == 2
3143                         /* rx_offset != 2 iff this is a 5701 card running
3144                          * in PCI-X mode [see tg3_get_invariants()] */
3145                 ) {
3146                         int skb_size;
3147
3148                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3149                                                     desc_idx, *post_ptr);
3150                         if (skb_size < 0)
3151                                 goto drop_it;
3152
3153                         pci_unmap_single(tp->pdev, dma_addr,
3154                                          skb_size - tp->rx_offset,
3155                                          PCI_DMA_FROMDEVICE);
3156
3157                         skb_put(skb, len);
3158                 } else {
3159                         struct sk_buff *copy_skb;
3160
3161                         tg3_recycle_rx(tp, opaque_key,
3162                                        desc_idx, *post_ptr);
3163
3164                         copy_skb = dev_alloc_skb(len + 2);
3165                         if (copy_skb == NULL)
3166                                 goto drop_it_no_recycle;
3167
3168                         copy_skb->dev = tp->dev;
3169                         skb_reserve(copy_skb, 2);
3170                         skb_put(copy_skb, len);
3171                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3172                         memcpy(copy_skb->data, skb->data, len);
3173                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3174
3175                         /* We'll reuse the original ring buffer. */
3176                         skb = copy_skb;
3177                 }
3178
3179                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3180                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3181                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3182                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3183                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3184                 else
3185                         skb->ip_summed = CHECKSUM_NONE;
3186
3187                 skb->protocol = eth_type_trans(skb, tp->dev);
3188 #if TG3_VLAN_TAG_USED
3189                 if (tp->vlgrp != NULL &&
3190                     desc->type_flags & RXD_FLAG_VLAN) {
3191                         tg3_vlan_rx(tp, skb,
3192                                     desc->err_vlan & RXD_VLAN_MASK);
3193                 } else
3194 #endif
3195                         netif_receive_skb(skb);
3196
3197                 tp->dev->last_rx = jiffies;
3198                 received++;
3199                 budget--;
3200
3201 next_pkt:
3202                 (*post_ptr)++;
3203 next_pkt_nopost:
3204                 sw_idx++;
3205                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3206
3207                 /* Refresh hw_idx to see if there is new work */
3208                 if (sw_idx == hw_idx) {
3209                         hw_idx = tp->hw_status->idx[0].rx_producer;
3210                         rmb();
3211                 }
3212         }
3213
3214         /* ACK the status ring. */
3215         tp->rx_rcb_ptr = sw_idx;
3216         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3217
3218         /* Refill RX ring(s). */
3219         if (work_mask & RXD_OPAQUE_RING_STD) {
3220                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3221                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3222                              sw_idx);
3223         }
3224         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3225                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3226                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3227                              sw_idx);
3228         }
3229         mmiowb();
3230
3231         return received;
3232 }
3233
3234 static int tg3_poll(struct net_device *netdev, int *budget)
3235 {
3236         struct tg3 *tp = netdev_priv(netdev);
3237         struct tg3_hw_status *sblk = tp->hw_status;
3238         int done;
3239
3240         /* handle link change and other phy events */
3241         if (!(tp->tg3_flags &
3242               (TG3_FLAG_USE_LINKCHG_REG |
3243                TG3_FLAG_POLL_SERDES))) {
3244                 if (sblk->status & SD_STATUS_LINK_CHG) {
3245                         sblk->status = SD_STATUS_UPDATED |
3246                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3247                         spin_lock(&tp->lock);
3248                         tg3_setup_phy(tp, 0);
3249                         spin_unlock(&tp->lock);
3250                 }
3251         }
3252
3253         /* run TX completion thread */
3254         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3255                 tg3_tx(tp);
3256         }
3257
3258         /* run RX thread, within the bounds set by NAPI.
3259          * All RX "locking" is done by ensuring outside
3260          * code synchronizes with dev->poll()
3261          */
3262         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3263                 int orig_budget = *budget;
3264                 int work_done;
3265
3266                 if (orig_budget > netdev->quota)
3267                         orig_budget = netdev->quota;
3268
3269                 work_done = tg3_rx(tp, orig_budget);
3270
3271                 *budget -= work_done;
3272                 netdev->quota -= work_done;
3273         }
3274
3275         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3276                 tp->last_tag = sblk->status_tag;
3277                 rmb();
3278         } else
3279                 sblk->status &= ~SD_STATUS_UPDATED;
3280
3281         /* if no more work, tell net stack and NIC we're done */
3282         done = !tg3_has_work(tp);
3283         if (done) {
3284                 netif_rx_complete(netdev);
3285                 tg3_restart_ints(tp);
3286         }
3287
3288         return (done ? 0 : 1);
3289 }
3290
3291 static void tg3_irq_quiesce(struct tg3 *tp)
3292 {
3293         BUG_ON(tp->irq_sync);
3294
3295         tp->irq_sync = 1;
3296         smp_mb();
3297
3298         synchronize_irq(tp->pdev->irq);
3299 }
3300
3301 static inline int tg3_irq_sync(struct tg3 *tp)
3302 {
3303         return tp->irq_sync;
3304 }
3305
3306 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3307  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3308  * with as well.  Most of the time, this is not necessary except when
3309  * shutting down the device.
3310  */
3311 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3312 {
3313         if (irq_sync)
3314                 tg3_irq_quiesce(tp);
3315         spin_lock_bh(&tp->lock);
3316         spin_lock(&tp->tx_lock);
3317 }
3318
3319 static inline void tg3_full_unlock(struct tg3 *tp)
3320 {
3321         spin_unlock(&tp->tx_lock);
3322         spin_unlock_bh(&tp->lock);
3323 }
3324
3325 /* MSI ISR - No need to check for interrupt sharing and no need to
3326  * flush status block and interrupt mailbox. PCI ordering rules
3327  * guarantee that MSI will arrive after the status block.
3328  */
3329 static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs)
3330 {
3331         struct net_device *dev = dev_id;
3332         struct tg3 *tp = netdev_priv(dev);
3333
3334         prefetch(tp->hw_status);
3335         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3336         /*
3337          * Writing any value to intr-mbox-0 clears PCI INTA# and
3338          * chip-internal interrupt pending events.
3339          * Writing non-zero to intr-mbox-0 additional tells the
3340          * NIC to stop sending us irqs, engaging "in-intr-handler"
3341          * event coalescing.
3342          */
3343         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3344         if (likely(!tg3_irq_sync(tp)))
3345                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3346
3347         return IRQ_RETVAL(1);
3348 }
3349
3350 static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3351 {
3352         struct net_device *dev = dev_id;
3353         struct tg3 *tp = netdev_priv(dev);
3354         struct tg3_hw_status *sblk = tp->hw_status;
3355         unsigned int handled = 1;
3356
3357         /* In INTx mode, it is possible for the interrupt to arrive at
3358          * the CPU before the status block posted prior to the interrupt.
3359          * Reading the PCI State register will confirm whether the
3360          * interrupt is ours and will flush the status block.
3361          */
3362         if ((sblk->status & SD_STATUS_UPDATED) ||
3363             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3364                 /*
3365                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3366                  * chip-internal interrupt pending events.
3367                  * Writing non-zero to intr-mbox-0 additional tells the
3368                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3369                  * event coalescing.
3370                  */
3371                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3372                              0x00000001);
3373                 if (tg3_irq_sync(tp))
3374                         goto out;
3375                 sblk->status &= ~SD_STATUS_UPDATED;
3376                 if (likely(tg3_has_work(tp))) {
3377                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3378                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3379                 } else {
3380                         /* No work, shared interrupt perhaps?  re-enable
3381                          * interrupts, and flush that PCI write
3382                          */
3383                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3384                                 0x00000000);
3385                 }
3386         } else {        /* shared interrupt */
3387                 handled = 0;
3388         }
3389 out:
3390         return IRQ_RETVAL(handled);
3391 }
3392
3393 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id, struct pt_regs *regs)
3394 {
3395         struct net_device *dev = dev_id;
3396         struct tg3 *tp = netdev_priv(dev);
3397         struct tg3_hw_status *sblk = tp->hw_status;
3398         unsigned int handled = 1;
3399
3400         /* In INTx mode, it is possible for the interrupt to arrive at
3401          * the CPU before the status block posted prior to the interrupt.
3402          * Reading the PCI State register will confirm whether the
3403          * interrupt is ours and will flush the status block.
3404          */
3405         if ((sblk->status_tag != tp->last_tag) ||
3406             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3407                 /*
3408                  * writing any value to intr-mbox-0 clears PCI INTA# and
3409                  * chip-internal interrupt pending events.
3410                  * writing non-zero to intr-mbox-0 additional tells the
3411                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3412                  * event coalescing.
3413                  */
3414                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3415                              0x00000001);
3416                 if (tg3_irq_sync(tp))
3417                         goto out;
3418                 if (netif_rx_schedule_prep(dev)) {
3419                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3420                         /* Update last_tag to mark that this status has been
3421                          * seen. Because interrupt may be shared, we may be
3422                          * racing with tg3_poll(), so only update last_tag
3423                          * if tg3_poll() is not scheduled.
3424                          */
3425                         tp->last_tag = sblk->status_tag;
3426                         __netif_rx_schedule(dev);
3427                 }
3428         } else {        /* shared interrupt */
3429                 handled = 0;
3430         }
3431 out:
3432         return IRQ_RETVAL(handled);
3433 }
3434
3435 /* ISR for interrupt test */
3436 static irqreturn_t tg3_test_isr(int irq, void *dev_id,
3437                 struct pt_regs *regs)
3438 {
3439         struct net_device *dev = dev_id;
3440         struct tg3 *tp = netdev_priv(dev);
3441         struct tg3_hw_status *sblk = tp->hw_status;
3442
3443         if ((sblk->status & SD_STATUS_UPDATED) ||
3444             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3445                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3446                              0x00000001);
3447                 return IRQ_RETVAL(1);
3448         }
3449         return IRQ_RETVAL(0);
3450 }
3451
3452 static int tg3_init_hw(struct tg3 *);
3453 static int tg3_halt(struct tg3 *, int, int);
3454
3455 #ifdef CONFIG_NET_POLL_CONTROLLER
3456 static void tg3_poll_controller(struct net_device *dev)
3457 {
3458         struct tg3 *tp = netdev_priv(dev);
3459
3460         tg3_interrupt(tp->pdev->irq, dev, NULL);
3461 }
3462 #endif
3463
3464 static void tg3_reset_task(void *_data)
3465 {
3466         struct tg3 *tp = _data;
3467         unsigned int restart_timer;
3468
3469         tg3_netif_stop(tp);
3470
3471         tg3_full_lock(tp, 1);
3472
3473         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3474         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3475
3476         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3477         tg3_init_hw(tp);
3478
3479         tg3_netif_start(tp);
3480
3481         tg3_full_unlock(tp);
3482
3483         if (restart_timer)
3484                 mod_timer(&tp->timer, jiffies + 1);
3485 }
3486
3487 static void tg3_tx_timeout(struct net_device *dev)
3488 {
3489         struct tg3 *tp = netdev_priv(dev);
3490
3491         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3492                dev->name);
3493
3494         schedule_work(&tp->reset_task);
3495 }
3496
3497 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3498 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3499 {
3500         u32 base = (u32) mapping & 0xffffffff;
3501
3502         return ((base > 0xffffdcc0) &&
3503                 (base + len + 8 < base));
3504 }
3505
3506 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3507
3508 static int tigon3_4gb_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3509                                        u32 last_plus_one, u32 *start,
3510                                        u32 base_flags, u32 mss)
3511 {
3512         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3513         dma_addr_t new_addr = 0;
3514         u32 entry = *start;
3515         int i, ret = 0;
3516
3517         if (!new_skb) {
3518                 ret = -1;
3519         } else {
3520                 /* New SKB is guaranteed to be linear. */
3521                 entry = *start;
3522                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3523                                           PCI_DMA_TODEVICE);
3524                 /* Make sure new skb does not cross any 4G boundaries.
3525                  * Drop the packet if it does.
3526                  */
3527                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3528                         ret = -1;
3529                         dev_kfree_skb(new_skb);
3530                         new_skb = NULL;
3531                 } else {
3532                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3533                                     base_flags, 1 | (mss << 1));
3534                         *start = NEXT_TX(entry);
3535                 }
3536         }
3537
3538         /* Now clean up the sw ring entries. */
3539         i = 0;
3540         while (entry != last_plus_one) {
3541                 int len;
3542
3543                 if (i == 0)
3544                         len = skb_headlen(skb);
3545                 else
3546                         len = skb_shinfo(skb)->frags[i-1].size;
3547                 pci_unmap_single(tp->pdev,
3548                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3549                                  len, PCI_DMA_TODEVICE);
3550                 if (i == 0) {
3551                         tp->tx_buffers[entry].skb = new_skb;
3552                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3553                 } else {
3554                         tp->tx_buffers[entry].skb = NULL;
3555                 }
3556                 entry = NEXT_TX(entry);
3557                 i++;
3558         }
3559
3560         dev_kfree_skb(skb);
3561
3562         return ret;
3563 }
3564
3565 static void tg3_set_txd(struct tg3 *tp, int entry,
3566                         dma_addr_t mapping, int len, u32 flags,
3567                         u32 mss_and_is_end)
3568 {
3569         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3570         int is_end = (mss_and_is_end & 0x1);
3571         u32 mss = (mss_and_is_end >> 1);
3572         u32 vlan_tag = 0;
3573
3574         if (is_end)
3575                 flags |= TXD_FLAG_END;
3576         if (flags & TXD_FLAG_VLAN) {
3577                 vlan_tag = flags >> 16;
3578                 flags &= 0xffff;
3579         }
3580         vlan_tag |= (mss << TXD_MSS_SHIFT);
3581
3582         txd->addr_hi = ((u64) mapping >> 32);
3583         txd->addr_lo = ((u64) mapping & 0xffffffff);
3584         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3585         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3586 }
3587
3588 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3589 {
3590         struct tg3 *tp = netdev_priv(dev);
3591         dma_addr_t mapping;
3592         u32 len, entry, base_flags, mss;
3593         int would_hit_hwbug;
3594
3595         len = skb_headlen(skb);
3596
3597         /* No BH disabling for tx_lock here.  We are running in BH disabled
3598          * context and TX reclaim runs via tp->poll inside of a software
3599          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3600          * no IRQ context deadlocks to worry about either.  Rejoice!
3601          */
3602         if (!spin_trylock(&tp->tx_lock))
3603                 return NETDEV_TX_LOCKED;
3604
3605         if (unlikely(TX_BUFFS_AVAIL(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3606                 if (!netif_queue_stopped(dev)) {
3607                         netif_stop_queue(dev);
3608
3609                         /* This is a hard error, log it. */
3610                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3611                                "queue awake!\n", dev->name);
3612                 }
3613                 spin_unlock(&tp->tx_lock);
3614                 return NETDEV_TX_BUSY;
3615         }
3616
3617         entry = tp->tx_prod;
3618         base_flags = 0;
3619         if (skb->ip_summed == CHECKSUM_HW)
3620                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3621 #if TG3_TSO_SUPPORT != 0
3622         mss = 0;
3623         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3624             (mss = skb_shinfo(skb)->tso_size) != 0) {
3625                 int tcp_opt_len, ip_tcp_len;
3626
3627                 if (skb_header_cloned(skb) &&
3628                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3629                         dev_kfree_skb(skb);
3630                         goto out_unlock;
3631                 }
3632
3633                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3634                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
3635
3636                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3637                                TXD_FLAG_CPU_POST_DMA);
3638
3639                 skb->nh.iph->check = 0;
3640                 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
3641                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
3642                         skb->h.th->check = 0;
3643                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
3644                 }
3645                 else {
3646                         skb->h.th->check =
3647                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
3648                                                    skb->nh.iph->daddr,
3649                                                    0, IPPROTO_TCP, 0);
3650                 }
3651
3652                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
3653                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
3654                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3655                                 int tsflags;
3656
3657                                 tsflags = ((skb->nh.iph->ihl - 5) +
3658                                            (tcp_opt_len >> 2));
3659                                 mss |= (tsflags << 11);
3660                         }
3661                 } else {
3662                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
3663                                 int tsflags;
3664
3665                                 tsflags = ((skb->nh.iph->ihl - 5) +
3666                                            (tcp_opt_len >> 2));
3667                                 base_flags |= tsflags << 12;
3668                         }
3669                 }
3670         }
3671 #else
3672         mss = 0;
3673 #endif
3674 #if TG3_VLAN_TAG_USED
3675         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3676                 base_flags |= (TXD_FLAG_VLAN |
3677                                (vlan_tx_tag_get(skb) << 16));
3678 #endif
3679
3680         /* Queue skb data, a.k.a. the main skb fragment. */
3681         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3682
3683         tp->tx_buffers[entry].skb = skb;
3684         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3685
3686         would_hit_hwbug = 0;
3687
3688         if (tg3_4g_overflow_test(mapping, len))
3689                 would_hit_hwbug = 1;
3690
3691         tg3_set_txd(tp, entry, mapping, len, base_flags,
3692                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3693
3694         entry = NEXT_TX(entry);
3695
3696         /* Now loop through additional data fragments, and queue them. */
3697         if (skb_shinfo(skb)->nr_frags > 0) {
3698                 unsigned int i, last;
3699
3700                 last = skb_shinfo(skb)->nr_frags - 1;
3701                 for (i = 0; i <= last; i++) {
3702                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3703
3704                         len = frag->size;
3705                         mapping = pci_map_page(tp->pdev,
3706                                                frag->page,
3707                                                frag->page_offset,
3708                                                len, PCI_DMA_TODEVICE);
3709
3710                         tp->tx_buffers[entry].skb = NULL;
3711                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3712
3713                         if (tg3_4g_overflow_test(mapping, len))
3714                                 would_hit_hwbug = 1;
3715
3716                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
3717                                 tg3_set_txd(tp, entry, mapping, len,
3718                                             base_flags, (i == last)|(mss << 1));
3719                         else
3720                                 tg3_set_txd(tp, entry, mapping, len,
3721                                             base_flags, (i == last));
3722
3723                         entry = NEXT_TX(entry);
3724                 }
3725         }
3726
3727         if (would_hit_hwbug) {
3728                 u32 last_plus_one = entry;
3729                 u32 start;
3730
3731                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
3732                 start &= (TG3_TX_RING_SIZE - 1);
3733
3734                 /* If the workaround fails due to memory/mapping
3735                  * failure, silently drop this packet.
3736                  */
3737                 if (tigon3_4gb_hwbug_workaround(tp, skb, last_plus_one,
3738                                                 &start, base_flags, mss))
3739                         goto out_unlock;
3740
3741                 entry = start;
3742         }
3743
3744         /* Packets are ready, update Tx producer idx local and on card. */
3745         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3746
3747         tp->tx_prod = entry;
3748         if (TX_BUFFS_AVAIL(tp) <= (MAX_SKB_FRAGS + 1)) {
3749                 netif_stop_queue(dev);
3750                 if (TX_BUFFS_AVAIL(tp) > TG3_TX_WAKEUP_THRESH)
3751                         netif_wake_queue(tp->dev);
3752         }
3753
3754 out_unlock:
3755         mmiowb();
3756         spin_unlock(&tp->tx_lock);
3757
3758         dev->trans_start = jiffies;
3759
3760         return NETDEV_TX_OK;
3761 }
3762
3763 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
3764                                int new_mtu)
3765 {
3766         dev->mtu = new_mtu;
3767
3768         if (new_mtu > ETH_DATA_LEN) {
3769                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
3770                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
3771                         ethtool_op_set_tso(dev, 0);
3772                 }
3773                 else
3774                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
3775         } else {
3776                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
3777                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
3778                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
3779         }
3780 }
3781
3782 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
3783 {
3784         struct tg3 *tp = netdev_priv(dev);
3785
3786         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
3787                 return -EINVAL;
3788
3789         if (!netif_running(dev)) {
3790                 /* We'll just catch it later when the
3791                  * device is up'd.
3792                  */
3793                 tg3_set_mtu(dev, tp, new_mtu);
3794                 return 0;
3795         }
3796
3797         tg3_netif_stop(tp);
3798
3799         tg3_full_lock(tp, 1);
3800
3801         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3802
3803         tg3_set_mtu(dev, tp, new_mtu);
3804
3805         tg3_init_hw(tp);
3806
3807         tg3_netif_start(tp);
3808
3809         tg3_full_unlock(tp);
3810
3811         return 0;
3812 }
3813
3814 /* Free up pending packets in all rx/tx rings.
3815  *
3816  * The chip has been shut down and the driver detached from
3817  * the networking, so no interrupts or new tx packets will
3818  * end up in the driver.  tp->{tx,}lock is not held and we are not
3819  * in an interrupt context and thus may sleep.
3820  */
3821 static void tg3_free_rings(struct tg3 *tp)
3822 {
3823         struct ring_info *rxp;
3824         int i;
3825
3826         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3827                 rxp = &tp->rx_std_buffers[i];
3828
3829                 if (rxp->skb == NULL)
3830                         continue;
3831                 pci_unmap_single(tp->pdev,
3832                                  pci_unmap_addr(rxp, mapping),
3833                                  tp->rx_pkt_buf_sz - tp->rx_offset,
3834                                  PCI_DMA_FROMDEVICE);
3835                 dev_kfree_skb_any(rxp->skb);
3836                 rxp->skb = NULL;
3837         }
3838
3839         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3840                 rxp = &tp->rx_jumbo_buffers[i];
3841
3842                 if (rxp->skb == NULL)
3843                         continue;
3844                 pci_unmap_single(tp->pdev,
3845                                  pci_unmap_addr(rxp, mapping),
3846                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
3847                                  PCI_DMA_FROMDEVICE);
3848                 dev_kfree_skb_any(rxp->skb);
3849                 rxp->skb = NULL;
3850         }
3851
3852         for (i = 0; i < TG3_TX_RING_SIZE; ) {
3853                 struct tx_ring_info *txp;
3854                 struct sk_buff *skb;
3855                 int j;
3856
3857                 txp = &tp->tx_buffers[i];
3858                 skb = txp->skb;
3859
3860                 if (skb == NULL) {
3861                         i++;
3862                         continue;
3863                 }
3864
3865                 pci_unmap_single(tp->pdev,
3866                                  pci_unmap_addr(txp, mapping),
3867                                  skb_headlen(skb),
3868                                  PCI_DMA_TODEVICE);
3869                 txp->skb = NULL;
3870
3871                 i++;
3872
3873                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
3874                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
3875                         pci_unmap_page(tp->pdev,
3876                                        pci_unmap_addr(txp, mapping),
3877                                        skb_shinfo(skb)->frags[j].size,
3878                                        PCI_DMA_TODEVICE);
3879                         i++;
3880                 }
3881
3882                 dev_kfree_skb_any(skb);
3883         }
3884 }
3885
3886 /* Initialize tx/rx rings for packet processing.
3887  *
3888  * The chip has been shut down and the driver detached from
3889  * the networking, so no interrupts or new tx packets will
3890  * end up in the driver.  tp->{tx,}lock are held and thus
3891  * we may not sleep.
3892  */
3893 static void tg3_init_rings(struct tg3 *tp)
3894 {
3895         u32 i;
3896
3897         /* Free up all the SKBs. */
3898         tg3_free_rings(tp);
3899
3900         /* Zero out all descriptors. */
3901         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
3902         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
3903         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
3904         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
3905
3906         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
3907         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
3908             (tp->dev->mtu > ETH_DATA_LEN))
3909                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
3910
3911         /* Initialize invariants of the rings, we only set this
3912          * stuff once.  This works because the card does not
3913          * write into the rx buffer posting rings.
3914          */
3915         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
3916                 struct tg3_rx_buffer_desc *rxd;
3917
3918                 rxd = &tp->rx_std[i];
3919                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
3920                         << RXD_LEN_SHIFT;
3921                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
3922                 rxd->opaque = (RXD_OPAQUE_RING_STD |
3923                                (i << RXD_OPAQUE_INDEX_SHIFT));
3924         }
3925
3926         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3927                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
3928                         struct tg3_rx_buffer_desc *rxd;
3929
3930                         rxd = &tp->rx_jumbo[i];
3931                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
3932                                 << RXD_LEN_SHIFT;
3933                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
3934                                 RXD_FLAG_JUMBO;
3935                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
3936                                (i << RXD_OPAQUE_INDEX_SHIFT));
3937                 }
3938         }
3939
3940         /* Now allocate fresh SKBs for each rx ring. */
3941         for (i = 0; i < tp->rx_pending; i++) {
3942                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD,
3943                                      -1, i) < 0)
3944                         break;
3945         }
3946
3947         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
3948                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
3949                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
3950                                              -1, i) < 0)
3951                                 break;
3952                 }
3953         }
3954 }
3955
3956 /*
3957  * Must not be invoked with interrupt sources disabled and
3958  * the hardware shutdown down.
3959  */
3960 static void tg3_free_consistent(struct tg3 *tp)
3961 {
3962         kfree(tp->rx_std_buffers);
3963         tp->rx_std_buffers = NULL;
3964         if (tp->rx_std) {
3965                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
3966                                     tp->rx_std, tp->rx_std_mapping);
3967                 tp->rx_std = NULL;
3968         }
3969         if (tp->rx_jumbo) {
3970                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
3971                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
3972                 tp->rx_jumbo = NULL;
3973         }
3974         if (tp->rx_rcb) {
3975                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
3976                                     tp->rx_rcb, tp->rx_rcb_mapping);
3977                 tp->rx_rcb = NULL;
3978         }
3979         if (tp->tx_ring) {
3980                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
3981                         tp->tx_ring, tp->tx_desc_mapping);
3982                 tp->tx_ring = NULL;
3983         }
3984         if (tp->hw_status) {
3985                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
3986                                     tp->hw_status, tp->status_mapping);
3987                 tp->hw_status = NULL;
3988         }
3989         if (tp->hw_stats) {
3990                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
3991                                     tp->hw_stats, tp->stats_mapping);
3992                 tp->hw_stats = NULL;
3993         }
3994 }
3995
3996 /*
3997  * Must not be invoked with interrupt sources disabled and
3998  * the hardware shutdown down.  Can sleep.
3999  */
4000 static int tg3_alloc_consistent(struct tg3 *tp)
4001 {
4002         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4003                                       (TG3_RX_RING_SIZE +
4004                                        TG3_RX_JUMBO_RING_SIZE)) +
4005                                      (sizeof(struct tx_ring_info) *
4006                                       TG3_TX_RING_SIZE),
4007                                      GFP_KERNEL);
4008         if (!tp->rx_std_buffers)
4009                 return -ENOMEM;
4010
4011         memset(tp->rx_std_buffers, 0,
4012                (sizeof(struct ring_info) *
4013                 (TG3_RX_RING_SIZE +
4014                  TG3_RX_JUMBO_RING_SIZE)) +
4015                (sizeof(struct tx_ring_info) *
4016                 TG3_TX_RING_SIZE));
4017
4018         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4019         tp->tx_buffers = (struct tx_ring_info *)
4020                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4021
4022         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4023                                           &tp->rx_std_mapping);
4024         if (!tp->rx_std)
4025                 goto err_out;
4026
4027         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4028                                             &tp->rx_jumbo_mapping);
4029
4030         if (!tp->rx_jumbo)
4031                 goto err_out;
4032
4033         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4034                                           &tp->rx_rcb_mapping);
4035         if (!tp->rx_rcb)
4036                 goto err_out;
4037
4038         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4039                                            &tp->tx_desc_mapping);
4040         if (!tp->tx_ring)
4041                 goto err_out;
4042
4043         tp->hw_status = pci_alloc_consistent(tp->pdev,
4044                                              TG3_HW_STATUS_SIZE,
4045                                              &tp->status_mapping);
4046         if (!tp->hw_status)
4047                 goto err_out;
4048
4049         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4050                                             sizeof(struct tg3_hw_stats),
4051                                             &tp->stats_mapping);
4052         if (!tp->hw_stats)
4053                 goto err_out;
4054
4055         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4056         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4057
4058         return 0;
4059
4060 err_out:
4061         tg3_free_consistent(tp);
4062         return -ENOMEM;
4063 }
4064
4065 #define MAX_WAIT_CNT 1000
4066
4067 /* To stop a block, clear the enable bit and poll till it
4068  * clears.  tp->lock is held.
4069  */
4070 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4071 {
4072         unsigned int i;
4073         u32 val;
4074
4075         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4076                 switch (ofs) {
4077                 case RCVLSC_MODE:
4078                 case DMAC_MODE:
4079                 case MBFREE_MODE:
4080                 case BUFMGR_MODE:
4081                 case MEMARB_MODE:
4082                         /* We can't enable/disable these bits of the
4083                          * 5705/5750, just say success.
4084                          */
4085                         return 0;
4086
4087                 default:
4088                         break;
4089                 };
4090         }
4091
4092         val = tr32(ofs);
4093         val &= ~enable_bit;
4094         tw32_f(ofs, val);
4095
4096         for (i = 0; i < MAX_WAIT_CNT; i++) {
4097                 udelay(100);
4098                 val = tr32(ofs);
4099                 if ((val & enable_bit) == 0)
4100                         break;
4101         }
4102
4103         if (i == MAX_WAIT_CNT && !silent) {
4104                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4105                        "ofs=%lx enable_bit=%x\n",
4106                        ofs, enable_bit);
4107                 return -ENODEV;
4108         }
4109
4110         return 0;
4111 }
4112
4113 /* tp->lock is held. */
4114 static int tg3_abort_hw(struct tg3 *tp, int silent)
4115 {
4116         int i, err;
4117
4118         tg3_disable_ints(tp);
4119
4120         tp->rx_mode &= ~RX_MODE_ENABLE;
4121         tw32_f(MAC_RX_MODE, tp->rx_mode);
4122         udelay(10);
4123
4124         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4125         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4126         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4127         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4128         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4129         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4130
4131         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4132         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4133         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4134         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4135         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4136         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4137         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4138
4139         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4140         tw32_f(MAC_MODE, tp->mac_mode);
4141         udelay(40);
4142
4143         tp->tx_mode &= ~TX_MODE_ENABLE;
4144         tw32_f(MAC_TX_MODE, tp->tx_mode);
4145
4146         for (i = 0; i < MAX_WAIT_CNT; i++) {
4147                 udelay(100);
4148                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4149                         break;
4150         }
4151         if (i >= MAX_WAIT_CNT) {
4152                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4153                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4154                        tp->dev->name, tr32(MAC_TX_MODE));
4155                 err |= -ENODEV;
4156         }
4157
4158         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4159         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4160         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4161
4162         tw32(FTQ_RESET, 0xffffffff);
4163         tw32(FTQ_RESET, 0x00000000);
4164
4165         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4166         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4167
4168         if (tp->hw_status)
4169                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4170         if (tp->hw_stats)
4171                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4172
4173         return err;
4174 }
4175
4176 /* tp->lock is held. */
4177 static int tg3_nvram_lock(struct tg3 *tp)
4178 {
4179         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4180                 int i;
4181
4182                 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4183                 for (i = 0; i < 8000; i++) {
4184                         if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4185                                 break;
4186                         udelay(20);
4187                 }
4188                 if (i == 8000)
4189                         return -ENODEV;
4190         }
4191         return 0;
4192 }
4193
4194 /* tp->lock is held. */
4195 static void tg3_nvram_unlock(struct tg3 *tp)
4196 {
4197         if (tp->tg3_flags & TG3_FLAG_NVRAM)
4198                 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4199 }
4200
4201 /* tp->lock is held. */
4202 static void tg3_enable_nvram_access(struct tg3 *tp)
4203 {
4204         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4205             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4206                 u32 nvaccess = tr32(NVRAM_ACCESS);
4207
4208                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4209         }
4210 }
4211
4212 /* tp->lock is held. */
4213 static void tg3_disable_nvram_access(struct tg3 *tp)
4214 {
4215         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4216             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4217                 u32 nvaccess = tr32(NVRAM_ACCESS);
4218
4219                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4220         }
4221 }
4222
4223 /* tp->lock is held. */
4224 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4225 {
4226         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4227                 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4228                               NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4229
4230         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4231                 switch (kind) {
4232                 case RESET_KIND_INIT:
4233                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4234                                       DRV_STATE_START);
4235                         break;
4236
4237                 case RESET_KIND_SHUTDOWN:
4238                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4239                                       DRV_STATE_UNLOAD);
4240                         break;
4241
4242                 case RESET_KIND_SUSPEND:
4243                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4244                                       DRV_STATE_SUSPEND);
4245                         break;
4246
4247                 default:
4248                         break;
4249                 };
4250         }
4251 }
4252
4253 /* tp->lock is held. */
4254 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4255 {
4256         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4257                 switch (kind) {
4258                 case RESET_KIND_INIT:
4259                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4260                                       DRV_STATE_START_DONE);
4261                         break;
4262
4263                 case RESET_KIND_SHUTDOWN:
4264                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4265                                       DRV_STATE_UNLOAD_DONE);
4266                         break;
4267
4268                 default:
4269                         break;
4270                 };
4271         }
4272 }
4273
4274 /* tp->lock is held. */
4275 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4276 {
4277         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4278                 switch (kind) {
4279                 case RESET_KIND_INIT:
4280                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4281                                       DRV_STATE_START);
4282                         break;
4283
4284                 case RESET_KIND_SHUTDOWN:
4285                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4286                                       DRV_STATE_UNLOAD);
4287                         break;
4288
4289                 case RESET_KIND_SUSPEND:
4290                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4291                                       DRV_STATE_SUSPEND);
4292                         break;
4293
4294                 default:
4295                         break;
4296                 };
4297         }
4298 }
4299
4300 static void tg3_stop_fw(struct tg3 *);
4301
4302 /* tp->lock is held. */
4303 static int tg3_chip_reset(struct tg3 *tp)
4304 {
4305         u32 val;
4306         void (*write_op)(struct tg3 *, u32, u32);
4307         int i;
4308
4309         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X))
4310                 tg3_nvram_lock(tp);
4311
4312         /*
4313          * We must avoid the readl() that normally takes place.
4314          * It locks machines, causes machine checks, and other
4315          * fun things.  So, temporarily disable the 5701
4316          * hardware workaround, while we do the reset.
4317          */
4318         write_op = tp->write32;
4319         if (write_op == tg3_write_flush_reg32)
4320                 tp->write32 = tg3_write32;
4321
4322         /* do the reset */
4323         val = GRC_MISC_CFG_CORECLK_RESET;
4324
4325         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4326                 if (tr32(0x7e2c) == 0x60) {
4327                         tw32(0x7e2c, 0x20);
4328                 }
4329                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4330                         tw32(GRC_MISC_CFG, (1 << 29));
4331                         val |= (1 << 29);
4332                 }
4333         }
4334
4335         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4336                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4337         tw32(GRC_MISC_CFG, val);
4338
4339         /* restore 5701 hardware bug workaround write method */
4340         tp->write32 = write_op;
4341
4342         /* Unfortunately, we have to delay before the PCI read back.
4343          * Some 575X chips even will not respond to a PCI cfg access
4344          * when the reset command is given to the chip.
4345          *
4346          * How do these hardware designers expect things to work
4347          * properly if the PCI write is posted for a long period
4348          * of time?  It is always necessary to have some method by
4349          * which a register read back can occur to push the write
4350          * out which does the reset.
4351          *
4352          * For most tg3 variants the trick below was working.
4353          * Ho hum...
4354          */
4355         udelay(120);
4356
4357         /* Flush PCI posted writes.  The normal MMIO registers
4358          * are inaccessible at this time so this is the only
4359          * way to make this reliably (actually, this is no longer
4360          * the case, see above).  I tried to use indirect
4361          * register read/write but this upset some 5701 variants.
4362          */
4363         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4364
4365         udelay(120);
4366
4367         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4368                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4369                         int i;
4370                         u32 cfg_val;
4371
4372                         /* Wait for link training to complete.  */
4373                         for (i = 0; i < 5000; i++)
4374                                 udelay(100);
4375
4376                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4377                         pci_write_config_dword(tp->pdev, 0xc4,
4378                                                cfg_val | (1 << 15));
4379                 }
4380                 /* Set PCIE max payload size and clear error status.  */
4381                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4382         }
4383
4384         /* Re-enable indirect register accesses. */
4385         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4386                                tp->misc_host_ctrl);
4387
4388         /* Set MAX PCI retry to zero. */
4389         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4390         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4391             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4392                 val |= PCISTATE_RETRY_SAME_DMA;
4393         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4394
4395         pci_restore_state(tp->pdev);
4396
4397         /* Make sure PCI-X relaxed ordering bit is clear. */
4398         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4399         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4400         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4401
4402         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4403                 u32 val;
4404
4405                 /* Chip reset on 5780 will reset MSI enable bit,
4406                  * so need to restore it.
4407                  */
4408                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4409                         u16 ctrl;
4410
4411                         pci_read_config_word(tp->pdev,
4412                                              tp->msi_cap + PCI_MSI_FLAGS,
4413                                              &ctrl);
4414                         pci_write_config_word(tp->pdev,
4415                                               tp->msi_cap + PCI_MSI_FLAGS,
4416                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4417                         val = tr32(MSGINT_MODE);
4418                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4419                 }
4420
4421                 val = tr32(MEMARB_MODE);
4422                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4423
4424         } else
4425                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4426
4427         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4428                 tg3_stop_fw(tp);
4429                 tw32(0x5000, 0x400);
4430         }
4431
4432         tw32(GRC_MODE, tp->grc_mode);
4433
4434         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4435                 u32 val = tr32(0xc4);
4436
4437                 tw32(0xc4, val | (1 << 15));
4438         }
4439
4440         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4441             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4442                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4443                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4444                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4445                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4446         }
4447
4448         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4449                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4450                 tw32_f(MAC_MODE, tp->mac_mode);
4451         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4452                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4453                 tw32_f(MAC_MODE, tp->mac_mode);
4454         } else
4455                 tw32_f(MAC_MODE, 0);
4456         udelay(40);
4457
4458         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_570X)) {
4459                 /* Wait for firmware initialization to complete. */
4460                 for (i = 0; i < 100000; i++) {
4461                         tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4462                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4463                                 break;
4464                         udelay(10);
4465                 }
4466                 if (i >= 100000) {
4467                         printk(KERN_ERR PFX "tg3_reset_hw timed out for %s, "
4468                                "firmware will not restart magic=%08x\n",
4469                                tp->dev->name, val);
4470                         return -ENODEV;
4471                 }
4472         }
4473
4474         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4475             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4476                 u32 val = tr32(0x7c00);
4477
4478                 tw32(0x7c00, val | (1 << 25));
4479         }
4480
4481         /* Reprobe ASF enable state.  */
4482         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4483         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4484         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4485         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4486                 u32 nic_cfg;
4487
4488                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4489                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4490                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4491                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4492                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4493                 }
4494         }
4495
4496         return 0;
4497 }
4498
4499 /* tp->lock is held. */
4500 static void tg3_stop_fw(struct tg3 *tp)
4501 {
4502         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4503                 u32 val;
4504                 int i;
4505
4506                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4507                 val = tr32(GRC_RX_CPU_EVENT);
4508                 val |= (1 << 14);
4509                 tw32(GRC_RX_CPU_EVENT, val);
4510
4511                 /* Wait for RX cpu to ACK the event.  */
4512                 for (i = 0; i < 100; i++) {
4513                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4514                                 break;
4515                         udelay(1);
4516                 }
4517         }
4518 }
4519
4520 /* tp->lock is held. */
4521 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4522 {
4523         int err;
4524
4525         tg3_stop_fw(tp);
4526
4527         tg3_write_sig_pre_reset(tp, kind);
4528
4529         tg3_abort_hw(tp, silent);
4530         err = tg3_chip_reset(tp);
4531
4532         tg3_write_sig_legacy(tp, kind);
4533         tg3_write_sig_post_reset(tp, kind);
4534
4535         if (err)
4536                 return err;
4537
4538         return 0;
4539 }
4540
4541 #define TG3_FW_RELEASE_MAJOR    0x0
4542 #define TG3_FW_RELASE_MINOR     0x0
4543 #define TG3_FW_RELEASE_FIX      0x0
4544 #define TG3_FW_START_ADDR       0x08000000
4545 #define TG3_FW_TEXT_ADDR        0x08000000
4546 #define TG3_FW_TEXT_LEN         0x9c0
4547 #define TG3_FW_RODATA_ADDR      0x080009c0
4548 #define TG3_FW_RODATA_LEN       0x60
4549 #define TG3_FW_DATA_ADDR        0x08000a40
4550 #define TG3_FW_DATA_LEN         0x20
4551 #define TG3_FW_SBSS_ADDR        0x08000a60
4552 #define TG3_FW_SBSS_LEN         0xc
4553 #define TG3_FW_BSS_ADDR         0x08000a70
4554 #define TG3_FW_BSS_LEN          0x10
4555
4556 static u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
4557         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
4558         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
4559         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
4560         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
4561         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
4562         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
4563         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
4564         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
4565         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
4566         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
4567         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
4568         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
4569         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
4570         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
4571         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
4572         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
4573         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
4574         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
4575         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
4576         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
4577         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
4578         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
4579         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
4580         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4581         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4582         0, 0, 0, 0, 0, 0,
4583         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
4584         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4585         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4586         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4587         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
4588         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
4589         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
4590         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
4591         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4592         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
4593         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
4594         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4595         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4596         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4597         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
4598         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
4599         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
4600         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
4601         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
4602         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
4603         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
4604         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
4605         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
4606         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
4607         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
4608         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
4609         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
4610         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
4611         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
4612         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
4613         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
4614         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
4615         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
4616         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
4617         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
4618         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
4619         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
4620         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
4621         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
4622         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
4623         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
4624         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
4625         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
4626         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
4627         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
4628         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
4629         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
4630         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
4631         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
4632         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
4633         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
4634         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
4635         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
4636         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
4637         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
4638         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
4639         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
4640         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
4641         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
4642         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
4643         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
4644         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
4645         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
4646         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
4647         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
4648 };
4649
4650 static u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
4651         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
4652         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
4653         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
4654         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
4655         0x00000000
4656 };
4657
4658 #if 0 /* All zeros, don't eat up space with it. */
4659 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
4660         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
4661         0x00000000, 0x00000000, 0x00000000, 0x00000000
4662 };
4663 #endif
4664
4665 #define RX_CPU_SCRATCH_BASE     0x30000
4666 #define RX_CPU_SCRATCH_SIZE     0x04000
4667 #define TX_CPU_SCRATCH_BASE     0x34000
4668 #define TX_CPU_SCRATCH_SIZE     0x04000
4669
4670 /* tp->lock is held. */
4671 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
4672 {
4673         int i;
4674
4675         if (offset == TX_CPU_BASE &&
4676             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
4677                 BUG();
4678
4679         if (offset == RX_CPU_BASE) {
4680                 for (i = 0; i < 10000; i++) {
4681                         tw32(offset + CPU_STATE, 0xffffffff);
4682                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4683                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4684                                 break;
4685                 }
4686
4687                 tw32(offset + CPU_STATE, 0xffffffff);
4688                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
4689                 udelay(10);
4690         } else {
4691                 for (i = 0; i < 10000; i++) {
4692                         tw32(offset + CPU_STATE, 0xffffffff);
4693                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
4694                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
4695                                 break;
4696                 }
4697         }
4698
4699         if (i >= 10000) {
4700                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
4701                        "and %s CPU\n",
4702                        tp->dev->name,
4703                        (offset == RX_CPU_BASE ? "RX" : "TX"));
4704                 return -ENODEV;
4705         }
4706         return 0;
4707 }
4708
4709 struct fw_info {
4710         unsigned int text_base;
4711         unsigned int text_len;
4712         u32 *text_data;
4713         unsigned int rodata_base;
4714         unsigned int rodata_len;
4715         u32 *rodata_data;
4716         unsigned int data_base;
4717         unsigned int data_len;
4718         u32 *data_data;
4719 };
4720
4721 /* tp->lock is held. */
4722 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
4723                                  int cpu_scratch_size, struct fw_info *info)
4724 {
4725         int err, i;
4726         void (*write_op)(struct tg3 *, u32, u32);
4727
4728         if (cpu_base == TX_CPU_BASE &&
4729             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4730                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
4731                        "TX cpu firmware on %s which is 5705.\n",
4732                        tp->dev->name);
4733                 return -EINVAL;
4734         }
4735
4736         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4737                 write_op = tg3_write_mem;
4738         else
4739                 write_op = tg3_write_indirect_reg32;
4740
4741         /* It is possible that bootcode is still loading at this point.
4742          * Get the nvram lock first before halting the cpu.
4743          */
4744         tg3_nvram_lock(tp);
4745         err = tg3_halt_cpu(tp, cpu_base);
4746         tg3_nvram_unlock(tp);
4747         if (err)
4748                 goto out;
4749
4750         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
4751                 write_op(tp, cpu_scratch_base + i, 0);
4752         tw32(cpu_base + CPU_STATE, 0xffffffff);
4753         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
4754         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
4755                 write_op(tp, (cpu_scratch_base +
4756                               (info->text_base & 0xffff) +
4757                               (i * sizeof(u32))),
4758                          (info->text_data ?
4759                           info->text_data[i] : 0));
4760         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
4761                 write_op(tp, (cpu_scratch_base +
4762                               (info->rodata_base & 0xffff) +
4763                               (i * sizeof(u32))),
4764                          (info->rodata_data ?
4765                           info->rodata_data[i] : 0));
4766         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
4767                 write_op(tp, (cpu_scratch_base +
4768                               (info->data_base & 0xffff) +
4769                               (i * sizeof(u32))),
4770                          (info->data_data ?
4771                           info->data_data[i] : 0));
4772
4773         err = 0;
4774
4775 out:
4776         return err;
4777 }
4778
4779 /* tp->lock is held. */
4780 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
4781 {
4782         struct fw_info info;
4783         int err, i;
4784
4785         info.text_base = TG3_FW_TEXT_ADDR;
4786         info.text_len = TG3_FW_TEXT_LEN;
4787         info.text_data = &tg3FwText[0];
4788         info.rodata_base = TG3_FW_RODATA_ADDR;
4789         info.rodata_len = TG3_FW_RODATA_LEN;
4790         info.rodata_data = &tg3FwRodata[0];
4791         info.data_base = TG3_FW_DATA_ADDR;
4792         info.data_len = TG3_FW_DATA_LEN;
4793         info.data_data = NULL;
4794
4795         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
4796                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
4797                                     &info);
4798         if (err)
4799                 return err;
4800
4801         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
4802                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
4803                                     &info);
4804         if (err)
4805                 return err;
4806
4807         /* Now startup only the RX cpu. */
4808         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4809         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4810
4811         for (i = 0; i < 5; i++) {
4812                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
4813                         break;
4814                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4815                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
4816                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
4817                 udelay(1000);
4818         }
4819         if (i >= 5) {
4820                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
4821                        "to set RX CPU PC, is %08x should be %08x\n",
4822                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
4823                        TG3_FW_TEXT_ADDR);
4824                 return -ENODEV;
4825         }
4826         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
4827         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
4828
4829         return 0;
4830 }
4831
4832 #if TG3_TSO_SUPPORT != 0
4833
4834 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
4835 #define TG3_TSO_FW_RELASE_MINOR         0x6
4836 #define TG3_TSO_FW_RELEASE_FIX          0x0
4837 #define TG3_TSO_FW_START_ADDR           0x08000000
4838 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
4839 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
4840 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
4841 #define TG3_TSO_FW_RODATA_LEN           0x60
4842 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
4843 #define TG3_TSO_FW_DATA_LEN             0x30
4844 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
4845 #define TG3_TSO_FW_SBSS_LEN             0x2c
4846 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
4847 #define TG3_TSO_FW_BSS_LEN              0x894
4848
4849 static u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
4850         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
4851         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
4852         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
4853         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
4854         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
4855         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
4856         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
4857         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
4858         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
4859         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
4860         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
4861         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
4862         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
4863         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
4864         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
4865         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
4866         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
4867         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
4868         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4869         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
4870         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
4871         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
4872         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
4873         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
4874         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
4875         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
4876         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
4877         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
4878         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
4879         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
4880         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
4881         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
4882         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
4883         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
4884         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
4885         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
4886         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
4887         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
4888         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
4889         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
4890         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
4891         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
4892         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
4893         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
4894         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
4895         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
4896         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
4897         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4898         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
4899         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
4900         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
4901         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
4902         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
4903         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
4904         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
4905         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
4906         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
4907         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
4908         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
4909         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
4910         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
4911         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
4912         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
4913         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
4914         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
4915         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
4916         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
4917         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
4918         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
4919         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
4920         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
4921         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
4922         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
4923         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
4924         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
4925         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
4926         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
4927         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
4928         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
4929         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
4930         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
4931         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
4932         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
4933         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
4934         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
4935         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
4936         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
4937         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
4938         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
4939         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
4940         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
4941         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
4942         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
4943         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
4944         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
4945         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
4946         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
4947         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
4948         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
4949         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
4950         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
4951         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
4952         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
4953         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
4954         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
4955         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
4956         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
4957         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
4958         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
4959         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
4960         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
4961         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
4962         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
4963         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
4964         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
4965         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
4966         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
4967         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
4968         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
4969         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
4970         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
4971         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
4972         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
4973         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
4974         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
4975         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
4976         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
4977         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
4978         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
4979         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
4980         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
4981         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
4982         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
4983         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
4984         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
4985         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
4986         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
4987         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
4988         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
4989         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
4990         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
4991         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
4992         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
4993         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
4994         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
4995         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
4996         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
4997         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
4998         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
4999         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5000         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5001         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5002         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5003         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5004         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5005         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5006         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5007         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5008         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5009         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5010         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5011         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5012         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5013         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5014         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5015         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5016         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5017         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5018         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5019         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5020         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5021         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5022         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5023         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5024         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5025         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5026         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5027         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5028         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5029         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5030         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5031         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5032         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5033         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5034         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5035         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5036         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5037         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5038         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5039         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5040         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5041         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5042         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5043         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5044         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5045         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5046         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5047         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5048         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5049         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5050         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5051         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5052         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5053         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5054         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5055         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5056         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5057         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5058         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5059         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5060         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5061         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5062         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5063         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5064         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5065         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5066         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5067         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5068         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5069         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5070         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5071         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5072         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5073         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5074         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5075         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5076         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5077         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5078         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5079         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5080         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5081         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5082         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5083         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5084         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5085         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5086         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5087         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5088         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5089         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5090         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5091         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5092         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5093         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5094         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5095         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5096         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5097         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5098         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5099         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5100         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5101         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5102         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5103         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5104         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5105         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5106         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5107         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5108         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5109         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5110         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5111         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5112         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5113         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5114         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5115         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5116         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5117         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5118         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5119         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5120         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5121         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5122         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5123         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5124         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5125         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5126         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5127         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5128         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5129         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5130         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5131         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5132         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5133         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5134 };
5135
5136 static u32 tg3TsoFwRodata[] = {
5137         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5138         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5139         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5140         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5141         0x00000000,
5142 };
5143
5144 static u32 tg3TsoFwData[] = {
5145         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5146         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5147         0x00000000,
5148 };
5149
5150 /* 5705 needs a special version of the TSO firmware.  */
5151 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5152 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5153 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5154 #define TG3_TSO5_FW_START_ADDR          0x00010000
5155 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5156 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5157 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5158 #define TG3_TSO5_FW_RODATA_LEN          0x50
5159 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5160 #define TG3_TSO5_FW_DATA_LEN            0x20
5161 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5162 #define TG3_TSO5_FW_SBSS_LEN            0x28
5163 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5164 #define TG3_TSO5_FW_BSS_LEN             0x88
5165
5166 static u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5167         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5168         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5169         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5170         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5171         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5172         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5173         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5174         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5175         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5176         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5177         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5178         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5179         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5180         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5181         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5182         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5183         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5184         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5185         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5186         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5187         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5188         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5189         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5190         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5191         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5192         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5193         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5194         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5195         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5196         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5197         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5198         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5199         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5200         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5201         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5202         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5203         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5204         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5205         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5206         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5207         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5208         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5209         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5210         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5211         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5212         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5213         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5214         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5215         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5216         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5217         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5218         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5219         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5220         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5221         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5222         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5223         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5224         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5225         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5226         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5227         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5228         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5229         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5230         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5231         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5232         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5233         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5234         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5235         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5236         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5237         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5238         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5239         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5240         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5241         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5242         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5243         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5244         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5245         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5246         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5247         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5248         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5249         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5250         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5251         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5252         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5253         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5254         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5255         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5256         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5257         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5258         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5259         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5260         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5261         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5262         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5263         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5264         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5265         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5266         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5267         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5268         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5269         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5270         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5271         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5272         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5273         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5274         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5275         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5276         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5277         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5278         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5279         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5280         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5281         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5282         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5283         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5284         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5285         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5286         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5287         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5288         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5289         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5290         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5291         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5292         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5293         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5294         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5295         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5296         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5297         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5298         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5299         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5300         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5301         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5302         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5303         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5304         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5305         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5306         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5307         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5308         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5309         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5310         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5311         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5312         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5313         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5314         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5315         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5316         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5317         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5318         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5319         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5320         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5321         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5322         0x00000000, 0x00000000, 0x00000000,
5323 };
5324
5325 static u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5326         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5327         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5328         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5329         0x00000000, 0x00000000, 0x00000000,
5330 };
5331
5332 static u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5333         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5334         0x00000000, 0x00000000, 0x00000000,
5335 };
5336
5337 /* tp->lock is held. */
5338 static int tg3_load_tso_firmware(struct tg3 *tp)
5339 {
5340         struct fw_info info;
5341         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5342         int err, i;
5343
5344         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5345                 return 0;
5346
5347         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5348                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5349                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5350                 info.text_data = &tg3Tso5FwText[0];
5351                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5352                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5353                 info.rodata_data = &tg3Tso5FwRodata[0];
5354                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5355                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5356                 info.data_data = &tg3Tso5FwData[0];
5357                 cpu_base = RX_CPU_BASE;
5358                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5359                 cpu_scratch_size = (info.text_len +
5360                                     info.rodata_len +
5361                                     info.data_len +
5362                                     TG3_TSO5_FW_SBSS_LEN +
5363                                     TG3_TSO5_FW_BSS_LEN);
5364         } else {
5365                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5366                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5367                 info.text_data = &tg3TsoFwText[0];
5368                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5369                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5370                 info.rodata_data = &tg3TsoFwRodata[0];
5371                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5372                 info.data_len = TG3_TSO_FW_DATA_LEN;
5373                 info.data_data = &tg3TsoFwData[0];
5374                 cpu_base = TX_CPU_BASE;
5375                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5376                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5377         }
5378
5379         err = tg3_load_firmware_cpu(tp, cpu_base,
5380                                     cpu_scratch_base, cpu_scratch_size,
5381                                     &info);
5382         if (err)
5383                 return err;
5384
5385         /* Now startup the cpu. */
5386         tw32(cpu_base + CPU_STATE, 0xffffffff);
5387         tw32_f(cpu_base + CPU_PC,    info.text_base);
5388
5389         for (i = 0; i < 5; i++) {
5390                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5391                         break;
5392                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5393                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5394                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5395                 udelay(1000);
5396         }
5397         if (i >= 5) {
5398                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5399                        "to set CPU PC, is %08x should be %08x\n",
5400                        tp->dev->name, tr32(cpu_base + CPU_PC),
5401                        info.text_base);
5402                 return -ENODEV;
5403         }
5404         tw32(cpu_base + CPU_STATE, 0xffffffff);
5405         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5406         return 0;
5407 }
5408
5409 #endif /* TG3_TSO_SUPPORT != 0 */
5410
5411 /* tp->lock is held. */
5412 static void __tg3_set_mac_addr(struct tg3 *tp)
5413 {
5414         u32 addr_high, addr_low;
5415         int i;
5416
5417         addr_high = ((tp->dev->dev_addr[0] << 8) |
5418                      tp->dev->dev_addr[1]);
5419         addr_low = ((tp->dev->dev_addr[2] << 24) |
5420                     (tp->dev->dev_addr[3] << 16) |
5421                     (tp->dev->dev_addr[4] <<  8) |
5422                     (tp->dev->dev_addr[5] <<  0));
5423         for (i = 0; i < 4; i++) {
5424                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5425                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5426         }
5427
5428         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5429             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5430                 for (i = 0; i < 12; i++) {
5431                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5432                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5433                 }
5434         }
5435
5436         addr_high = (tp->dev->dev_addr[0] +
5437                      tp->dev->dev_addr[1] +
5438                      tp->dev->dev_addr[2] +
5439                      tp->dev->dev_addr[3] +
5440                      tp->dev->dev_addr[4] +
5441                      tp->dev->dev_addr[5]) &
5442                 TX_BACKOFF_SEED_MASK;
5443         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5444 }
5445
5446 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5447 {
5448         struct tg3 *tp = netdev_priv(dev);
5449         struct sockaddr *addr = p;
5450
5451         if (!is_valid_ether_addr(addr->sa_data))
5452                 return -EINVAL;
5453
5454         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5455
5456         spin_lock_bh(&tp->lock);
5457         __tg3_set_mac_addr(tp);
5458         spin_unlock_bh(&tp->lock);
5459
5460         return 0;
5461 }
5462
5463 /* tp->lock is held. */
5464 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5465                            dma_addr_t mapping, u32 maxlen_flags,
5466                            u32 nic_addr)
5467 {
5468         tg3_write_mem(tp,
5469                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5470                       ((u64) mapping >> 32));
5471         tg3_write_mem(tp,
5472                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5473                       ((u64) mapping & 0xffffffff));
5474         tg3_write_mem(tp,
5475                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5476                        maxlen_flags);
5477
5478         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5479                 tg3_write_mem(tp,
5480                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5481                               nic_addr);
5482 }
5483
5484 static void __tg3_set_rx_mode(struct net_device *);
5485 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5486 {
5487         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5488         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5489         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5490         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5491         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5492                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5493                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5494         }
5495         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5496         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5497         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5498                 u32 val = ec->stats_block_coalesce_usecs;
5499
5500                 if (!netif_carrier_ok(tp->dev))
5501                         val = 0;
5502
5503                 tw32(HOSTCC_STAT_COAL_TICKS, val);
5504         }
5505 }
5506
5507 /* tp->lock is held. */
5508 static int tg3_reset_hw(struct tg3 *tp)
5509 {
5510         u32 val, rdmac_mode;
5511         int i, err, limit;
5512
5513         tg3_disable_ints(tp);
5514
5515         tg3_stop_fw(tp);
5516
5517         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
5518
5519         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
5520                 tg3_abort_hw(tp, 1);
5521         }
5522
5523         err = tg3_chip_reset(tp);
5524         if (err)
5525                 return err;
5526
5527         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
5528
5529         /* This works around an issue with Athlon chipsets on
5530          * B3 tigon3 silicon.  This bit has no effect on any
5531          * other revision.  But do not set this on PCI Express
5532          * chips.
5533          */
5534         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
5535                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
5536         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
5537
5538         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
5539             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
5540                 val = tr32(TG3PCI_PCISTATE);
5541                 val |= PCISTATE_RETRY_SAME_DMA;
5542                 tw32(TG3PCI_PCISTATE, val);
5543         }
5544
5545         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
5546                 /* Enable some hw fixes.  */
5547                 val = tr32(TG3PCI_MSI_DATA);
5548                 val |= (1 << 26) | (1 << 28) | (1 << 29);
5549                 tw32(TG3PCI_MSI_DATA, val);
5550         }
5551
5552         /* Descriptor ring init may make accesses to the
5553          * NIC SRAM area to setup the TX descriptors, so we
5554          * can only do this after the hardware has been
5555          * successfully reset.
5556          */
5557         tg3_init_rings(tp);
5558
5559         /* This value is determined during the probe time DMA
5560          * engine test, tg3_test_dma.
5561          */
5562         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
5563
5564         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
5565                           GRC_MODE_4X_NIC_SEND_RINGS |
5566                           GRC_MODE_NO_TX_PHDR_CSUM |
5567                           GRC_MODE_NO_RX_PHDR_CSUM);
5568         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
5569         if (tp->tg3_flags & TG3_FLAG_NO_TX_PSEUDO_CSUM)
5570                 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
5571         if (tp->tg3_flags & TG3_FLAG_NO_RX_PSEUDO_CSUM)
5572                 tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
5573
5574         tw32(GRC_MODE,
5575              tp->grc_mode |
5576              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
5577
5578         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
5579         val = tr32(GRC_MISC_CFG);
5580         val &= ~0xff;
5581         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
5582         tw32(GRC_MISC_CFG, val);
5583
5584         /* Initialize MBUF/DESC pool. */
5585         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5586                 /* Do nothing.  */
5587         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5588                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
5589                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
5590                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
5591                 else
5592                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
5593                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
5594                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
5595         }
5596 #if TG3_TSO_SUPPORT != 0
5597         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5598                 int fw_len;
5599
5600                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
5601                           TG3_TSO5_FW_RODATA_LEN +
5602                           TG3_TSO5_FW_DATA_LEN +
5603                           TG3_TSO5_FW_SBSS_LEN +
5604                           TG3_TSO5_FW_BSS_LEN);
5605                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
5606                 tw32(BUFMGR_MB_POOL_ADDR,
5607                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
5608                 tw32(BUFMGR_MB_POOL_SIZE,
5609                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
5610         }
5611 #endif
5612
5613         if (tp->dev->mtu <= ETH_DATA_LEN) {
5614                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5615                      tp->bufmgr_config.mbuf_read_dma_low_water);
5616                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5617                      tp->bufmgr_config.mbuf_mac_rx_low_water);
5618                 tw32(BUFMGR_MB_HIGH_WATER,
5619                      tp->bufmgr_config.mbuf_high_water);
5620         } else {
5621                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
5622                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
5623                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
5624                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
5625                 tw32(BUFMGR_MB_HIGH_WATER,
5626                      tp->bufmgr_config.mbuf_high_water_jumbo);
5627         }
5628         tw32(BUFMGR_DMA_LOW_WATER,
5629              tp->bufmgr_config.dma_low_water);
5630         tw32(BUFMGR_DMA_HIGH_WATER,
5631              tp->bufmgr_config.dma_high_water);
5632
5633         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
5634         for (i = 0; i < 2000; i++) {
5635                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
5636                         break;
5637                 udelay(10);
5638         }
5639         if (i >= 2000) {
5640                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
5641                        tp->dev->name);
5642                 return -ENODEV;
5643         }
5644
5645         /* Setup replenish threshold. */
5646         tw32(RCVBDI_STD_THRESH, tp->rx_pending / 8);
5647
5648         /* Initialize TG3_BDINFO's at:
5649          *  RCVDBDI_STD_BD:     standard eth size rx ring
5650          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
5651          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
5652          *
5653          * like so:
5654          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
5655          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
5656          *                              ring attribute flags
5657          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
5658          *
5659          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
5660          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
5661          *
5662          * The size of each ring is fixed in the firmware, but the location is
5663          * configurable.
5664          */
5665         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5666              ((u64) tp->rx_std_mapping >> 32));
5667         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5668              ((u64) tp->rx_std_mapping & 0xffffffff));
5669         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
5670              NIC_SRAM_RX_BUFFER_DESC);
5671
5672         /* Don't even try to program the JUMBO/MINI buffer descriptor
5673          * configs on 5705.
5674          */
5675         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
5676                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5677                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
5678         } else {
5679                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
5680                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5681
5682                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
5683                      BDINFO_FLAGS_DISABLED);
5684
5685                 /* Setup replenish threshold. */
5686                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
5687
5688                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
5689                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
5690                              ((u64) tp->rx_jumbo_mapping >> 32));
5691                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
5692                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
5693                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5694                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
5695                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
5696                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
5697                 } else {
5698                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
5699                              BDINFO_FLAGS_DISABLED);
5700                 }
5701
5702         }
5703
5704         /* There is only one send ring on 5705/5750, no need to explicitly
5705          * disable the others.
5706          */
5707         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5708                 /* Clear out send RCB ring in SRAM. */
5709                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
5710                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5711                                       BDINFO_FLAGS_DISABLED);
5712         }
5713
5714         tp->tx_prod = 0;
5715         tp->tx_cons = 0;
5716         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5717         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
5718
5719         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
5720                        tp->tx_desc_mapping,
5721                        (TG3_TX_RING_SIZE <<
5722                         BDINFO_FLAGS_MAXLEN_SHIFT),
5723                        NIC_SRAM_TX_BUFFER_DESC);
5724
5725         /* There is only one receive return ring on 5705/5750, no need
5726          * to explicitly disable the others.
5727          */
5728         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5729                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
5730                      i += TG3_BDINFO_SIZE) {
5731                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
5732                                       BDINFO_FLAGS_DISABLED);
5733                 }
5734         }
5735
5736         tp->rx_rcb_ptr = 0;
5737         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
5738
5739         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
5740                        tp->rx_rcb_mapping,
5741                        (TG3_RX_RCB_RING_SIZE(tp) <<
5742                         BDINFO_FLAGS_MAXLEN_SHIFT),
5743                        0);
5744
5745         tp->rx_std_ptr = tp->rx_pending;
5746         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
5747                      tp->rx_std_ptr);
5748
5749         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
5750                                                 tp->rx_jumbo_pending : 0;
5751         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
5752                      tp->rx_jumbo_ptr);
5753
5754         /* Initialize MAC address and backoff seed. */
5755         __tg3_set_mac_addr(tp);
5756
5757         /* MTU + ethernet header + FCS + optional VLAN tag */
5758         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
5759
5760         /* The slot time is changed by tg3_setup_phy if we
5761          * run at gigabit with half duplex.
5762          */
5763         tw32(MAC_TX_LENGTHS,
5764              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
5765              (6 << TX_LENGTHS_IPG_SHIFT) |
5766              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
5767
5768         /* Receive rules. */
5769         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
5770         tw32(RCVLPC_CONFIG, 0x0181);
5771
5772         /* Calculate RDMAC_MODE setting early, we need it to determine
5773          * the RCVLPC_STATE_ENABLE mask.
5774          */
5775         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
5776                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
5777                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
5778                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
5779                       RDMAC_MODE_LNGREAD_ENAB);
5780         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5781                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5782
5783         /* If statement applies to 5705 and 5750 PCI devices only */
5784         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5785              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5786             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
5787                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5788                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5789                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5790                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
5791                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5792                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
5793                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5794                 }
5795         }
5796
5797         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
5798                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
5799
5800 #if TG3_TSO_SUPPORT != 0
5801         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5802                 rdmac_mode |= (1 << 27);
5803 #endif
5804
5805         /* Receive/send statistics. */
5806         if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
5807             (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
5808                 val = tr32(RCVLPC_STATS_ENABLE);
5809                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
5810                 tw32(RCVLPC_STATS_ENABLE, val);
5811         } else {
5812                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
5813         }
5814         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
5815         tw32(SNDDATAI_STATSENAB, 0xffffff);
5816         tw32(SNDDATAI_STATSCTRL,
5817              (SNDDATAI_SCTRL_ENABLE |
5818               SNDDATAI_SCTRL_FASTUPD));
5819
5820         /* Setup host coalescing engine. */
5821         tw32(HOSTCC_MODE, 0);
5822         for (i = 0; i < 2000; i++) {
5823                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
5824                         break;
5825                 udelay(10);
5826         }
5827
5828         __tg3_set_coalesce(tp, &tp->coal);
5829
5830         /* set status block DMA address */
5831         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5832              ((u64) tp->status_mapping >> 32));
5833         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5834              ((u64) tp->status_mapping & 0xffffffff));
5835
5836         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5837                 /* Status/statistics block address.  See tg3_timer,
5838                  * the tg3_periodic_fetch_stats call there, and
5839                  * tg3_get_stats to see how this works for 5705/5750 chips.
5840                  */
5841                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
5842                      ((u64) tp->stats_mapping >> 32));
5843                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
5844                      ((u64) tp->stats_mapping & 0xffffffff));
5845                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
5846                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
5847         }
5848
5849         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
5850
5851         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
5852         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
5853         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5854                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
5855
5856         /* Clear statistics/status block in chip, and status block in ram. */
5857         for (i = NIC_SRAM_STATS_BLK;
5858              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
5859              i += sizeof(u32)) {
5860                 tg3_write_mem(tp, i, 0);
5861                 udelay(40);
5862         }
5863         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
5864
5865         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
5866                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
5867                 /* reset to prevent losing 1st rx packet intermittently */
5868                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
5869                 udelay(10);
5870         }
5871
5872         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
5873                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
5874         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
5875         udelay(40);
5876
5877         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
5878          * If TG3_FLAG_EEPROM_WRITE_PROT is set, we should read the
5879          * register to preserve the GPIO settings for LOMs. The GPIOs,
5880          * whether used as inputs or outputs, are set by boot code after
5881          * reset.
5882          */
5883         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
5884                 u32 gpio_mask;
5885
5886                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE2 |
5887                             GRC_LCLCTRL_GPIO_OUTPUT0 | GRC_LCLCTRL_GPIO_OUTPUT2;
5888
5889                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
5890                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
5891                                      GRC_LCLCTRL_GPIO_OUTPUT3;
5892
5893                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
5894
5895                 /* GPIO1 must be driven high for eeprom write protect */
5896                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
5897                                        GRC_LCLCTRL_GPIO_OUTPUT1);
5898         }
5899         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
5900         udelay(100);
5901
5902         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
5903         tp->last_tag = 0;
5904
5905         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5906                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
5907                 udelay(40);
5908         }
5909
5910         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
5911                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
5912                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
5913                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
5914                WDMAC_MODE_LNGREAD_ENAB);
5915
5916         /* If statement applies to 5705 and 5750 PCI devices only */
5917         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5918              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5919             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
5920                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5921                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5922                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
5923                         /* nothing */
5924                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
5925                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
5926                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5927                         val |= WDMAC_MODE_RX_ACCEL;
5928                 }
5929         }
5930
5931         tw32_f(WDMAC_MODE, val);
5932         udelay(40);
5933
5934         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
5935                 val = tr32(TG3PCI_X_CAPS);
5936                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
5937                         val &= ~PCIX_CAPS_BURST_MASK;
5938                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5939                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5940                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
5941                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
5942                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
5943                                 val |= (tp->split_mode_max_reqs <<
5944                                         PCIX_CAPS_SPLIT_SHIFT);
5945                 }
5946                 tw32(TG3PCI_X_CAPS, val);
5947         }
5948
5949         tw32_f(RDMAC_MODE, rdmac_mode);
5950         udelay(40);
5951
5952         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
5953         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5954                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
5955         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
5956         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
5957         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
5958         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
5959         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
5960 #if TG3_TSO_SUPPORT != 0
5961         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5962                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
5963 #endif
5964         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
5965         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
5966
5967         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
5968                 err = tg3_load_5701_a0_firmware_fix(tp);
5969                 if (err)
5970                         return err;
5971         }
5972
5973 #if TG3_TSO_SUPPORT != 0
5974         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
5975                 err = tg3_load_tso_firmware(tp);
5976                 if (err)
5977                         return err;
5978         }
5979 #endif
5980
5981         tp->tx_mode = TX_MODE_ENABLE;
5982         tw32_f(MAC_TX_MODE, tp->tx_mode);
5983         udelay(100);
5984
5985         tp->rx_mode = RX_MODE_ENABLE;
5986         tw32_f(MAC_RX_MODE, tp->rx_mode);
5987         udelay(10);
5988
5989         if (tp->link_config.phy_is_low_power) {
5990                 tp->link_config.phy_is_low_power = 0;
5991                 tp->link_config.speed = tp->link_config.orig_speed;
5992                 tp->link_config.duplex = tp->link_config.orig_duplex;
5993                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
5994         }
5995
5996         tp->mi_mode = MAC_MI_MODE_BASE;
5997         tw32_f(MAC_MI_MODE, tp->mi_mode);
5998         udelay(80);
5999
6000         tw32(MAC_LED_CTRL, tp->led_ctrl);
6001
6002         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6003         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6004                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6005                 udelay(10);
6006         }
6007         tw32_f(MAC_RX_MODE, tp->rx_mode);
6008         udelay(10);
6009
6010         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6011                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6012                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6013                         /* Set drive transmission level to 1.2V  */
6014                         /* only if the signal pre-emphasis bit is not set  */
6015                         val = tr32(MAC_SERDES_CFG);
6016                         val &= 0xfffff000;
6017                         val |= 0x880;
6018                         tw32(MAC_SERDES_CFG, val);
6019                 }
6020                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6021                         tw32(MAC_SERDES_CFG, 0x616000);
6022         }
6023
6024         /* Prevent chip from dropping frames when flow control
6025          * is enabled.
6026          */
6027         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6028
6029         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6030             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6031                 /* Use hardware link auto-negotiation */
6032                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6033         }
6034
6035         err = tg3_setup_phy(tp, 1);
6036         if (err)
6037                 return err;
6038
6039         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6040                 u32 tmp;
6041
6042                 /* Clear CRC stats. */
6043                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6044                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6045                         tg3_readphy(tp, 0x14, &tmp);
6046                 }
6047         }
6048
6049         __tg3_set_rx_mode(tp->dev);
6050
6051         /* Initialize receive rules. */
6052         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6053         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6054         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6055         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6056
6057         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6058             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6059                 limit = 8;
6060         else
6061                 limit = 16;
6062         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6063                 limit -= 4;
6064         switch (limit) {
6065         case 16:
6066                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6067         case 15:
6068                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6069         case 14:
6070                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6071         case 13:
6072                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6073         case 12:
6074                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6075         case 11:
6076                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6077         case 10:
6078                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6079         case 9:
6080                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6081         case 8:
6082                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6083         case 7:
6084                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6085         case 6:
6086                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6087         case 5:
6088                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6089         case 4:
6090                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6091         case 3:
6092                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6093         case 2:
6094         case 1:
6095
6096         default:
6097                 break;
6098         };
6099
6100         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6101
6102         return 0;
6103 }
6104
6105 /* Called at device open time to get the chip ready for
6106  * packet processing.  Invoked with tp->lock held.
6107  */
6108 static int tg3_init_hw(struct tg3 *tp)
6109 {
6110         int err;
6111
6112         /* Force the chip into D0. */
6113         err = tg3_set_power_state(tp, 0);
6114         if (err)
6115                 goto out;
6116
6117         tg3_switch_clocks(tp);
6118
6119         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6120
6121         err = tg3_reset_hw(tp);
6122
6123 out:
6124         return err;
6125 }
6126
6127 #define TG3_STAT_ADD32(PSTAT, REG) \
6128 do {    u32 __val = tr32(REG); \
6129         (PSTAT)->low += __val; \
6130         if ((PSTAT)->low < __val) \
6131                 (PSTAT)->high += 1; \
6132 } while (0)
6133
6134 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6135 {
6136         struct tg3_hw_stats *sp = tp->hw_stats;
6137
6138         if (!netif_carrier_ok(tp->dev))
6139                 return;
6140
6141         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6142         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6143         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6144         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6145         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6146         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6147         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6148         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6149         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6150         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6151         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6152         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6153         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6154
6155         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6156         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6157         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6158         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6159         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6160         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6161         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6162         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6163         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6164         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6165         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6166         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6167         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6168         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6169 }
6170
6171 static void tg3_timer(unsigned long __opaque)
6172 {
6173         struct tg3 *tp = (struct tg3 *) __opaque;
6174
6175         spin_lock(&tp->lock);
6176
6177         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6178                 /* All of this garbage is because when using non-tagged
6179                  * IRQ status the mailbox/status_block protocol the chip
6180                  * uses with the cpu is race prone.
6181                  */
6182                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6183                         tw32(GRC_LOCAL_CTRL,
6184                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6185                 } else {
6186                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6187                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6188                 }
6189
6190                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6191                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6192                         spin_unlock(&tp->lock);
6193                         schedule_work(&tp->reset_task);
6194                         return;
6195                 }
6196         }
6197
6198         /* This part only runs once per second. */
6199         if (!--tp->timer_counter) {
6200                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6201                         tg3_periodic_fetch_stats(tp);
6202
6203                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6204                         u32 mac_stat;
6205                         int phy_event;
6206
6207                         mac_stat = tr32(MAC_STATUS);
6208
6209                         phy_event = 0;
6210                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6211                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6212                                         phy_event = 1;
6213                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6214                                 phy_event = 1;
6215
6216                         if (phy_event)
6217                                 tg3_setup_phy(tp, 0);
6218                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6219                         u32 mac_stat = tr32(MAC_STATUS);
6220                         int need_setup = 0;
6221
6222                         if (netif_carrier_ok(tp->dev) &&
6223                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6224                                 need_setup = 1;
6225                         }
6226                         if (! netif_carrier_ok(tp->dev) &&
6227                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6228                                          MAC_STATUS_SIGNAL_DET))) {
6229                                 need_setup = 1;
6230                         }
6231                         if (need_setup) {
6232                                 tw32_f(MAC_MODE,
6233                                      (tp->mac_mode &
6234                                       ~MAC_MODE_PORT_MODE_MASK));
6235                                 udelay(40);
6236                                 tw32_f(MAC_MODE, tp->mac_mode);
6237                                 udelay(40);
6238                                 tg3_setup_phy(tp, 0);
6239                         }
6240                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6241                         tg3_serdes_parallel_detect(tp);
6242
6243                 tp->timer_counter = tp->timer_multiplier;
6244         }
6245
6246         /* Heartbeat is only sent once every 2 seconds.  */
6247         if (!--tp->asf_counter) {
6248                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6249                         u32 val;
6250
6251                         tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_MBOX,
6252                                            FWCMD_NICDRV_ALIVE2);
6253                         tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6254                         /* 5 seconds timeout */
6255                         tg3_write_mem_fast(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6256                         val = tr32(GRC_RX_CPU_EVENT);
6257                         val |= (1 << 14);
6258                         tw32(GRC_RX_CPU_EVENT, val);
6259                 }
6260                 tp->asf_counter = tp->asf_multiplier;
6261         }
6262
6263         spin_unlock(&tp->lock);
6264
6265         tp->timer.expires = jiffies + tp->timer_offset;
6266         add_timer(&tp->timer);
6267 }
6268
6269 static int tg3_test_interrupt(struct tg3 *tp)
6270 {
6271         struct net_device *dev = tp->dev;
6272         int err, i;
6273         u32 int_mbox = 0;
6274
6275         if (!netif_running(dev))
6276                 return -ENODEV;
6277
6278         tg3_disable_ints(tp);
6279
6280         free_irq(tp->pdev->irq, dev);
6281
6282         err = request_irq(tp->pdev->irq, tg3_test_isr,
6283                           SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6284         if (err)
6285                 return err;
6286
6287         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6288         tg3_enable_ints(tp);
6289
6290         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6291                HOSTCC_MODE_NOW);
6292
6293         for (i = 0; i < 5; i++) {
6294                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6295                                         TG3_64BIT_REG_LOW);
6296                 if (int_mbox != 0)
6297                         break;
6298                 msleep(10);
6299         }
6300
6301         tg3_disable_ints(tp);
6302
6303         free_irq(tp->pdev->irq, dev);
6304
6305         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6306                 err = request_irq(tp->pdev->irq, tg3_msi,
6307                                   SA_SAMPLE_RANDOM, dev->name, dev);
6308         else {
6309                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6310                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6311                         fn = tg3_interrupt_tagged;
6312                 err = request_irq(tp->pdev->irq, fn,
6313                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6314         }
6315
6316         if (err)
6317                 return err;
6318
6319         if (int_mbox != 0)
6320                 return 0;
6321
6322         return -EIO;
6323 }
6324
6325 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6326  * successfully restored
6327  */
6328 static int tg3_test_msi(struct tg3 *tp)
6329 {
6330         struct net_device *dev = tp->dev;
6331         int err;
6332         u16 pci_cmd;
6333
6334         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6335                 return 0;
6336
6337         /* Turn off SERR reporting in case MSI terminates with Master
6338          * Abort.
6339          */
6340         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6341         pci_write_config_word(tp->pdev, PCI_COMMAND,
6342                               pci_cmd & ~PCI_COMMAND_SERR);
6343
6344         err = tg3_test_interrupt(tp);
6345
6346         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6347
6348         if (!err)
6349                 return 0;
6350
6351         /* other failures */
6352         if (err != -EIO)
6353                 return err;
6354
6355         /* MSI test failed, go back to INTx mode */
6356         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6357                "switching to INTx mode. Please report this failure to "
6358                "the PCI maintainer and include system chipset information.\n",
6359                        tp->dev->name);
6360
6361         free_irq(tp->pdev->irq, dev);
6362         pci_disable_msi(tp->pdev);
6363
6364         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6365
6366         {
6367                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6368                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6369                         fn = tg3_interrupt_tagged;
6370
6371                 err = request_irq(tp->pdev->irq, fn,
6372                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6373         }
6374         if (err)
6375                 return err;
6376
6377         /* Need to reset the chip because the MSI cycle may have terminated
6378          * with Master Abort.
6379          */
6380         tg3_full_lock(tp, 1);
6381
6382         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6383         err = tg3_init_hw(tp);
6384
6385         tg3_full_unlock(tp);
6386
6387         if (err)
6388                 free_irq(tp->pdev->irq, dev);
6389
6390         return err;
6391 }
6392
6393 static int tg3_open(struct net_device *dev)
6394 {
6395         struct tg3 *tp = netdev_priv(dev);
6396         int err;
6397
6398         tg3_full_lock(tp, 0);
6399
6400         tg3_disable_ints(tp);
6401         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6402
6403         tg3_full_unlock(tp);
6404
6405         /* The placement of this call is tied
6406          * to the setup and use of Host TX descriptors.
6407          */
6408         err = tg3_alloc_consistent(tp);
6409         if (err)
6410                 return err;
6411
6412         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
6413             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
6414             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) {
6415                 /* All MSI supporting chips should support tagged
6416                  * status.  Assert that this is the case.
6417                  */
6418                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6419                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
6420                                "Not using MSI.\n", tp->dev->name);
6421                 } else if (pci_enable_msi(tp->pdev) == 0) {
6422                         u32 msi_mode;
6423
6424                         msi_mode = tr32(MSGINT_MODE);
6425                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
6426                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
6427                 }
6428         }
6429         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
6430                 err = request_irq(tp->pdev->irq, tg3_msi,
6431                                   SA_SAMPLE_RANDOM, dev->name, dev);
6432         else {
6433                 irqreturn_t (*fn)(int, void *, struct pt_regs *)=tg3_interrupt;
6434                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6435                         fn = tg3_interrupt_tagged;
6436
6437                 err = request_irq(tp->pdev->irq, fn,
6438                                   SA_SHIRQ | SA_SAMPLE_RANDOM, dev->name, dev);
6439         }
6440
6441         if (err) {
6442                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6443                         pci_disable_msi(tp->pdev);
6444                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6445                 }
6446                 tg3_free_consistent(tp);
6447                 return err;
6448         }
6449
6450         tg3_full_lock(tp, 0);
6451
6452         err = tg3_init_hw(tp);
6453         if (err) {
6454                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6455                 tg3_free_rings(tp);
6456         } else {
6457                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6458                         tp->timer_offset = HZ;
6459                 else
6460                         tp->timer_offset = HZ / 10;
6461
6462                 BUG_ON(tp->timer_offset > HZ);
6463                 tp->timer_counter = tp->timer_multiplier =
6464                         (HZ / tp->timer_offset);
6465                 tp->asf_counter = tp->asf_multiplier =
6466                         ((HZ / tp->timer_offset) * 2);
6467
6468                 init_timer(&tp->timer);
6469                 tp->timer.expires = jiffies + tp->timer_offset;
6470                 tp->timer.data = (unsigned long) tp;
6471                 tp->timer.function = tg3_timer;
6472         }
6473
6474         tg3_full_unlock(tp);
6475
6476         if (err) {
6477                 free_irq(tp->pdev->irq, dev);
6478                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6479                         pci_disable_msi(tp->pdev);
6480                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6481                 }
6482                 tg3_free_consistent(tp);
6483                 return err;
6484         }
6485
6486         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6487                 err = tg3_test_msi(tp);
6488
6489                 if (err) {
6490                         tg3_full_lock(tp, 0);
6491
6492                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6493                                 pci_disable_msi(tp->pdev);
6494                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6495                         }
6496                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6497                         tg3_free_rings(tp);
6498                         tg3_free_consistent(tp);
6499
6500                         tg3_full_unlock(tp);
6501
6502                         return err;
6503                 }
6504         }
6505
6506         tg3_full_lock(tp, 0);
6507
6508         add_timer(&tp->timer);
6509         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
6510         tg3_enable_ints(tp);
6511
6512         tg3_full_unlock(tp);
6513
6514         netif_start_queue(dev);
6515
6516         return 0;
6517 }
6518
6519 #if 0
6520 /*static*/ void tg3_dump_state(struct tg3 *tp)
6521 {
6522         u32 val32, val32_2, val32_3, val32_4, val32_5;
6523         u16 val16;
6524         int i;
6525
6526         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
6527         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
6528         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
6529                val16, val32);
6530
6531         /* MAC block */
6532         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
6533                tr32(MAC_MODE), tr32(MAC_STATUS));
6534         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
6535                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
6536         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
6537                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
6538         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
6539                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
6540
6541         /* Send data initiator control block */
6542         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
6543                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
6544         printk("       SNDDATAI_STATSCTRL[%08x]\n",
6545                tr32(SNDDATAI_STATSCTRL));
6546
6547         /* Send data completion control block */
6548         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
6549
6550         /* Send BD ring selector block */
6551         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
6552                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
6553
6554         /* Send BD initiator control block */
6555         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
6556                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
6557
6558         /* Send BD completion control block */
6559         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
6560
6561         /* Receive list placement control block */
6562         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
6563                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
6564         printk("       RCVLPC_STATSCTRL[%08x]\n",
6565                tr32(RCVLPC_STATSCTRL));
6566
6567         /* Receive data and receive BD initiator control block */
6568         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
6569                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
6570
6571         /* Receive data completion control block */
6572         printk("DEBUG: RCVDCC_MODE[%08x]\n",
6573                tr32(RCVDCC_MODE));
6574
6575         /* Receive BD initiator control block */
6576         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
6577                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
6578
6579         /* Receive BD completion control block */
6580         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
6581                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
6582
6583         /* Receive list selector control block */
6584         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
6585                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
6586
6587         /* Mbuf cluster free block */
6588         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
6589                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
6590
6591         /* Host coalescing control block */
6592         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
6593                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
6594         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
6595                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6596                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6597         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
6598                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
6599                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
6600         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
6601                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
6602         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
6603                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
6604
6605         /* Memory arbiter control block */
6606         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
6607                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
6608
6609         /* Buffer manager control block */
6610         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
6611                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
6612         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
6613                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
6614         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
6615                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
6616                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
6617                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
6618
6619         /* Read DMA control block */
6620         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
6621                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
6622
6623         /* Write DMA control block */
6624         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
6625                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
6626
6627         /* DMA completion block */
6628         printk("DEBUG: DMAC_MODE[%08x]\n",
6629                tr32(DMAC_MODE));
6630
6631         /* GRC block */
6632         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
6633                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
6634         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
6635                tr32(GRC_LOCAL_CTRL));
6636
6637         /* TG3_BDINFOs */
6638         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
6639                tr32(RCVDBDI_JUMBO_BD + 0x0),
6640                tr32(RCVDBDI_JUMBO_BD + 0x4),
6641                tr32(RCVDBDI_JUMBO_BD + 0x8),
6642                tr32(RCVDBDI_JUMBO_BD + 0xc));
6643         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
6644                tr32(RCVDBDI_STD_BD + 0x0),
6645                tr32(RCVDBDI_STD_BD + 0x4),
6646                tr32(RCVDBDI_STD_BD + 0x8),
6647                tr32(RCVDBDI_STD_BD + 0xc));
6648         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
6649                tr32(RCVDBDI_MINI_BD + 0x0),
6650                tr32(RCVDBDI_MINI_BD + 0x4),
6651                tr32(RCVDBDI_MINI_BD + 0x8),
6652                tr32(RCVDBDI_MINI_BD + 0xc));
6653
6654         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
6655         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
6656         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
6657         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
6658         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
6659                val32, val32_2, val32_3, val32_4);
6660
6661         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
6662         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
6663         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
6664         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
6665         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
6666                val32, val32_2, val32_3, val32_4);
6667
6668         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
6669         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
6670         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
6671         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
6672         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
6673         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
6674                val32, val32_2, val32_3, val32_4, val32_5);
6675
6676         /* SW status block */
6677         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6678                tp->hw_status->status,
6679                tp->hw_status->status_tag,
6680                tp->hw_status->rx_jumbo_consumer,
6681                tp->hw_status->rx_consumer,
6682                tp->hw_status->rx_mini_consumer,
6683                tp->hw_status->idx[0].rx_producer,
6684                tp->hw_status->idx[0].tx_consumer);
6685
6686         /* SW statistics block */
6687         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
6688                ((u32 *)tp->hw_stats)[0],
6689                ((u32 *)tp->hw_stats)[1],
6690                ((u32 *)tp->hw_stats)[2],
6691                ((u32 *)tp->hw_stats)[3]);
6692
6693         /* Mailboxes */
6694         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
6695                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
6696                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
6697                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
6698                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
6699
6700         /* NIC side send descriptors. */
6701         for (i = 0; i < 6; i++) {
6702                 unsigned long txd;
6703
6704                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
6705                         + (i * sizeof(struct tg3_tx_buffer_desc));
6706                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
6707                        i,
6708                        readl(txd + 0x0), readl(txd + 0x4),
6709                        readl(txd + 0x8), readl(txd + 0xc));
6710         }
6711
6712         /* NIC side RX descriptors. */
6713         for (i = 0; i < 6; i++) {
6714                 unsigned long rxd;
6715
6716                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
6717                         + (i * sizeof(struct tg3_rx_buffer_desc));
6718                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
6719                        i,
6720                        readl(rxd + 0x0), readl(rxd + 0x4),
6721                        readl(rxd + 0x8), readl(rxd + 0xc));
6722                 rxd += (4 * sizeof(u32));
6723                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
6724                        i,
6725                        readl(rxd + 0x0), readl(rxd + 0x4),
6726                        readl(rxd + 0x8), readl(rxd + 0xc));
6727         }
6728
6729         for (i = 0; i < 6; i++) {
6730                 unsigned long rxd;
6731
6732                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
6733                         + (i * sizeof(struct tg3_rx_buffer_desc));
6734                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
6735                        i,
6736                        readl(rxd + 0x0), readl(rxd + 0x4),
6737                        readl(rxd + 0x8), readl(rxd + 0xc));
6738                 rxd += (4 * sizeof(u32));
6739                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
6740                        i,
6741                        readl(rxd + 0x0), readl(rxd + 0x4),
6742                        readl(rxd + 0x8), readl(rxd + 0xc));
6743         }
6744 }
6745 #endif
6746
6747 static struct net_device_stats *tg3_get_stats(struct net_device *);
6748 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
6749
6750 static int tg3_close(struct net_device *dev)
6751 {
6752         struct tg3 *tp = netdev_priv(dev);
6753
6754         netif_stop_queue(dev);
6755
6756         del_timer_sync(&tp->timer);
6757
6758         tg3_full_lock(tp, 1);
6759 #if 0
6760         tg3_dump_state(tp);
6761 #endif
6762
6763         tg3_disable_ints(tp);
6764
6765         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6766         tg3_free_rings(tp);
6767         tp->tg3_flags &=
6768                 ~(TG3_FLAG_INIT_COMPLETE |
6769                   TG3_FLAG_GOT_SERDES_FLOWCTL);
6770         netif_carrier_off(tp->dev);
6771
6772         tg3_full_unlock(tp);
6773
6774         free_irq(tp->pdev->irq, dev);
6775         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6776                 pci_disable_msi(tp->pdev);
6777                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6778         }
6779
6780         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
6781                sizeof(tp->net_stats_prev));
6782         memcpy(&tp->estats_prev, tg3_get_estats(tp),
6783                sizeof(tp->estats_prev));
6784
6785         tg3_free_consistent(tp);
6786
6787         return 0;
6788 }
6789
6790 static inline unsigned long get_stat64(tg3_stat64_t *val)
6791 {
6792         unsigned long ret;
6793
6794 #if (BITS_PER_LONG == 32)
6795         ret = val->low;
6796 #else
6797         ret = ((u64)val->high << 32) | ((u64)val->low);
6798 #endif
6799         return ret;
6800 }
6801
6802 static unsigned long calc_crc_errors(struct tg3 *tp)
6803 {
6804         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6805
6806         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6807             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
6808              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
6809                 u32 val;
6810
6811                 spin_lock_bh(&tp->lock);
6812                 if (!tg3_readphy(tp, 0x1e, &val)) {
6813                         tg3_writephy(tp, 0x1e, val | 0x8000);
6814                         tg3_readphy(tp, 0x14, &val);
6815                 } else
6816                         val = 0;
6817                 spin_unlock_bh(&tp->lock);
6818
6819                 tp->phy_crc_errors += val;
6820
6821                 return tp->phy_crc_errors;
6822         }
6823
6824         return get_stat64(&hw_stats->rx_fcs_errors);
6825 }
6826
6827 #define ESTAT_ADD(member) \
6828         estats->member =        old_estats->member + \
6829                                 get_stat64(&hw_stats->member)
6830
6831 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
6832 {
6833         struct tg3_ethtool_stats *estats = &tp->estats;
6834         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
6835         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6836
6837         if (!hw_stats)
6838                 return old_estats;
6839
6840         ESTAT_ADD(rx_octets);
6841         ESTAT_ADD(rx_fragments);
6842         ESTAT_ADD(rx_ucast_packets);
6843         ESTAT_ADD(rx_mcast_packets);
6844         ESTAT_ADD(rx_bcast_packets);
6845         ESTAT_ADD(rx_fcs_errors);
6846         ESTAT_ADD(rx_align_errors);
6847         ESTAT_ADD(rx_xon_pause_rcvd);
6848         ESTAT_ADD(rx_xoff_pause_rcvd);
6849         ESTAT_ADD(rx_mac_ctrl_rcvd);
6850         ESTAT_ADD(rx_xoff_entered);
6851         ESTAT_ADD(rx_frame_too_long_errors);
6852         ESTAT_ADD(rx_jabbers);
6853         ESTAT_ADD(rx_undersize_packets);
6854         ESTAT_ADD(rx_in_length_errors);
6855         ESTAT_ADD(rx_out_length_errors);
6856         ESTAT_ADD(rx_64_or_less_octet_packets);
6857         ESTAT_ADD(rx_65_to_127_octet_packets);
6858         ESTAT_ADD(rx_128_to_255_octet_packets);
6859         ESTAT_ADD(rx_256_to_511_octet_packets);
6860         ESTAT_ADD(rx_512_to_1023_octet_packets);
6861         ESTAT_ADD(rx_1024_to_1522_octet_packets);
6862         ESTAT_ADD(rx_1523_to_2047_octet_packets);
6863         ESTAT_ADD(rx_2048_to_4095_octet_packets);
6864         ESTAT_ADD(rx_4096_to_8191_octet_packets);
6865         ESTAT_ADD(rx_8192_to_9022_octet_packets);
6866
6867         ESTAT_ADD(tx_octets);
6868         ESTAT_ADD(tx_collisions);
6869         ESTAT_ADD(tx_xon_sent);
6870         ESTAT_ADD(tx_xoff_sent);
6871         ESTAT_ADD(tx_flow_control);
6872         ESTAT_ADD(tx_mac_errors);
6873         ESTAT_ADD(tx_single_collisions);
6874         ESTAT_ADD(tx_mult_collisions);
6875         ESTAT_ADD(tx_deferred);
6876         ESTAT_ADD(tx_excessive_collisions);
6877         ESTAT_ADD(tx_late_collisions);
6878         ESTAT_ADD(tx_collide_2times);
6879         ESTAT_ADD(tx_collide_3times);
6880         ESTAT_ADD(tx_collide_4times);
6881         ESTAT_ADD(tx_collide_5times);
6882         ESTAT_ADD(tx_collide_6times);
6883         ESTAT_ADD(tx_collide_7times);
6884         ESTAT_ADD(tx_collide_8times);
6885         ESTAT_ADD(tx_collide_9times);
6886         ESTAT_ADD(tx_collide_10times);
6887         ESTAT_ADD(tx_collide_11times);
6888         ESTAT_ADD(tx_collide_12times);
6889         ESTAT_ADD(tx_collide_13times);
6890         ESTAT_ADD(tx_collide_14times);
6891         ESTAT_ADD(tx_collide_15times);
6892         ESTAT_ADD(tx_ucast_packets);
6893         ESTAT_ADD(tx_mcast_packets);
6894         ESTAT_ADD(tx_bcast_packets);
6895         ESTAT_ADD(tx_carrier_sense_errors);
6896         ESTAT_ADD(tx_discards);
6897         ESTAT_ADD(tx_errors);
6898
6899         ESTAT_ADD(dma_writeq_full);
6900         ESTAT_ADD(dma_write_prioq_full);
6901         ESTAT_ADD(rxbds_empty);
6902         ESTAT_ADD(rx_discards);
6903         ESTAT_ADD(rx_errors);
6904         ESTAT_ADD(rx_threshold_hit);
6905
6906         ESTAT_ADD(dma_readq_full);
6907         ESTAT_ADD(dma_read_prioq_full);
6908         ESTAT_ADD(tx_comp_queue_full);
6909
6910         ESTAT_ADD(ring_set_send_prod_index);
6911         ESTAT_ADD(ring_status_update);
6912         ESTAT_ADD(nic_irqs);
6913         ESTAT_ADD(nic_avoided_irqs);
6914         ESTAT_ADD(nic_tx_threshold_hit);
6915
6916         return estats;
6917 }
6918
6919 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
6920 {
6921         struct tg3 *tp = netdev_priv(dev);
6922         struct net_device_stats *stats = &tp->net_stats;
6923         struct net_device_stats *old_stats = &tp->net_stats_prev;
6924         struct tg3_hw_stats *hw_stats = tp->hw_stats;
6925
6926         if (!hw_stats)
6927                 return old_stats;
6928
6929         stats->rx_packets = old_stats->rx_packets +
6930                 get_stat64(&hw_stats->rx_ucast_packets) +
6931                 get_stat64(&hw_stats->rx_mcast_packets) +
6932                 get_stat64(&hw_stats->rx_bcast_packets);
6933
6934         stats->tx_packets = old_stats->tx_packets +
6935                 get_stat64(&hw_stats->tx_ucast_packets) +
6936                 get_stat64(&hw_stats->tx_mcast_packets) +
6937                 get_stat64(&hw_stats->tx_bcast_packets);
6938
6939         stats->rx_bytes = old_stats->rx_bytes +
6940                 get_stat64(&hw_stats->rx_octets);
6941         stats->tx_bytes = old_stats->tx_bytes +
6942                 get_stat64(&hw_stats->tx_octets);
6943
6944         stats->rx_errors = old_stats->rx_errors +
6945                 get_stat64(&hw_stats->rx_errors);
6946         stats->tx_errors = old_stats->tx_errors +
6947                 get_stat64(&hw_stats->tx_errors) +
6948                 get_stat64(&hw_stats->tx_mac_errors) +
6949                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
6950                 get_stat64(&hw_stats->tx_discards);
6951
6952         stats->multicast = old_stats->multicast +
6953                 get_stat64(&hw_stats->rx_mcast_packets);
6954         stats->collisions = old_stats->collisions +
6955                 get_stat64(&hw_stats->tx_collisions);
6956
6957         stats->rx_length_errors = old_stats->rx_length_errors +
6958                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
6959                 get_stat64(&hw_stats->rx_undersize_packets);
6960
6961         stats->rx_over_errors = old_stats->rx_over_errors +
6962                 get_stat64(&hw_stats->rxbds_empty);
6963         stats->rx_frame_errors = old_stats->rx_frame_errors +
6964                 get_stat64(&hw_stats->rx_align_errors);
6965         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
6966                 get_stat64(&hw_stats->tx_discards);
6967         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
6968                 get_stat64(&hw_stats->tx_carrier_sense_errors);
6969
6970         stats->rx_crc_errors = old_stats->rx_crc_errors +
6971                 calc_crc_errors(tp);
6972
6973         stats->rx_missed_errors = old_stats->rx_missed_errors +
6974                 get_stat64(&hw_stats->rx_discards);
6975
6976         return stats;
6977 }
6978
6979 static inline u32 calc_crc(unsigned char *buf, int len)
6980 {
6981         u32 reg;
6982         u32 tmp;
6983         int j, k;
6984
6985         reg = 0xffffffff;
6986
6987         for (j = 0; j < len; j++) {
6988                 reg ^= buf[j];
6989
6990                 for (k = 0; k < 8; k++) {
6991                         tmp = reg & 0x01;
6992
6993                         reg >>= 1;
6994
6995                         if (tmp) {
6996                                 reg ^= 0xedb88320;
6997                         }
6998                 }
6999         }
7000
7001         return ~reg;
7002 }
7003
7004 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7005 {
7006         /* accept or reject all multicast frames */
7007         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7008         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7009         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7010         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7011 }
7012
7013 static void __tg3_set_rx_mode(struct net_device *dev)
7014 {
7015         struct tg3 *tp = netdev_priv(dev);
7016         u32 rx_mode;
7017
7018         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7019                                   RX_MODE_KEEP_VLAN_TAG);
7020
7021         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7022          * flag clear.
7023          */
7024 #if TG3_VLAN_TAG_USED
7025         if (!tp->vlgrp &&
7026             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7027                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7028 #else
7029         /* By definition, VLAN is disabled always in this
7030          * case.
7031          */
7032         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7033                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7034 #endif
7035
7036         if (dev->flags & IFF_PROMISC) {
7037                 /* Promiscuous mode. */
7038                 rx_mode |= RX_MODE_PROMISC;
7039         } else if (dev->flags & IFF_ALLMULTI) {
7040                 /* Accept all multicast. */
7041                 tg3_set_multi (tp, 1);
7042         } else if (dev->mc_count < 1) {
7043                 /* Reject all multicast. */
7044                 tg3_set_multi (tp, 0);
7045         } else {
7046                 /* Accept one or more multicast(s). */
7047                 struct dev_mc_list *mclist;
7048                 unsigned int i;
7049                 u32 mc_filter[4] = { 0, };
7050                 u32 regidx;
7051                 u32 bit;
7052                 u32 crc;
7053
7054                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7055                      i++, mclist = mclist->next) {
7056
7057                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7058                         bit = ~crc & 0x7f;
7059                         regidx = (bit & 0x60) >> 5;
7060                         bit &= 0x1f;
7061                         mc_filter[regidx] |= (1 << bit);
7062                 }
7063
7064                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7065                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7066                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7067                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7068         }
7069
7070         if (rx_mode != tp->rx_mode) {
7071                 tp->rx_mode = rx_mode;
7072                 tw32_f(MAC_RX_MODE, rx_mode);
7073                 udelay(10);
7074         }
7075 }
7076
7077 static void tg3_set_rx_mode(struct net_device *dev)
7078 {
7079         struct tg3 *tp = netdev_priv(dev);
7080
7081         tg3_full_lock(tp, 0);
7082         __tg3_set_rx_mode(dev);
7083         tg3_full_unlock(tp);
7084 }
7085
7086 #define TG3_REGDUMP_LEN         (32 * 1024)
7087
7088 static int tg3_get_regs_len(struct net_device *dev)
7089 {
7090         return TG3_REGDUMP_LEN;
7091 }
7092
7093 static void tg3_get_regs(struct net_device *dev,
7094                 struct ethtool_regs *regs, void *_p)
7095 {
7096         u32 *p = _p;
7097         struct tg3 *tp = netdev_priv(dev);
7098         u8 *orig_p = _p;
7099         int i;
7100
7101         regs->version = 0;
7102
7103         memset(p, 0, TG3_REGDUMP_LEN);
7104
7105         tg3_full_lock(tp, 0);
7106
7107 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7108 #define GET_REG32_LOOP(base,len)                \
7109 do {    p = (u32 *)(orig_p + (base));           \
7110         for (i = 0; i < len; i += 4)            \
7111                 __GET_REG32((base) + i);        \
7112 } while (0)
7113 #define GET_REG32_1(reg)                        \
7114 do {    p = (u32 *)(orig_p + (reg));            \
7115         __GET_REG32((reg));                     \
7116 } while (0)
7117
7118         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7119         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7120         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7121         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7122         GET_REG32_1(SNDDATAC_MODE);
7123         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7124         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7125         GET_REG32_1(SNDBDC_MODE);
7126         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7127         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7128         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7129         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7130         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7131         GET_REG32_1(RCVDCC_MODE);
7132         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7133         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7134         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7135         GET_REG32_1(MBFREE_MODE);
7136         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7137         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7138         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7139         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7140         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7141         GET_REG32_LOOP(RX_CPU_BASE, 0x280);
7142         GET_REG32_LOOP(TX_CPU_BASE, 0x280);
7143         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7144         GET_REG32_LOOP(FTQ_RESET, 0x120);
7145         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7146         GET_REG32_1(DMAC_MODE);
7147         GET_REG32_LOOP(GRC_MODE, 0x4c);
7148         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7149                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7150
7151 #undef __GET_REG32
7152 #undef GET_REG32_LOOP
7153 #undef GET_REG32_1
7154
7155         tg3_full_unlock(tp);
7156 }
7157
7158 static int tg3_get_eeprom_len(struct net_device *dev)
7159 {
7160         struct tg3 *tp = netdev_priv(dev);
7161
7162         return tp->nvram_size;
7163 }
7164
7165 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7166
7167 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7168 {
7169         struct tg3 *tp = netdev_priv(dev);
7170         int ret;
7171         u8  *pd;
7172         u32 i, offset, len, val, b_offset, b_count;
7173
7174         offset = eeprom->offset;
7175         len = eeprom->len;
7176         eeprom->len = 0;
7177
7178         eeprom->magic = TG3_EEPROM_MAGIC;
7179
7180         if (offset & 3) {
7181                 /* adjustments to start on required 4 byte boundary */
7182                 b_offset = offset & 3;
7183                 b_count = 4 - b_offset;
7184                 if (b_count > len) {
7185                         /* i.e. offset=1 len=2 */
7186                         b_count = len;
7187                 }
7188                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7189                 if (ret)
7190                         return ret;
7191                 val = cpu_to_le32(val);
7192                 memcpy(data, ((char*)&val) + b_offset, b_count);
7193                 len -= b_count;
7194                 offset += b_count;
7195                 eeprom->len += b_count;
7196         }
7197
7198         /* read bytes upto the last 4 byte boundary */
7199         pd = &data[eeprom->len];
7200         for (i = 0; i < (len - (len & 3)); i += 4) {
7201                 ret = tg3_nvram_read(tp, offset + i, &val);
7202                 if (ret) {
7203                         eeprom->len += i;
7204                         return ret;
7205                 }
7206                 val = cpu_to_le32(val);
7207                 memcpy(pd + i, &val, 4);
7208         }
7209         eeprom->len += i;
7210
7211         if (len & 3) {
7212                 /* read last bytes not ending on 4 byte boundary */
7213                 pd = &data[eeprom->len];
7214                 b_count = len & 3;
7215                 b_offset = offset + len - b_count;
7216                 ret = tg3_nvram_read(tp, b_offset, &val);
7217                 if (ret)
7218                         return ret;
7219                 val = cpu_to_le32(val);
7220                 memcpy(pd, ((char*)&val), b_count);
7221                 eeprom->len += b_count;
7222         }
7223         return 0;
7224 }
7225
7226 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7227
7228 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7229 {
7230         struct tg3 *tp = netdev_priv(dev);
7231         int ret;
7232         u32 offset, len, b_offset, odd_len, start, end;
7233         u8 *buf;
7234
7235         if (eeprom->magic != TG3_EEPROM_MAGIC)
7236                 return -EINVAL;
7237
7238         offset = eeprom->offset;
7239         len = eeprom->len;
7240
7241         if ((b_offset = (offset & 3))) {
7242                 /* adjustments to start on required 4 byte boundary */
7243                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7244                 if (ret)
7245                         return ret;
7246                 start = cpu_to_le32(start);
7247                 len += b_offset;
7248                 offset &= ~3;
7249                 if (len < 4)
7250                         len = 4;
7251         }
7252
7253         odd_len = 0;
7254         if (len & 3) {
7255                 /* adjustments to end on required 4 byte boundary */
7256                 odd_len = 1;
7257                 len = (len + 3) & ~3;
7258                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7259                 if (ret)
7260                         return ret;
7261                 end = cpu_to_le32(end);
7262         }
7263
7264         buf = data;
7265         if (b_offset || odd_len) {
7266                 buf = kmalloc(len, GFP_KERNEL);
7267                 if (buf == 0)
7268                         return -ENOMEM;
7269                 if (b_offset)
7270                         memcpy(buf, &start, 4);
7271                 if (odd_len)
7272                         memcpy(buf+len-4, &end, 4);
7273                 memcpy(buf + b_offset, data, eeprom->len);
7274         }
7275
7276         ret = tg3_nvram_write_block(tp, offset, len, buf);
7277
7278         if (buf != data)
7279                 kfree(buf);
7280
7281         return ret;
7282 }
7283
7284 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7285 {
7286         struct tg3 *tp = netdev_priv(dev);
7287
7288         cmd->supported = (SUPPORTED_Autoneg);
7289
7290         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7291                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7292                                    SUPPORTED_1000baseT_Full);
7293
7294         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
7295                 cmd->supported |= (SUPPORTED_100baseT_Half |
7296                                   SUPPORTED_100baseT_Full |
7297                                   SUPPORTED_10baseT_Half |
7298                                   SUPPORTED_10baseT_Full |
7299                                   SUPPORTED_MII);
7300         else
7301                 cmd->supported |= SUPPORTED_FIBRE;
7302
7303         cmd->advertising = tp->link_config.advertising;
7304         if (netif_running(dev)) {
7305                 cmd->speed = tp->link_config.active_speed;
7306                 cmd->duplex = tp->link_config.active_duplex;
7307         }
7308         cmd->port = 0;
7309         cmd->phy_address = PHY_ADDR;
7310         cmd->transceiver = 0;
7311         cmd->autoneg = tp->link_config.autoneg;
7312         cmd->maxtxpkt = 0;
7313         cmd->maxrxpkt = 0;
7314         return 0;
7315 }
7316
7317 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7318 {
7319         struct tg3 *tp = netdev_priv(dev);
7320
7321         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7322                 /* These are the only valid advertisement bits allowed.  */
7323                 if (cmd->autoneg == AUTONEG_ENABLE &&
7324                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7325                                           ADVERTISED_1000baseT_Full |
7326                                           ADVERTISED_Autoneg |
7327                                           ADVERTISED_FIBRE)))
7328                         return -EINVAL;
7329                 /* Fiber can only do SPEED_1000.  */
7330                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7331                          (cmd->speed != SPEED_1000))
7332                         return -EINVAL;
7333         /* Copper cannot force SPEED_1000.  */
7334         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7335                    (cmd->speed == SPEED_1000))
7336                 return -EINVAL;
7337         else if ((cmd->speed == SPEED_1000) &&
7338                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7339                 return -EINVAL;
7340
7341         tg3_full_lock(tp, 0);
7342
7343         tp->link_config.autoneg = cmd->autoneg;
7344         if (cmd->autoneg == AUTONEG_ENABLE) {
7345                 tp->link_config.advertising = cmd->advertising;
7346                 tp->link_config.speed = SPEED_INVALID;
7347                 tp->link_config.duplex = DUPLEX_INVALID;
7348         } else {
7349                 tp->link_config.advertising = 0;
7350                 tp->link_config.speed = cmd->speed;
7351                 tp->link_config.duplex = cmd->duplex;
7352         }
7353
7354         if (netif_running(dev))
7355                 tg3_setup_phy(tp, 1);
7356
7357         tg3_full_unlock(tp);
7358
7359         return 0;
7360 }
7361
7362 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7363 {
7364         struct tg3 *tp = netdev_priv(dev);
7365
7366         strcpy(info->driver, DRV_MODULE_NAME);
7367         strcpy(info->version, DRV_MODULE_VERSION);
7368         strcpy(info->bus_info, pci_name(tp->pdev));
7369 }
7370
7371 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7372 {
7373         struct tg3 *tp = netdev_priv(dev);
7374
7375         wol->supported = WAKE_MAGIC;
7376         wol->wolopts = 0;
7377         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
7378                 wol->wolopts = WAKE_MAGIC;
7379         memset(&wol->sopass, 0, sizeof(wol->sopass));
7380 }
7381
7382 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
7383 {
7384         struct tg3 *tp = netdev_priv(dev);
7385
7386         if (wol->wolopts & ~WAKE_MAGIC)
7387                 return -EINVAL;
7388         if ((wol->wolopts & WAKE_MAGIC) &&
7389             tp->tg3_flags2 & TG3_FLG2_PHY_SERDES &&
7390             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
7391                 return -EINVAL;
7392
7393         spin_lock_bh(&tp->lock);
7394         if (wol->wolopts & WAKE_MAGIC)
7395                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
7396         else
7397                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
7398         spin_unlock_bh(&tp->lock);
7399
7400         return 0;
7401 }
7402
7403 static u32 tg3_get_msglevel(struct net_device *dev)
7404 {
7405         struct tg3 *tp = netdev_priv(dev);
7406         return tp->msg_enable;
7407 }
7408
7409 static void tg3_set_msglevel(struct net_device *dev, u32 value)
7410 {
7411         struct tg3 *tp = netdev_priv(dev);
7412         tp->msg_enable = value;
7413 }
7414
7415 #if TG3_TSO_SUPPORT != 0
7416 static int tg3_set_tso(struct net_device *dev, u32 value)
7417 {
7418         struct tg3 *tp = netdev_priv(dev);
7419
7420         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7421                 if (value)
7422                         return -EINVAL;
7423                 return 0;
7424         }
7425         return ethtool_op_set_tso(dev, value);
7426 }
7427 #endif
7428
7429 static int tg3_nway_reset(struct net_device *dev)
7430 {
7431         struct tg3 *tp = netdev_priv(dev);
7432         u32 bmcr;
7433         int r;
7434
7435         if (!netif_running(dev))
7436                 return -EAGAIN;
7437
7438         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
7439                 return -EINVAL;
7440
7441         spin_lock_bh(&tp->lock);
7442         r = -EINVAL;
7443         tg3_readphy(tp, MII_BMCR, &bmcr);
7444         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
7445             ((bmcr & BMCR_ANENABLE) ||
7446              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
7447                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
7448                                            BMCR_ANENABLE);
7449                 r = 0;
7450         }
7451         spin_unlock_bh(&tp->lock);
7452
7453         return r;
7454 }
7455
7456 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7457 {
7458         struct tg3 *tp = netdev_priv(dev);
7459
7460         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
7461         ering->rx_mini_max_pending = 0;
7462         ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
7463
7464         ering->rx_pending = tp->rx_pending;
7465         ering->rx_mini_pending = 0;
7466         ering->rx_jumbo_pending = tp->rx_jumbo_pending;
7467         ering->tx_pending = tp->tx_pending;
7468 }
7469
7470 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
7471 {
7472         struct tg3 *tp = netdev_priv(dev);
7473         int irq_sync = 0;
7474
7475         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
7476             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
7477             (ering->tx_pending > TG3_TX_RING_SIZE - 1))
7478                 return -EINVAL;
7479
7480         if (netif_running(dev)) {
7481                 tg3_netif_stop(tp);
7482                 irq_sync = 1;
7483         }
7484
7485         tg3_full_lock(tp, irq_sync);
7486
7487         tp->rx_pending = ering->rx_pending;
7488
7489         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
7490             tp->rx_pending > 63)
7491                 tp->rx_pending = 63;
7492         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
7493         tp->tx_pending = ering->tx_pending;
7494
7495         if (netif_running(dev)) {
7496                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7497                 tg3_init_hw(tp);
7498                 tg3_netif_start(tp);
7499         }
7500
7501         tg3_full_unlock(tp);
7502
7503         return 0;
7504 }
7505
7506 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7507 {
7508         struct tg3 *tp = netdev_priv(dev);
7509
7510         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
7511         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
7512         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
7513 }
7514
7515 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
7516 {
7517         struct tg3 *tp = netdev_priv(dev);
7518         int irq_sync = 0;
7519
7520         if (netif_running(dev)) {
7521                 tg3_netif_stop(tp);
7522                 irq_sync = 1;
7523         }
7524
7525         tg3_full_lock(tp, irq_sync);
7526
7527         if (epause->autoneg)
7528                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
7529         else
7530                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
7531         if (epause->rx_pause)
7532                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
7533         else
7534                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
7535         if (epause->tx_pause)
7536                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
7537         else
7538                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
7539
7540         if (netif_running(dev)) {
7541                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7542                 tg3_init_hw(tp);
7543                 tg3_netif_start(tp);
7544         }
7545
7546         tg3_full_unlock(tp);
7547
7548         return 0;
7549 }
7550
7551 static u32 tg3_get_rx_csum(struct net_device *dev)
7552 {
7553         struct tg3 *tp = netdev_priv(dev);
7554         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
7555 }
7556
7557 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
7558 {
7559         struct tg3 *tp = netdev_priv(dev);
7560
7561         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7562                 if (data != 0)
7563                         return -EINVAL;
7564                 return 0;
7565         }
7566
7567         spin_lock_bh(&tp->lock);
7568         if (data)
7569                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
7570         else
7571                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
7572         spin_unlock_bh(&tp->lock);
7573
7574         return 0;
7575 }
7576
7577 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
7578 {
7579         struct tg3 *tp = netdev_priv(dev);
7580
7581         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
7582                 if (data != 0)
7583                         return -EINVAL;
7584                 return 0;
7585         }
7586
7587         if (data)
7588                 dev->features |= NETIF_F_IP_CSUM;
7589         else
7590                 dev->features &= ~NETIF_F_IP_CSUM;
7591
7592         return 0;
7593 }
7594
7595 static int tg3_get_stats_count (struct net_device *dev)
7596 {
7597         return TG3_NUM_STATS;
7598 }
7599
7600 static int tg3_get_test_count (struct net_device *dev)
7601 {
7602         return TG3_NUM_TEST;
7603 }
7604
7605 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
7606 {
7607         switch (stringset) {
7608         case ETH_SS_STATS:
7609                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
7610                 break;
7611         case ETH_SS_TEST:
7612                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
7613                 break;
7614         default:
7615                 WARN_ON(1);     /* we need a WARN() */
7616                 break;
7617         }
7618 }
7619
7620 static int tg3_phys_id(struct net_device *dev, u32 data)
7621 {
7622         struct tg3 *tp = netdev_priv(dev);
7623         int i;
7624
7625         if (!netif_running(tp->dev))
7626                 return -EAGAIN;
7627
7628         if (data == 0)
7629                 data = 2;
7630
7631         for (i = 0; i < (data * 2); i++) {
7632                 if ((i % 2) == 0)
7633                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7634                                            LED_CTRL_1000MBPS_ON |
7635                                            LED_CTRL_100MBPS_ON |
7636                                            LED_CTRL_10MBPS_ON |
7637                                            LED_CTRL_TRAFFIC_OVERRIDE |
7638                                            LED_CTRL_TRAFFIC_BLINK |
7639                                            LED_CTRL_TRAFFIC_LED);
7640
7641                 else
7642                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
7643                                            LED_CTRL_TRAFFIC_OVERRIDE);
7644
7645                 if (msleep_interruptible(500))
7646                         break;
7647         }
7648         tw32(MAC_LED_CTRL, tp->led_ctrl);
7649         return 0;
7650 }
7651
7652 static void tg3_get_ethtool_stats (struct net_device *dev,
7653                                    struct ethtool_stats *estats, u64 *tmp_stats)
7654 {
7655         struct tg3 *tp = netdev_priv(dev);
7656         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
7657 }
7658
7659 #define NVRAM_TEST_SIZE 0x100
7660
7661 static int tg3_test_nvram(struct tg3 *tp)
7662 {
7663         u32 *buf, csum;
7664         int i, j, err = 0;
7665
7666         buf = kmalloc(NVRAM_TEST_SIZE, GFP_KERNEL);
7667         if (buf == NULL)
7668                 return -ENOMEM;
7669
7670         for (i = 0, j = 0; i < NVRAM_TEST_SIZE; i += 4, j++) {
7671                 u32 val;
7672
7673                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
7674                         break;
7675                 buf[j] = cpu_to_le32(val);
7676         }
7677         if (i < NVRAM_TEST_SIZE)
7678                 goto out;
7679
7680         err = -EIO;
7681         if (cpu_to_be32(buf[0]) != TG3_EEPROM_MAGIC)
7682                 goto out;
7683
7684         /* Bootstrap checksum at offset 0x10 */
7685         csum = calc_crc((unsigned char *) buf, 0x10);
7686         if(csum != cpu_to_le32(buf[0x10/4]))
7687                 goto out;
7688
7689         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
7690         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
7691         if (csum != cpu_to_le32(buf[0xfc/4]))
7692                  goto out;
7693
7694         err = 0;
7695
7696 out:
7697         kfree(buf);
7698         return err;
7699 }
7700
7701 #define TG3_SERDES_TIMEOUT_SEC  2
7702 #define TG3_COPPER_TIMEOUT_SEC  6
7703
7704 static int tg3_test_link(struct tg3 *tp)
7705 {
7706         int i, max;
7707
7708         if (!netif_running(tp->dev))
7709                 return -ENODEV;
7710
7711         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
7712                 max = TG3_SERDES_TIMEOUT_SEC;
7713         else
7714                 max = TG3_COPPER_TIMEOUT_SEC;
7715
7716         for (i = 0; i < max; i++) {
7717                 if (netif_carrier_ok(tp->dev))
7718                         return 0;
7719
7720                 if (msleep_interruptible(1000))
7721                         break;
7722         }
7723
7724         return -EIO;
7725 }
7726
7727 /* Only test the commonly used registers */
7728 static int tg3_test_registers(struct tg3 *tp)
7729 {
7730         int i, is_5705;
7731         u32 offset, read_mask, write_mask, val, save_val, read_val;
7732         static struct {
7733                 u16 offset;
7734                 u16 flags;
7735 #define TG3_FL_5705     0x1
7736 #define TG3_FL_NOT_5705 0x2
7737 #define TG3_FL_NOT_5788 0x4
7738                 u32 read_mask;
7739                 u32 write_mask;
7740         } reg_tbl[] = {
7741                 /* MAC Control Registers */
7742                 { MAC_MODE, TG3_FL_NOT_5705,
7743                         0x00000000, 0x00ef6f8c },
7744                 { MAC_MODE, TG3_FL_5705,
7745                         0x00000000, 0x01ef6b8c },
7746                 { MAC_STATUS, TG3_FL_NOT_5705,
7747                         0x03800107, 0x00000000 },
7748                 { MAC_STATUS, TG3_FL_5705,
7749                         0x03800100, 0x00000000 },
7750                 { MAC_ADDR_0_HIGH, 0x0000,
7751                         0x00000000, 0x0000ffff },
7752                 { MAC_ADDR_0_LOW, 0x0000,
7753                         0x00000000, 0xffffffff },
7754                 { MAC_RX_MTU_SIZE, 0x0000,
7755                         0x00000000, 0x0000ffff },
7756                 { MAC_TX_MODE, 0x0000,
7757                         0x00000000, 0x00000070 },
7758                 { MAC_TX_LENGTHS, 0x0000,
7759                         0x00000000, 0x00003fff },
7760                 { MAC_RX_MODE, TG3_FL_NOT_5705,
7761                         0x00000000, 0x000007fc },
7762                 { MAC_RX_MODE, TG3_FL_5705,
7763                         0x00000000, 0x000007dc },
7764                 { MAC_HASH_REG_0, 0x0000,
7765                         0x00000000, 0xffffffff },
7766                 { MAC_HASH_REG_1, 0x0000,
7767                         0x00000000, 0xffffffff },
7768                 { MAC_HASH_REG_2, 0x0000,
7769                         0x00000000, 0xffffffff },
7770                 { MAC_HASH_REG_3, 0x0000,
7771                         0x00000000, 0xffffffff },
7772
7773                 /* Receive Data and Receive BD Initiator Control Registers. */
7774                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
7775                         0x00000000, 0xffffffff },
7776                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
7777                         0x00000000, 0xffffffff },
7778                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
7779                         0x00000000, 0x00000003 },
7780                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
7781                         0x00000000, 0xffffffff },
7782                 { RCVDBDI_STD_BD+0, 0x0000,
7783                         0x00000000, 0xffffffff },
7784                 { RCVDBDI_STD_BD+4, 0x0000,
7785                         0x00000000, 0xffffffff },
7786                 { RCVDBDI_STD_BD+8, 0x0000,
7787                         0x00000000, 0xffff0002 },
7788                 { RCVDBDI_STD_BD+0xc, 0x0000,
7789                         0x00000000, 0xffffffff },
7790
7791                 /* Receive BD Initiator Control Registers. */
7792                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
7793                         0x00000000, 0xffffffff },
7794                 { RCVBDI_STD_THRESH, TG3_FL_5705,
7795                         0x00000000, 0x000003ff },
7796                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
7797                         0x00000000, 0xffffffff },
7798
7799                 /* Host Coalescing Control Registers. */
7800                 { HOSTCC_MODE, TG3_FL_NOT_5705,
7801                         0x00000000, 0x00000004 },
7802                 { HOSTCC_MODE, TG3_FL_5705,
7803                         0x00000000, 0x000000f6 },
7804                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
7805                         0x00000000, 0xffffffff },
7806                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
7807                         0x00000000, 0x000003ff },
7808                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
7809                         0x00000000, 0xffffffff },
7810                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
7811                         0x00000000, 0x000003ff },
7812                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
7813                         0x00000000, 0xffffffff },
7814                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7815                         0x00000000, 0x000000ff },
7816                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
7817                         0x00000000, 0xffffffff },
7818                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
7819                         0x00000000, 0x000000ff },
7820                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
7821                         0x00000000, 0xffffffff },
7822                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
7823                         0x00000000, 0xffffffff },
7824                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7825                         0x00000000, 0xffffffff },
7826                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7827                         0x00000000, 0x000000ff },
7828                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
7829                         0x00000000, 0xffffffff },
7830                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
7831                         0x00000000, 0x000000ff },
7832                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
7833                         0x00000000, 0xffffffff },
7834                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
7835                         0x00000000, 0xffffffff },
7836                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
7837                         0x00000000, 0xffffffff },
7838                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
7839                         0x00000000, 0xffffffff },
7840                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
7841                         0x00000000, 0xffffffff },
7842                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
7843                         0xffffffff, 0x00000000 },
7844                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
7845                         0xffffffff, 0x00000000 },
7846
7847                 /* Buffer Manager Control Registers. */
7848                 { BUFMGR_MB_POOL_ADDR, 0x0000,
7849                         0x00000000, 0x007fff80 },
7850                 { BUFMGR_MB_POOL_SIZE, 0x0000,
7851                         0x00000000, 0x007fffff },
7852                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
7853                         0x00000000, 0x0000003f },
7854                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
7855                         0x00000000, 0x000001ff },
7856                 { BUFMGR_MB_HIGH_WATER, 0x0000,
7857                         0x00000000, 0x000001ff },
7858                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
7859                         0xffffffff, 0x00000000 },
7860                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
7861                         0xffffffff, 0x00000000 },
7862
7863                 /* Mailbox Registers */
7864                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
7865                         0x00000000, 0x000001ff },
7866                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
7867                         0x00000000, 0x000001ff },
7868                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
7869                         0x00000000, 0x000007ff },
7870                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
7871                         0x00000000, 0x000001ff },
7872
7873                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
7874         };
7875
7876         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7877                 is_5705 = 1;
7878         else
7879                 is_5705 = 0;
7880
7881         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
7882                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
7883                         continue;
7884
7885                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
7886                         continue;
7887
7888                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
7889                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
7890                         continue;
7891
7892                 offset = (u32) reg_tbl[i].offset;
7893                 read_mask = reg_tbl[i].read_mask;
7894                 write_mask = reg_tbl[i].write_mask;
7895
7896                 /* Save the original register content */
7897                 save_val = tr32(offset);
7898
7899                 /* Determine the read-only value. */
7900                 read_val = save_val & read_mask;
7901
7902                 /* Write zero to the register, then make sure the read-only bits
7903                  * are not changed and the read/write bits are all zeros.
7904                  */
7905                 tw32(offset, 0);
7906
7907                 val = tr32(offset);
7908
7909                 /* Test the read-only and read/write bits. */
7910                 if (((val & read_mask) != read_val) || (val & write_mask))
7911                         goto out;
7912
7913                 /* Write ones to all the bits defined by RdMask and WrMask, then
7914                  * make sure the read-only bits are not changed and the
7915                  * read/write bits are all ones.
7916                  */
7917                 tw32(offset, read_mask | write_mask);
7918
7919                 val = tr32(offset);
7920
7921                 /* Test the read-only bits. */
7922                 if ((val & read_mask) != read_val)
7923                         goto out;
7924
7925                 /* Test the read/write bits. */
7926                 if ((val & write_mask) != write_mask)
7927                         goto out;
7928
7929                 tw32(offset, save_val);
7930         }
7931
7932         return 0;
7933
7934 out:
7935         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
7936         tw32(offset, save_val);
7937         return -EIO;
7938 }
7939
7940 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
7941 {
7942         static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
7943         int i;
7944         u32 j;
7945
7946         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
7947                 for (j = 0; j < len; j += 4) {
7948                         u32 val;
7949
7950                         tg3_write_mem(tp, offset + j, test_pattern[i]);
7951                         tg3_read_mem(tp, offset + j, &val);
7952                         if (val != test_pattern[i])
7953                                 return -EIO;
7954                 }
7955         }
7956         return 0;
7957 }
7958
7959 static int tg3_test_memory(struct tg3 *tp)
7960 {
7961         static struct mem_entry {
7962                 u32 offset;
7963                 u32 len;
7964         } mem_tbl_570x[] = {
7965                 { 0x00000000, 0x01000},
7966                 { 0x00002000, 0x1c000},
7967                 { 0xffffffff, 0x00000}
7968         }, mem_tbl_5705[] = {
7969                 { 0x00000100, 0x0000c},
7970                 { 0x00000200, 0x00008},
7971                 { 0x00000b50, 0x00400},
7972                 { 0x00004000, 0x00800},
7973                 { 0x00006000, 0x01000},
7974                 { 0x00008000, 0x02000},
7975                 { 0x00010000, 0x0e000},
7976                 { 0xffffffff, 0x00000}
7977         };
7978         struct mem_entry *mem_tbl;
7979         int err = 0;
7980         int i;
7981
7982         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7983                 mem_tbl = mem_tbl_5705;
7984         else
7985                 mem_tbl = mem_tbl_570x;
7986
7987         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
7988                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
7989                     mem_tbl[i].len)) != 0)
7990                         break;
7991         }
7992
7993         return err;
7994 }
7995
7996 #define TG3_MAC_LOOPBACK        0
7997 #define TG3_PHY_LOOPBACK        1
7998
7999 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8000 {
8001         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8002         u32 desc_idx;
8003         struct sk_buff *skb, *rx_skb;
8004         u8 *tx_data;
8005         dma_addr_t map;
8006         int num_pkts, tx_len, rx_len, i, err;
8007         struct tg3_rx_buffer_desc *desc;
8008
8009         if (loopback_mode == TG3_MAC_LOOPBACK) {
8010                 /* HW errata - mac loopback fails in some cases on 5780.
8011                  * Normal traffic and PHY loopback are not affected by
8012                  * errata.
8013                  */
8014                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8015                         return 0;
8016
8017                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8018                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY |
8019                            MAC_MODE_PORT_MODE_GMII;
8020                 tw32(MAC_MODE, mac_mode);
8021         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8022                 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK | BMCR_FULLDPLX |
8023                                            BMCR_SPEED1000);
8024                 udelay(40);
8025                 /* reset to prevent losing 1st rx packet intermittently */
8026                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8027                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8028                         udelay(10);
8029                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8030                 }
8031                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8032                            MAC_MODE_LINK_POLARITY | MAC_MODE_PORT_MODE_GMII;
8033                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
8034                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8035                 tw32(MAC_MODE, mac_mode);
8036         }
8037         else
8038                 return -EINVAL;
8039
8040         err = -EIO;
8041
8042         tx_len = 1514;
8043         skb = dev_alloc_skb(tx_len);
8044         tx_data = skb_put(skb, tx_len);
8045         memcpy(tx_data, tp->dev->dev_addr, 6);
8046         memset(tx_data + 6, 0x0, 8);
8047
8048         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8049
8050         for (i = 14; i < tx_len; i++)
8051                 tx_data[i] = (u8) (i & 0xff);
8052
8053         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8054
8055         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8056              HOSTCC_MODE_NOW);
8057
8058         udelay(10);
8059
8060         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8061
8062         num_pkts = 0;
8063
8064         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8065
8066         tp->tx_prod++;
8067         num_pkts++;
8068
8069         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8070                      tp->tx_prod);
8071         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8072
8073         udelay(10);
8074
8075         for (i = 0; i < 10; i++) {
8076                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8077                        HOSTCC_MODE_NOW);
8078
8079                 udelay(10);
8080
8081                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8082                 rx_idx = tp->hw_status->idx[0].rx_producer;
8083                 if ((tx_idx == tp->tx_prod) &&
8084                     (rx_idx == (rx_start_idx + num_pkts)))
8085                         break;
8086         }
8087
8088         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8089         dev_kfree_skb(skb);
8090
8091         if (tx_idx != tp->tx_prod)
8092                 goto out;
8093
8094         if (rx_idx != rx_start_idx + num_pkts)
8095                 goto out;
8096
8097         desc = &tp->rx_rcb[rx_start_idx];
8098         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8099         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8100         if (opaque_key != RXD_OPAQUE_RING_STD)
8101                 goto out;
8102
8103         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8104             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8105                 goto out;
8106
8107         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8108         if (rx_len != tx_len)
8109                 goto out;
8110
8111         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8112
8113         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8114         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8115
8116         for (i = 14; i < tx_len; i++) {
8117                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8118                         goto out;
8119         }
8120         err = 0;
8121
8122         /* tg3_free_rings will unmap and free the rx_skb */
8123 out:
8124         return err;
8125 }
8126
8127 #define TG3_MAC_LOOPBACK_FAILED         1
8128 #define TG3_PHY_LOOPBACK_FAILED         2
8129 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8130                                          TG3_PHY_LOOPBACK_FAILED)
8131
8132 static int tg3_test_loopback(struct tg3 *tp)
8133 {
8134         int err = 0;
8135
8136         if (!netif_running(tp->dev))
8137                 return TG3_LOOPBACK_FAILED;
8138
8139         tg3_reset_hw(tp);
8140
8141         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8142                 err |= TG3_MAC_LOOPBACK_FAILED;
8143         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8144                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8145                         err |= TG3_PHY_LOOPBACK_FAILED;
8146         }
8147
8148         return err;
8149 }
8150
8151 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8152                           u64 *data)
8153 {
8154         struct tg3 *tp = netdev_priv(dev);
8155
8156         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8157
8158         if (tg3_test_nvram(tp) != 0) {
8159                 etest->flags |= ETH_TEST_FL_FAILED;
8160                 data[0] = 1;
8161         }
8162         if (tg3_test_link(tp) != 0) {
8163                 etest->flags |= ETH_TEST_FL_FAILED;
8164                 data[1] = 1;
8165         }
8166         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8167                 int irq_sync = 0;
8168
8169                 if (netif_running(dev)) {
8170                         tg3_netif_stop(tp);
8171                         irq_sync = 1;
8172                 }
8173
8174                 tg3_full_lock(tp, irq_sync);
8175
8176                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8177                 tg3_nvram_lock(tp);
8178                 tg3_halt_cpu(tp, RX_CPU_BASE);
8179                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8180                         tg3_halt_cpu(tp, TX_CPU_BASE);
8181                 tg3_nvram_unlock(tp);
8182
8183                 if (tg3_test_registers(tp) != 0) {
8184                         etest->flags |= ETH_TEST_FL_FAILED;
8185                         data[2] = 1;
8186                 }
8187                 if (tg3_test_memory(tp) != 0) {
8188                         etest->flags |= ETH_TEST_FL_FAILED;
8189                         data[3] = 1;
8190                 }
8191                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8192                         etest->flags |= ETH_TEST_FL_FAILED;
8193
8194                 tg3_full_unlock(tp);
8195
8196                 if (tg3_test_interrupt(tp) != 0) {
8197                         etest->flags |= ETH_TEST_FL_FAILED;
8198                         data[5] = 1;
8199                 }
8200
8201                 tg3_full_lock(tp, 0);
8202
8203                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8204                 if (netif_running(dev)) {
8205                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8206                         tg3_init_hw(tp);
8207                         tg3_netif_start(tp);
8208                 }
8209
8210                 tg3_full_unlock(tp);
8211         }
8212 }
8213
8214 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
8215 {
8216         struct mii_ioctl_data *data = if_mii(ifr);
8217         struct tg3 *tp = netdev_priv(dev);
8218         int err;
8219
8220         switch(cmd) {
8221         case SIOCGMIIPHY:
8222                 data->phy_id = PHY_ADDR;
8223
8224                 /* fallthru */
8225         case SIOCGMIIREG: {
8226                 u32 mii_regval;
8227
8228                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8229                         break;                  /* We have no PHY */
8230
8231                 spin_lock_bh(&tp->lock);
8232                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
8233                 spin_unlock_bh(&tp->lock);
8234
8235                 data->val_out = mii_regval;
8236
8237                 return err;
8238         }
8239
8240         case SIOCSMIIREG:
8241                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8242                         break;                  /* We have no PHY */
8243
8244                 if (!capable(CAP_NET_ADMIN))
8245                         return -EPERM;
8246
8247                 spin_lock_bh(&tp->lock);
8248                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
8249                 spin_unlock_bh(&tp->lock);
8250
8251                 return err;
8252
8253         default:
8254                 /* do nothing */
8255                 break;
8256         }
8257         return -EOPNOTSUPP;
8258 }
8259
8260 #if TG3_VLAN_TAG_USED
8261 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
8262 {
8263         struct tg3 *tp = netdev_priv(dev);
8264
8265         tg3_full_lock(tp, 0);
8266
8267         tp->vlgrp = grp;
8268
8269         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
8270         __tg3_set_rx_mode(dev);
8271
8272         tg3_full_unlock(tp);
8273 }
8274
8275 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
8276 {
8277         struct tg3 *tp = netdev_priv(dev);
8278
8279         tg3_full_lock(tp, 0);
8280         if (tp->vlgrp)
8281                 tp->vlgrp->vlan_devices[vid] = NULL;
8282         tg3_full_unlock(tp);
8283 }
8284 #endif
8285
8286 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8287 {
8288         struct tg3 *tp = netdev_priv(dev);
8289
8290         memcpy(ec, &tp->coal, sizeof(*ec));
8291         return 0;
8292 }
8293
8294 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
8295 {
8296         struct tg3 *tp = netdev_priv(dev);
8297         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
8298         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
8299
8300         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8301                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
8302                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
8303                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
8304                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
8305         }
8306
8307         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
8308             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
8309             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
8310             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
8311             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
8312             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
8313             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
8314             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
8315             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
8316             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
8317                 return -EINVAL;
8318
8319         /* No rx interrupts will be generated if both are zero */
8320         if ((ec->rx_coalesce_usecs == 0) &&
8321             (ec->rx_max_coalesced_frames == 0))
8322                 return -EINVAL;
8323
8324         /* No tx interrupts will be generated if both are zero */
8325         if ((ec->tx_coalesce_usecs == 0) &&
8326             (ec->tx_max_coalesced_frames == 0))
8327                 return -EINVAL;
8328
8329         /* Only copy relevant parameters, ignore all others. */
8330         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
8331         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
8332         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
8333         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
8334         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
8335         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
8336         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
8337         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
8338         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
8339
8340         if (netif_running(dev)) {
8341                 tg3_full_lock(tp, 0);
8342                 __tg3_set_coalesce(tp, &tp->coal);
8343                 tg3_full_unlock(tp);
8344         }
8345         return 0;
8346 }
8347
8348 static struct ethtool_ops tg3_ethtool_ops = {
8349         .get_settings           = tg3_get_settings,
8350         .set_settings           = tg3_set_settings,
8351         .get_drvinfo            = tg3_get_drvinfo,
8352         .get_regs_len           = tg3_get_regs_len,
8353         .get_regs               = tg3_get_regs,
8354         .get_wol                = tg3_get_wol,
8355         .set_wol                = tg3_set_wol,
8356         .get_msglevel           = tg3_get_msglevel,
8357         .set_msglevel           = tg3_set_msglevel,
8358         .nway_reset             = tg3_nway_reset,
8359         .get_link               = ethtool_op_get_link,
8360         .get_eeprom_len         = tg3_get_eeprom_len,
8361         .get_eeprom             = tg3_get_eeprom,
8362         .set_eeprom             = tg3_set_eeprom,
8363         .get_ringparam          = tg3_get_ringparam,
8364         .set_ringparam          = tg3_set_ringparam,
8365         .get_pauseparam         = tg3_get_pauseparam,
8366         .set_pauseparam         = tg3_set_pauseparam,
8367         .get_rx_csum            = tg3_get_rx_csum,
8368         .set_rx_csum            = tg3_set_rx_csum,
8369         .get_tx_csum            = ethtool_op_get_tx_csum,
8370         .set_tx_csum            = tg3_set_tx_csum,
8371         .get_sg                 = ethtool_op_get_sg,
8372         .set_sg                 = ethtool_op_set_sg,
8373 #if TG3_TSO_SUPPORT != 0
8374         .get_tso                = ethtool_op_get_tso,
8375         .set_tso                = tg3_set_tso,
8376 #endif
8377         .self_test_count        = tg3_get_test_count,
8378         .self_test              = tg3_self_test,
8379         .get_strings            = tg3_get_strings,
8380         .phys_id                = tg3_phys_id,
8381         .get_stats_count        = tg3_get_stats_count,
8382         .get_ethtool_stats      = tg3_get_ethtool_stats,
8383         .get_coalesce           = tg3_get_coalesce,
8384         .set_coalesce           = tg3_set_coalesce,
8385         .get_perm_addr          = ethtool_op_get_perm_addr,
8386 };
8387
8388 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
8389 {
8390         u32 cursize, val;
8391
8392         tp->nvram_size = EEPROM_CHIP_SIZE;
8393
8394         if (tg3_nvram_read(tp, 0, &val) != 0)
8395                 return;
8396
8397         if (swab32(val) != TG3_EEPROM_MAGIC)
8398                 return;
8399
8400         /*
8401          * Size the chip by reading offsets at increasing powers of two.
8402          * When we encounter our validation signature, we know the addressing
8403          * has wrapped around, and thus have our chip size.
8404          */
8405         cursize = 0x800;
8406
8407         while (cursize < tp->nvram_size) {
8408                 if (tg3_nvram_read(tp, cursize, &val) != 0)
8409                         return;
8410
8411                 if (swab32(val) == TG3_EEPROM_MAGIC)
8412                         break;
8413
8414                 cursize <<= 1;
8415         }
8416
8417         tp->nvram_size = cursize;
8418 }
8419
8420 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
8421 {
8422         u32 val;
8423
8424         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
8425                 if (val != 0) {
8426                         tp->nvram_size = (val >> 16) * 1024;
8427                         return;
8428                 }
8429         }
8430         tp->nvram_size = 0x20000;
8431 }
8432
8433 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
8434 {
8435         u32 nvcfg1;
8436
8437         nvcfg1 = tr32(NVRAM_CFG1);
8438         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
8439                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
8440         }
8441         else {
8442                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8443                 tw32(NVRAM_CFG1, nvcfg1);
8444         }
8445
8446         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
8447             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
8448                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
8449                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
8450                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8451                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8452                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8453                                 break;
8454                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
8455                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8456                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
8457                                 break;
8458                         case FLASH_VENDOR_ATMEL_EEPROM:
8459                                 tp->nvram_jedecnum = JEDEC_ATMEL;
8460                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8461                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8462                                 break;
8463                         case FLASH_VENDOR_ST:
8464                                 tp->nvram_jedecnum = JEDEC_ST;
8465                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
8466                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8467                                 break;
8468                         case FLASH_VENDOR_SAIFUN:
8469                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
8470                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
8471                                 break;
8472                         case FLASH_VENDOR_SST_SMALL:
8473                         case FLASH_VENDOR_SST_LARGE:
8474                                 tp->nvram_jedecnum = JEDEC_SST;
8475                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
8476                                 break;
8477                 }
8478         }
8479         else {
8480                 tp->nvram_jedecnum = JEDEC_ATMEL;
8481                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
8482                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8483         }
8484 }
8485
8486 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
8487 {
8488         u32 nvcfg1;
8489
8490         nvcfg1 = tr32(NVRAM_CFG1);
8491
8492         /* NVRAM protection for TPM */
8493         if (nvcfg1 & (1 << 27))
8494                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
8495
8496         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
8497                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
8498                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
8499                         tp->nvram_jedecnum = JEDEC_ATMEL;
8500                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8501                         break;
8502                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
8503                         tp->nvram_jedecnum = JEDEC_ATMEL;
8504                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8505                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8506                         break;
8507                 case FLASH_5752VENDOR_ST_M45PE10:
8508                 case FLASH_5752VENDOR_ST_M45PE20:
8509                 case FLASH_5752VENDOR_ST_M45PE40:
8510                         tp->nvram_jedecnum = JEDEC_ST;
8511                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
8512                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
8513                         break;
8514         }
8515
8516         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
8517                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
8518                         case FLASH_5752PAGE_SIZE_256:
8519                                 tp->nvram_pagesize = 256;
8520                                 break;
8521                         case FLASH_5752PAGE_SIZE_512:
8522                                 tp->nvram_pagesize = 512;
8523                                 break;
8524                         case FLASH_5752PAGE_SIZE_1K:
8525                                 tp->nvram_pagesize = 1024;
8526                                 break;
8527                         case FLASH_5752PAGE_SIZE_2K:
8528                                 tp->nvram_pagesize = 2048;
8529                                 break;
8530                         case FLASH_5752PAGE_SIZE_4K:
8531                                 tp->nvram_pagesize = 4096;
8532                                 break;
8533                         case FLASH_5752PAGE_SIZE_264:
8534                                 tp->nvram_pagesize = 264;
8535                                 break;
8536                 }
8537         }
8538         else {
8539                 /* For eeprom, set pagesize to maximum eeprom size */
8540                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
8541
8542                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
8543                 tw32(NVRAM_CFG1, nvcfg1);
8544         }
8545 }
8546
8547 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
8548 static void __devinit tg3_nvram_init(struct tg3 *tp)
8549 {
8550         int j;
8551
8552         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X)
8553                 return;
8554
8555         tw32_f(GRC_EEPROM_ADDR,
8556              (EEPROM_ADDR_FSM_RESET |
8557               (EEPROM_DEFAULT_CLOCK_PERIOD <<
8558                EEPROM_ADDR_CLKPERD_SHIFT)));
8559
8560         /* XXX schedule_timeout() ... */
8561         for (j = 0; j < 100; j++)
8562                 udelay(10);
8563
8564         /* Enable seeprom accesses. */
8565         tw32_f(GRC_LOCAL_CTRL,
8566              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
8567         udelay(100);
8568
8569         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
8570             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
8571                 tp->tg3_flags |= TG3_FLAG_NVRAM;
8572
8573                 tg3_nvram_lock(tp);
8574                 tg3_enable_nvram_access(tp);
8575
8576                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8577                         tg3_get_5752_nvram_info(tp);
8578                 else
8579                         tg3_get_nvram_info(tp);
8580
8581                 tg3_get_nvram_size(tp);
8582
8583                 tg3_disable_nvram_access(tp);
8584                 tg3_nvram_unlock(tp);
8585
8586         } else {
8587                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
8588
8589                 tg3_get_eeprom_size(tp);
8590         }
8591 }
8592
8593 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
8594                                         u32 offset, u32 *val)
8595 {
8596         u32 tmp;
8597         int i;
8598
8599         if (offset > EEPROM_ADDR_ADDR_MASK ||
8600             (offset % 4) != 0)
8601                 return -EINVAL;
8602
8603         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
8604                                         EEPROM_ADDR_DEVID_MASK |
8605                                         EEPROM_ADDR_READ);
8606         tw32(GRC_EEPROM_ADDR,
8607              tmp |
8608              (0 << EEPROM_ADDR_DEVID_SHIFT) |
8609              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
8610               EEPROM_ADDR_ADDR_MASK) |
8611              EEPROM_ADDR_READ | EEPROM_ADDR_START);
8612
8613         for (i = 0; i < 10000; i++) {
8614                 tmp = tr32(GRC_EEPROM_ADDR);
8615
8616                 if (tmp & EEPROM_ADDR_COMPLETE)
8617                         break;
8618                 udelay(100);
8619         }
8620         if (!(tmp & EEPROM_ADDR_COMPLETE))
8621                 return -EBUSY;
8622
8623         *val = tr32(GRC_EEPROM_DATA);
8624         return 0;
8625 }
8626
8627 #define NVRAM_CMD_TIMEOUT 10000
8628
8629 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
8630 {
8631         int i;
8632
8633         tw32(NVRAM_CMD, nvram_cmd);
8634         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
8635                 udelay(10);
8636                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
8637                         udelay(10);
8638                         break;
8639                 }
8640         }
8641         if (i == NVRAM_CMD_TIMEOUT) {
8642                 return -EBUSY;
8643         }
8644         return 0;
8645 }
8646
8647 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
8648 {
8649         int ret;
8650
8651         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8652                 printk(KERN_ERR PFX "Attempt to do nvram_read on Sun 570X\n");
8653                 return -EINVAL;
8654         }
8655
8656         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
8657                 return tg3_nvram_read_using_eeprom(tp, offset, val);
8658
8659         if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
8660                 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8661                 (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8662
8663                 offset = ((offset / tp->nvram_pagesize) <<
8664                           ATMEL_AT45DB0X1B_PAGE_POS) +
8665                         (offset % tp->nvram_pagesize);
8666         }
8667
8668         if (offset > NVRAM_ADDR_MSK)
8669                 return -EINVAL;
8670
8671         tg3_nvram_lock(tp);
8672
8673         tg3_enable_nvram_access(tp);
8674
8675         tw32(NVRAM_ADDR, offset);
8676         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
8677                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
8678
8679         if (ret == 0)
8680                 *val = swab32(tr32(NVRAM_RDDATA));
8681
8682         tg3_disable_nvram_access(tp);
8683
8684         tg3_nvram_unlock(tp);
8685
8686         return ret;
8687 }
8688
8689 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
8690                                     u32 offset, u32 len, u8 *buf)
8691 {
8692         int i, j, rc = 0;
8693         u32 val;
8694
8695         for (i = 0; i < len; i += 4) {
8696                 u32 addr, data;
8697
8698                 addr = offset + i;
8699
8700                 memcpy(&data, buf + i, 4);
8701
8702                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
8703
8704                 val = tr32(GRC_EEPROM_ADDR);
8705                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
8706
8707                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
8708                         EEPROM_ADDR_READ);
8709                 tw32(GRC_EEPROM_ADDR, val |
8710                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
8711                         (addr & EEPROM_ADDR_ADDR_MASK) |
8712                         EEPROM_ADDR_START |
8713                         EEPROM_ADDR_WRITE);
8714
8715                 for (j = 0; j < 10000; j++) {
8716                         val = tr32(GRC_EEPROM_ADDR);
8717
8718                         if (val & EEPROM_ADDR_COMPLETE)
8719                                 break;
8720                         udelay(100);
8721                 }
8722                 if (!(val & EEPROM_ADDR_COMPLETE)) {
8723                         rc = -EBUSY;
8724                         break;
8725                 }
8726         }
8727
8728         return rc;
8729 }
8730
8731 /* offset and length are dword aligned */
8732 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
8733                 u8 *buf)
8734 {
8735         int ret = 0;
8736         u32 pagesize = tp->nvram_pagesize;
8737         u32 pagemask = pagesize - 1;
8738         u32 nvram_cmd;
8739         u8 *tmp;
8740
8741         tmp = kmalloc(pagesize, GFP_KERNEL);
8742         if (tmp == NULL)
8743                 return -ENOMEM;
8744
8745         while (len) {
8746                 int j;
8747                 u32 phy_addr, page_off, size;
8748
8749                 phy_addr = offset & ~pagemask;
8750
8751                 for (j = 0; j < pagesize; j += 4) {
8752                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
8753                                                 (u32 *) (tmp + j))))
8754                                 break;
8755                 }
8756                 if (ret)
8757                         break;
8758
8759                 page_off = offset & pagemask;
8760                 size = pagesize;
8761                 if (len < size)
8762                         size = len;
8763
8764                 len -= size;
8765
8766                 memcpy(tmp + page_off, buf, size);
8767
8768                 offset = offset + (pagesize - page_off);
8769
8770                 /* Nvram lock released by tg3_nvram_read() above,
8771                  * so need to get it again.
8772                  */
8773                 tg3_nvram_lock(tp);
8774                 tg3_enable_nvram_access(tp);
8775
8776                 /*
8777                  * Before we can erase the flash page, we need
8778                  * to issue a special "write enable" command.
8779                  */
8780                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8781
8782                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8783                         break;
8784
8785                 /* Erase the target page */
8786                 tw32(NVRAM_ADDR, phy_addr);
8787
8788                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
8789                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
8790
8791                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8792                         break;
8793
8794                 /* Issue another write enable to start the write. */
8795                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8796
8797                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
8798                         break;
8799
8800                 for (j = 0; j < pagesize; j += 4) {
8801                         u32 data;
8802
8803                         data = *((u32 *) (tmp + j));
8804                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
8805
8806                         tw32(NVRAM_ADDR, phy_addr + j);
8807
8808                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
8809                                 NVRAM_CMD_WR;
8810
8811                         if (j == 0)
8812                                 nvram_cmd |= NVRAM_CMD_FIRST;
8813                         else if (j == (pagesize - 4))
8814                                 nvram_cmd |= NVRAM_CMD_LAST;
8815
8816                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8817                                 break;
8818                 }
8819                 if (ret)
8820                         break;
8821         }
8822
8823         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
8824         tg3_nvram_exec_cmd(tp, nvram_cmd);
8825
8826         kfree(tmp);
8827
8828         return ret;
8829 }
8830
8831 /* offset and length are dword aligned */
8832 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
8833                 u8 *buf)
8834 {
8835         int i, ret = 0;
8836
8837         for (i = 0; i < len; i += 4, offset += 4) {
8838                 u32 data, page_off, phy_addr, nvram_cmd;
8839
8840                 memcpy(&data, buf + i, 4);
8841                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
8842
8843                 page_off = offset % tp->nvram_pagesize;
8844
8845                 if ((tp->tg3_flags2 & TG3_FLG2_FLASH) &&
8846                         (tp->nvram_jedecnum == JEDEC_ATMEL)) {
8847
8848                         phy_addr = ((offset / tp->nvram_pagesize) <<
8849                                     ATMEL_AT45DB0X1B_PAGE_POS) + page_off;
8850                 }
8851                 else {
8852                         phy_addr = offset;
8853                 }
8854
8855                 tw32(NVRAM_ADDR, phy_addr);
8856
8857                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
8858
8859                 if ((page_off == 0) || (i == 0))
8860                         nvram_cmd |= NVRAM_CMD_FIRST;
8861                 else if (page_off == (tp->nvram_pagesize - 4))
8862                         nvram_cmd |= NVRAM_CMD_LAST;
8863
8864                 if (i == (len - 4))
8865                         nvram_cmd |= NVRAM_CMD_LAST;
8866
8867                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
8868                     (tp->nvram_jedecnum == JEDEC_ST) &&
8869                     (nvram_cmd & NVRAM_CMD_FIRST)) {
8870
8871                         if ((ret = tg3_nvram_exec_cmd(tp,
8872                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
8873                                 NVRAM_CMD_DONE)))
8874
8875                                 break;
8876                 }
8877                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8878                         /* We always do complete word writes to eeprom. */
8879                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
8880                 }
8881
8882                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
8883                         break;
8884         }
8885         return ret;
8886 }
8887
8888 /* offset and length are dword aligned */
8889 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
8890 {
8891         int ret;
8892
8893         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
8894                 printk(KERN_ERR PFX "Attempt to do nvram_write on Sun 570X\n");
8895                 return -EINVAL;
8896         }
8897
8898         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8899                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
8900                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
8901                 udelay(40);
8902         }
8903
8904         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
8905                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
8906         }
8907         else {
8908                 u32 grc_mode;
8909
8910                 tg3_nvram_lock(tp);
8911
8912                 tg3_enable_nvram_access(tp);
8913                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
8914                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
8915                         tw32(NVRAM_WRITE1, 0x406);
8916
8917                 grc_mode = tr32(GRC_MODE);
8918                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
8919
8920                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
8921                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
8922
8923                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
8924                                 buf);
8925                 }
8926                 else {
8927                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
8928                                 buf);
8929                 }
8930
8931                 grc_mode = tr32(GRC_MODE);
8932                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
8933
8934                 tg3_disable_nvram_access(tp);
8935                 tg3_nvram_unlock(tp);
8936         }
8937
8938         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
8939                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8940                 udelay(40);
8941         }
8942
8943         return ret;
8944 }
8945
8946 struct subsys_tbl_ent {
8947         u16 subsys_vendor, subsys_devid;
8948         u32 phy_id;
8949 };
8950
8951 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
8952         /* Broadcom boards. */
8953         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
8954         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
8955         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
8956         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
8957         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
8958         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
8959         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
8960         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
8961         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
8962         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
8963         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
8964
8965         /* 3com boards. */
8966         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
8967         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
8968         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
8969         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
8970         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
8971
8972         /* DELL boards. */
8973         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
8974         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
8975         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
8976         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
8977
8978         /* Compaq boards. */
8979         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
8980         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
8981         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
8982         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
8983         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
8984
8985         /* IBM boards. */
8986         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
8987 };
8988
8989 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
8990 {
8991         int i;
8992
8993         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
8994                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
8995                      tp->pdev->subsystem_vendor) &&
8996                     (subsys_id_to_phy_id[i].subsys_devid ==
8997                      tp->pdev->subsystem_device))
8998                         return &subsys_id_to_phy_id[i];
8999         }
9000         return NULL;
9001 }
9002
9003 /* Since this function may be called in D3-hot power state during
9004  * tg3_init_one(), only config cycles are allowed.
9005  */
9006 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9007 {
9008         u32 val;
9009
9010         /* Make sure register accesses (indirect or otherwise)
9011          * will function correctly.
9012          */
9013         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9014                                tp->misc_host_ctrl);
9015
9016         tp->phy_id = PHY_ID_INVALID;
9017         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9018
9019         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9020         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9021                 u32 nic_cfg, led_cfg;
9022                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9023                 int eeprom_phy_serdes = 0;
9024
9025                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9026                 tp->nic_sram_data_cfg = nic_cfg;
9027
9028                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9029                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9030                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9031                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9032                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9033                     (ver > 0) && (ver < 0x100))
9034                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9035
9036                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9037                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
9038                         eeprom_phy_serdes = 1;
9039
9040                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
9041                 if (nic_phy_id != 0) {
9042                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
9043                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
9044
9045                         eeprom_phy_id  = (id1 >> 16) << 10;
9046                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
9047                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
9048                 } else
9049                         eeprom_phy_id = 0;
9050
9051                 tp->phy_id = eeprom_phy_id;
9052                 if (eeprom_phy_serdes) {
9053                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
9054                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
9055                         else
9056                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9057                 }
9058
9059                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9060                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
9061                                     SHASTA_EXT_LED_MODE_MASK);
9062                 else
9063                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
9064
9065                 switch (led_cfg) {
9066                 default:
9067                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
9068                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9069                         break;
9070
9071                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
9072                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9073                         break;
9074
9075                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
9076                         tp->led_ctrl = LED_CTRL_MODE_MAC;
9077
9078                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
9079                          * read on some older 5700/5701 bootcode.
9080                          */
9081                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
9082                             ASIC_REV_5700 ||
9083                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
9084                             ASIC_REV_5701)
9085                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9086
9087                         break;
9088
9089                 case SHASTA_EXT_LED_SHARED:
9090                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
9091                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
9092                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
9093                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9094                                                  LED_CTRL_MODE_PHY_2);
9095                         break;
9096
9097                 case SHASTA_EXT_LED_MAC:
9098                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
9099                         break;
9100
9101                 case SHASTA_EXT_LED_COMBO:
9102                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
9103                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
9104                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
9105                                                  LED_CTRL_MODE_PHY_2);
9106                         break;
9107
9108                 };
9109
9110                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9111                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
9112                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
9113                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
9114
9115                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9116                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9117                     (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
9118                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9119
9120                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
9121                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
9122                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9123                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
9124                 }
9125                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
9126                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
9127
9128                 if (cfg2 & (1 << 17))
9129                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
9130
9131                 /* serdes signal pre-emphasis in register 0x590 set by */
9132                 /* bootcode if bit 18 is set */
9133                 if (cfg2 & (1 << 18))
9134                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
9135         }
9136 }
9137
9138 static int __devinit tg3_phy_probe(struct tg3 *tp)
9139 {
9140         u32 hw_phy_id_1, hw_phy_id_2;
9141         u32 hw_phy_id, hw_phy_id_masked;
9142         int err;
9143
9144         /* Reading the PHY ID register can conflict with ASF
9145          * firwmare access to the PHY hardware.
9146          */
9147         err = 0;
9148         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
9149                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
9150         } else {
9151                 /* Now read the physical PHY_ID from the chip and verify
9152                  * that it is sane.  If it doesn't look good, we fall back
9153                  * to either the hard-coded table based PHY_ID and failing
9154                  * that the value found in the eeprom area.
9155                  */
9156                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
9157                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
9158
9159                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
9160                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
9161                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
9162
9163                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
9164         }
9165
9166         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
9167                 tp->phy_id = hw_phy_id;
9168                 if (hw_phy_id_masked == PHY_ID_BCM8002)
9169                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9170                 else
9171                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
9172         } else {
9173                 if (tp->phy_id != PHY_ID_INVALID) {
9174                         /* Do nothing, phy ID already set up in
9175                          * tg3_get_eeprom_hw_cfg().
9176                          */
9177                 } else {
9178                         struct subsys_tbl_ent *p;
9179
9180                         /* No eeprom signature?  Try the hardcoded
9181                          * subsys device table.
9182                          */
9183                         p = lookup_by_subsys(tp);
9184                         if (!p)
9185                                 return -ENODEV;
9186
9187                         tp->phy_id = p->phy_id;
9188                         if (!tp->phy_id ||
9189                             tp->phy_id == PHY_ID_BCM8002)
9190                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
9191                 }
9192         }
9193
9194         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
9195             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
9196                 u32 bmsr, adv_reg, tg3_ctrl;
9197
9198                 tg3_readphy(tp, MII_BMSR, &bmsr);
9199                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
9200                     (bmsr & BMSR_LSTATUS))
9201                         goto skip_phy_reset;
9202
9203                 err = tg3_phy_reset(tp);
9204                 if (err)
9205                         return err;
9206
9207                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
9208                            ADVERTISE_100HALF | ADVERTISE_100FULL |
9209                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
9210                 tg3_ctrl = 0;
9211                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
9212                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
9213                                     MII_TG3_CTRL_ADV_1000_FULL);
9214                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9215                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
9216                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
9217                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
9218                 }
9219
9220                 if (!tg3_copper_is_advertising_all(tp)) {
9221                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9222
9223                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9224                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9225
9226                         tg3_writephy(tp, MII_BMCR,
9227                                      BMCR_ANENABLE | BMCR_ANRESTART);
9228                 }
9229                 tg3_phy_set_wirespeed(tp);
9230
9231                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
9232                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9233                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
9234         }
9235
9236 skip_phy_reset:
9237         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
9238                 err = tg3_init_5401phy_dsp(tp);
9239                 if (err)
9240                         return err;
9241         }
9242
9243         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
9244                 err = tg3_init_5401phy_dsp(tp);
9245         }
9246
9247         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
9248                 tp->link_config.advertising =
9249                         (ADVERTISED_1000baseT_Half |
9250                          ADVERTISED_1000baseT_Full |
9251                          ADVERTISED_Autoneg |
9252                          ADVERTISED_FIBRE);
9253         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
9254                 tp->link_config.advertising &=
9255                         ~(ADVERTISED_1000baseT_Half |
9256                           ADVERTISED_1000baseT_Full);
9257
9258         return err;
9259 }
9260
9261 static void __devinit tg3_read_partno(struct tg3 *tp)
9262 {
9263         unsigned char vpd_data[256];
9264         int i;
9265
9266         if (tp->tg3_flags2 & TG3_FLG2_SUN_570X) {
9267                 /* Sun decided not to put the necessary bits in the
9268                  * NVRAM of their onboard tg3 parts :(
9269                  */
9270                 strcpy(tp->board_part_number, "Sun 570X");
9271                 return;
9272         }
9273
9274         for (i = 0; i < 256; i += 4) {
9275                 u32 tmp;
9276
9277                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
9278                         goto out_not_found;
9279
9280                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
9281                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
9282                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
9283                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
9284         }
9285
9286         /* Now parse and find the part number. */
9287         for (i = 0; i < 256; ) {
9288                 unsigned char val = vpd_data[i];
9289                 int block_end;
9290
9291                 if (val == 0x82 || val == 0x91) {
9292                         i = (i + 3 +
9293                              (vpd_data[i + 1] +
9294                               (vpd_data[i + 2] << 8)));
9295                         continue;
9296                 }
9297
9298                 if (val != 0x90)
9299                         goto out_not_found;
9300
9301                 block_end = (i + 3 +
9302                              (vpd_data[i + 1] +
9303                               (vpd_data[i + 2] << 8)));
9304                 i += 3;
9305                 while (i < block_end) {
9306                         if (vpd_data[i + 0] == 'P' &&
9307                             vpd_data[i + 1] == 'N') {
9308                                 int partno_len = vpd_data[i + 2];
9309
9310                                 if (partno_len > 24)
9311                                         goto out_not_found;
9312
9313                                 memcpy(tp->board_part_number,
9314                                        &vpd_data[i + 3],
9315                                        partno_len);
9316
9317                                 /* Success. */
9318                                 return;
9319                         }
9320                 }
9321
9322                 /* Part number not found. */
9323                 goto out_not_found;
9324         }
9325
9326 out_not_found:
9327         strcpy(tp->board_part_number, "none");
9328 }
9329
9330 #ifdef CONFIG_SPARC64
9331 static int __devinit tg3_is_sun_570X(struct tg3 *tp)
9332 {
9333         struct pci_dev *pdev = tp->pdev;
9334         struct pcidev_cookie *pcp = pdev->sysdata;
9335
9336         if (pcp != NULL) {
9337                 int node = pcp->prom_node;
9338                 u32 venid;
9339                 int err;
9340
9341                 err = prom_getproperty(node, "subsystem-vendor-id",
9342                                        (char *) &venid, sizeof(venid));
9343                 if (err == 0 || err == -1)
9344                         return 0;
9345                 if (venid == PCI_VENDOR_ID_SUN)
9346                         return 1;
9347         }
9348         return 0;
9349 }
9350 #endif
9351
9352 static int __devinit tg3_get_invariants(struct tg3 *tp)
9353 {
9354         static struct pci_device_id write_reorder_chipsets[] = {
9355                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
9356                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
9357                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
9358                              PCI_DEVICE_ID_VIA_8385_0) },
9359                 { },
9360         };
9361         u32 misc_ctrl_reg;
9362         u32 cacheline_sz_reg;
9363         u32 pci_state_reg, grc_misc_cfg;
9364         u32 val;
9365         u16 pci_cmd;
9366         int err;
9367
9368 #ifdef CONFIG_SPARC64
9369         if (tg3_is_sun_570X(tp))
9370                 tp->tg3_flags2 |= TG3_FLG2_SUN_570X;
9371 #endif
9372
9373         /* Force memory write invalidate off.  If we leave it on,
9374          * then on 5700_BX chips we have to enable a workaround.
9375          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
9376          * to match the cacheline size.  The Broadcom driver have this
9377          * workaround but turns MWI off all the times so never uses
9378          * it.  This seems to suggest that the workaround is insufficient.
9379          */
9380         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9381         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
9382         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9383
9384         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
9385          * has the register indirect write enable bit set before
9386          * we try to access any of the MMIO registers.  It is also
9387          * critical that the PCI-X hw workaround situation is decided
9388          * before that as well.
9389          */
9390         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9391                               &misc_ctrl_reg);
9392
9393         tp->pci_chip_rev_id = (misc_ctrl_reg >>
9394                                MISC_HOST_CTRL_CHIPREV_SHIFT);
9395
9396         /* Wrong chip ID in 5752 A0. This code can be removed later
9397          * as A0 is not in production.
9398          */
9399         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
9400                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
9401
9402         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
9403          * we need to disable memory and use config. cycles
9404          * only to access all registers. The 5702/03 chips
9405          * can mistakenly decode the special cycles from the
9406          * ICH chipsets as memory write cycles, causing corruption
9407          * of register and memory space. Only certain ICH bridges
9408          * will drive special cycles with non-zero data during the
9409          * address phase which can fall within the 5703's address
9410          * range. This is not an ICH bug as the PCI spec allows
9411          * non-zero address during special cycles. However, only
9412          * these ICH bridges are known to drive non-zero addresses
9413          * during special cycles.
9414          *
9415          * Since special cycles do not cross PCI bridges, we only
9416          * enable this workaround if the 5703 is on the secondary
9417          * bus of these ICH bridges.
9418          */
9419         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
9420             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
9421                 static struct tg3_dev_id {
9422                         u32     vendor;
9423                         u32     device;
9424                         u32     rev;
9425                 } ich_chipsets[] = {
9426                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
9427                           PCI_ANY_ID },
9428                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
9429                           PCI_ANY_ID },
9430                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
9431                           0xa },
9432                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
9433                           PCI_ANY_ID },
9434                         { },
9435                 };
9436                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
9437                 struct pci_dev *bridge = NULL;
9438
9439                 while (pci_id->vendor != 0) {
9440                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
9441                                                 bridge);
9442                         if (!bridge) {
9443                                 pci_id++;
9444                                 continue;
9445                         }
9446                         if (pci_id->rev != PCI_ANY_ID) {
9447                                 u8 rev;
9448
9449                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
9450                                                      &rev);
9451                                 if (rev > pci_id->rev)
9452                                         continue;
9453                         }
9454                         if (bridge->subordinate &&
9455                             (bridge->subordinate->number ==
9456                              tp->pdev->bus->number)) {
9457
9458                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
9459                                 pci_dev_put(bridge);
9460                                 break;
9461                         }
9462                 }
9463         }
9464
9465         /* Find msi capability. */
9466         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
9467             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
9468                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
9469                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
9470         }
9471
9472         /* Initialize misc host control in PCI block. */
9473         tp->misc_host_ctrl |= (misc_ctrl_reg &
9474                                MISC_HOST_CTRL_CHIPREV);
9475         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9476                                tp->misc_host_ctrl);
9477
9478         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9479                               &cacheline_sz_reg);
9480
9481         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
9482         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
9483         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
9484         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
9485
9486         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
9487             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
9488             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
9489                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
9490
9491         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
9492             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
9493                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
9494
9495         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
9496                 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
9497
9498         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
9499             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
9500             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
9501                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
9502
9503         if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
9504                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
9505
9506         /* If we have an AMD 762 or VIA K8T800 chipset, write
9507          * reordering to the mailbox registers done by the host
9508          * controller can cause major troubles.  We read back from
9509          * every mailbox register write to force the writes to be
9510          * posted to the chip in order.
9511          */
9512         if (pci_dev_present(write_reorder_chipsets) &&
9513             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9514                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
9515
9516         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9517             tp->pci_lat_timer < 64) {
9518                 tp->pci_lat_timer = 64;
9519
9520                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
9521                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
9522                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
9523                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
9524
9525                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
9526                                        cacheline_sz_reg);
9527         }
9528
9529         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9530                               &pci_state_reg);
9531
9532         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
9533                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
9534
9535                 /* If this is a 5700 BX chipset, and we are in PCI-X
9536                  * mode, enable register write workaround.
9537                  *
9538                  * The workaround is to use indirect register accesses
9539                  * for all chip writes not to mailbox registers.
9540                  */
9541                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
9542                         u32 pm_reg;
9543                         u16 pci_cmd;
9544
9545                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9546
9547                         /* The chip can have it's power management PCI config
9548                          * space registers clobbered due to this bug.
9549                          * So explicitly force the chip into D0 here.
9550                          */
9551                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9552                                               &pm_reg);
9553                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
9554                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
9555                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
9556                                                pm_reg);
9557
9558                         /* Also, force SERR#/PERR# in PCI command. */
9559                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9560                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
9561                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9562                 }
9563         }
9564
9565         /* 5700 BX chips need to have their TX producer index mailboxes
9566          * written twice to workaround a bug.
9567          */
9568         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
9569                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
9570
9571         /* Back to back register writes can cause problems on this chip,
9572          * the workaround is to read back all reg writes except those to
9573          * mailbox regs.  See tg3_write_indirect_reg32().
9574          *
9575          * PCI Express 5750_A0 rev chips need this workaround too.
9576          */
9577         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
9578             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
9579              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
9580                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
9581
9582         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
9583                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
9584         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
9585                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
9586
9587         /* Chip-specific fixup from Broadcom driver */
9588         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
9589             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
9590                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
9591                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
9592         }
9593
9594         /* Default fast path register access methods */
9595         tp->read32 = tg3_read32;
9596         tp->write32 = tg3_write32;
9597         tp->read32_mbox = tg3_read32;
9598         tp->write32_mbox = tg3_write32;
9599         tp->write32_tx_mbox = tg3_write32;
9600         tp->write32_rx_mbox = tg3_write32;
9601
9602         /* Various workaround register access methods */
9603         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
9604                 tp->write32 = tg3_write_indirect_reg32;
9605         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
9606                 tp->write32 = tg3_write_flush_reg32;
9607
9608         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
9609             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
9610                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
9611                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
9612                         tp->write32_rx_mbox = tg3_write_flush_reg32;
9613         }
9614
9615         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
9616                 tp->read32 = tg3_read_indirect_reg32;
9617                 tp->write32 = tg3_write_indirect_reg32;
9618                 tp->read32_mbox = tg3_read_indirect_mbox;
9619                 tp->write32_mbox = tg3_write_indirect_mbox;
9620                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
9621                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
9622
9623                 iounmap(tp->regs);
9624                 tp->regs = NULL;
9625
9626                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
9627                 pci_cmd &= ~PCI_COMMAND_MEMORY;
9628                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
9629         }
9630
9631         /* Get eeprom hw config before calling tg3_set_power_state().
9632          * In particular, the TG3_FLAG_EEPROM_WRITE_PROT flag must be
9633          * determined before calling tg3_set_power_state() so that
9634          * we know whether or not to switch out of Vaux power.
9635          * When the flag is set, it means that GPIO1 is used for eeprom
9636          * write protect and also implies that it is a LOM where GPIOs
9637          * are not used to switch power.
9638          */
9639         tg3_get_eeprom_hw_cfg(tp);
9640
9641         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
9642          * GPIO1 driven high will bring 5700's external PHY out of reset.
9643          * It is also used as eeprom write protect on LOMs.
9644          */
9645         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
9646         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9647             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
9648                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
9649                                        GRC_LCLCTRL_GPIO_OUTPUT1);
9650         /* Unused GPIO3 must be driven as output on 5752 because there
9651          * are no pull-up resistors on unused GPIO pins.
9652          */
9653         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9654                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
9655
9656         /* Force the chip into D0. */
9657         err = tg3_set_power_state(tp, 0);
9658         if (err) {
9659                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
9660                        pci_name(tp->pdev));
9661                 return err;
9662         }
9663
9664         /* 5700 B0 chips do not support checksumming correctly due
9665          * to hardware bugs.
9666          */
9667         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
9668                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
9669
9670         /* Pseudo-header checksum is done by hardware logic and not
9671          * the offload processers, so make the chip do the pseudo-
9672          * header checksums on receive.  For transmit it is more
9673          * convenient to do the pseudo-header checksum in software
9674          * as Linux does that on transmit for us in all cases.
9675          */
9676         tp->tg3_flags |= TG3_FLAG_NO_TX_PSEUDO_CSUM;
9677         tp->tg3_flags &= ~TG3_FLAG_NO_RX_PSEUDO_CSUM;
9678
9679         /* Derive initial jumbo mode from MTU assigned in
9680          * ether_setup() via the alloc_etherdev() call
9681          */
9682         if (tp->dev->mtu > ETH_DATA_LEN &&
9683             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
9684                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
9685
9686         /* Determine WakeOnLan speed to use. */
9687         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9688             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
9689             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
9690             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
9691                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
9692         } else {
9693                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
9694         }
9695
9696         /* A few boards don't want Ethernet@WireSpeed phy feature */
9697         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
9698             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
9699              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
9700              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
9701             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9702                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
9703
9704         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
9705             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
9706                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
9707         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
9708                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
9709
9710         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
9711                 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
9712
9713         tp->coalesce_mode = 0;
9714         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
9715             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
9716                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
9717
9718         /* Initialize MAC MI mode, polling disabled. */
9719         tw32_f(MAC_MI_MODE, tp->mi_mode);
9720         udelay(80);
9721
9722         /* Initialize data/descriptor byte/word swapping. */
9723         val = tr32(GRC_MODE);
9724         val &= GRC_MODE_HOST_STACKUP;
9725         tw32(GRC_MODE, val | tp->grc_mode);
9726
9727         tg3_switch_clocks(tp);
9728
9729         /* Clear this out for sanity. */
9730         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
9731
9732         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
9733                               &pci_state_reg);
9734         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
9735             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
9736                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
9737
9738                 if (chiprevid == CHIPREV_ID_5701_A0 ||
9739                     chiprevid == CHIPREV_ID_5701_B0 ||
9740                     chiprevid == CHIPREV_ID_5701_B2 ||
9741                     chiprevid == CHIPREV_ID_5701_B5) {
9742                         void __iomem *sram_base;
9743
9744                         /* Write some dummy words into the SRAM status block
9745                          * area, see if it reads back correctly.  If the return
9746                          * value is bad, force enable the PCIX workaround.
9747                          */
9748                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
9749
9750                         writel(0x00000000, sram_base);
9751                         writel(0x00000000, sram_base + 4);
9752                         writel(0xffffffff, sram_base + 4);
9753                         if (readl(sram_base) != 0x00000000)
9754                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
9755                 }
9756         }
9757
9758         udelay(50);
9759         tg3_nvram_init(tp);
9760
9761         grc_misc_cfg = tr32(GRC_MISC_CFG);
9762         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
9763
9764         /* Broadcom's driver says that CIOBE multisplit has a bug */
9765 #if 0
9766         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9767             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
9768                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
9769                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
9770         }
9771 #endif
9772         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9773             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
9774              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
9775                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
9776
9777         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
9778             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
9779                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
9780         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
9781                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
9782                                       HOSTCC_MODE_CLRTICK_TXBD);
9783
9784                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
9785                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9786                                        tp->misc_host_ctrl);
9787         }
9788
9789         /* these are limited to 10/100 only */
9790         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
9791              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
9792             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
9793              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9794              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
9795               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
9796               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
9797             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
9798              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
9799               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F)))
9800                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
9801
9802         err = tg3_phy_probe(tp);
9803         if (err) {
9804                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
9805                        pci_name(tp->pdev), err);
9806                 /* ... but do not return immediately ... */
9807         }
9808
9809         tg3_read_partno(tp);
9810
9811         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
9812                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9813         } else {
9814                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9815                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
9816                 else
9817                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
9818         }
9819
9820         /* 5700 {AX,BX} chips have a broken status block link
9821          * change bit implementation, so we must use the
9822          * status register in those cases.
9823          */
9824         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
9825                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
9826         else
9827                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
9828
9829         /* The led_ctrl is set during tg3_phy_probe, here we might
9830          * have to force the link status polling mechanism based
9831          * upon subsystem IDs.
9832          */
9833         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
9834             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
9835                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
9836                                   TG3_FLAG_USE_LINKCHG_REG);
9837         }
9838
9839         /* For all SERDES we poll the MAC status register. */
9840         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9841                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
9842         else
9843                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
9844
9845         /* It seems all chips can get confused if TX buffers
9846          * straddle the 4GB address boundary in some cases.
9847          */
9848         tp->dev->hard_start_xmit = tg3_start_xmit;
9849
9850         tp->rx_offset = 2;
9851         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
9852             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
9853                 tp->rx_offset = 0;
9854
9855         /* By default, disable wake-on-lan.  User can change this
9856          * using ETHTOOL_SWOL.
9857          */
9858         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9859
9860         return err;
9861 }
9862
9863 #ifdef CONFIG_SPARC64
9864 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
9865 {
9866         struct net_device *dev = tp->dev;
9867         struct pci_dev *pdev = tp->pdev;
9868         struct pcidev_cookie *pcp = pdev->sysdata;
9869
9870         if (pcp != NULL) {
9871                 int node = pcp->prom_node;
9872
9873                 if (prom_getproplen(node, "local-mac-address") == 6) {
9874                         prom_getproperty(node, "local-mac-address",
9875                                          dev->dev_addr, 6);
9876                         memcpy(dev->perm_addr, dev->dev_addr, 6);
9877                         return 0;
9878                 }
9879         }
9880         return -ENODEV;
9881 }
9882
9883 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
9884 {
9885         struct net_device *dev = tp->dev;
9886
9887         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
9888         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
9889         return 0;
9890 }
9891 #endif
9892
9893 static int __devinit tg3_get_device_address(struct tg3 *tp)
9894 {
9895         struct net_device *dev = tp->dev;
9896         u32 hi, lo, mac_offset;
9897
9898 #ifdef CONFIG_SPARC64
9899         if (!tg3_get_macaddr_sparc(tp))
9900                 return 0;
9901 #endif
9902
9903         mac_offset = 0x7c;
9904         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9905              !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9906             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9907                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9908                         mac_offset = 0xcc;
9909                 if (tg3_nvram_lock(tp))
9910                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
9911                 else
9912                         tg3_nvram_unlock(tp);
9913         }
9914
9915         /* First try to get it from MAC address mailbox. */
9916         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
9917         if ((hi >> 16) == 0x484b) {
9918                 dev->dev_addr[0] = (hi >>  8) & 0xff;
9919                 dev->dev_addr[1] = (hi >>  0) & 0xff;
9920
9921                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
9922                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9923                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9924                 dev->dev_addr[4] = (lo >>  8) & 0xff;
9925                 dev->dev_addr[5] = (lo >>  0) & 0xff;
9926         }
9927         /* Next, try NVRAM. */
9928         else if (!(tp->tg3_flags & TG3_FLG2_SUN_570X) &&
9929                  !tg3_nvram_read(tp, mac_offset + 0, &hi) &&
9930                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
9931                 dev->dev_addr[0] = ((hi >> 16) & 0xff);
9932                 dev->dev_addr[1] = ((hi >> 24) & 0xff);
9933                 dev->dev_addr[2] = ((lo >>  0) & 0xff);
9934                 dev->dev_addr[3] = ((lo >>  8) & 0xff);
9935                 dev->dev_addr[4] = ((lo >> 16) & 0xff);
9936                 dev->dev_addr[5] = ((lo >> 24) & 0xff);
9937         }
9938         /* Finally just fetch it out of the MAC control regs. */
9939         else {
9940                 hi = tr32(MAC_ADDR_0_HIGH);
9941                 lo = tr32(MAC_ADDR_0_LOW);
9942
9943                 dev->dev_addr[5] = lo & 0xff;
9944                 dev->dev_addr[4] = (lo >> 8) & 0xff;
9945                 dev->dev_addr[3] = (lo >> 16) & 0xff;
9946                 dev->dev_addr[2] = (lo >> 24) & 0xff;
9947                 dev->dev_addr[1] = hi & 0xff;
9948                 dev->dev_addr[0] = (hi >> 8) & 0xff;
9949         }
9950
9951         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
9952 #ifdef CONFIG_SPARC64
9953                 if (!tg3_get_default_macaddr_sparc(tp))
9954                         return 0;
9955 #endif
9956                 return -EINVAL;
9957         }
9958         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
9959         return 0;
9960 }
9961
9962 #define BOUNDARY_SINGLE_CACHELINE       1
9963 #define BOUNDARY_MULTI_CACHELINE        2
9964
9965 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
9966 {
9967         int cacheline_size;
9968         u8 byte;
9969         int goal;
9970
9971         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
9972         if (byte == 0)
9973                 cacheline_size = 1024;
9974         else
9975                 cacheline_size = (int) byte * 4;
9976
9977         /* On 5703 and later chips, the boundary bits have no
9978          * effect.
9979          */
9980         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9981             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
9982             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
9983                 goto out;
9984
9985 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
9986         goal = BOUNDARY_MULTI_CACHELINE;
9987 #else
9988 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
9989         goal = BOUNDARY_SINGLE_CACHELINE;
9990 #else
9991         goal = 0;
9992 #endif
9993 #endif
9994
9995         if (!goal)
9996                 goto out;
9997
9998         /* PCI controllers on most RISC systems tend to disconnect
9999          * when a device tries to burst across a cache-line boundary.
10000          * Therefore, letting tg3 do so just wastes PCI bandwidth.
10001          *
10002          * Unfortunately, for PCI-E there are only limited
10003          * write-side controls for this, and thus for reads
10004          * we will still get the disconnects.  We'll also waste
10005          * these PCI cycles for both read and write for chips
10006          * other than 5700 and 5701 which do not implement the
10007          * boundary bits.
10008          */
10009         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10010             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
10011                 switch (cacheline_size) {
10012                 case 16:
10013                 case 32:
10014                 case 64:
10015                 case 128:
10016                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10017                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
10018                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
10019                         } else {
10020                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10021                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10022                         }
10023                         break;
10024
10025                 case 256:
10026                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
10027                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
10028                         break;
10029
10030                 default:
10031                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
10032                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
10033                         break;
10034                 };
10035         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10036                 switch (cacheline_size) {
10037                 case 16:
10038                 case 32:
10039                 case 64:
10040                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10041                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10042                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
10043                                 break;
10044                         }
10045                         /* fallthrough */
10046                 case 128:
10047                 default:
10048                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
10049                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
10050                         break;
10051                 };
10052         } else {
10053                 switch (cacheline_size) {
10054                 case 16:
10055                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10056                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
10057                                         DMA_RWCTRL_WRITE_BNDRY_16);
10058                                 break;
10059                         }
10060                         /* fallthrough */
10061                 case 32:
10062                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10063                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
10064                                         DMA_RWCTRL_WRITE_BNDRY_32);
10065                                 break;
10066                         }
10067                         /* fallthrough */
10068                 case 64:
10069                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10070                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
10071                                         DMA_RWCTRL_WRITE_BNDRY_64);
10072                                 break;
10073                         }
10074                         /* fallthrough */
10075                 case 128:
10076                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
10077                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
10078                                         DMA_RWCTRL_WRITE_BNDRY_128);
10079                                 break;
10080                         }
10081                         /* fallthrough */
10082                 case 256:
10083                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
10084                                 DMA_RWCTRL_WRITE_BNDRY_256);
10085                         break;
10086                 case 512:
10087                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
10088                                 DMA_RWCTRL_WRITE_BNDRY_512);
10089                         break;
10090                 case 1024:
10091                 default:
10092                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
10093                                 DMA_RWCTRL_WRITE_BNDRY_1024);
10094                         break;
10095                 };
10096         }
10097
10098 out:
10099         return val;
10100 }
10101
10102 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
10103 {
10104         struct tg3_internal_buffer_desc test_desc;
10105         u32 sram_dma_descs;
10106         int i, ret;
10107
10108         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
10109
10110         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
10111         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
10112         tw32(RDMAC_STATUS, 0);
10113         tw32(WDMAC_STATUS, 0);
10114
10115         tw32(BUFMGR_MODE, 0);
10116         tw32(FTQ_RESET, 0);
10117
10118         test_desc.addr_hi = ((u64) buf_dma) >> 32;
10119         test_desc.addr_lo = buf_dma & 0xffffffff;
10120         test_desc.nic_mbuf = 0x00002100;
10121         test_desc.len = size;
10122
10123         /*
10124          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
10125          * the *second* time the tg3 driver was getting loaded after an
10126          * initial scan.
10127          *
10128          * Broadcom tells me:
10129          *   ...the DMA engine is connected to the GRC block and a DMA
10130          *   reset may affect the GRC block in some unpredictable way...
10131          *   The behavior of resets to individual blocks has not been tested.
10132          *
10133          * Broadcom noted the GRC reset will also reset all sub-components.
10134          */
10135         if (to_device) {
10136                 test_desc.cqid_sqid = (13 << 8) | 2;
10137
10138                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
10139                 udelay(40);
10140         } else {
10141                 test_desc.cqid_sqid = (16 << 8) | 7;
10142
10143                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
10144                 udelay(40);
10145         }
10146         test_desc.flags = 0x00000005;
10147
10148         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
10149                 u32 val;
10150
10151                 val = *(((u32 *)&test_desc) + i);
10152                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
10153                                        sram_dma_descs + (i * sizeof(u32)));
10154                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
10155         }
10156         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
10157
10158         if (to_device) {
10159                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
10160         } else {
10161                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
10162         }
10163
10164         ret = -ENODEV;
10165         for (i = 0; i < 40; i++) {
10166                 u32 val;
10167
10168                 if (to_device)
10169                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
10170                 else
10171                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
10172                 if ((val & 0xffff) == sram_dma_descs) {
10173                         ret = 0;
10174                         break;
10175                 }
10176
10177                 udelay(100);
10178         }
10179
10180         return ret;
10181 }
10182
10183 #define TEST_BUFFER_SIZE        0x2000
10184
10185 static int __devinit tg3_test_dma(struct tg3 *tp)
10186 {
10187         dma_addr_t buf_dma;
10188         u32 *buf, saved_dma_rwctrl;
10189         int ret;
10190
10191         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
10192         if (!buf) {
10193                 ret = -ENOMEM;
10194                 goto out_nofree;
10195         }
10196
10197         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
10198                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
10199
10200         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
10201
10202         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10203                 /* DMA read watermark not used on PCIE */
10204                 tp->dma_rwctrl |= 0x00180000;
10205         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
10206                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
10207                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
10208                         tp->dma_rwctrl |= 0x003f0000;
10209                 else
10210                         tp->dma_rwctrl |= 0x003f000f;
10211         } else {
10212                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10213                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
10214                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
10215
10216                         if (ccval == 0x6 || ccval == 0x7)
10217                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
10218
10219                         /* Set bit 23 to enable PCIX hw bug fix */
10220                         tp->dma_rwctrl |= 0x009f0000;
10221                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
10222                         /* 5780 always in PCIX mode */
10223                         tp->dma_rwctrl |= 0x00144000;
10224                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10225                         /* 5714 always in PCIX mode */
10226                         tp->dma_rwctrl |= 0x00148000;
10227                 } else {
10228                         tp->dma_rwctrl |= 0x001b000f;
10229                 }
10230         }
10231
10232         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
10233             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
10234                 tp->dma_rwctrl &= 0xfffffff0;
10235
10236         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10237             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
10238                 /* Remove this if it causes problems for some boards. */
10239                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
10240
10241                 /* On 5700/5701 chips, we need to set this bit.
10242                  * Otherwise the chip will issue cacheline transactions
10243                  * to streamable DMA memory with not all the byte
10244                  * enables turned on.  This is an error on several
10245                  * RISC PCI controllers, in particular sparc64.
10246                  *
10247                  * On 5703/5704 chips, this bit has been reassigned
10248                  * a different meaning.  In particular, it is used
10249                  * on those chips to enable a PCI-X workaround.
10250                  */
10251                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
10252         }
10253
10254         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10255
10256 #if 0
10257         /* Unneeded, already done by tg3_get_invariants.  */
10258         tg3_switch_clocks(tp);
10259 #endif
10260
10261         ret = 0;
10262         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
10263             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
10264                 goto out;
10265
10266         /* It is best to perform DMA test with maximum write burst size
10267          * to expose the 5700/5701 write DMA bug.
10268          */
10269         saved_dma_rwctrl = tp->dma_rwctrl;
10270         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10271         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10272
10273         while (1) {
10274                 u32 *p = buf, i;
10275
10276                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
10277                         p[i] = i;
10278
10279                 /* Send the buffer to the chip. */
10280                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
10281                 if (ret) {
10282                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
10283                         break;
10284                 }
10285
10286 #if 0
10287                 /* validate data reached card RAM correctly. */
10288                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10289                         u32 val;
10290                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
10291                         if (le32_to_cpu(val) != p[i]) {
10292                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
10293                                 /* ret = -ENODEV here? */
10294                         }
10295                         p[i] = 0;
10296                 }
10297 #endif
10298                 /* Now read it back. */
10299                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
10300                 if (ret) {
10301                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
10302
10303                         break;
10304                 }
10305
10306                 /* Verify it. */
10307                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
10308                         if (p[i] == i)
10309                                 continue;
10310
10311                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10312                             DMA_RWCTRL_WRITE_BNDRY_16) {
10313                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10314                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10315                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10316                                 break;
10317                         } else {
10318                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
10319                                 ret = -ENODEV;
10320                                 goto out;
10321                         }
10322                 }
10323
10324                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
10325                         /* Success. */
10326                         ret = 0;
10327                         break;
10328                 }
10329         }
10330         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
10331             DMA_RWCTRL_WRITE_BNDRY_16) {
10332                 static struct pci_device_id dma_wait_state_chipsets[] = {
10333                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
10334                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
10335                         { },
10336                 };
10337
10338                 /* DMA test passed without adjusting DMA boundary,
10339                  * now look for chipsets that are known to expose the
10340                  * DMA bug without failing the test.
10341                  */
10342                 if (pci_dev_present(dma_wait_state_chipsets)) {
10343                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
10344                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
10345                 }
10346                 else
10347                         /* Safe to use the calculated DMA boundary. */
10348                         tp->dma_rwctrl = saved_dma_rwctrl;
10349
10350                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
10351         }
10352
10353 out:
10354         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
10355 out_nofree:
10356         return ret;
10357 }
10358
10359 static void __devinit tg3_init_link_config(struct tg3 *tp)
10360 {
10361         tp->link_config.advertising =
10362                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10363                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10364                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
10365                  ADVERTISED_Autoneg | ADVERTISED_MII);
10366         tp->link_config.speed = SPEED_INVALID;
10367         tp->link_config.duplex = DUPLEX_INVALID;
10368         tp->link_config.autoneg = AUTONEG_ENABLE;
10369         netif_carrier_off(tp->dev);
10370         tp->link_config.active_speed = SPEED_INVALID;
10371         tp->link_config.active_duplex = DUPLEX_INVALID;
10372         tp->link_config.phy_is_low_power = 0;
10373         tp->link_config.orig_speed = SPEED_INVALID;
10374         tp->link_config.orig_duplex = DUPLEX_INVALID;
10375         tp->link_config.orig_autoneg = AUTONEG_INVALID;
10376 }
10377
10378 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
10379 {
10380         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10381                 tp->bufmgr_config.mbuf_read_dma_low_water =
10382                         DEFAULT_MB_RDMA_LOW_WATER_5705;
10383                 tp->bufmgr_config.mbuf_mac_rx_low_water =
10384                         DEFAULT_MB_MACRX_LOW_WATER_5705;
10385                 tp->bufmgr_config.mbuf_high_water =
10386                         DEFAULT_MB_HIGH_WATER_5705;
10387
10388                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10389                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
10390                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10391                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
10392                 tp->bufmgr_config.mbuf_high_water_jumbo =
10393                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
10394         } else {
10395                 tp->bufmgr_config.mbuf_read_dma_low_water =
10396                         DEFAULT_MB_RDMA_LOW_WATER;
10397                 tp->bufmgr_config.mbuf_mac_rx_low_water =
10398                         DEFAULT_MB_MACRX_LOW_WATER;
10399                 tp->bufmgr_config.mbuf_high_water =
10400                         DEFAULT_MB_HIGH_WATER;
10401
10402                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
10403                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
10404                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
10405                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
10406                 tp->bufmgr_config.mbuf_high_water_jumbo =
10407                         DEFAULT_MB_HIGH_WATER_JUMBO;
10408         }
10409
10410         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
10411         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
10412 }
10413
10414 static char * __devinit tg3_phy_string(struct tg3 *tp)
10415 {
10416         switch (tp->phy_id & PHY_ID_MASK) {
10417         case PHY_ID_BCM5400:    return "5400";
10418         case PHY_ID_BCM5401:    return "5401";
10419         case PHY_ID_BCM5411:    return "5411";
10420         case PHY_ID_BCM5701:    return "5701";
10421         case PHY_ID_BCM5703:    return "5703";
10422         case PHY_ID_BCM5704:    return "5704";
10423         case PHY_ID_BCM5705:    return "5705";
10424         case PHY_ID_BCM5750:    return "5750";
10425         case PHY_ID_BCM5752:    return "5752";
10426         case PHY_ID_BCM5714:    return "5714";
10427         case PHY_ID_BCM5780:    return "5780";
10428         case PHY_ID_BCM8002:    return "8002/serdes";
10429         case 0:                 return "serdes";
10430         default:                return "unknown";
10431         };
10432 }
10433
10434 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
10435 {
10436         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
10437                 strcpy(str, "PCI Express");
10438                 return str;
10439         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
10440                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
10441
10442                 strcpy(str, "PCIX:");
10443
10444                 if ((clock_ctrl == 7) ||
10445                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
10446                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
10447                         strcat(str, "133MHz");
10448                 else if (clock_ctrl == 0)
10449                         strcat(str, "33MHz");
10450                 else if (clock_ctrl == 2)
10451                         strcat(str, "50MHz");
10452                 else if (clock_ctrl == 4)
10453                         strcat(str, "66MHz");
10454                 else if (clock_ctrl == 6)
10455                         strcat(str, "100MHz");
10456                 else if (clock_ctrl == 7)
10457                         strcat(str, "133MHz");
10458         } else {
10459                 strcpy(str, "PCI:");
10460                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
10461                         strcat(str, "66MHz");
10462                 else
10463                         strcat(str, "33MHz");
10464         }
10465         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
10466                 strcat(str, ":32-bit");
10467         else
10468                 strcat(str, ":64-bit");
10469         return str;
10470 }
10471
10472 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
10473 {
10474         struct pci_dev *peer;
10475         unsigned int func, devnr = tp->pdev->devfn & ~7;
10476
10477         for (func = 0; func < 8; func++) {
10478                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
10479                 if (peer && peer != tp->pdev)
10480                         break;
10481                 pci_dev_put(peer);
10482         }
10483         /* 5704 can be configured in single-port mode, set peer to
10484          * tp->pdev in that case.
10485          */
10486         if (!peer) {
10487                 peer = tp->pdev;
10488                 return peer;
10489         }
10490
10491         /*
10492          * We don't need to keep the refcount elevated; there's no way
10493          * to remove one half of this device without removing the other
10494          */
10495         pci_dev_put(peer);
10496
10497         return peer;
10498 }
10499
10500 static void __devinit tg3_init_coal(struct tg3 *tp)
10501 {
10502         struct ethtool_coalesce *ec = &tp->coal;
10503
10504         memset(ec, 0, sizeof(*ec));
10505         ec->cmd = ETHTOOL_GCOALESCE;
10506         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
10507         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
10508         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
10509         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
10510         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
10511         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
10512         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
10513         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
10514         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
10515
10516         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
10517                                  HOSTCC_MODE_CLRTICK_TXBD)) {
10518                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
10519                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
10520                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
10521                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
10522         }
10523
10524         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10525                 ec->rx_coalesce_usecs_irq = 0;
10526                 ec->tx_coalesce_usecs_irq = 0;
10527                 ec->stats_block_coalesce_usecs = 0;
10528         }
10529 }
10530
10531 static int __devinit tg3_init_one(struct pci_dev *pdev,
10532                                   const struct pci_device_id *ent)
10533 {
10534         static int tg3_version_printed = 0;
10535         unsigned long tg3reg_base, tg3reg_len;
10536         struct net_device *dev;
10537         struct tg3 *tp;
10538         int i, err, pci_using_dac, pm_cap;
10539         char str[40];
10540
10541         if (tg3_version_printed++ == 0)
10542                 printk(KERN_INFO "%s", version);
10543
10544         err = pci_enable_device(pdev);
10545         if (err) {
10546                 printk(KERN_ERR PFX "Cannot enable PCI device, "
10547                        "aborting.\n");
10548                 return err;
10549         }
10550
10551         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
10552                 printk(KERN_ERR PFX "Cannot find proper PCI device "
10553                        "base address, aborting.\n");
10554                 err = -ENODEV;
10555                 goto err_out_disable_pdev;
10556         }
10557
10558         err = pci_request_regions(pdev, DRV_MODULE_NAME);
10559         if (err) {
10560                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
10561                        "aborting.\n");
10562                 goto err_out_disable_pdev;
10563         }
10564
10565         pci_set_master(pdev);
10566
10567         /* Find power-management capability. */
10568         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
10569         if (pm_cap == 0) {
10570                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
10571                        "aborting.\n");
10572                 err = -EIO;
10573                 goto err_out_free_res;
10574         }
10575
10576         /* Configure DMA attributes. */
10577         err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
10578         if (!err) {
10579                 pci_using_dac = 1;
10580                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
10581                 if (err < 0) {
10582                         printk(KERN_ERR PFX "Unable to obtain 64 bit DMA "
10583                                "for consistent allocations\n");
10584                         goto err_out_free_res;
10585                 }
10586         } else {
10587                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
10588                 if (err) {
10589                         printk(KERN_ERR PFX "No usable DMA configuration, "
10590                                "aborting.\n");
10591                         goto err_out_free_res;
10592                 }
10593                 pci_using_dac = 0;
10594         }
10595
10596         tg3reg_base = pci_resource_start(pdev, 0);
10597         tg3reg_len = pci_resource_len(pdev, 0);
10598
10599         dev = alloc_etherdev(sizeof(*tp));
10600         if (!dev) {
10601                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
10602                 err = -ENOMEM;
10603                 goto err_out_free_res;
10604         }
10605
10606         SET_MODULE_OWNER(dev);
10607         SET_NETDEV_DEV(dev, &pdev->dev);
10608
10609         if (pci_using_dac)
10610                 dev->features |= NETIF_F_HIGHDMA;
10611         dev->features |= NETIF_F_LLTX;
10612 #if TG3_VLAN_TAG_USED
10613         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
10614         dev->vlan_rx_register = tg3_vlan_rx_register;
10615         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
10616 #endif
10617
10618         tp = netdev_priv(dev);
10619         tp->pdev = pdev;
10620         tp->dev = dev;
10621         tp->pm_cap = pm_cap;
10622         tp->mac_mode = TG3_DEF_MAC_MODE;
10623         tp->rx_mode = TG3_DEF_RX_MODE;
10624         tp->tx_mode = TG3_DEF_TX_MODE;
10625         tp->mi_mode = MAC_MI_MODE_BASE;
10626         if (tg3_debug > 0)
10627                 tp->msg_enable = tg3_debug;
10628         else
10629                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
10630
10631         /* The word/byte swap controls here control register access byte
10632          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
10633          * setting below.
10634          */
10635         tp->misc_host_ctrl =
10636                 MISC_HOST_CTRL_MASK_PCI_INT |
10637                 MISC_HOST_CTRL_WORD_SWAP |
10638                 MISC_HOST_CTRL_INDIR_ACCESS |
10639                 MISC_HOST_CTRL_PCISTATE_RW;
10640
10641         /* The NONFRM (non-frame) byte/word swap controls take effect
10642          * on descriptor entries, anything which isn't packet data.
10643          *
10644          * The StrongARM chips on the board (one for tx, one for rx)
10645          * are running in big-endian mode.
10646          */
10647         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
10648                         GRC_MODE_WSWAP_NONFRM_DATA);
10649 #ifdef __BIG_ENDIAN
10650         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
10651 #endif
10652         spin_lock_init(&tp->lock);
10653         spin_lock_init(&tp->tx_lock);
10654         spin_lock_init(&tp->indirect_lock);
10655         INIT_WORK(&tp->reset_task, tg3_reset_task, tp);
10656
10657         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
10658         if (tp->regs == 0UL) {
10659                 printk(KERN_ERR PFX "Cannot map device registers, "
10660                        "aborting.\n");
10661                 err = -ENOMEM;
10662                 goto err_out_free_dev;
10663         }
10664
10665         tg3_init_link_config(tp);
10666
10667         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10668         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10669         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
10670
10671         dev->open = tg3_open;
10672         dev->stop = tg3_close;
10673         dev->get_stats = tg3_get_stats;
10674         dev->set_multicast_list = tg3_set_rx_mode;
10675         dev->set_mac_address = tg3_set_mac_addr;
10676         dev->do_ioctl = tg3_ioctl;
10677         dev->tx_timeout = tg3_tx_timeout;
10678         dev->poll = tg3_poll;
10679         dev->ethtool_ops = &tg3_ethtool_ops;
10680         dev->weight = 64;
10681         dev->watchdog_timeo = TG3_TX_TIMEOUT;
10682         dev->change_mtu = tg3_change_mtu;
10683         dev->irq = pdev->irq;
10684 #ifdef CONFIG_NET_POLL_CONTROLLER
10685         dev->poll_controller = tg3_poll_controller;
10686 #endif
10687
10688         err = tg3_get_invariants(tp);
10689         if (err) {
10690                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
10691                        "aborting.\n");
10692                 goto err_out_iounmap;
10693         }
10694
10695         tg3_init_bufmgr_config(tp);
10696
10697 #if TG3_TSO_SUPPORT != 0
10698         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
10699                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10700         }
10701         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10702             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10703             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
10704             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
10705                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
10706         } else {
10707                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
10708         }
10709
10710         /* TSO is off by default, user can enable using ethtool.  */
10711 #if 0
10712         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)
10713                 dev->features |= NETIF_F_TSO;
10714 #endif
10715
10716 #endif
10717
10718         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
10719             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
10720             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
10721                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
10722                 tp->rx_pending = 63;
10723         }
10724
10725         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
10726             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
10727                 tp->pdev_peer = tg3_find_peer(tp);
10728
10729         err = tg3_get_device_address(tp);
10730         if (err) {
10731                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
10732                        "aborting.\n");
10733                 goto err_out_iounmap;
10734         }
10735
10736         /*
10737          * Reset chip in case UNDI or EFI driver did not shutdown
10738          * DMA self test will enable WDMAC and we'll see (spurious)
10739          * pending DMA on the PCI bus at that point.
10740          */
10741         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
10742             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
10743                 pci_save_state(tp->pdev);
10744                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
10745                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10746         }
10747
10748         err = tg3_test_dma(tp);
10749         if (err) {
10750                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
10751                 goto err_out_iounmap;
10752         }
10753
10754         /* Tigon3 can do ipv4 only... and some chips have buggy
10755          * checksumming.
10756          */
10757         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
10758                 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
10759                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10760         } else
10761                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10762
10763         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
10764                 dev->features &= ~NETIF_F_HIGHDMA;
10765
10766         /* flow control autonegotiation is default behavior */
10767         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10768
10769         tg3_init_coal(tp);
10770
10771         /* Now that we have fully setup the chip, save away a snapshot
10772          * of the PCI config space.  We need to restore this after
10773          * GRC_MISC_CFG core clock resets and some resume events.
10774          */
10775         pci_save_state(tp->pdev);
10776
10777         err = register_netdev(dev);
10778         if (err) {
10779                 printk(KERN_ERR PFX "Cannot register net device, "
10780                        "aborting.\n");
10781                 goto err_out_iounmap;
10782         }
10783
10784         pci_set_drvdata(pdev, dev);
10785
10786         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
10787                dev->name,
10788                tp->board_part_number,
10789                tp->pci_chip_rev_id,
10790                tg3_phy_string(tp),
10791                tg3_bus_string(tp, str),
10792                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
10793
10794         for (i = 0; i < 6; i++)
10795                 printk("%2.2x%c", dev->dev_addr[i],
10796                        i == 5 ? '\n' : ':');
10797
10798         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
10799                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
10800                "TSOcap[%d] \n",
10801                dev->name,
10802                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
10803                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
10804                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
10805                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
10806                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
10807                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
10808                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
10809         printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
10810                dev->name, tp->dma_rwctrl);
10811
10812         return 0;
10813
10814 err_out_iounmap:
10815         if (tp->regs) {
10816                 iounmap(tp->regs);
10817                 tp->regs = NULL;
10818         }
10819
10820 err_out_free_dev:
10821         free_netdev(dev);
10822
10823 err_out_free_res:
10824         pci_release_regions(pdev);
10825
10826 err_out_disable_pdev:
10827         pci_disable_device(pdev);
10828         pci_set_drvdata(pdev, NULL);
10829         return err;
10830 }
10831
10832 static void __devexit tg3_remove_one(struct pci_dev *pdev)
10833 {
10834         struct net_device *dev = pci_get_drvdata(pdev);
10835
10836         if (dev) {
10837                 struct tg3 *tp = netdev_priv(dev);
10838
10839                 unregister_netdev(dev);
10840                 if (tp->regs) {
10841                         iounmap(tp->regs);
10842                         tp->regs = NULL;
10843                 }
10844                 free_netdev(dev);
10845                 pci_release_regions(pdev);
10846                 pci_disable_device(pdev);
10847                 pci_set_drvdata(pdev, NULL);
10848         }
10849 }
10850
10851 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
10852 {
10853         struct net_device *dev = pci_get_drvdata(pdev);
10854         struct tg3 *tp = netdev_priv(dev);
10855         int err;
10856
10857         if (!netif_running(dev))
10858                 return 0;
10859
10860         tg3_netif_stop(tp);
10861
10862         del_timer_sync(&tp->timer);
10863
10864         tg3_full_lock(tp, 1);
10865         tg3_disable_ints(tp);
10866         tg3_full_unlock(tp);
10867
10868         netif_device_detach(dev);
10869
10870         tg3_full_lock(tp, 0);
10871         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10872         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
10873         tg3_full_unlock(tp);
10874
10875         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
10876         if (err) {
10877                 tg3_full_lock(tp, 0);
10878
10879                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10880                 tg3_init_hw(tp);
10881
10882                 tp->timer.expires = jiffies + tp->timer_offset;
10883                 add_timer(&tp->timer);
10884
10885                 netif_device_attach(dev);
10886                 tg3_netif_start(tp);
10887
10888                 tg3_full_unlock(tp);
10889         }
10890
10891         return err;
10892 }
10893
10894 static int tg3_resume(struct pci_dev *pdev)
10895 {
10896         struct net_device *dev = pci_get_drvdata(pdev);
10897         struct tg3 *tp = netdev_priv(dev);
10898         int err;
10899
10900         if (!netif_running(dev))
10901                 return 0;
10902
10903         pci_restore_state(tp->pdev);
10904
10905         err = tg3_set_power_state(tp, 0);
10906         if (err)
10907                 return err;
10908
10909         netif_device_attach(dev);
10910
10911         tg3_full_lock(tp, 0);
10912
10913         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
10914         tg3_init_hw(tp);
10915
10916         tp->timer.expires = jiffies + tp->timer_offset;
10917         add_timer(&tp->timer);
10918
10919         tg3_netif_start(tp);
10920
10921         tg3_full_unlock(tp);
10922
10923         return 0;
10924 }
10925
10926 static struct pci_driver tg3_driver = {
10927         .name           = DRV_MODULE_NAME,
10928         .id_table       = tg3_pci_tbl,
10929         .probe          = tg3_init_one,
10930         .remove         = __devexit_p(tg3_remove_one),
10931         .suspend        = tg3_suspend,
10932         .resume         = tg3_resume
10933 };
10934
10935 static int __init tg3_init(void)
10936 {
10937         return pci_module_init(&tg3_driver);
10938 }
10939
10940 static void __exit tg3_cleanup(void)
10941 {
10942         pci_unregister_driver(&tg3_driver);
10943 }
10944
10945 module_init(tg3_init);
10946 module_exit(tg3_cleanup);