err.no Git - linux-2.6/blob - drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #ifdef NETIF_F_TSO
  62 #define TG3_TSO_SUPPORT 1
  63 #else
  64 #define TG3_TSO_SUPPORT 0
  65 #endif
  66
  67 #include "tg3.h"
  68
  69 #define DRV_MODULE_NAME         "tg3"
  70 #define PFX DRV_MODULE_NAME     ": "
  71 #define DRV_MODULE_VERSION      "3.69"
  72 #define DRV_MODULE_RELDATE      "November 15, 2006"
  73
  74 #define TG3_DEF_MAC_MODE        0
  75 #define TG3_DEF_RX_MODE         0
  76 #define TG3_DEF_TX_MODE         0
  77 #define TG3_DEF_MSG_ENABLE        \
  78         (NETIF_MSG_DRV          | \
  79          NETIF_MSG_PROBE        | \
  80          NETIF_MSG_LINK         | \
  81          NETIF_MSG_TIMER        | \
  82          NETIF_MSG_IFDOWN       | \
  83          NETIF_MSG_IFUP         | \
  84          NETIF_MSG_RX_ERR       | \
  85          NETIF_MSG_TX_ERR)
  86
  87 /* length of time before we decide the hardware is borked,
  88  * and dev->tx_timeout() should be called to fix the problem
  89  */
  90 #define TG3_TX_TIMEOUT                  (5 * HZ)
  91
  92 /* hardware minimum and maximum for a single frame's data payload */
  93 #define TG3_MIN_MTU                     60
  94 #define TG3_MAX_MTU(tp) \
  95         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  96
  97 /* These numbers seem to be hard coded in the NIC firmware somehow.
  98  * You can't change the ring sizes, but you can change where you place
  99  * them in the NIC onboard memory.
 100  */
 101 #define TG3_RX_RING_SIZE                512
 102 #define TG3_DEF_RX_RING_PENDING         200
 103 #define TG3_RX_JUMBO_RING_SIZE          256
 104 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 105
 106 /* Do not place this n-ring entries value into the tp struct itself,
 107  * we really want to expose these constants to GCC so that modulo et
 108  * al.  operations are done with shifts and masks instead of with
 109  * hw multiply/modulo instructions.  Another solution would be to
 110  * replace things like '% foo' with '& (foo - 1)'.
 111  */
 112 #define TG3_RX_RCB_RING_SIZE(tp)        \
 113         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 114
 115 #define TG3_TX_RING_SIZE                512
 116 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 117
 118 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 119                                  TG3_RX_RING_SIZE)
 120 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 121                                  TG3_RX_JUMBO_RING_SIZE)
 122 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 123                                    TG3_RX_RCB_RING_SIZE(tp))
 124 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 125                                  TG3_TX_RING_SIZE)
 126 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 127
 128 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 129 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 130
 131 /* minimum number of free TX descriptors required to wake up TX process */
 132 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 133
 134 /* number of ETHTOOL_GSTATS u64's */
 135 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 136
 137 #define TG3_NUM_TEST            6
 138
 139 static char version[] __devinitdata =
 140         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 141
 142 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 143 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 144 MODULE_LICENSE("GPL");
 145 MODULE_VERSION(DRV_MODULE_VERSION);
 146
 147 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 148 module_param(tg3_debug, int, 0);
 149 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 150
 151 static struct pci_device_id tg3_pci_tbl[] = {
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 208         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 209         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 210         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 211         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 212         {}
 213 };
 214
 215 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 216
 217 static const struct {
 218         const char string[ETH_GSTRING_LEN];
 219 } ethtool_stats_keys[TG3_NUM_STATS] = {
 220         { "rx_octets" },
 221         { "rx_fragments" },
 222         { "rx_ucast_packets" },
 223         { "rx_mcast_packets" },
 224         { "rx_bcast_packets" },
 225         { "rx_fcs_errors" },
 226         { "rx_align_errors" },
 227         { "rx_xon_pause_rcvd" },
 228         { "rx_xoff_pause_rcvd" },
 229         { "rx_mac_ctrl_rcvd" },
 230         { "rx_xoff_entered" },
 231         { "rx_frame_too_long_errors" },
 232         { "rx_jabbers" },
 233         { "rx_undersize_packets" },
 234         { "rx_in_length_errors" },
 235         { "rx_out_length_errors" },
 236         { "rx_64_or_less_octet_packets" },
 237         { "rx_65_to_127_octet_packets" },
 238         { "rx_128_to_255_octet_packets" },
 239         { "rx_256_to_511_octet_packets" },
 240         { "rx_512_to_1023_octet_packets" },
 241         { "rx_1024_to_1522_octet_packets" },
 242         { "rx_1523_to_2047_octet_packets" },
 243         { "rx_2048_to_4095_octet_packets" },
 244         { "rx_4096_to_8191_octet_packets" },
 245         { "rx_8192_to_9022_octet_packets" },
 246
 247         { "tx_octets" },
 248         { "tx_collisions" },
 249
 250         { "tx_xon_sent" },
 251         { "tx_xoff_sent" },
 252         { "tx_flow_control" },
 253         { "tx_mac_errors" },
 254         { "tx_single_collisions" },
 255         { "tx_mult_collisions" },
 256         { "tx_deferred" },
 257         { "tx_excessive_collisions" },
 258         { "tx_late_collisions" },
 259         { "tx_collide_2times" },
 260         { "tx_collide_3times" },
 261         { "tx_collide_4times" },
 262         { "tx_collide_5times" },
 263         { "tx_collide_6times" },
 264         { "tx_collide_7times" },
 265         { "tx_collide_8times" },
 266         { "tx_collide_9times" },
 267         { "tx_collide_10times" },
 268         { "tx_collide_11times" },
 269         { "tx_collide_12times" },
 270         { "tx_collide_13times" },
 271         { "tx_collide_14times" },
 272         { "tx_collide_15times" },
 273         { "tx_ucast_packets" },
 274         { "tx_mcast_packets" },
 275         { "tx_bcast_packets" },
 276         { "tx_carrier_sense_errors" },
 277         { "tx_discards" },
 278         { "tx_errors" },
 279
 280         { "dma_writeq_full" },
 281         { "dma_write_prioq_full" },
 282         { "rxbds_empty" },
 283         { "rx_discards" },
 284         { "rx_errors" },
 285         { "rx_threshold_hit" },
 286
 287         { "dma_readq_full" },
 288         { "dma_read_prioq_full" },
 289         { "tx_comp_queue_full" },
 290
 291         { "ring_set_send_prod_index" },
 292         { "ring_status_update" },
 293         { "nic_irqs" },
 294         { "nic_avoided_irqs" },
 295         { "nic_tx_threshold_hit" }
 296 };
 297
 298 static const struct {
 299         const char string[ETH_GSTRING_LEN];
 300 } ethtool_test_keys[TG3_NUM_TEST] = {
 301         { "nvram test     (online) " },
 302         { "link test      (online) " },
 303         { "register test  (offline)" },
 304         { "memory test    (offline)" },
 305         { "loopback test  (offline)" },
 306         { "interrupt test (offline)" },
 307 };
 308
 309 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 310 {
 311         writel(val, tp->regs + off);
 312 }
 313
 314 static u32 tg3_read32(struct tg3 *tp, u32 off)
 315 {
 316         return (readl(tp->regs + off));
 317 }
 318
 319 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 320 {
 321         unsigned long flags;
 322
 323         spin_lock_irqsave(&tp->indirect_lock, flags);
 324         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 325         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 326         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 327 }
 328
 329 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 330 {
 331         writel(val, tp->regs + off);
 332         readl(tp->regs + off);
 333 }
 334
 335 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 336 {
 337         unsigned long flags;
 338         u32 val;
 339
 340         spin_lock_irqsave(&tp->indirect_lock, flags);
 341         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 342         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 343         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 344         return val;
 345 }
 346
 347 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 348 {
 349         unsigned long flags;
 350
 351         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 352                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 353                                        TG3_64BIT_REG_LOW, val);
 354                 return;
 355         }
 356         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 357                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 358                                        TG3_64BIT_REG_LOW, val);
 359                 return;
 360         }
 361
 362         spin_lock_irqsave(&tp->indirect_lock, flags);
 363         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 364         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 365         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 366
 367         /* In indirect mode when disabling interrupts, we also need
 368          * to clear the interrupt bit in the GRC local ctrl register.
 369          */
 370         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 371             (val == 0x1)) {
 372                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 373                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 374         }
 375 }
 376
 377 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 378 {
 379         unsigned long flags;
 380         u32 val;
 381
 382         spin_lock_irqsave(&tp->indirect_lock, flags);
 383         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 384         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 385         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 386         return val;
 387 }
 388
 389 /* usec_wait specifies the wait time in usec when writing to certain registers
 390  * where it is unsafe to read back the register without some delay.
 391  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 392  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 393  */
 394 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 395 {
 396         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 397             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 398                 /* Non-posted methods */
 399                 tp->write32(tp, off, val);
 400         else {
 401                 /* Posted method */
 402                 tg3_write32(tp, off, val);
 403                 if (usec_wait)
 404                         udelay(usec_wait);
 405                 tp->read32(tp, off);
 406         }
 407         /* Wait again after the read for the posted method to guarantee that
 408          * the wait time is met.
 409          */
 410         if (usec_wait)
 411                 udelay(usec_wait);
 412 }
 413
 414 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 415 {
 416         tp->write32_mbox(tp, off, val);
 417         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 418             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 419                 tp->read32_mbox(tp, off);
 420 }
 421
 422 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 423 {
 424         void __iomem *mbox = tp->regs + off;
 425         writel(val, mbox);
 426         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 427                 writel(val, mbox);
 428         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 429                 readl(mbox);
 430 }
 431
 432 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 433 {
 434         return (readl(tp->regs + off + GRCMBOX_BASE));
 435 }
 436
 437 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 438 {
 439         writel(val, tp->regs + off + GRCMBOX_BASE);
 440 }
 441
 442 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 443 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 444 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 445 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 446 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 447
 448 #define tw32(reg,val)           tp->write32(tp, reg, val)
 449 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 450 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 451 #define tr32(reg)               tp->read32(tp, reg)
 452
 453 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 454 {
 455         unsigned long flags;
 456
 457         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 458             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 459                 return;
 460
 461         spin_lock_irqsave(&tp->indirect_lock, flags);
 462         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 464                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 465
 466                 /* Always leave this as zero. */
 467                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 468         } else {
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 470                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 471
 472                 /* Always leave this as zero. */
 473                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 474         }
 475         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 476 }
 477
 478 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 479 {
 480         unsigned long flags;
 481
 482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 483             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 484                 *val = 0;
 485                 return;
 486         }
 487
 488         spin_lock_irqsave(&tp->indirect_lock, flags);
 489         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 491                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 492
 493                 /* Always leave this as zero. */
 494                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 495         } else {
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 497                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 498
 499                 /* Always leave this as zero. */
 500                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 501         }
 502         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 503 }
 504
 505 static void tg3_disable_ints(struct tg3 *tp)
 506 {
 507         tw32(TG3PCI_MISC_HOST_CTRL,
 508              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 509         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 510 }
 511
 512 static inline void tg3_cond_int(struct tg3 *tp)
 513 {
 514         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 515             (tp->hw_status->status & SD_STATUS_UPDATED))
 516                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 517         else
 518                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 519                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 520 }
 521
 522 static void tg3_enable_ints(struct tg3 *tp)
 523 {
 524         tp->irq_sync = 0;
 525         wmb();
 526
 527         tw32(TG3PCI_MISC_HOST_CTRL,
 528              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 529         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 530                        (tp->last_tag << 24));
 531         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 532                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 533                                (tp->last_tag << 24));
 534         tg3_cond_int(tp);
 535 }
 536
 537 static inline unsigned int tg3_has_work(struct tg3 *tp)
 538 {
 539         struct tg3_hw_status *sblk = tp->hw_status;
 540         unsigned int work_exists = 0;
 541
 542         /* check for phy events */
 543         if (!(tp->tg3_flags &
 544               (TG3_FLAG_USE_LINKCHG_REG |
 545                TG3_FLAG_POLL_SERDES))) {
 546                 if (sblk->status & SD_STATUS_LINK_CHG)
 547                         work_exists = 1;
 548         }
 549         /* check for RX/TX work to do */
 550         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 551             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 552                 work_exists = 1;
 553
 554         return work_exists;
 555 }
 556
 557 /* tg3_restart_ints
 558  *  similar to tg3_enable_ints, but it accurately determines whether there
 559  *  is new work pending and can return without flushing the PIO write
 560  *  which reenables interrupts
 561  */
 562 static void tg3_restart_ints(struct tg3 *tp)
 563 {
 564         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 565                      tp->last_tag << 24);
 566         mmiowb();
 567
 568         /* When doing tagged status, this work check is unnecessary.
 569          * The last_tag we write above tells the chip which piece of
 570          * work we've completed.
 571          */
 572         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 573             tg3_has_work(tp))
 574                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 575                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 576 }
 577
 578 static inline void tg3_netif_stop(struct tg3 *tp)
 579 {
 580         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 581         netif_poll_disable(tp->dev);
 582         netif_tx_disable(tp->dev);
 583 }
 584
 585 static inline void tg3_netif_start(struct tg3 *tp)
 586 {
 587         netif_wake_queue(tp->dev);
 588         /* NOTE: unconditional netif_wake_queue is only appropriate
 589          * so long as all callers are assured to have free tx slots
 590          * (such as after tg3_init_hw)
 591          */
 592         netif_poll_enable(tp->dev);
 593         tp->hw_status->status |= SD_STATUS_UPDATED;
 594         tg3_enable_ints(tp);
 595 }
 596
 597 static void tg3_switch_clocks(struct tg3 *tp)
 598 {
 599         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 600         u32 orig_clock_ctrl;
 601
 602         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 603                 return;
 604
 605         orig_clock_ctrl = clock_ctrl;
 606         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 607                        CLOCK_CTRL_CLKRUN_OENABLE |
 608                        0x1f);
 609         tp->pci_clock_ctrl = clock_ctrl;
 610
 611         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 612                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 613                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 615                 }
 616         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl |
 619                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 620                             40);
 621                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 622                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 623                             40);
 624         }
 625         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 626 }
 627
 628 #define PHY_BUSY_LOOPS  5000
 629
 630 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 631 {
 632         u32 frame_val;
 633         unsigned int loops;
 634         int ret;
 635
 636         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 637                 tw32_f(MAC_MI_MODE,
 638                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 639                 udelay(80);
 640         }
 641
 642         *val = 0x0;
 643
 644         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 645                       MI_COM_PHY_ADDR_MASK);
 646         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 647                       MI_COM_REG_ADDR_MASK);
 648         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 649
 650         tw32_f(MAC_MI_COM, frame_val);
 651
 652         loops = PHY_BUSY_LOOPS;
 653         while (loops != 0) {
 654                 udelay(10);
 655                 frame_val = tr32(MAC_MI_COM);
 656
 657                 if ((frame_val & MI_COM_BUSY) == 0) {
 658                         udelay(5);
 659                         frame_val = tr32(MAC_MI_COM);
 660                         break;
 661                 }
 662                 loops -= 1;
 663         }
 664
 665         ret = -EBUSY;
 666         if (loops != 0) {
 667                 *val = frame_val & MI_COM_DATA_MASK;
 668                 ret = 0;
 669         }
 670
 671         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 672                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 673                 udelay(80);
 674         }
 675
 676         return ret;
 677 }
 678
 679 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 680 {
 681         u32 frame_val;
 682         unsigned int loops;
 683         int ret;
 684
 685         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 686             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 687                 return 0;
 688
 689         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 690                 tw32_f(MAC_MI_MODE,
 691                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 692                 udelay(80);
 693         }
 694
 695         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 696                       MI_COM_PHY_ADDR_MASK);
 697         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 698                       MI_COM_REG_ADDR_MASK);
 699         frame_val |= (val & MI_COM_DATA_MASK);
 700         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 701
 702         tw32_f(MAC_MI_COM, frame_val);
 703
 704         loops = PHY_BUSY_LOOPS;
 705         while (loops != 0) {
 706                 udelay(10);
 707                 frame_val = tr32(MAC_MI_COM);
 708                 if ((frame_val & MI_COM_BUSY) == 0) {
 709                         udelay(5);
 710                         frame_val = tr32(MAC_MI_COM);
 711                         break;
 712                 }
 713                 loops -= 1;
 714         }
 715
 716         ret = -EBUSY;
 717         if (loops != 0)
 718                 ret = 0;
 719
 720         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 721                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 722                 udelay(80);
 723         }
 724
 725         return ret;
 726 }
 727
 728 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 729 {
 730         u32 val;
 731
 732         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 733                 return;
 734
 735         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 736             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 737                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 738                              (val | (1 << 15) | (1 << 4)));
 739 }
 740
 741 static int tg3_bmcr_reset(struct tg3 *tp)
 742 {
 743         u32 phy_control;
 744         int limit, err;
 745
 746         /* OK, reset it, and poll the BMCR_RESET bit until it
 747          * clears or we time out.
 748          */
 749         phy_control = BMCR_RESET;
 750         err = tg3_writephy(tp, MII_BMCR, phy_control);
 751         if (err != 0)
 752                 return -EBUSY;
 753
 754         limit = 5000;
 755         while (limit--) {
 756                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 757                 if (err != 0)
 758                         return -EBUSY;
 759
 760                 if ((phy_control & BMCR_RESET) == 0) {
 761                         udelay(40);
 762                         break;
 763                 }
 764                 udelay(10);
 765         }
 766         if (limit <= 0)
 767                 return -EBUSY;
 768
 769         return 0;
 770 }
 771
 772 static int tg3_wait_macro_done(struct tg3 *tp)
 773 {
 774         int limit = 100;
 775
 776         while (limit--) {
 777                 u32 tmp32;
 778
 779                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 780                         if ((tmp32 & 0x1000) == 0)
 781                                 break;
 782                 }
 783         }
 784         if (limit <= 0)
 785                 return -EBUSY;
 786
 787         return 0;
 788 }
 789
 790 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 791 {
 792         static const u32 test_pat[4][6] = {
 793         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 794         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 795         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 796         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 797         };
 798         int chan;
 799
 800         for (chan = 0; chan < 4; chan++) {
 801                 int i;
 802
 803                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 804                              (chan * 0x2000) | 0x0200);
 805                 tg3_writephy(tp, 0x16, 0x0002);
 806
 807                 for (i = 0; i < 6; i++)
 808                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 809                                      test_pat[chan][i]);
 810
 811                 tg3_writephy(tp, 0x16, 0x0202);
 812                 if (tg3_wait_macro_done(tp)) {
 813                         *resetp = 1;
 814                         return -EBUSY;
 815                 }
 816
 817                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 818                              (chan * 0x2000) | 0x0200);
 819                 tg3_writephy(tp, 0x16, 0x0082);
 820                 if (tg3_wait_macro_done(tp)) {
 821                         *resetp = 1;
 822                         return -EBUSY;
 823                 }
 824
 825                 tg3_writephy(tp, 0x16, 0x0802);
 826                 if (tg3_wait_macro_done(tp)) {
 827                         *resetp = 1;
 828                         return -EBUSY;
 829                 }
 830
 831                 for (i = 0; i < 6; i += 2) {
 832                         u32 low, high;
 833
 834                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 835                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 836                             tg3_wait_macro_done(tp)) {
 837                                 *resetp = 1;
 838                                 return -EBUSY;
 839                         }
 840                         low &= 0x7fff;
 841                         high &= 0x000f;
 842                         if (low != test_pat[chan][i] ||
 843                             high != test_pat[chan][i+1]) {
 844                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 845                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 846                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 847
 848                                 return -EBUSY;
 849                         }
 850                 }
 851         }
 852
 853         return 0;
 854 }
 855
 856 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 857 {
 858         int chan;
 859
 860         for (chan = 0; chan < 4; chan++) {
 861                 int i;
 862
 863                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 864                              (chan * 0x2000) | 0x0200);
 865                 tg3_writephy(tp, 0x16, 0x0002);
 866                 for (i = 0; i < 6; i++)
 867                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 868                 tg3_writephy(tp, 0x16, 0x0202);
 869                 if (tg3_wait_macro_done(tp))
 870                         return -EBUSY;
 871         }
 872
 873         return 0;
 874 }
 875
 876 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 877 {
 878         u32 reg32, phy9_orig;
 879         int retries, do_phy_reset, err;
 880
 881         retries = 10;
 882         do_phy_reset = 1;
 883         do {
 884                 if (do_phy_reset) {
 885                         err = tg3_bmcr_reset(tp);
 886                         if (err)
 887                                 return err;
 888                         do_phy_reset = 0;
 889                 }
 890
 891                 /* Disable transmitter and interrupt.  */
 892                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 893                         continue;
 894
 895                 reg32 |= 0x3000;
 896                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 897
 898                 /* Set full-duplex, 1000 mbps.  */
 899                 tg3_writephy(tp, MII_BMCR,
 900                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 901
 902                 /* Set to master mode.  */
 903                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 904                         continue;
 905
 906                 tg3_writephy(tp, MII_TG3_CTRL,
 907                              (MII_TG3_CTRL_AS_MASTER |
 908                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 909
 910                 /* Enable SM_DSP_CLOCK and 6dB.  */
 911                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 912
 913                 /* Block the PHY control access.  */
 914                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 915                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 916
 917                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 918                 if (!err)
 919                         break;
 920         } while (--retries);
 921
 922         err = tg3_phy_reset_chanpat(tp);
 923         if (err)
 924                 return err;
 925
 926         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 927         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 928
 929         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 930         tg3_writephy(tp, 0x16, 0x0000);
 931
 932         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 933             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 934                 /* Set Extended packet length bit for jumbo frames */
 935                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 936         }
 937         else {
 938                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 939         }
 940
 941         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 942
 943         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 944                 reg32 &= ~0x3000;
 945                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 946         } else if (!err)
 947                 err = -EBUSY;
 948
 949         return err;
 950 }
 951
 952 static void tg3_link_report(struct tg3 *);
 953
 954 /* This will reset the tigon3 PHY if there is no valid
 955  * link unless the FORCE argument is non-zero.
 956  */
 957 static int tg3_phy_reset(struct tg3 *tp)
 958 {
 959         u32 phy_status;
 960         int err;
 961
 962         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 963         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 964         if (err != 0)
 965                 return -EBUSY;
 966
 967         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 968                 netif_carrier_off(tp->dev);
 969                 tg3_link_report(tp);
 970         }
 971
 972         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 973             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 974             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 975                 err = tg3_phy_reset_5703_4_5(tp);
 976                 if (err)
 977                         return err;
 978                 goto out;
 979         }
 980
 981         err = tg3_bmcr_reset(tp);
 982         if (err)
 983                 return err;
 984
 985 out:
 986         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 987                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 988                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 989                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 990                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 991                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 992                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 993         }
 994         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 995                 tg3_writephy(tp, 0x1c, 0x8d68);
 996                 tg3_writephy(tp, 0x1c, 0x8d68);
 997         }
 998         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
 999                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1000                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1001                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1002                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1003                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1004                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1005                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1006                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1007         }
1008         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1010                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1011                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1013         }
1014         /* Set Extended packet length bit (bit 14) on all chips that */
1015         /* support jumbo frames */
1016         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1017                 /* Cannot do read-modify-write on 5401 */
1018                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1019         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1020                 u32 phy_reg;
1021
1022                 /* Set bit 14 with read-modify-write to preserve other bits */
1023                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1024                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1025                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1026         }
1027
1028         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1029          * jumbo frames transmission.
1030          */
1031         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1032                 u32 phy_reg;
1033
1034                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1035                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1036                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1037         }
1038
1039         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1040                 u32 phy_reg;
1041
1042                 /* adjust output voltage */
1043                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1044
1045                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1046                         u32 phy_reg2;
1047
1048                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1049                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1050                         /* Enable auto-MDIX */
1051                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1052                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1053                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1054                 }
1055         }
1056
1057         tg3_phy_set_wirespeed(tp);
1058         return 0;
1059 }
1060
1061 static void tg3_frob_aux_power(struct tg3 *tp)
1062 {
1063         struct tg3 *tp_peer = tp;
1064
1065         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1066                 return;
1067
1068         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1069             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1070                 struct net_device *dev_peer;
1071
1072                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1073                 /* remove_one() may have been run on the peer. */
1074                 if (!dev_peer)
1075                         tp_peer = tp;
1076                 else
1077                         tp_peer = netdev_priv(dev_peer);
1078         }
1079
1080         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1081             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1082             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1083             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1084                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1085                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1086                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1087                                     (GRC_LCLCTRL_GPIO_OE0 |
1088                                      GRC_LCLCTRL_GPIO_OE1 |
1089                                      GRC_LCLCTRL_GPIO_OE2 |
1090                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1091                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1092                                     100);
1093                 } else {
1094                         u32 no_gpio2;
1095                         u32 grc_local_ctrl = 0;
1096
1097                         if (tp_peer != tp &&
1098                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1099                                 return;
1100
1101                         /* Workaround to prevent overdrawing Amps. */
1102                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1103                             ASIC_REV_5714) {
1104                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1105                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1106                                             grc_local_ctrl, 100);
1107                         }
1108
1109                         /* On 5753 and variants, GPIO2 cannot be used. */
1110                         no_gpio2 = tp->nic_sram_data_cfg &
1111                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1112
1113                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1114                                          GRC_LCLCTRL_GPIO_OE1 |
1115                                          GRC_LCLCTRL_GPIO_OE2 |
1116                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1117                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1118                         if (no_gpio2) {
1119                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1120                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1121                         }
1122                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1123                                                     grc_local_ctrl, 100);
1124
1125                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1126
1127                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1128                                                     grc_local_ctrl, 100);
1129
1130                         if (!no_gpio2) {
1131                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1132                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1133                                             grc_local_ctrl, 100);
1134                         }
1135                 }
1136         } else {
1137                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1138                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1139                         if (tp_peer != tp &&
1140                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1141                                 return;
1142
1143                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1144                                     (GRC_LCLCTRL_GPIO_OE1 |
1145                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1146
1147                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1148                                     GRC_LCLCTRL_GPIO_OE1, 100);
1149
1150                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1151                                     (GRC_LCLCTRL_GPIO_OE1 |
1152                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1153                 }
1154         }
1155 }
1156
1157 static int tg3_setup_phy(struct tg3 *, int);
1158
1159 #define RESET_KIND_SHUTDOWN     0
1160 #define RESET_KIND_INIT         1
1161 #define RESET_KIND_SUSPEND      2
1162
1163 static void tg3_write_sig_post_reset(struct tg3 *, int);
1164 static int tg3_halt_cpu(struct tg3 *, u32);
1165 static int tg3_nvram_lock(struct tg3 *);
1166 static void tg3_nvram_unlock(struct tg3 *);
1167
1168 static void tg3_power_down_phy(struct tg3 *tp)
1169 {
1170         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
1171                 return;
1172
1173         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
1174                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1175                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1176                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1177         }
1178
1179         /* The PHY should not be powered down on some chips because
1180          * of bugs.
1181          */
1182         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1183             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1184             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1185              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1186                 return;
1187         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1188 }
1189
1190 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1191 {
1192         u32 misc_host_ctrl;
1193         u16 power_control, power_caps;
1194         int pm = tp->pm_cap;
1195
1196         /* Make sure register accesses (indirect or otherwise)
1197          * will function correctly.
1198          */
1199         pci_write_config_dword(tp->pdev,
1200                                TG3PCI_MISC_HOST_CTRL,
1201                                tp->misc_host_ctrl);
1202
1203         pci_read_config_word(tp->pdev,
1204                              pm + PCI_PM_CTRL,
1205                              &power_control);
1206         power_control |= PCI_PM_CTRL_PME_STATUS;
1207         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1208         switch (state) {
1209         case PCI_D0:
1210                 power_control |= 0;
1211                 pci_write_config_word(tp->pdev,
1212                                       pm + PCI_PM_CTRL,
1213                                       power_control);
1214                 udelay(100);    /* Delay after power state change */
1215
1216                 /* Switch out of Vaux if it is a NIC */
1217                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1218                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1219
1220                 return 0;
1221
1222         case PCI_D1:
1223                 power_control |= 1;
1224                 break;
1225
1226         case PCI_D2:
1227                 power_control |= 2;
1228                 break;
1229
1230         case PCI_D3hot:
1231                 power_control |= 3;
1232                 break;
1233
1234         default:
1235                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1236                        "requested.\n",
1237                        tp->dev->name, state);
1238                 return -EINVAL;
1239         };
1240
1241         power_control |= PCI_PM_CTRL_PME_ENABLE;
1242
1243         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1244         tw32(TG3PCI_MISC_HOST_CTRL,
1245              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1246
1247         if (tp->link_config.phy_is_low_power == 0) {
1248                 tp->link_config.phy_is_low_power = 1;
1249                 tp->link_config.orig_speed = tp->link_config.speed;
1250                 tp->link_config.orig_duplex = tp->link_config.duplex;
1251                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1252         }
1253
1254         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1255                 tp->link_config.speed = SPEED_10;
1256                 tp->link_config.duplex = DUPLEX_HALF;
1257                 tp->link_config.autoneg = AUTONEG_ENABLE;
1258                 tg3_setup_phy(tp, 0);
1259         }
1260
1261         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1262                 u32 val;
1263
1264                 val = tr32(GRC_VCPU_EXT_CTRL);
1265                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1266         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1267                 int i;
1268                 u32 val;
1269
1270                 for (i = 0; i < 200; i++) {
1271                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1272                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1273                                 break;
1274                         msleep(1);
1275                 }
1276         }
1277         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1278                                              WOL_DRV_STATE_SHUTDOWN |
1279                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1280
1281         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1282
1283         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1284                 u32 mac_mode;
1285
1286                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1287                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1288                         udelay(40);
1289
1290                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1291                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1292                         else
1293                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1294
1295                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1296                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1297                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1298                 } else {
1299                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1300                 }
1301
1302                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1303                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1304
1305                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1306                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1307                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1308
1309                 tw32_f(MAC_MODE, mac_mode);
1310                 udelay(100);
1311
1312                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1313                 udelay(10);
1314         }
1315
1316         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1317             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1318              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1319                 u32 base_val;
1320
1321                 base_val = tp->pci_clock_ctrl;
1322                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1323                              CLOCK_CTRL_TXCLK_DISABLE);
1324
1325                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1326                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1327         } else if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
1328                 /* do nothing */
1329         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1330                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1331                 u32 newbits1, newbits2;
1332
1333                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1334                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1335                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1336                                     CLOCK_CTRL_TXCLK_DISABLE |
1337                                     CLOCK_CTRL_ALTCLK);
1338                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1339                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1340                         newbits1 = CLOCK_CTRL_625_CORE;
1341                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1342                 } else {
1343                         newbits1 = CLOCK_CTRL_ALTCLK;
1344                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1345                 }
1346
1347                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1348                             40);
1349
1350                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1351                             40);
1352
1353                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1354                         u32 newbits3;
1355
1356                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1357                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1358                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1359                                             CLOCK_CTRL_TXCLK_DISABLE |
1360                                             CLOCK_CTRL_44MHZ_CORE);
1361                         } else {
1362                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1363                         }
1364
1365                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1366                                     tp->pci_clock_ctrl | newbits3, 40);
1367                 }
1368         }
1369
1370         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1371             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1372                 tg3_power_down_phy(tp);
1373
1374         tg3_frob_aux_power(tp);
1375
1376         /* Workaround for unstable PLL clock */
1377         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1378             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1379                 u32 val = tr32(0x7d00);
1380
1381                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1382                 tw32(0x7d00, val);
1383                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1384                         int err;
1385
1386                         err = tg3_nvram_lock(tp);
1387                         tg3_halt_cpu(tp, RX_CPU_BASE);
1388                         if (!err)
1389                                 tg3_nvram_unlock(tp);
1390                 }
1391         }
1392
1393         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1394
1395         /* Finally, set the new power state. */
1396         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1397         udelay(100);    /* Delay after power state change */
1398
1399         return 0;
1400 }
1401
1402 static void tg3_link_report(struct tg3 *tp)
1403 {
1404         if (!netif_carrier_ok(tp->dev)) {
1405                 printk(KERN_INFO PFX "%s: Link is down.\n", tp->dev->name);
1406         } else {
1407                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1408                        tp->dev->name,
1409                        (tp->link_config.active_speed == SPEED_1000 ?
1410                         1000 :
1411                         (tp->link_config.active_speed == SPEED_100 ?
1412                          100 : 10)),
1413                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1414                         "full" : "half"));
1415
1416                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1417                        "%s for RX.\n",
1418                        tp->dev->name,
1419                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1420                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1421         }
1422 }
1423
1424 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1425 {
1426         u32 new_tg3_flags = 0;
1427         u32 old_rx_mode = tp->rx_mode;
1428         u32 old_tx_mode = tp->tx_mode;
1429
1430         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1431
1432                 /* Convert 1000BaseX flow control bits to 1000BaseT
1433                  * bits before resolving flow control.
1434                  */
1435                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1436                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1437                                        ADVERTISE_PAUSE_ASYM);
1438                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1439
1440                         if (local_adv & ADVERTISE_1000XPAUSE)
1441                                 local_adv |= ADVERTISE_PAUSE_CAP;
1442                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1443                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1444                         if (remote_adv & LPA_1000XPAUSE)
1445                                 remote_adv |= LPA_PAUSE_CAP;
1446                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1447                                 remote_adv |= LPA_PAUSE_ASYM;
1448                 }
1449
1450                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1451                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1452                                 if (remote_adv & LPA_PAUSE_CAP)
1453                                         new_tg3_flags |=
1454                                                 (TG3_FLAG_RX_PAUSE |
1455                                                 TG3_FLAG_TX_PAUSE);
1456                                 else if (remote_adv & LPA_PAUSE_ASYM)
1457                                         new_tg3_flags |=
1458                                                 (TG3_FLAG_RX_PAUSE);
1459                         } else {
1460                                 if (remote_adv & LPA_PAUSE_CAP)
1461                                         new_tg3_flags |=
1462                                                 (TG3_FLAG_RX_PAUSE |
1463                                                 TG3_FLAG_TX_PAUSE);
1464                         }
1465                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1466                         if ((remote_adv & LPA_PAUSE_CAP) &&
1467                         (remote_adv & LPA_PAUSE_ASYM))
1468                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1469                 }
1470
1471                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1472                 tp->tg3_flags |= new_tg3_flags;
1473         } else {
1474                 new_tg3_flags = tp->tg3_flags;
1475         }
1476
1477         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1478                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1479         else
1480                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1481
1482         if (old_rx_mode != tp->rx_mode) {
1483                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1484         }
1485
1486         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1487                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1488         else
1489                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1490
1491         if (old_tx_mode != tp->tx_mode) {
1492                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1493         }
1494 }
1495
1496 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1497 {
1498         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1499         case MII_TG3_AUX_STAT_10HALF:
1500                 *speed = SPEED_10;
1501                 *duplex = DUPLEX_HALF;
1502                 break;
1503
1504         case MII_TG3_AUX_STAT_10FULL:
1505                 *speed = SPEED_10;
1506                 *duplex = DUPLEX_FULL;
1507                 break;
1508
1509         case MII_TG3_AUX_STAT_100HALF:
1510                 *speed = SPEED_100;
1511                 *duplex = DUPLEX_HALF;
1512                 break;
1513
1514         case MII_TG3_AUX_STAT_100FULL:
1515                 *speed = SPEED_100;
1516                 *duplex = DUPLEX_FULL;
1517                 break;
1518
1519         case MII_TG3_AUX_STAT_1000HALF:
1520                 *speed = SPEED_1000;
1521                 *duplex = DUPLEX_HALF;
1522                 break;
1523
1524         case MII_TG3_AUX_STAT_1000FULL:
1525                 *speed = SPEED_1000;
1526                 *duplex = DUPLEX_FULL;
1527                 break;
1528
1529         default:
1530                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1531                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1532                                  SPEED_10;
1533                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1534                                   DUPLEX_HALF;
1535                         break;
1536                 }
1537                 *speed = SPEED_INVALID;
1538                 *duplex = DUPLEX_INVALID;
1539                 break;
1540         };
1541 }
1542
1543 static void tg3_phy_copper_begin(struct tg3 *tp)
1544 {
1545         u32 new_adv;
1546         int i;
1547
1548         if (tp->link_config.phy_is_low_power) {
1549                 /* Entering low power mode.  Disable gigabit and
1550                  * 100baseT advertisements.
1551                  */
1552                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1553
1554                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1555                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1556                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1557                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1558
1559                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1560         } else if (tp->link_config.speed == SPEED_INVALID) {
1561                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1562                         tp->link_config.advertising &=
1563                                 ~(ADVERTISED_1000baseT_Half |
1564                                   ADVERTISED_1000baseT_Full);
1565
1566                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1567                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1568                         new_adv |= ADVERTISE_10HALF;
1569                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1570                         new_adv |= ADVERTISE_10FULL;
1571                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1572                         new_adv |= ADVERTISE_100HALF;
1573                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1574                         new_adv |= ADVERTISE_100FULL;
1575                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1576
1577                 if (tp->link_config.advertising &
1578                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1579                         new_adv = 0;
1580                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1581                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1582                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1583                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1584                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1585                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1586                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1587                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1588                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1589                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1590                 } else {
1591                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1592                 }
1593         } else {
1594                 /* Asking for a specific link mode. */
1595                 if (tp->link_config.speed == SPEED_1000) {
1596                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1597                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1598
1599                         if (tp->link_config.duplex == DUPLEX_FULL)
1600                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1601                         else
1602                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1603                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1604                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1605                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1606                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1607                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1608                 } else {
1609                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1610
1611                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1612                         if (tp->link_config.speed == SPEED_100) {
1613                                 if (tp->link_config.duplex == DUPLEX_FULL)
1614                                         new_adv |= ADVERTISE_100FULL;
1615                                 else
1616                                         new_adv |= ADVERTISE_100HALF;
1617                         } else {
1618                                 if (tp->link_config.duplex == DUPLEX_FULL)
1619                                         new_adv |= ADVERTISE_10FULL;
1620                                 else
1621                                         new_adv |= ADVERTISE_10HALF;
1622                         }
1623                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1624                 }
1625         }
1626
1627         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1628             tp->link_config.speed != SPEED_INVALID) {
1629                 u32 bmcr, orig_bmcr;
1630
1631                 tp->link_config.active_speed = tp->link_config.speed;
1632                 tp->link_config.active_duplex = tp->link_config.duplex;
1633
1634                 bmcr = 0;
1635                 switch (tp->link_config.speed) {
1636                 default:
1637                 case SPEED_10:
1638                         break;
1639
1640                 case SPEED_100:
1641                         bmcr |= BMCR_SPEED100;
1642                         break;
1643
1644                 case SPEED_1000:
1645                         bmcr |= TG3_BMCR_SPEED1000;
1646                         break;
1647                 };
1648
1649                 if (tp->link_config.duplex == DUPLEX_FULL)
1650                         bmcr |= BMCR_FULLDPLX;
1651
1652                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1653                     (bmcr != orig_bmcr)) {
1654                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1655                         for (i = 0; i < 1500; i++) {
1656                                 u32 tmp;
1657
1658                                 udelay(10);
1659                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1660                                     tg3_readphy(tp, MII_BMSR, &tmp))
1661                                         continue;
1662                                 if (!(tmp & BMSR_LSTATUS)) {
1663                                         udelay(40);
1664                                         break;
1665                                 }
1666                         }
1667                         tg3_writephy(tp, MII_BMCR, bmcr);
1668                         udelay(40);
1669                 }
1670         } else {
1671                 tg3_writephy(tp, MII_BMCR,
1672                              BMCR_ANENABLE | BMCR_ANRESTART);
1673         }
1674 }
1675
1676 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1677 {
1678         int err;
1679
1680         /* Turn off tap power management. */
1681         /* Set Extended packet length bit */
1682         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1683
1684         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1685         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1686
1687         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1688         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1689
1690         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1691         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1692
1693         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1694         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1695
1696         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1697         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1698
1699         udelay(40);
1700
1701         return err;
1702 }
1703
1704 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1705 {
1706         u32 adv_reg, all_mask = 0;
1707
1708         if (mask & ADVERTISED_10baseT_Half)
1709                 all_mask |= ADVERTISE_10HALF;
1710         if (mask & ADVERTISED_10baseT_Full)
1711                 all_mask |= ADVERTISE_10FULL;
1712         if (mask & ADVERTISED_100baseT_Half)
1713                 all_mask |= ADVERTISE_100HALF;
1714         if (mask & ADVERTISED_100baseT_Full)
1715                 all_mask |= ADVERTISE_100FULL;
1716
1717         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1718                 return 0;
1719
1720         if ((adv_reg & all_mask) != all_mask)
1721                 return 0;
1722         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1723                 u32 tg3_ctrl;
1724
1725                 all_mask = 0;
1726                 if (mask & ADVERTISED_1000baseT_Half)
1727                         all_mask |= ADVERTISE_1000HALF;
1728                 if (mask & ADVERTISED_1000baseT_Full)
1729                         all_mask |= ADVERTISE_1000FULL;
1730
1731                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1732                         return 0;
1733
1734                 if ((tg3_ctrl & all_mask) != all_mask)
1735                         return 0;
1736         }
1737         return 1;
1738 }
1739
1740 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1741 {
1742         int current_link_up;
1743         u32 bmsr, dummy;
1744         u16 current_speed;
1745         u8 current_duplex;
1746         int i, err;
1747
1748         tw32(MAC_EVENT, 0);
1749
1750         tw32_f(MAC_STATUS,
1751              (MAC_STATUS_SYNC_CHANGED |
1752               MAC_STATUS_CFG_CHANGED |
1753               MAC_STATUS_MI_COMPLETION |
1754               MAC_STATUS_LNKSTATE_CHANGED));
1755         udelay(40);
1756
1757         tp->mi_mode = MAC_MI_MODE_BASE;
1758         tw32_f(MAC_MI_MODE, tp->mi_mode);
1759         udelay(80);
1760
1761         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1762
1763         /* Some third-party PHYs need to be reset on link going
1764          * down.
1765          */
1766         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1767              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1768              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1769             netif_carrier_ok(tp->dev)) {
1770                 tg3_readphy(tp, MII_BMSR, &bmsr);
1771                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1772                     !(bmsr & BMSR_LSTATUS))
1773                         force_reset = 1;
1774         }
1775         if (force_reset)
1776                 tg3_phy_reset(tp);
1777
1778         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1779                 tg3_readphy(tp, MII_BMSR, &bmsr);
1780                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1781                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1782                         bmsr = 0;
1783
1784                 if (!(bmsr & BMSR_LSTATUS)) {
1785                         err = tg3_init_5401phy_dsp(tp);
1786                         if (err)
1787                                 return err;
1788
1789                         tg3_readphy(tp, MII_BMSR, &bmsr);
1790                         for (i = 0; i < 1000; i++) {
1791                                 udelay(10);
1792                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1793                                     (bmsr & BMSR_LSTATUS)) {
1794                                         udelay(40);
1795                                         break;
1796                                 }
1797                         }
1798
1799                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1800                             !(bmsr & BMSR_LSTATUS) &&
1801                             tp->link_config.active_speed == SPEED_1000) {
1802                                 err = tg3_phy_reset(tp);
1803                                 if (!err)
1804                                         err = tg3_init_5401phy_dsp(tp);
1805                                 if (err)
1806                                         return err;
1807                         }
1808                 }
1809         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1810                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1811                 /* 5701 {A0,B0} CRC bug workaround */
1812                 tg3_writephy(tp, 0x15, 0x0a75);
1813                 tg3_writephy(tp, 0x1c, 0x8c68);
1814                 tg3_writephy(tp, 0x1c, 0x8d68);
1815                 tg3_writephy(tp, 0x1c, 0x8c68);
1816         }
1817
1818         /* Clear pending interrupts... */
1819         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1820         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1821
1822         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1823                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1824         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1825                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1826
1827         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1828             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1829                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1830                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1831                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1832                 else
1833                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1834         }
1835
1836         current_link_up = 0;
1837         current_speed = SPEED_INVALID;
1838         current_duplex = DUPLEX_INVALID;
1839
1840         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1841                 u32 val;
1842
1843                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1844                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1845                 if (!(val & (1 << 10))) {
1846                         val |= (1 << 10);
1847                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1848                         goto relink;
1849                 }
1850         }
1851
1852         bmsr = 0;
1853         for (i = 0; i < 100; i++) {
1854                 tg3_readphy(tp, MII_BMSR, &bmsr);
1855                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1856                     (bmsr & BMSR_LSTATUS))
1857                         break;
1858                 udelay(40);
1859         }
1860
1861         if (bmsr & BMSR_LSTATUS) {
1862                 u32 aux_stat, bmcr;
1863
1864                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1865                 for (i = 0; i < 2000; i++) {
1866                         udelay(10);
1867                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1868                             aux_stat)
1869                                 break;
1870                 }
1871
1872                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1873                                              &current_speed,
1874                                              &current_duplex);
1875
1876                 bmcr = 0;
1877                 for (i = 0; i < 200; i++) {
1878                         tg3_readphy(tp, MII_BMCR, &bmcr);
1879                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1880                                 continue;
1881                         if (bmcr && bmcr != 0x7fff)
1882                                 break;
1883                         udelay(10);
1884                 }
1885
1886                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1887                         if (bmcr & BMCR_ANENABLE) {
1888                                 current_link_up = 1;
1889
1890                                 /* Force autoneg restart if we are exiting
1891                                  * low power mode.
1892                                  */
1893                                 if (!tg3_copper_is_advertising_all(tp,
1894                                                 tp->link_config.advertising))
1895                                         current_link_up = 0;
1896                         } else {
1897                                 current_link_up = 0;
1898                         }
1899                 } else {
1900                         if (!(bmcr & BMCR_ANENABLE) &&
1901                             tp->link_config.speed == current_speed &&
1902                             tp->link_config.duplex == current_duplex) {
1903                                 current_link_up = 1;
1904                         } else {
1905                                 current_link_up = 0;
1906                         }
1907                 }
1908
1909                 tp->link_config.active_speed = current_speed;
1910                 tp->link_config.active_duplex = current_duplex;
1911         }
1912
1913         if (current_link_up == 1 &&
1914             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1915             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1916                 u32 local_adv, remote_adv;
1917
1918                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1919                         local_adv = 0;
1920                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1921
1922                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1923                         remote_adv = 0;
1924
1925                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1926
1927                 /* If we are not advertising full pause capability,
1928                  * something is wrong.  Bring the link down and reconfigure.
1929                  */
1930                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1931                         current_link_up = 0;
1932                 } else {
1933                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1934                 }
1935         }
1936 relink:
1937         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1938                 u32 tmp;
1939
1940                 tg3_phy_copper_begin(tp);
1941
1942                 tg3_readphy(tp, MII_BMSR, &tmp);
1943                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1944                     (tmp & BMSR_LSTATUS))
1945                         current_link_up = 1;
1946         }
1947
1948         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1949         if (current_link_up == 1) {
1950                 if (tp->link_config.active_speed == SPEED_100 ||
1951                     tp->link_config.active_speed == SPEED_10)
1952                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1953                 else
1954                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1955         } else
1956                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1957
1958         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1959         if (tp->link_config.active_duplex == DUPLEX_HALF)
1960                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1961
1962         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1963         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1964                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1965                     (current_link_up == 1 &&
1966                      tp->link_config.active_speed == SPEED_10))
1967                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1968         } else {
1969                 if (current_link_up == 1)
1970                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1971         }
1972
1973         /* ??? Without this setting Netgear GA302T PHY does not
1974          * ??? send/receive packets...
1975          */
1976         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
1977             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1978                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1979                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1980                 udelay(80);
1981         }
1982
1983         tw32_f(MAC_MODE, tp->mac_mode);
1984         udelay(40);
1985
1986         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
1987                 /* Polled via timer. */
1988                 tw32_f(MAC_EVENT, 0);
1989         } else {
1990                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1991         }
1992         udelay(40);
1993
1994         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1995             current_link_up == 1 &&
1996             tp->link_config.active_speed == SPEED_1000 &&
1997             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
1998              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
1999                 udelay(120);
2000                 tw32_f(MAC_STATUS,
2001                      (MAC_STATUS_SYNC_CHANGED |
2002                       MAC_STATUS_CFG_CHANGED));
2003                 udelay(40);
2004                 tg3_write_mem(tp,
2005                               NIC_SRAM_FIRMWARE_MBOX,
2006                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2007         }
2008
2009         if (current_link_up != netif_carrier_ok(tp->dev)) {
2010                 if (current_link_up)
2011                         netif_carrier_on(tp->dev);
2012                 else
2013                         netif_carrier_off(tp->dev);
2014                 tg3_link_report(tp);
2015         }
2016
2017         return 0;
2018 }
2019
2020 struct tg3_fiber_aneginfo {
2021         int state;
2022 #define ANEG_STATE_UNKNOWN              0
2023 #define ANEG_STATE_AN_ENABLE            1
2024 #define ANEG_STATE_RESTART_INIT         2
2025 #define ANEG_STATE_RESTART              3
2026 #define ANEG_STATE_DISABLE_LINK_OK      4
2027 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2028 #define ANEG_STATE_ABILITY_DETECT       6
2029 #define ANEG_STATE_ACK_DETECT_INIT      7
2030 #define ANEG_STATE_ACK_DETECT           8
2031 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2032 #define ANEG_STATE_COMPLETE_ACK         10
2033 #define ANEG_STATE_IDLE_DETECT_INIT     11
2034 #define ANEG_STATE_IDLE_DETECT          12
2035 #define ANEG_STATE_LINK_OK              13
2036 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2037 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2038
2039         u32 flags;
2040 #define MR_AN_ENABLE            0x00000001
2041 #define MR_RESTART_AN           0x00000002
2042 #define MR_AN_COMPLETE          0x00000004
2043 #define MR_PAGE_RX              0x00000008
2044 #define MR_NP_LOADED            0x00000010
2045 #define MR_TOGGLE_TX            0x00000020
2046 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2047 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2048 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2049 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2050 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2051 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2052 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2053 #define MR_TOGGLE_RX            0x00002000
2054 #define MR_NP_RX                0x00004000
2055
2056 #define MR_LINK_OK              0x80000000
2057
2058         unsigned long link_time, cur_time;
2059
2060         u32 ability_match_cfg;
2061         int ability_match_count;
2062
2063         char ability_match, idle_match, ack_match;
2064
2065         u32 txconfig, rxconfig;
2066 #define ANEG_CFG_NP             0x00000080
2067 #define ANEG_CFG_ACK            0x00000040
2068 #define ANEG_CFG_RF2            0x00000020
2069 #define ANEG_CFG_RF1            0x00000010
2070 #define ANEG_CFG_PS2            0x00000001
2071 #define ANEG_CFG_PS1            0x00008000
2072 #define ANEG_CFG_HD             0x00004000
2073 #define ANEG_CFG_FD             0x00002000
2074 #define ANEG_CFG_INVAL          0x00001f06
2075
2076 };
2077 #define ANEG_OK         0
2078 #define ANEG_DONE       1
2079 #define ANEG_TIMER_ENAB 2
2080 #define ANEG_FAILED     -1
2081
2082 #define ANEG_STATE_SETTLE_TIME  10000
2083
2084 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2085                                    struct tg3_fiber_aneginfo *ap)
2086 {
2087         unsigned long delta;
2088         u32 rx_cfg_reg;
2089         int ret;
2090
2091         if (ap->state == ANEG_STATE_UNKNOWN) {
2092                 ap->rxconfig = 0;
2093                 ap->link_time = 0;
2094                 ap->cur_time = 0;
2095                 ap->ability_match_cfg = 0;
2096                 ap->ability_match_count = 0;
2097                 ap->ability_match = 0;
2098                 ap->idle_match = 0;
2099                 ap->ack_match = 0;
2100         }
2101         ap->cur_time++;
2102
2103         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2104                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2105
2106                 if (rx_cfg_reg != ap->ability_match_cfg) {
2107                         ap->ability_match_cfg = rx_cfg_reg;
2108                         ap->ability_match = 0;
2109                         ap->ability_match_count = 0;
2110                 } else {
2111                         if (++ap->ability_match_count > 1) {
2112                                 ap->ability_match = 1;
2113                                 ap->ability_match_cfg = rx_cfg_reg;
2114                         }
2115                 }
2116                 if (rx_cfg_reg & ANEG_CFG_ACK)
2117                         ap->ack_match = 1;
2118                 else
2119                         ap->ack_match = 0;
2120
2121                 ap->idle_match = 0;
2122         } else {
2123                 ap->idle_match = 1;
2124                 ap->ability_match_cfg = 0;
2125                 ap->ability_match_count = 0;
2126                 ap->ability_match = 0;
2127                 ap->ack_match = 0;
2128
2129                 rx_cfg_reg = 0;
2130         }
2131
2132         ap->rxconfig = rx_cfg_reg;
2133         ret = ANEG_OK;
2134
2135         switch(ap->state) {
2136         case ANEG_STATE_UNKNOWN:
2137                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2138                         ap->state = ANEG_STATE_AN_ENABLE;
2139
2140                 /* fallthru */
2141         case ANEG_STATE_AN_ENABLE:
2142                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2143                 if (ap->flags & MR_AN_ENABLE) {
2144                         ap->link_time = 0;
2145                         ap->cur_time = 0;
2146                         ap->ability_match_cfg = 0;
2147                         ap->ability_match_count = 0;
2148                         ap->ability_match = 0;
2149                         ap->idle_match = 0;
2150                         ap->ack_match = 0;
2151
2152                         ap->state = ANEG_STATE_RESTART_INIT;
2153                 } else {
2154                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2155                 }
2156                 break;
2157
2158         case ANEG_STATE_RESTART_INIT:
2159                 ap->link_time = ap->cur_time;
2160                 ap->flags &= ~(MR_NP_LOADED);
2161                 ap->txconfig = 0;
2162                 tw32(MAC_TX_AUTO_NEG, 0);
2163                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2164                 tw32_f(MAC_MODE, tp->mac_mode);
2165                 udelay(40);
2166
2167                 ret = ANEG_TIMER_ENAB;
2168                 ap->state = ANEG_STATE_RESTART;
2169
2170                 /* fallthru */
2171         case ANEG_STATE_RESTART:
2172                 delta = ap->cur_time - ap->link_time;
2173                 if (delta > ANEG_STATE_SETTLE_TIME) {
2174                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2175                 } else {
2176                         ret = ANEG_TIMER_ENAB;
2177                 }
2178                 break;
2179
2180         case ANEG_STATE_DISABLE_LINK_OK:
2181                 ret = ANEG_DONE;
2182                 break;
2183
2184         case ANEG_STATE_ABILITY_DETECT_INIT:
2185                 ap->flags &= ~(MR_TOGGLE_TX);
2186                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2187                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2188                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2189                 tw32_f(MAC_MODE, tp->mac_mode);
2190                 udelay(40);
2191
2192                 ap->state = ANEG_STATE_ABILITY_DETECT;
2193                 break;
2194
2195         case ANEG_STATE_ABILITY_DETECT:
2196                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2197                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2198                 }
2199                 break;
2200
2201         case ANEG_STATE_ACK_DETECT_INIT:
2202                 ap->txconfig |= ANEG_CFG_ACK;
2203                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2204                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2205                 tw32_f(MAC_MODE, tp->mac_mode);
2206                 udelay(40);
2207
2208                 ap->state = ANEG_STATE_ACK_DETECT;
2209
2210                 /* fallthru */
2211         case ANEG_STATE_ACK_DETECT:
2212                 if (ap->ack_match != 0) {
2213                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2214                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2215                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2216                         } else {
2217                                 ap->state = ANEG_STATE_AN_ENABLE;
2218                         }
2219                 } else if (ap->ability_match != 0 &&
2220                            ap->rxconfig == 0) {
2221                         ap->state = ANEG_STATE_AN_ENABLE;
2222                 }
2223                 break;
2224
2225         case ANEG_STATE_COMPLETE_ACK_INIT:
2226                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2227                         ret = ANEG_FAILED;
2228                         break;
2229                 }
2230                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2231                                MR_LP_ADV_HALF_DUPLEX |
2232                                MR_LP_ADV_SYM_PAUSE |
2233                                MR_LP_ADV_ASYM_PAUSE |
2234                                MR_LP_ADV_REMOTE_FAULT1 |
2235                                MR_LP_ADV_REMOTE_FAULT2 |
2236                                MR_LP_ADV_NEXT_PAGE |
2237                                MR_TOGGLE_RX |
2238                                MR_NP_RX);
2239                 if (ap->rxconfig & ANEG_CFG_FD)
2240                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2241                 if (ap->rxconfig & ANEG_CFG_HD)
2242                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2243                 if (ap->rxconfig & ANEG_CFG_PS1)
2244                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2245                 if (ap->rxconfig & ANEG_CFG_PS2)
2246                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2247                 if (ap->rxconfig & ANEG_CFG_RF1)
2248                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2249                 if (ap->rxconfig & ANEG_CFG_RF2)
2250                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2251                 if (ap->rxconfig & ANEG_CFG_NP)
2252                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2253
2254                 ap->link_time = ap->cur_time;
2255
2256                 ap->flags ^= (MR_TOGGLE_TX);
2257                 if (ap->rxconfig & 0x0008)
2258                         ap->flags |= MR_TOGGLE_RX;
2259                 if (ap->rxconfig & ANEG_CFG_NP)
2260                         ap->flags |= MR_NP_RX;
2261                 ap->flags |= MR_PAGE_RX;
2262
2263                 ap->state = ANEG_STATE_COMPLETE_ACK;
2264                 ret = ANEG_TIMER_ENAB;
2265                 break;
2266
2267         case ANEG_STATE_COMPLETE_ACK:
2268                 if (ap->ability_match != 0 &&
2269                     ap->rxconfig == 0) {
2270                         ap->state = ANEG_STATE_AN_ENABLE;
2271                         break;
2272                 }
2273                 delta = ap->cur_time - ap->link_time;
2274                 if (delta > ANEG_STATE_SETTLE_TIME) {
2275                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2276                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2277                         } else {
2278                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2279                                     !(ap->flags & MR_NP_RX)) {
2280                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2281                                 } else {
2282                                         ret = ANEG_FAILED;
2283                                 }
2284                         }
2285                 }
2286                 break;
2287
2288         case ANEG_STATE_IDLE_DETECT_INIT:
2289                 ap->link_time = ap->cur_time;
2290                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2291                 tw32_f(MAC_MODE, tp->mac_mode);
2292                 udelay(40);
2293
2294                 ap->state = ANEG_STATE_IDLE_DETECT;
2295                 ret = ANEG_TIMER_ENAB;
2296                 break;
2297
2298         case ANEG_STATE_IDLE_DETECT:
2299                 if (ap->ability_match != 0 &&
2300                     ap->rxconfig == 0) {
2301                         ap->state = ANEG_STATE_AN_ENABLE;
2302                         break;
2303                 }
2304                 delta = ap->cur_time - ap->link_time;
2305                 if (delta > ANEG_STATE_SETTLE_TIME) {
2306                         /* XXX another gem from the Broadcom driver :( */
2307                         ap->state = ANEG_STATE_LINK_OK;
2308                 }
2309                 break;
2310
2311         case ANEG_STATE_LINK_OK:
2312                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2313                 ret = ANEG_DONE;
2314                 break;
2315
2316         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2317                 /* ??? unimplemented */
2318                 break;
2319
2320         case ANEG_STATE_NEXT_PAGE_WAIT:
2321                 /* ??? unimplemented */
2322                 break;
2323
2324         default:
2325                 ret = ANEG_FAILED;
2326                 break;
2327         };
2328
2329         return ret;
2330 }
2331
2332 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2333 {
2334         int res = 0;
2335         struct tg3_fiber_aneginfo aninfo;
2336         int status = ANEG_FAILED;
2337         unsigned int tick;
2338         u32 tmp;
2339
2340         tw32_f(MAC_TX_AUTO_NEG, 0);
2341
2342         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2343         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2344         udelay(40);
2345
2346         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2347         udelay(40);
2348
2349         memset(&aninfo, 0, sizeof(aninfo));
2350         aninfo.flags |= MR_AN_ENABLE;
2351         aninfo.state = ANEG_STATE_UNKNOWN;
2352         aninfo.cur_time = 0;
2353         tick = 0;
2354         while (++tick < 195000) {
2355                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2356                 if (status == ANEG_DONE || status == ANEG_FAILED)
2357                         break;
2358
2359                 udelay(1);
2360         }
2361
2362         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2363         tw32_f(MAC_MODE, tp->mac_mode);
2364         udelay(40);
2365
2366         *flags = aninfo.flags;
2367
2368         if (status == ANEG_DONE &&
2369             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2370                              MR_LP_ADV_FULL_DUPLEX)))
2371                 res = 1;
2372
2373         return res;
2374 }
2375
2376 static void tg3_init_bcm8002(struct tg3 *tp)
2377 {
2378         u32 mac_status = tr32(MAC_STATUS);
2379         int i;
2380
2381         /* Reset when initting first time or we have a link. */
2382         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2383             !(mac_status & MAC_STATUS_PCS_SYNCED))
2384                 return;
2385
2386         /* Set PLL lock range. */
2387         tg3_writephy(tp, 0x16, 0x8007);
2388
2389         /* SW reset */
2390         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2391
2392         /* Wait for reset to complete. */
2393         /* XXX schedule_timeout() ... */
2394         for (i = 0; i < 500; i++)
2395                 udelay(10);
2396
2397         /* Config mode; select PMA/Ch 1 regs. */
2398         tg3_writephy(tp, 0x10, 0x8411);
2399
2400         /* Enable auto-lock and comdet, select txclk for tx. */
2401         tg3_writephy(tp, 0x11, 0x0a10);
2402
2403         tg3_writephy(tp, 0x18, 0x00a0);
2404         tg3_writephy(tp, 0x16, 0x41ff);
2405
2406         /* Assert and deassert POR. */
2407         tg3_writephy(tp, 0x13, 0x0400);
2408         udelay(40);
2409         tg3_writephy(tp, 0x13, 0x0000);
2410
2411         tg3_writephy(tp, 0x11, 0x0a50);
2412         udelay(40);
2413         tg3_writephy(tp, 0x11, 0x0a10);
2414
2415         /* Wait for signal to stabilize */
2416         /* XXX schedule_timeout() ... */
2417         for (i = 0; i < 15000; i++)
2418                 udelay(10);
2419
2420         /* Deselect the channel register so we can read the PHYID
2421          * later.
2422          */
2423         tg3_writephy(tp, 0x10, 0x8011);
2424 }
2425
2426 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2427 {
2428         u32 sg_dig_ctrl, sg_dig_status;
2429         u32 serdes_cfg, expected_sg_dig_ctrl;
2430         int workaround, port_a;
2431         int current_link_up;
2432
2433         serdes_cfg = 0;
2434         expected_sg_dig_ctrl = 0;
2435         workaround = 0;
2436         port_a = 1;
2437         current_link_up = 0;
2438
2439         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2440             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2441                 workaround = 1;
2442                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2443                         port_a = 0;
2444
2445                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2446                 /* preserve bits 20-23 for voltage regulator */
2447                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2448         }
2449
2450         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2451
2452         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2453                 if (sg_dig_ctrl & (1 << 31)) {
2454                         if (workaround) {
2455                                 u32 val = serdes_cfg;
2456
2457                                 if (port_a)
2458                                         val |= 0xc010000;
2459                                 else
2460                                         val |= 0x4010000;
2461                                 tw32_f(MAC_SERDES_CFG, val);
2462                         }
2463                         tw32_f(SG_DIG_CTRL, 0x01388400);
2464                 }
2465                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2466                         tg3_setup_flow_control(tp, 0, 0);
2467                         current_link_up = 1;
2468                 }
2469                 goto out;
2470         }
2471
2472         /* Want auto-negotiation.  */
2473         expected_sg_dig_ctrl = 0x81388400;
2474
2475         /* Pause capability */
2476         expected_sg_dig_ctrl |= (1 << 11);
2477
2478         /* Asymettric pause */
2479         expected_sg_dig_ctrl |= (1 << 12);
2480
2481         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2482                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2483                     tp->serdes_counter &&
2484                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2485                                     MAC_STATUS_RCVD_CFG)) ==
2486                      MAC_STATUS_PCS_SYNCED)) {
2487                         tp->serdes_counter--;
2488                         current_link_up = 1;
2489                         goto out;
2490                 }
2491 restart_autoneg:
2492                 if (workaround)
2493                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2494                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2495                 udelay(5);
2496                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2497
2498                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2499                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2500         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2501                                  MAC_STATUS_SIGNAL_DET)) {
2502                 sg_dig_status = tr32(SG_DIG_STATUS);
2503                 mac_status = tr32(MAC_STATUS);
2504
2505                 if ((sg_dig_status & (1 << 1)) &&
2506                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2507                         u32 local_adv, remote_adv;
2508
2509                         local_adv = ADVERTISE_PAUSE_CAP;
2510                         remote_adv = 0;
2511                         if (sg_dig_status & (1 << 19))
2512                                 remote_adv |= LPA_PAUSE_CAP;
2513                         if (sg_dig_status & (1 << 20))
2514                                 remote_adv |= LPA_PAUSE_ASYM;
2515
2516                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2517                         current_link_up = 1;
2518                         tp->serdes_counter = 0;
2519                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2520                 } else if (!(sg_dig_status & (1 << 1))) {
2521                         if (tp->serdes_counter)
2522                                 tp->serdes_counter--;
2523                         else {
2524                                 if (workaround) {
2525                                         u32 val = serdes_cfg;
2526
2527                                         if (port_a)
2528                                                 val |= 0xc010000;
2529                                         else
2530                                                 val |= 0x4010000;
2531
2532                                         tw32_f(MAC_SERDES_CFG, val);
2533                                 }
2534
2535                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2536                                 udelay(40);
2537
2538                                 /* Link parallel detection - link is up */
2539                                 /* only if we have PCS_SYNC and not */
2540                                 /* receiving config code words */
2541                                 mac_status = tr32(MAC_STATUS);
2542                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2543                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2544                                         tg3_setup_flow_control(tp, 0, 0);
2545                                         current_link_up = 1;
2546                                         tp->tg3_flags2 |=
2547                                                 TG3_FLG2_PARALLEL_DETECT;
2548                                         tp->serdes_counter =
2549                                                 SERDES_PARALLEL_DET_TIMEOUT;
2550                                 } else
2551                                         goto restart_autoneg;
2552                         }
2553                 }
2554         } else {
2555                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2556                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2557         }
2558
2559 out:
2560         return current_link_up;
2561 }
2562
2563 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2564 {
2565         int current_link_up = 0;
2566
2567         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2568                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2569                 goto out;
2570         }
2571
2572         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2573                 u32 flags;
2574                 int i;
2575
2576                 if (fiber_autoneg(tp, &flags)) {
2577                         u32 local_adv, remote_adv;
2578
2579                         local_adv = ADVERTISE_PAUSE_CAP;
2580                         remote_adv = 0;
2581                         if (flags & MR_LP_ADV_SYM_PAUSE)
2582                                 remote_adv |= LPA_PAUSE_CAP;
2583                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2584                                 remote_adv |= LPA_PAUSE_ASYM;
2585
2586                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2587
2588                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2589                         current_link_up = 1;
2590                 }
2591                 for (i = 0; i < 30; i++) {
2592                         udelay(20);
2593                         tw32_f(MAC_STATUS,
2594                                (MAC_STATUS_SYNC_CHANGED |
2595                                 MAC_STATUS_CFG_CHANGED));
2596                         udelay(40);
2597                         if ((tr32(MAC_STATUS) &
2598                              (MAC_STATUS_SYNC_CHANGED |
2599                               MAC_STATUS_CFG_CHANGED)) == 0)
2600                                 break;
2601                 }
2602
2603                 mac_status = tr32(MAC_STATUS);
2604                 if (current_link_up == 0 &&
2605                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2606                     !(mac_status & MAC_STATUS_RCVD_CFG))
2607                         current_link_up = 1;
2608         } else {
2609                 /* Forcing 1000FD link up. */
2610                 current_link_up = 1;
2611                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2612
2613                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2614                 udelay(40);
2615         }
2616
2617 out:
2618         return current_link_up;
2619 }
2620
2621 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2622 {
2623         u32 orig_pause_cfg;
2624         u16 orig_active_speed;
2625         u8 orig_active_duplex;
2626         u32 mac_status;
2627         int current_link_up;
2628         int i;
2629
2630         orig_pause_cfg =
2631                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2632                                   TG3_FLAG_TX_PAUSE));
2633         orig_active_speed = tp->link_config.active_speed;
2634         orig_active_duplex = tp->link_config.active_duplex;
2635
2636         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2637             netif_carrier_ok(tp->dev) &&
2638             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2639                 mac_status = tr32(MAC_STATUS);
2640                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2641                                MAC_STATUS_SIGNAL_DET |
2642                                MAC_STATUS_CFG_CHANGED |
2643                                MAC_STATUS_RCVD_CFG);
2644                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2645                                    MAC_STATUS_SIGNAL_DET)) {
2646                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2647                                             MAC_STATUS_CFG_CHANGED));
2648                         return 0;
2649                 }
2650         }
2651
2652         tw32_f(MAC_TX_AUTO_NEG, 0);
2653
2654         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2655         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2656         tw32_f(MAC_MODE, tp->mac_mode);
2657         udelay(40);
2658
2659         if (tp->phy_id == PHY_ID_BCM8002)
2660                 tg3_init_bcm8002(tp);
2661
2662         /* Enable link change event even when serdes polling.  */
2663         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2664         udelay(40);
2665
2666         current_link_up = 0;
2667         mac_status = tr32(MAC_STATUS);
2668
2669         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2670                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2671         else
2672                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2673
2674         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2675         tw32_f(MAC_MODE, tp->mac_mode);
2676         udelay(40);
2677
2678         tp->hw_status->status =
2679                 (SD_STATUS_UPDATED |
2680                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2681
2682         for (i = 0; i < 100; i++) {
2683                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2684                                     MAC_STATUS_CFG_CHANGED));
2685                 udelay(5);
2686                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2687                                          MAC_STATUS_CFG_CHANGED |
2688                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2689                         break;
2690         }
2691
2692         mac_status = tr32(MAC_STATUS);
2693         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2694                 current_link_up = 0;
2695                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2696                     tp->serdes_counter == 0) {
2697                         tw32_f(MAC_MODE, (tp->mac_mode |
2698                                           MAC_MODE_SEND_CONFIGS));
2699                         udelay(1);
2700                         tw32_f(MAC_MODE, tp->mac_mode);
2701                 }
2702         }
2703
2704         if (current_link_up == 1) {
2705                 tp->link_config.active_speed = SPEED_1000;
2706                 tp->link_config.active_duplex = DUPLEX_FULL;
2707                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2708                                     LED_CTRL_LNKLED_OVERRIDE |
2709                                     LED_CTRL_1000MBPS_ON));
2710         } else {
2711                 tp->link_config.active_speed = SPEED_INVALID;
2712                 tp->link_config.active_duplex = DUPLEX_INVALID;
2713                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2714                                     LED_CTRL_LNKLED_OVERRIDE |
2715                                     LED_CTRL_TRAFFIC_OVERRIDE));
2716         }
2717
2718         if (current_link_up != netif_carrier_ok(tp->dev)) {
2719                 if (current_link_up)
2720                         netif_carrier_on(tp->dev);
2721                 else
2722                         netif_carrier_off(tp->dev);
2723                 tg3_link_report(tp);
2724         } else {
2725                 u32 now_pause_cfg =
2726                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2727                                          TG3_FLAG_TX_PAUSE);
2728                 if (orig_pause_cfg != now_pause_cfg ||
2729                     orig_active_speed != tp->link_config.active_speed ||
2730                     orig_active_duplex != tp->link_config.active_duplex)
2731                         tg3_link_report(tp);
2732         }
2733
2734         return 0;
2735 }
2736
2737 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2738 {
2739         int current_link_up, err = 0;
2740         u32 bmsr, bmcr;
2741         u16 current_speed;
2742         u8 current_duplex;
2743
2744         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2745         tw32_f(MAC_MODE, tp->mac_mode);
2746         udelay(40);
2747
2748         tw32(MAC_EVENT, 0);
2749
2750         tw32_f(MAC_STATUS,
2751              (MAC_STATUS_SYNC_CHANGED |
2752               MAC_STATUS_CFG_CHANGED |
2753               MAC_STATUS_MI_COMPLETION |
2754               MAC_STATUS_LNKSTATE_CHANGED));
2755         udelay(40);
2756
2757         if (force_reset)
2758                 tg3_phy_reset(tp);
2759
2760         current_link_up = 0;
2761         current_speed = SPEED_INVALID;
2762         current_duplex = DUPLEX_INVALID;
2763
2764         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2765         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2766         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2767                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2768                         bmsr |= BMSR_LSTATUS;
2769                 else
2770                         bmsr &= ~BMSR_LSTATUS;
2771         }
2772
2773         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2774
2775         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2776             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2777                 /* do nothing, just check for link up at the end */
2778         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2779                 u32 adv, new_adv;
2780
2781                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2782                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2783                                   ADVERTISE_1000XPAUSE |
2784                                   ADVERTISE_1000XPSE_ASYM |
2785                                   ADVERTISE_SLCT);
2786
2787                 /* Always advertise symmetric PAUSE just like copper */
2788                 new_adv |= ADVERTISE_1000XPAUSE;
2789
2790                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2791                         new_adv |= ADVERTISE_1000XHALF;
2792                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2793                         new_adv |= ADVERTISE_1000XFULL;
2794
2795                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2796                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2797                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2798                         tg3_writephy(tp, MII_BMCR, bmcr);
2799
2800                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2801                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2802                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2803
2804                         return err;
2805                 }
2806         } else {
2807                 u32 new_bmcr;
2808
2809                 bmcr &= ~BMCR_SPEED1000;
2810                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2811
2812                 if (tp->link_config.duplex == DUPLEX_FULL)
2813                         new_bmcr |= BMCR_FULLDPLX;
2814
2815                 if (new_bmcr != bmcr) {
2816                         /* BMCR_SPEED1000 is a reserved bit that needs
2817                          * to be set on write.
2818                          */
2819                         new_bmcr |= BMCR_SPEED1000;
2820
2821                         /* Force a linkdown */
2822                         if (netif_carrier_ok(tp->dev)) {
2823                                 u32 adv;
2824
2825                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2826                                 adv &= ~(ADVERTISE_1000XFULL |
2827                                          ADVERTISE_1000XHALF |
2828                                          ADVERTISE_SLCT);
2829                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2830                                 tg3_writephy(tp, MII_BMCR, bmcr |
2831                                                            BMCR_ANRESTART |
2832                                                            BMCR_ANENABLE);
2833                                 udelay(10);
2834                                 netif_carrier_off(tp->dev);
2835                         }
2836                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2837                         bmcr = new_bmcr;
2838                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2839                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2840                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2841                             ASIC_REV_5714) {
2842                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2843                                         bmsr |= BMSR_LSTATUS;
2844                                 else
2845                                         bmsr &= ~BMSR_LSTATUS;
2846                         }
2847                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2848                 }
2849         }
2850
2851         if (bmsr & BMSR_LSTATUS) {
2852                 current_speed = SPEED_1000;
2853                 current_link_up = 1;
2854                 if (bmcr & BMCR_FULLDPLX)
2855                         current_duplex = DUPLEX_FULL;
2856                 else
2857                         current_duplex = DUPLEX_HALF;
2858
2859                 if (bmcr & BMCR_ANENABLE) {
2860                         u32 local_adv, remote_adv, common;
2861
2862                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2863                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2864                         common = local_adv & remote_adv;
2865                         if (common & (ADVERTISE_1000XHALF |
2866                                       ADVERTISE_1000XFULL)) {
2867                                 if (common & ADVERTISE_1000XFULL)
2868                                         current_duplex = DUPLEX_FULL;
2869                                 else
2870                                         current_duplex = DUPLEX_HALF;
2871
2872                                 tg3_setup_flow_control(tp, local_adv,
2873                                                        remote_adv);
2874                         }
2875                         else
2876                                 current_link_up = 0;
2877                 }
2878         }
2879
2880         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2881         if (tp->link_config.active_duplex == DUPLEX_HALF)
2882                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2883
2884         tw32_f(MAC_MODE, tp->mac_mode);
2885         udelay(40);
2886
2887         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2888
2889         tp->link_config.active_speed = current_speed;
2890         tp->link_config.active_duplex = current_duplex;
2891
2892         if (current_link_up != netif_carrier_ok(tp->dev)) {
2893                 if (current_link_up)
2894                         netif_carrier_on(tp->dev);
2895                 else {
2896                         netif_carrier_off(tp->dev);
2897                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2898                 }
2899                 tg3_link_report(tp);
2900         }
2901         return err;
2902 }
2903
2904 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2905 {
2906         if (tp->serdes_counter) {
2907                 /* Give autoneg time to complete. */
2908                 tp->serdes_counter--;
2909                 return;
2910         }
2911         if (!netif_carrier_ok(tp->dev) &&
2912             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2913                 u32 bmcr;
2914
2915                 tg3_readphy(tp, MII_BMCR, &bmcr);
2916                 if (bmcr & BMCR_ANENABLE) {
2917                         u32 phy1, phy2;
2918
2919                         /* Select shadow register 0x1f */
2920                         tg3_writephy(tp, 0x1c, 0x7c00);
2921                         tg3_readphy(tp, 0x1c, &phy1);
2922
2923                         /* Select expansion interrupt status register */
2924                         tg3_writephy(tp, 0x17, 0x0f01);
2925                         tg3_readphy(tp, 0x15, &phy2);
2926                         tg3_readphy(tp, 0x15, &phy2);
2927
2928                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2929                                 /* We have signal detect and not receiving
2930                                  * config code words, link is up by parallel
2931                                  * detection.
2932                                  */
2933
2934                                 bmcr &= ~BMCR_ANENABLE;
2935                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2936                                 tg3_writephy(tp, MII_BMCR, bmcr);
2937                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2938                         }
2939                 }
2940         }
2941         else if (netif_carrier_ok(tp->dev) &&
2942                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2943                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2944                 u32 phy2;
2945
2946                 /* Select expansion interrupt status register */
2947                 tg3_writephy(tp, 0x17, 0x0f01);
2948                 tg3_readphy(tp, 0x15, &phy2);
2949                 if (phy2 & 0x20) {
2950                         u32 bmcr;
2951
2952                         /* Config code words received, turn on autoneg. */
2953                         tg3_readphy(tp, MII_BMCR, &bmcr);
2954                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2955
2956                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2957
2958                 }
2959         }
2960 }
2961
2962 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2963 {
2964         int err;
2965
2966         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2967                 err = tg3_setup_fiber_phy(tp, force_reset);
2968         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2969                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2970         } else {
2971                 err = tg3_setup_copper_phy(tp, force_reset);
2972         }
2973
2974         if (tp->link_config.active_speed == SPEED_1000 &&
2975             tp->link_config.active_duplex == DUPLEX_HALF)
2976                 tw32(MAC_TX_LENGTHS,
2977                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2978                       (6 << TX_LENGTHS_IPG_SHIFT) |
2979                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
2980         else
2981                 tw32(MAC_TX_LENGTHS,
2982                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2983                       (6 << TX_LENGTHS_IPG_SHIFT) |
2984                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
2985
2986         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2987                 if (netif_carrier_ok(tp->dev)) {
2988                         tw32(HOSTCC_STAT_COAL_TICKS,
2989                              tp->coal.stats_block_coalesce_usecs);
2990                 } else {
2991                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
2992                 }
2993         }
2994
2995         return err;
2996 }
2997
2998 /* This is called whenever we suspect that the system chipset is re-
2999  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3000  * is bogus tx completions. We try to recover by setting the
3001  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3002  * in the workqueue.
3003  */
3004 static void tg3_tx_recover(struct tg3 *tp)
3005 {
3006         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3007                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3008
3009         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3010                "mapped I/O cycles to the network device, attempting to "
3011                "recover. Please report the problem to the driver maintainer "
3012                "and include system chipset information.\n", tp->dev->name);
3013
3014         spin_lock(&tp->lock);
3015         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3016         spin_unlock(&tp->lock);
3017 }
3018
3019 static inline u32 tg3_tx_avail(struct tg3 *tp)
3020 {
3021         smp_mb();
3022         return (tp->tx_pending -
3023                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3024 }
3025
3026 /* Tigon3 never reports partial packet sends.  So we do not
3027  * need special logic to handle SKBs that have not had all
3028  * of their frags sent yet, like SunGEM does.
3029  */
3030 static void tg3_tx(struct tg3 *tp)
3031 {
3032         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3033         u32 sw_idx = tp->tx_cons;
3034
3035         while (sw_idx != hw_idx) {
3036                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3037                 struct sk_buff *skb = ri->skb;
3038                 int i, tx_bug = 0;
3039
3040                 if (unlikely(skb == NULL)) {
3041                         tg3_tx_recover(tp);
3042                         return;
3043                 }
3044
3045                 pci_unmap_single(tp->pdev,
3046                                  pci_unmap_addr(ri, mapping),
3047                                  skb_headlen(skb),
3048                                  PCI_DMA_TODEVICE);
3049
3050                 ri->skb = NULL;
3051
3052                 sw_idx = NEXT_TX(sw_idx);
3053
3054                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3055                         ri = &tp->tx_buffers[sw_idx];
3056                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3057                                 tx_bug = 1;
3058
3059                         pci_unmap_page(tp->pdev,
3060                                        pci_unmap_addr(ri, mapping),
3061                                        skb_shinfo(skb)->frags[i].size,
3062                                        PCI_DMA_TODEVICE);
3063
3064                         sw_idx = NEXT_TX(sw_idx);
3065                 }
3066
3067                 dev_kfree_skb(skb);
3068
3069                 if (unlikely(tx_bug)) {
3070                         tg3_tx_recover(tp);
3071                         return;
3072                 }
3073         }
3074
3075         tp->tx_cons = sw_idx;
3076
3077         /* Need to make the tx_cons update visible to tg3_start_xmit()
3078          * before checking for netif_queue_stopped().  Without the
3079          * memory barrier, there is a small possibility that tg3_start_xmit()
3080          * will miss it and cause the queue to be stopped forever.
3081          */
3082         smp_mb();
3083
3084         if (unlikely(netif_queue_stopped(tp->dev) &&
3085                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3086                 netif_tx_lock(tp->dev);
3087                 if (netif_queue_stopped(tp->dev) &&
3088                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3089                         netif_wake_queue(tp->dev);
3090                 netif_tx_unlock(tp->dev);
3091         }
3092 }
3093
3094 /* Returns size of skb allocated or < 0 on error.
3095  *
3096  * We only need to fill in the address because the other members
3097  * of the RX descriptor are invariant, see tg3_init_rings.
3098  *
3099  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3100  * posting buffers we only dirty the first cache line of the RX
3101  * descriptor (containing the address).  Whereas for the RX status
3102  * buffers the cpu only reads the last cacheline of the RX descriptor
3103  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3104  */
3105 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3106                             int src_idx, u32 dest_idx_unmasked)
3107 {
3108         struct tg3_rx_buffer_desc *desc;
3109         struct ring_info *map, *src_map;
3110         struct sk_buff *skb;
3111         dma_addr_t mapping;
3112         int skb_size, dest_idx;
3113
3114         src_map = NULL;
3115         switch (opaque_key) {
3116         case RXD_OPAQUE_RING_STD:
3117                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3118                 desc = &tp->rx_std[dest_idx];
3119                 map = &tp->rx_std_buffers[dest_idx];
3120                 if (src_idx >= 0)
3121                         src_map = &tp->rx_std_buffers[src_idx];
3122                 skb_size = tp->rx_pkt_buf_sz;
3123                 break;
3124
3125         case RXD_OPAQUE_RING_JUMBO:
3126                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3127                 desc = &tp->rx_jumbo[dest_idx];
3128                 map = &tp->rx_jumbo_buffers[dest_idx];
3129                 if (src_idx >= 0)
3130                         src_map = &tp->rx_jumbo_buffers[src_idx];
3131                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3132                 break;
3133
3134         default:
3135                 return -EINVAL;
3136         };
3137
3138         /* Do not overwrite any of the map or rp information
3139          * until we are sure we can commit to a new buffer.
3140          *
3141          * Callers depend upon this behavior and assume that
3142          * we leave everything unchanged if we fail.
3143          */
3144         skb = netdev_alloc_skb(tp->dev, skb_size);
3145         if (skb == NULL)
3146                 return -ENOMEM;
3147
3148         skb_reserve(skb, tp->rx_offset);
3149
3150         mapping = pci_map_single(tp->pdev, skb->data,
3151                                  skb_size - tp->rx_offset,
3152                                  PCI_DMA_FROMDEVICE);
3153
3154         map->skb = skb;
3155         pci_unmap_addr_set(map, mapping, mapping);
3156
3157         if (src_map != NULL)
3158                 src_map->skb = NULL;
3159
3160         desc->addr_hi = ((u64)mapping >> 32);
3161         desc->addr_lo = ((u64)mapping & 0xffffffff);
3162
3163         return skb_size;
3164 }
3165
3166 /* We only need to move over in the address because the other
3167  * members of the RX descriptor are invariant.  See notes above
3168  * tg3_alloc_rx_skb for full details.
3169  */
3170 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3171                            int src_idx, u32 dest_idx_unmasked)
3172 {
3173         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3174         struct ring_info *src_map, *dest_map;
3175         int dest_idx;
3176
3177         switch (opaque_key) {
3178         case RXD_OPAQUE_RING_STD:
3179                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3180                 dest_desc = &tp->rx_std[dest_idx];
3181                 dest_map = &tp->rx_std_buffers[dest_idx];
3182                 src_desc = &tp->rx_std[src_idx];
3183                 src_map = &tp->rx_std_buffers[src_idx];
3184                 break;
3185
3186         case RXD_OPAQUE_RING_JUMBO:
3187                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3188                 dest_desc = &tp->rx_jumbo[dest_idx];
3189                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3190                 src_desc = &tp->rx_jumbo[src_idx];
3191                 src_map = &tp->rx_jumbo_buffers[src_idx];
3192                 break;
3193
3194         default:
3195                 return;
3196         };
3197
3198         dest_map->skb = src_map->skb;
3199         pci_unmap_addr_set(dest_map, mapping,
3200                            pci_unmap_addr(src_map, mapping));
3201         dest_desc->addr_hi = src_desc->addr_hi;
3202         dest_desc->addr_lo = src_desc->addr_lo;
3203
3204         src_map->skb = NULL;
3205 }
3206
3207 #if TG3_VLAN_TAG_USED
3208 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3209 {
3210         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3211 }
3212 #endif
3213
3214 /* The RX ring scheme is composed of multiple rings which post fresh
3215  * buffers to the chip, and one special ring the chip uses to report
3216  * status back to the host.
3217  *
3218  * The special ring reports the status of received packets to the
3219  * host.  The chip does not write into the original descriptor the
3220  * RX buffer was obtained from.  The chip simply takes the original
3221  * descriptor as provided by the host, updates the status and length
3222  * field, then writes this into the next status ring entry.
3223  *
3224  * Each ring the host uses to post buffers to the chip is described
3225  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3226  * it is first placed into the on-chip ram.  When the packet's length
3227  * is known, it walks down the TG3_BDINFO entries to select the ring.
3228  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3229  * which is within the range of the new packet's length is chosen.
3230  *
3231  * The "separate ring for rx status" scheme may sound queer, but it makes
3232  * sense from a cache coherency perspective.  If only the host writes
3233  * to the buffer post rings, and only the chip writes to the rx status
3234  * rings, then cache lines never move beyond shared-modified state.
3235  * If both the host and chip were to write into the same ring, cache line
3236  * eviction could occur since both entities want it in an exclusive state.
3237  */
3238 static int tg3_rx(struct tg3 *tp, int budget)
3239 {
3240         u32 work_mask, rx_std_posted = 0;
3241         u32 sw_idx = tp->rx_rcb_ptr;
3242         u16 hw_idx;
3243         int received;
3244
3245         hw_idx = tp->hw_status->idx[0].rx_producer;
3246         /*
3247          * We need to order the read of hw_idx and the read of
3248          * the opaque cookie.
3249          */
3250         rmb();
3251         work_mask = 0;
3252         received = 0;
3253         while (sw_idx != hw_idx && budget > 0) {
3254                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3255                 unsigned int len;
3256                 struct sk_buff *skb;
3257                 dma_addr_t dma_addr;
3258                 u32 opaque_key, desc_idx, *post_ptr;
3259
3260                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3261                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3262                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3263                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3264                                                   mapping);
3265                         skb = tp->rx_std_buffers[desc_idx].skb;
3266                         post_ptr = &tp->rx_std_ptr;
3267                         rx_std_posted++;
3268                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3269                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3270                                                   mapping);
3271                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3272                         post_ptr = &tp->rx_jumbo_ptr;
3273                 }
3274                 else {
3275                         goto next_pkt_nopost;
3276                 }
3277
3278                 work_mask |= opaque_key;
3279
3280                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3281                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3282                 drop_it:
3283                         tg3_recycle_rx(tp, opaque_key,
3284                                        desc_idx, *post_ptr);
3285                 drop_it_no_recycle:
3286                         /* Other statistics kept track of by card. */
3287                         tp->net_stats.rx_dropped++;
3288                         goto next_pkt;
3289                 }
3290
3291                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3292
3293                 if (len > RX_COPY_THRESHOLD
3294                         && tp->rx_offset == 2
3295                         /* rx_offset != 2 iff this is a 5701 card running
3296                          * in PCI-X mode [see tg3_get_invariants()] */
3297                 ) {
3298                         int skb_size;
3299
3300                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3301                                                     desc_idx, *post_ptr);
3302                         if (skb_size < 0)
3303                                 goto drop_it;
3304
3305                         pci_unmap_single(tp->pdev, dma_addr,
3306                                          skb_size - tp->rx_offset,
3307                                          PCI_DMA_FROMDEVICE);
3308
3309                         skb_put(skb, len);
3310                 } else {
3311                         struct sk_buff *copy_skb;
3312
3313                         tg3_recycle_rx(tp, opaque_key,
3314                                        desc_idx, *post_ptr);
3315
3316                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3317                         if (copy_skb == NULL)
3318                                 goto drop_it_no_recycle;
3319
3320                         skb_reserve(copy_skb, 2);
3321                         skb_put(copy_skb, len);
3322                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3323                         memcpy(copy_skb->data, skb->data, len);
3324                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3325
3326                         /* We'll reuse the original ring buffer. */
3327                         skb = copy_skb;
3328                 }
3329
3330                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3331                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3332                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3333                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3334                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3335                 else
3336                         skb->ip_summed = CHECKSUM_NONE;
3337
3338                 skb->protocol = eth_type_trans(skb, tp->dev);
3339 #if TG3_VLAN_TAG_USED
3340                 if (tp->vlgrp != NULL &&
3341                     desc->type_flags & RXD_FLAG_VLAN) {
3342                         tg3_vlan_rx(tp, skb,
3343                                     desc->err_vlan & RXD_VLAN_MASK);
3344                 } else
3345 #endif
3346                         netif_receive_skb(skb);
3347
3348                 tp->dev->last_rx = jiffies;
3349                 received++;
3350                 budget--;
3351
3352 next_pkt:
3353                 (*post_ptr)++;
3354
3355                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3356                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3357
3358                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3359                                      TG3_64BIT_REG_LOW, idx);
3360                         work_mask &= ~RXD_OPAQUE_RING_STD;
3361                         rx_std_posted = 0;
3362                 }
3363 next_pkt_nopost:
3364                 sw_idx++;
3365                 sw_idx %= TG3_RX_RCB_RING_SIZE(tp);
3366
3367                 /* Refresh hw_idx to see if there is new work */
3368                 if (sw_idx == hw_idx) {
3369                         hw_idx = tp->hw_status->idx[0].rx_producer;
3370                         rmb();
3371                 }
3372         }
3373
3374         /* ACK the status ring. */
3375         tp->rx_rcb_ptr = sw_idx;
3376         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3377
3378         /* Refill RX ring(s). */
3379         if (work_mask & RXD_OPAQUE_RING_STD) {
3380                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3381                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3382                              sw_idx);
3383         }
3384         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3385                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3386                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3387                              sw_idx);
3388         }
3389         mmiowb();
3390
3391         return received;
3392 }
3393
3394 static int tg3_poll(struct net_device *netdev, int *budget)
3395 {
3396         struct tg3 *tp = netdev_priv(netdev);
3397         struct tg3_hw_status *sblk = tp->hw_status;
3398         int done;
3399
3400         /* handle link change and other phy events */
3401         if (!(tp->tg3_flags &
3402               (TG3_FLAG_USE_LINKCHG_REG |
3403                TG3_FLAG_POLL_SERDES))) {
3404                 if (sblk->status & SD_STATUS_LINK_CHG) {
3405                         sblk->status = SD_STATUS_UPDATED |
3406                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3407                         spin_lock(&tp->lock);
3408                         tg3_setup_phy(tp, 0);
3409                         spin_unlock(&tp->lock);
3410                 }
3411         }
3412
3413         /* run TX completion thread */
3414         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3415                 tg3_tx(tp);
3416                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3417                         netif_rx_complete(netdev);
3418                         schedule_work(&tp->reset_task);
3419                         return 0;
3420                 }
3421         }
3422
3423         /* run RX thread, within the bounds set by NAPI.
3424          * All RX "locking" is done by ensuring outside
3425          * code synchronizes with dev->poll()
3426          */
3427         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3428                 int orig_budget = *budget;
3429                 int work_done;
3430
3431                 if (orig_budget > netdev->quota)
3432                         orig_budget = netdev->quota;
3433
3434                 work_done = tg3_rx(tp, orig_budget);
3435
3436                 *budget -= work_done;
3437                 netdev->quota -= work_done;
3438         }
3439
3440         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3441                 tp->last_tag = sblk->status_tag;
3442                 rmb();
3443         } else
3444                 sblk->status &= ~SD_STATUS_UPDATED;
3445
3446         /* if no more work, tell net stack and NIC we're done */
3447         done = !tg3_has_work(tp);
3448         if (done) {
3449                 netif_rx_complete(netdev);
3450                 tg3_restart_ints(tp);
3451         }
3452
3453         return (done ? 0 : 1);
3454 }
3455
3456 static void tg3_irq_quiesce(struct tg3 *tp)
3457 {
3458         BUG_ON(tp->irq_sync);
3459
3460         tp->irq_sync = 1;
3461         smp_mb();
3462
3463         synchronize_irq(tp->pdev->irq);
3464 }
3465
3466 static inline int tg3_irq_sync(struct tg3 *tp)
3467 {
3468         return tp->irq_sync;
3469 }
3470
3471 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3472  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3473  * with as well.  Most of the time, this is not necessary except when
3474  * shutting down the device.
3475  */
3476 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3477 {
3478         if (irq_sync)
3479                 tg3_irq_quiesce(tp);
3480         spin_lock_bh(&tp->lock);
3481 }
3482
3483 static inline void tg3_full_unlock(struct tg3 *tp)
3484 {
3485         spin_unlock_bh(&tp->lock);
3486 }
3487
3488 /* One-shot MSI handler - Chip automatically disables interrupt
3489  * after sending MSI so driver doesn't have to do it.
3490  */
3491 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3492 {
3493         struct net_device *dev = dev_id;
3494         struct tg3 *tp = netdev_priv(dev);
3495
3496         prefetch(tp->hw_status);
3497         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3498
3499         if (likely(!tg3_irq_sync(tp)))
3500                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3501
3502         return IRQ_HANDLED;
3503 }
3504
3505 /* MSI ISR - No need to check for interrupt sharing and no need to
3506  * flush status block and interrupt mailbox. PCI ordering rules
3507  * guarantee that MSI will arrive after the status block.
3508  */
3509 static irqreturn_t tg3_msi(int irq, void *dev_id)
3510 {
3511         struct net_device *dev = dev_id;
3512         struct tg3 *tp = netdev_priv(dev);
3513
3514         prefetch(tp->hw_status);
3515         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3516         /*
3517          * Writing any value to intr-mbox-0 clears PCI INTA# and
3518          * chip-internal interrupt pending events.
3519          * Writing non-zero to intr-mbox-0 additional tells the
3520          * NIC to stop sending us irqs, engaging "in-intr-handler"
3521          * event coalescing.
3522          */
3523         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3524         if (likely(!tg3_irq_sync(tp)))
3525                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3526
3527         return IRQ_RETVAL(1);
3528 }
3529
3530 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3531 {
3532         struct net_device *dev = dev_id;
3533         struct tg3 *tp = netdev_priv(dev);
3534         struct tg3_hw_status *sblk = tp->hw_status;
3535         unsigned int handled = 1;
3536
3537         /* In INTx mode, it is possible for the interrupt to arrive at
3538          * the CPU before the status block posted prior to the interrupt.
3539          * Reading the PCI State register will confirm whether the
3540          * interrupt is ours and will flush the status block.
3541          */
3542         if ((sblk->status & SD_STATUS_UPDATED) ||
3543             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3544                 /*
3545                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3546                  * chip-internal interrupt pending events.
3547                  * Writing non-zero to intr-mbox-0 additional tells the
3548                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3549                  * event coalescing.
3550                  */
3551                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3552                              0x00000001);
3553                 if (tg3_irq_sync(tp))
3554                         goto out;
3555                 sblk->status &= ~SD_STATUS_UPDATED;
3556                 if (likely(tg3_has_work(tp))) {
3557                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3558                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3559                 } else {
3560                         /* No work, shared interrupt perhaps?  re-enable
3561                          * interrupts, and flush that PCI write
3562                          */
3563                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3564                                 0x00000000);
3565                 }
3566         } else {        /* shared interrupt */
3567                 handled = 0;
3568         }
3569 out:
3570         return IRQ_RETVAL(handled);
3571 }
3572
3573 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3574 {
3575         struct net_device *dev = dev_id;
3576         struct tg3 *tp = netdev_priv(dev);
3577         struct tg3_hw_status *sblk = tp->hw_status;
3578         unsigned int handled = 1;
3579
3580         /* In INTx mode, it is possible for the interrupt to arrive at
3581          * the CPU before the status block posted prior to the interrupt.
3582          * Reading the PCI State register will confirm whether the
3583          * interrupt is ours and will flush the status block.
3584          */
3585         if ((sblk->status_tag != tp->last_tag) ||
3586             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3587                 /*
3588                  * writing any value to intr-mbox-0 clears PCI INTA# and
3589                  * chip-internal interrupt pending events.
3590                  * writing non-zero to intr-mbox-0 additional tells the
3591                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3592                  * event coalescing.
3593                  */
3594                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3595                              0x00000001);
3596                 if (tg3_irq_sync(tp))
3597                         goto out;
3598                 if (netif_rx_schedule_prep(dev)) {
3599                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3600                         /* Update last_tag to mark that this status has been
3601                          * seen. Because interrupt may be shared, we may be
3602                          * racing with tg3_poll(), so only update last_tag
3603                          * if tg3_poll() is not scheduled.
3604                          */
3605                         tp->last_tag = sblk->status_tag;
3606                         __netif_rx_schedule(dev);
3607                 }
3608         } else {        /* shared interrupt */
3609                 handled = 0;
3610         }
3611 out:
3612         return IRQ_RETVAL(handled);
3613 }
3614
3615 /* ISR for interrupt test */
3616 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3617 {
3618         struct net_device *dev = dev_id;
3619         struct tg3 *tp = netdev_priv(dev);
3620         struct tg3_hw_status *sblk = tp->hw_status;
3621
3622         if ((sblk->status & SD_STATUS_UPDATED) ||
3623             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3624                 tg3_disable_ints(tp);
3625                 return IRQ_RETVAL(1);
3626         }
3627         return IRQ_RETVAL(0);
3628 }
3629
3630 static int tg3_init_hw(struct tg3 *, int);
3631 static int tg3_halt(struct tg3 *, int, int);
3632
3633 /* Restart hardware after configuration changes, self-test, etc.
3634  * Invoked with tp->lock held.
3635  */
3636 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3637 {
3638         int err;
3639
3640         err = tg3_init_hw(tp, reset_phy);
3641         if (err) {
3642                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3643                        "aborting.\n", tp->dev->name);
3644                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3645                 tg3_full_unlock(tp);
3646                 del_timer_sync(&tp->timer);
3647                 tp->irq_sync = 0;
3648                 netif_poll_enable(tp->dev);
3649                 dev_close(tp->dev);
3650                 tg3_full_lock(tp, 0);
3651         }
3652         return err;
3653 }
3654
3655 #ifdef CONFIG_NET_POLL_CONTROLLER
3656 static void tg3_poll_controller(struct net_device *dev)
3657 {
3658         struct tg3 *tp = netdev_priv(dev);
3659
3660         tg3_interrupt(tp->pdev->irq, dev);
3661 }
3662 #endif
3663
3664 static void tg3_reset_task(struct work_struct *work)
3665 {
3666         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3667         unsigned int restart_timer;
3668
3669         tg3_full_lock(tp, 0);
3670         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3671
3672         if (!netif_running(tp->dev)) {
3673                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3674                 tg3_full_unlock(tp);
3675                 return;
3676         }
3677
3678         tg3_full_unlock(tp);
3679
3680         tg3_netif_stop(tp);
3681
3682         tg3_full_lock(tp, 1);
3683
3684         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3685         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3686
3687         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3688                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3689                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3690                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3691                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3692         }
3693
3694         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3695         if (tg3_init_hw(tp, 1))
3696                 goto out;
3697
3698         tg3_netif_start(tp);
3699
3700         if (restart_timer)
3701                 mod_timer(&tp->timer, jiffies + 1);
3702
3703 out:
3704         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3705
3706         tg3_full_unlock(tp);
3707 }
3708
3709 static void tg3_tx_timeout(struct net_device *dev)
3710 {
3711         struct tg3 *tp = netdev_priv(dev);
3712
3713         printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3714                dev->name);
3715
3716         schedule_work(&tp->reset_task);
3717 }
3718
3719 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3720 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3721 {
3722         u32 base = (u32) mapping & 0xffffffff;
3723
3724         return ((base > 0xffffdcc0) &&
3725                 (base + len + 8 < base));
3726 }
3727
3728 /* Test for DMA addresses > 40-bit */
3729 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3730                                           int len)
3731 {
3732 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3733         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3734                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3735         return 0;
3736 #else
3737         return 0;
3738 #endif
3739 }
3740
3741 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3742
3743 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3744 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3745                                        u32 last_plus_one, u32 *start,
3746                                        u32 base_flags, u32 mss)
3747 {
3748         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3749         dma_addr_t new_addr = 0;
3750         u32 entry = *start;
3751         int i, ret = 0;
3752
3753         if (!new_skb) {
3754                 ret = -1;
3755         } else {
3756                 /* New SKB is guaranteed to be linear. */
3757                 entry = *start;
3758                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3759                                           PCI_DMA_TODEVICE);
3760                 /* Make sure new skb does not cross any 4G boundaries.
3761                  * Drop the packet if it does.
3762                  */
3763                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3764                         ret = -1;
3765                         dev_kfree_skb(new_skb);
3766                         new_skb = NULL;
3767                 } else {
3768                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3769                                     base_flags, 1 | (mss << 1));
3770                         *start = NEXT_TX(entry);
3771                 }
3772         }
3773
3774         /* Now clean up the sw ring entries. */
3775         i = 0;
3776         while (entry != last_plus_one) {
3777                 int len;
3778
3779                 if (i == 0)
3780                         len = skb_headlen(skb);
3781                 else
3782                         len = skb_shinfo(skb)->frags[i-1].size;
3783                 pci_unmap_single(tp->pdev,
3784                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3785                                  len, PCI_DMA_TODEVICE);
3786                 if (i == 0) {
3787                         tp->tx_buffers[entry].skb = new_skb;
3788                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3789                 } else {
3790                         tp->tx_buffers[entry].skb = NULL;
3791                 }
3792                 entry = NEXT_TX(entry);
3793                 i++;
3794         }
3795
3796         dev_kfree_skb(skb);
3797
3798         return ret;
3799 }
3800
3801 static void tg3_set_txd(struct tg3 *tp, int entry,
3802                         dma_addr_t mapping, int len, u32 flags,
3803                         u32 mss_and_is_end)
3804 {
3805         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3806         int is_end = (mss_and_is_end & 0x1);
3807         u32 mss = (mss_and_is_end >> 1);
3808         u32 vlan_tag = 0;
3809
3810         if (is_end)
3811                 flags |= TXD_FLAG_END;
3812         if (flags & TXD_FLAG_VLAN) {
3813                 vlan_tag = flags >> 16;
3814                 flags &= 0xffff;
3815         }
3816         vlan_tag |= (mss << TXD_MSS_SHIFT);
3817
3818         txd->addr_hi = ((u64) mapping >> 32);
3819         txd->addr_lo = ((u64) mapping & 0xffffffff);
3820         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3821         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3822 }
3823
3824 /* hard_start_xmit for devices that don't have any bugs and
3825  * support TG3_FLG2_HW_TSO_2 only.
3826  */
3827 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3828 {
3829         struct tg3 *tp = netdev_priv(dev);
3830         dma_addr_t mapping;
3831         u32 len, entry, base_flags, mss;
3832
3833         len = skb_headlen(skb);
3834
3835         /* We are running in BH disabled context with netif_tx_lock
3836          * and TX reclaim runs via tp->poll inside of a software
3837          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3838          * no IRQ context deadlocks to worry about either.  Rejoice!
3839          */
3840         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3841                 if (!netif_queue_stopped(dev)) {
3842                         netif_stop_queue(dev);
3843
3844                         /* This is a hard error, log it. */
3845                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3846                                "queue awake!\n", dev->name);
3847                 }
3848                 return NETDEV_TX_BUSY;
3849         }
3850
3851         entry = tp->tx_prod;
3852         base_flags = 0;
3853 #if TG3_TSO_SUPPORT != 0
3854         mss = 0;
3855         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3856             (mss = skb_shinfo(skb)->gso_size) != 0) {
3857                 int tcp_opt_len, ip_tcp_len;
3858
3859                 if (skb_header_cloned(skb) &&
3860                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3861                         dev_kfree_skb(skb);
3862                         goto out_unlock;
3863                 }
3864
3865                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3866                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3867                 else {
3868                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3869                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3870                                      sizeof(struct tcphdr);
3871
3872                         skb->nh.iph->check = 0;
3873                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3874                                                      tcp_opt_len);
3875                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3876                 }
3877
3878                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3879                                TXD_FLAG_CPU_POST_DMA);
3880
3881                 skb->h.th->check = 0;
3882
3883         }
3884         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3885                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3886 #else
3887         mss = 0;
3888         if (skb->ip_summed == CHECKSUM_PARTIAL)
3889                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3890 #endif
3891 #if TG3_VLAN_TAG_USED
3892         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3893                 base_flags |= (TXD_FLAG_VLAN |
3894                                (vlan_tx_tag_get(skb) << 16));
3895 #endif
3896
3897         /* Queue skb data, a.k.a. the main skb fragment. */
3898         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3899
3900         tp->tx_buffers[entry].skb = skb;
3901         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3902
3903         tg3_set_txd(tp, entry, mapping, len, base_flags,
3904                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3905
3906         entry = NEXT_TX(entry);
3907
3908         /* Now loop through additional data fragments, and queue them. */
3909         if (skb_shinfo(skb)->nr_frags > 0) {
3910                 unsigned int i, last;
3911
3912                 last = skb_shinfo(skb)->nr_frags - 1;
3913                 for (i = 0; i <= last; i++) {
3914                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3915
3916                         len = frag->size;
3917                         mapping = pci_map_page(tp->pdev,
3918                                                frag->page,
3919                                                frag->page_offset,
3920                                                len, PCI_DMA_TODEVICE);
3921
3922                         tp->tx_buffers[entry].skb = NULL;
3923                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3924
3925                         tg3_set_txd(tp, entry, mapping, len,
3926                                     base_flags, (i == last) | (mss << 1));
3927
3928                         entry = NEXT_TX(entry);
3929                 }
3930         }
3931
3932         /* Packets are ready, update Tx producer idx local and on card. */
3933         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3934
3935         tp->tx_prod = entry;
3936         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3937                 netif_stop_queue(dev);
3938                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3939                         netif_wake_queue(tp->dev);
3940         }
3941
3942 out_unlock:
3943         mmiowb();
3944
3945         dev->trans_start = jiffies;
3946
3947         return NETDEV_TX_OK;
3948 }
3949
3950 #if TG3_TSO_SUPPORT != 0
3951 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3952
3953 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3954  * TSO header is greater than 80 bytes.
3955  */
3956 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3957 {
3958         struct sk_buff *segs, *nskb;
3959
3960         /* Estimate the number of fragments in the worst case */
3961         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3962                 netif_stop_queue(tp->dev);
3963                 return NETDEV_TX_BUSY;
3964         }
3965
3966         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
3967         if (unlikely(IS_ERR(segs)))
3968                 goto tg3_tso_bug_end;
3969
3970         do {
3971                 nskb = segs;
3972                 segs = segs->next;
3973                 nskb->next = NULL;
3974                 tg3_start_xmit_dma_bug(nskb, tp->dev);
3975         } while (segs);
3976
3977 tg3_tso_bug_end:
3978         dev_kfree_skb(skb);
3979
3980         return NETDEV_TX_OK;
3981 }
3982 #endif
3983
3984 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
3985  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
3986  */
3987 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
3988 {
3989         struct tg3 *tp = netdev_priv(dev);
3990         dma_addr_t mapping;
3991         u32 len, entry, base_flags, mss;
3992         int would_hit_hwbug;
3993
3994         len = skb_headlen(skb);
3995
3996         /* We are running in BH disabled context with netif_tx_lock
3997          * and TX reclaim runs via tp->poll inside of a software
3998          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3999          * no IRQ context deadlocks to worry about either.  Rejoice!
4000          */
4001         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4002                 if (!netif_queue_stopped(dev)) {
4003                         netif_stop_queue(dev);
4004
4005                         /* This is a hard error, log it. */
4006                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4007                                "queue awake!\n", dev->name);
4008                 }
4009                 return NETDEV_TX_BUSY;
4010         }
4011
4012         entry = tp->tx_prod;
4013         base_flags = 0;
4014         if (skb->ip_summed == CHECKSUM_PARTIAL)
4015                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4016 #if TG3_TSO_SUPPORT != 0
4017         mss = 0;
4018         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4019             (mss = skb_shinfo(skb)->gso_size) != 0) {
4020                 int tcp_opt_len, ip_tcp_len, hdr_len;
4021
4022                 if (skb_header_cloned(skb) &&
4023                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4024                         dev_kfree_skb(skb);
4025                         goto out_unlock;
4026                 }
4027
4028                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4029                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4030
4031                 hdr_len = ip_tcp_len + tcp_opt_len;
4032                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4033                              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4034                         return (tg3_tso_bug(tp, skb));
4035
4036                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4037                                TXD_FLAG_CPU_POST_DMA);
4038
4039                 skb->nh.iph->check = 0;
4040                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4041                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4042                         skb->h.th->check = 0;
4043                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4044                 }
4045                 else {
4046                         skb->h.th->check =
4047                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4048                                                    skb->nh.iph->daddr,
4049                                                    0, IPPROTO_TCP, 0);
4050                 }
4051
4052                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4053                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4054                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4055                                 int tsflags;
4056
4057                                 tsflags = ((skb->nh.iph->ihl - 5) +
4058                                            (tcp_opt_len >> 2));
4059                                 mss |= (tsflags << 11);
4060                         }
4061                 } else {
4062                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4063                                 int tsflags;
4064
4065                                 tsflags = ((skb->nh.iph->ihl - 5) +
4066                                            (tcp_opt_len >> 2));
4067                                 base_flags |= tsflags << 12;
4068                         }
4069                 }
4070         }
4071 #else
4072         mss = 0;
4073 #endif
4074 #if TG3_VLAN_TAG_USED
4075         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4076                 base_flags |= (TXD_FLAG_VLAN |
4077                                (vlan_tx_tag_get(skb) << 16));
4078 #endif
4079
4080         /* Queue skb data, a.k.a. the main skb fragment. */
4081         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4082
4083         tp->tx_buffers[entry].skb = skb;
4084         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4085
4086         would_hit_hwbug = 0;
4087
4088         if (tg3_4g_overflow_test(mapping, len))
4089                 would_hit_hwbug = 1;
4090
4091         tg3_set_txd(tp, entry, mapping, len, base_flags,
4092                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4093
4094         entry = NEXT_TX(entry);
4095
4096         /* Now loop through additional data fragments, and queue them. */
4097         if (skb_shinfo(skb)->nr_frags > 0) {
4098                 unsigned int i, last;
4099
4100                 last = skb_shinfo(skb)->nr_frags - 1;
4101                 for (i = 0; i <= last; i++) {
4102                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4103
4104                         len = frag->size;
4105                         mapping = pci_map_page(tp->pdev,
4106                                                frag->page,
4107                                                frag->page_offset,
4108                                                len, PCI_DMA_TODEVICE);
4109
4110                         tp->tx_buffers[entry].skb = NULL;
4111                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4112
4113                         if (tg3_4g_overflow_test(mapping, len))
4114                                 would_hit_hwbug = 1;
4115
4116                         if (tg3_40bit_overflow_test(tp, mapping, len))
4117                                 would_hit_hwbug = 1;
4118
4119                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4120                                 tg3_set_txd(tp, entry, mapping, len,
4121                                             base_flags, (i == last)|(mss << 1));
4122                         else
4123                                 tg3_set_txd(tp, entry, mapping, len,
4124                                             base_flags, (i == last));
4125
4126                         entry = NEXT_TX(entry);
4127                 }
4128         }
4129
4130         if (would_hit_hwbug) {
4131                 u32 last_plus_one = entry;
4132                 u32 start;
4133
4134                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4135                 start &= (TG3_TX_RING_SIZE - 1);
4136
4137                 /* If the workaround fails due to memory/mapping
4138                  * failure, silently drop this packet.
4139                  */
4140                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4141                                                 &start, base_flags, mss))
4142                         goto out_unlock;
4143
4144                 entry = start;
4145         }
4146
4147         /* Packets are ready, update Tx producer idx local and on card. */
4148         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4149
4150         tp->tx_prod = entry;
4151         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4152                 netif_stop_queue(dev);
4153                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4154                         netif_wake_queue(tp->dev);
4155         }
4156
4157 out_unlock:
4158         mmiowb();
4159
4160         dev->trans_start = jiffies;
4161
4162         return NETDEV_TX_OK;
4163 }
4164
4165 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4166                                int new_mtu)
4167 {
4168         dev->mtu = new_mtu;
4169
4170         if (new_mtu > ETH_DATA_LEN) {
4171                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4172                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4173                         ethtool_op_set_tso(dev, 0);
4174                 }
4175                 else
4176                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4177         } else {
4178                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4179                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4180                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4181         }
4182 }
4183
4184 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4185 {
4186         struct tg3 *tp = netdev_priv(dev);
4187         int err;
4188
4189         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4190                 return -EINVAL;
4191
4192         if (!netif_running(dev)) {
4193                 /* We'll just catch it later when the
4194                  * device is up'd.
4195                  */
4196                 tg3_set_mtu(dev, tp, new_mtu);
4197                 return 0;
4198         }
4199
4200         tg3_netif_stop(tp);
4201
4202         tg3_full_lock(tp, 1);
4203
4204         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4205
4206         tg3_set_mtu(dev, tp, new_mtu);
4207
4208         err = tg3_restart_hw(tp, 0);
4209
4210         if (!err)
4211                 tg3_netif_start(tp);
4212
4213         tg3_full_unlock(tp);
4214
4215         return err;
4216 }
4217
4218 /* Free up pending packets in all rx/tx rings.
4219  *
4220  * The chip has been shut down and the driver detached from
4221  * the networking, so no interrupts or new tx packets will
4222  * end up in the driver.  tp->{tx,}lock is not held and we are not
4223  * in an interrupt context and thus may sleep.
4224  */
4225 static void tg3_free_rings(struct tg3 *tp)
4226 {
4227         struct ring_info *rxp;
4228         int i;
4229
4230         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4231                 rxp = &tp->rx_std_buffers[i];
4232
4233                 if (rxp->skb == NULL)
4234                         continue;
4235                 pci_unmap_single(tp->pdev,
4236                                  pci_unmap_addr(rxp, mapping),
4237                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4238                                  PCI_DMA_FROMDEVICE);
4239                 dev_kfree_skb_any(rxp->skb);
4240                 rxp->skb = NULL;
4241         }
4242
4243         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4244                 rxp = &tp->rx_jumbo_buffers[i];
4245
4246                 if (rxp->skb == NULL)
4247                         continue;
4248                 pci_unmap_single(tp->pdev,
4249                                  pci_unmap_addr(rxp, mapping),
4250                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4251                                  PCI_DMA_FROMDEVICE);
4252                 dev_kfree_skb_any(rxp->skb);
4253                 rxp->skb = NULL;
4254         }
4255
4256         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4257                 struct tx_ring_info *txp;
4258                 struct sk_buff *skb;
4259                 int j;
4260
4261                 txp = &tp->tx_buffers[i];
4262                 skb = txp->skb;
4263
4264                 if (skb == NULL) {
4265                         i++;
4266                         continue;
4267                 }
4268
4269                 pci_unmap_single(tp->pdev,
4270                                  pci_unmap_addr(txp, mapping),
4271                                  skb_headlen(skb),
4272                                  PCI_DMA_TODEVICE);
4273                 txp->skb = NULL;
4274
4275                 i++;
4276
4277                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4278                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4279                         pci_unmap_page(tp->pdev,
4280                                        pci_unmap_addr(txp, mapping),
4281                                        skb_shinfo(skb)->frags[j].size,
4282                                        PCI_DMA_TODEVICE);
4283                         i++;
4284                 }
4285
4286                 dev_kfree_skb_any(skb);
4287         }
4288 }
4289
4290 /* Initialize tx/rx rings for packet processing.
4291  *
4292  * The chip has been shut down and the driver detached from
4293  * the networking, so no interrupts or new tx packets will
4294  * end up in the driver.  tp->{tx,}lock are held and thus
4295  * we may not sleep.
4296  */
4297 static int tg3_init_rings(struct tg3 *tp)
4298 {
4299         u32 i;
4300
4301         /* Free up all the SKBs. */
4302         tg3_free_rings(tp);
4303
4304         /* Zero out all descriptors. */
4305         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4306         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4307         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4308         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4309
4310         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4311         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4312             (tp->dev->mtu > ETH_DATA_LEN))
4313                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4314
4315         /* Initialize invariants of the rings, we only set this
4316          * stuff once.  This works because the card does not
4317          * write into the rx buffer posting rings.
4318          */
4319         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4320                 struct tg3_rx_buffer_desc *rxd;
4321
4322                 rxd = &tp->rx_std[i];
4323                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4324                         << RXD_LEN_SHIFT;
4325                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4326                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4327                                (i << RXD_OPAQUE_INDEX_SHIFT));
4328         }
4329
4330         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4331                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4332                         struct tg3_rx_buffer_desc *rxd;
4333
4334                         rxd = &tp->rx_jumbo[i];
4335                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4336                                 << RXD_LEN_SHIFT;
4337                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4338                                 RXD_FLAG_JUMBO;
4339                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4340                                (i << RXD_OPAQUE_INDEX_SHIFT));
4341                 }
4342         }
4343
4344         /* Now allocate fresh SKBs for each rx ring. */
4345         for (i = 0; i < tp->rx_pending; i++) {
4346                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4347                         printk(KERN_WARNING PFX
4348                                "%s: Using a smaller RX standard ring, "
4349                                "only %d out of %d buffers were allocated "
4350                                "successfully.\n",
4351                                tp->dev->name, i, tp->rx_pending);
4352                         if (i == 0)
4353                                 return -ENOMEM;
4354                         tp->rx_pending = i;
4355                         break;
4356                 }
4357         }
4358
4359         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4360                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4361                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4362                                              -1, i) < 0) {
4363                                 printk(KERN_WARNING PFX
4364                                        "%s: Using a smaller RX jumbo ring, "
4365                                        "only %d out of %d buffers were "
4366                                        "allocated successfully.\n",
4367                                        tp->dev->name, i, tp->rx_jumbo_pending);
4368                                 if (i == 0) {
4369                                         tg3_free_rings(tp);
4370                                         return -ENOMEM;
4371                                 }
4372                                 tp->rx_jumbo_pending = i;
4373                                 break;
4374                         }
4375                 }
4376         }
4377         return 0;
4378 }
4379
4380 /*
4381  * Must not be invoked with interrupt sources disabled and
4382  * the hardware shutdown down.
4383  */
4384 static void tg3_free_consistent(struct tg3 *tp)
4385 {
4386         kfree(tp->rx_std_buffers);
4387         tp->rx_std_buffers = NULL;
4388         if (tp->rx_std) {
4389                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4390                                     tp->rx_std, tp->rx_std_mapping);
4391                 tp->rx_std = NULL;
4392         }
4393         if (tp->rx_jumbo) {
4394                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4395                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4396                 tp->rx_jumbo = NULL;
4397         }
4398         if (tp->rx_rcb) {
4399                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4400                                     tp->rx_rcb, tp->rx_rcb_mapping);
4401                 tp->rx_rcb = NULL;
4402         }
4403         if (tp->tx_ring) {
4404                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4405                         tp->tx_ring, tp->tx_desc_mapping);
4406                 tp->tx_ring = NULL;
4407         }
4408         if (tp->hw_status) {
4409                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4410                                     tp->hw_status, tp->status_mapping);
4411                 tp->hw_status = NULL;
4412         }
4413         if (tp->hw_stats) {
4414                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4415                                     tp->hw_stats, tp->stats_mapping);
4416                 tp->hw_stats = NULL;
4417         }
4418 }
4419
4420 /*
4421  * Must not be invoked with interrupt sources disabled and
4422  * the hardware shutdown down.  Can sleep.
4423  */
4424 static int tg3_alloc_consistent(struct tg3 *tp)
4425 {
4426         tp->rx_std_buffers = kmalloc((sizeof(struct ring_info) *
4427                                       (TG3_RX_RING_SIZE +
4428                                        TG3_RX_JUMBO_RING_SIZE)) +
4429                                      (sizeof(struct tx_ring_info) *
4430                                       TG3_TX_RING_SIZE),
4431                                      GFP_KERNEL);
4432         if (!tp->rx_std_buffers)
4433                 return -ENOMEM;
4434
4435         memset(tp->rx_std_buffers, 0,
4436                (sizeof(struct ring_info) *
4437                 (TG3_RX_RING_SIZE +
4438                  TG3_RX_JUMBO_RING_SIZE)) +
4439                (sizeof(struct tx_ring_info) *
4440                 TG3_TX_RING_SIZE));
4441
4442         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4443         tp->tx_buffers = (struct tx_ring_info *)
4444                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4445
4446         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4447                                           &tp->rx_std_mapping);
4448         if (!tp->rx_std)
4449                 goto err_out;
4450
4451         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4452                                             &tp->rx_jumbo_mapping);
4453
4454         if (!tp->rx_jumbo)
4455                 goto err_out;
4456
4457         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4458                                           &tp->rx_rcb_mapping);
4459         if (!tp->rx_rcb)
4460                 goto err_out;
4461
4462         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4463                                            &tp->tx_desc_mapping);
4464         if (!tp->tx_ring)
4465                 goto err_out;
4466
4467         tp->hw_status = pci_alloc_consistent(tp->pdev,
4468                                              TG3_HW_STATUS_SIZE,
4469                                              &tp->status_mapping);
4470         if (!tp->hw_status)
4471                 goto err_out;
4472
4473         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4474                                             sizeof(struct tg3_hw_stats),
4475                                             &tp->stats_mapping);
4476         if (!tp->hw_stats)
4477                 goto err_out;
4478
4479         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4480         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4481
4482         return 0;
4483
4484 err_out:
4485         tg3_free_consistent(tp);
4486         return -ENOMEM;
4487 }
4488
4489 #define MAX_WAIT_CNT 1000
4490
4491 /* To stop a block, clear the enable bit and poll till it
4492  * clears.  tp->lock is held.
4493  */
4494 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4495 {
4496         unsigned int i;
4497         u32 val;
4498
4499         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4500                 switch (ofs) {
4501                 case RCVLSC_MODE:
4502                 case DMAC_MODE:
4503                 case MBFREE_MODE:
4504                 case BUFMGR_MODE:
4505                 case MEMARB_MODE:
4506                         /* We can't enable/disable these bits of the
4507                          * 5705/5750, just say success.
4508                          */
4509                         return 0;
4510
4511                 default:
4512                         break;
4513                 };
4514         }
4515
4516         val = tr32(ofs);
4517         val &= ~enable_bit;
4518         tw32_f(ofs, val);
4519
4520         for (i = 0; i < MAX_WAIT_CNT; i++) {
4521                 udelay(100);
4522                 val = tr32(ofs);
4523                 if ((val & enable_bit) == 0)
4524                         break;
4525         }
4526
4527         if (i == MAX_WAIT_CNT && !silent) {
4528                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4529                        "ofs=%lx enable_bit=%x\n",
4530                        ofs, enable_bit);
4531                 return -ENODEV;
4532         }
4533
4534         return 0;
4535 }
4536
4537 /* tp->lock is held. */
4538 static int tg3_abort_hw(struct tg3 *tp, int silent)
4539 {
4540         int i, err;
4541
4542         tg3_disable_ints(tp);
4543
4544         tp->rx_mode &= ~RX_MODE_ENABLE;
4545         tw32_f(MAC_RX_MODE, tp->rx_mode);
4546         udelay(10);
4547
4548         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4549         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4550         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4551         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4552         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4553         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4554
4555         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4556         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4557         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4558         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4559         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4560         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4561         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4562
4563         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4564         tw32_f(MAC_MODE, tp->mac_mode);
4565         udelay(40);
4566
4567         tp->tx_mode &= ~TX_MODE_ENABLE;
4568         tw32_f(MAC_TX_MODE, tp->tx_mode);
4569
4570         for (i = 0; i < MAX_WAIT_CNT; i++) {
4571                 udelay(100);
4572                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4573                         break;
4574         }
4575         if (i >= MAX_WAIT_CNT) {
4576                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4577                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4578                        tp->dev->name, tr32(MAC_TX_MODE));
4579                 err |= -ENODEV;
4580         }
4581
4582         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4583         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4584         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4585
4586         tw32(FTQ_RESET, 0xffffffff);
4587         tw32(FTQ_RESET, 0x00000000);
4588
4589         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4590         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4591
4592         if (tp->hw_status)
4593                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4594         if (tp->hw_stats)
4595                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4596
4597         return err;
4598 }
4599
4600 /* tp->lock is held. */
4601 static int tg3_nvram_lock(struct tg3 *tp)
4602 {
4603         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4604                 int i;
4605
4606                 if (tp->nvram_lock_cnt == 0) {
4607                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4608                         for (i = 0; i < 8000; i++) {
4609                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4610                                         break;
4611                                 udelay(20);
4612                         }
4613                         if (i == 8000) {
4614                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4615                                 return -ENODEV;
4616                         }
4617                 }
4618                 tp->nvram_lock_cnt++;
4619         }
4620         return 0;
4621 }
4622
4623 /* tp->lock is held. */
4624 static void tg3_nvram_unlock(struct tg3 *tp)
4625 {
4626         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4627                 if (tp->nvram_lock_cnt > 0)
4628                         tp->nvram_lock_cnt--;
4629                 if (tp->nvram_lock_cnt == 0)
4630                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4631         }
4632 }
4633
4634 /* tp->lock is held. */
4635 static void tg3_enable_nvram_access(struct tg3 *tp)
4636 {
4637         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4638             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4639                 u32 nvaccess = tr32(NVRAM_ACCESS);
4640
4641                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4642         }
4643 }
4644
4645 /* tp->lock is held. */
4646 static void tg3_disable_nvram_access(struct tg3 *tp)
4647 {
4648         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4649             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4650                 u32 nvaccess = tr32(NVRAM_ACCESS);
4651
4652                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4653         }
4654 }
4655
4656 /* tp->lock is held. */
4657 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4658 {
4659         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4660                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4661
4662         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4663                 switch (kind) {
4664                 case RESET_KIND_INIT:
4665                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4666                                       DRV_STATE_START);
4667                         break;
4668
4669                 case RESET_KIND_SHUTDOWN:
4670                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4671                                       DRV_STATE_UNLOAD);
4672                         break;
4673
4674                 case RESET_KIND_SUSPEND:
4675                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4676                                       DRV_STATE_SUSPEND);
4677                         break;
4678
4679                 default:
4680                         break;
4681                 };
4682         }
4683 }
4684
4685 /* tp->lock is held. */
4686 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4687 {
4688         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4689                 switch (kind) {
4690                 case RESET_KIND_INIT:
4691                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4692                                       DRV_STATE_START_DONE);
4693                         break;
4694
4695                 case RESET_KIND_SHUTDOWN:
4696                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4697                                       DRV_STATE_UNLOAD_DONE);
4698                         break;
4699
4700                 default:
4701                         break;
4702                 };
4703         }
4704 }
4705
4706 /* tp->lock is held. */
4707 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4708 {
4709         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4710                 switch (kind) {
4711                 case RESET_KIND_INIT:
4712                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4713                                       DRV_STATE_START);
4714                         break;
4715
4716                 case RESET_KIND_SHUTDOWN:
4717                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4718                                       DRV_STATE_UNLOAD);
4719                         break;
4720
4721                 case RESET_KIND_SUSPEND:
4722                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4723                                       DRV_STATE_SUSPEND);
4724                         break;
4725
4726                 default:
4727                         break;
4728                 };
4729         }
4730 }
4731
4732 static int tg3_poll_fw(struct tg3 *tp)
4733 {
4734         int i;
4735         u32 val;
4736
4737         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4738                 /* Wait up to 20ms for init done. */
4739                 for (i = 0; i < 200; i++) {
4740                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4741                                 return 0;
4742                         udelay(100);
4743                 }
4744                 return -ENODEV;
4745         }
4746
4747         /* Wait for firmware initialization to complete. */
4748         for (i = 0; i < 100000; i++) {
4749                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4750                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4751                         break;
4752                 udelay(10);
4753         }
4754
4755         /* Chip might not be fitted with firmware.  Some Sun onboard
4756          * parts are configured like that.  So don't signal the timeout
4757          * of the above loop as an error, but do report the lack of
4758          * running firmware once.
4759          */
4760         if (i >= 100000 &&
4761             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4762                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4763
4764                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4765                        tp->dev->name);
4766         }
4767
4768         return 0;
4769 }
4770
4771 static void tg3_stop_fw(struct tg3 *);
4772
4773 /* tp->lock is held. */
4774 static int tg3_chip_reset(struct tg3 *tp)
4775 {
4776         u32 val;
4777         void (*write_op)(struct tg3 *, u32, u32);
4778         int err;
4779
4780         tg3_nvram_lock(tp);
4781
4782         /* No matching tg3_nvram_unlock() after this because
4783          * chip reset below will undo the nvram lock.
4784          */
4785         tp->nvram_lock_cnt = 0;
4786
4787         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4788             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4789             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4790                 tw32(GRC_FASTBOOT_PC, 0);
4791
4792         /*
4793          * We must avoid the readl() that normally takes place.
4794          * It locks machines, causes machine checks, and other
4795          * fun things.  So, temporarily disable the 5701
4796          * hardware workaround, while we do the reset.
4797          */
4798         write_op = tp->write32;
4799         if (write_op == tg3_write_flush_reg32)
4800                 tp->write32 = tg3_write32;
4801
4802         /* do the reset */
4803         val = GRC_MISC_CFG_CORECLK_RESET;
4804
4805         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4806                 if (tr32(0x7e2c) == 0x60) {
4807                         tw32(0x7e2c, 0x20);
4808                 }
4809                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4810                         tw32(GRC_MISC_CFG, (1 << 29));
4811                         val |= (1 << 29);
4812                 }
4813         }
4814
4815         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4816                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4817                 tw32(GRC_VCPU_EXT_CTRL,
4818                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4819         }
4820
4821         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4822                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4823         tw32(GRC_MISC_CFG, val);
4824
4825         /* restore 5701 hardware bug workaround write method */
4826         tp->write32 = write_op;
4827
4828         /* Unfortunately, we have to delay before the PCI read back.
4829          * Some 575X chips even will not respond to a PCI cfg access
4830          * when the reset command is given to the chip.
4831          *
4832          * How do these hardware designers expect things to work
4833          * properly if the PCI write is posted for a long period
4834          * of time?  It is always necessary to have some method by
4835          * which a register read back can occur to push the write
4836          * out which does the reset.
4837          *
4838          * For most tg3 variants the trick below was working.
4839          * Ho hum...
4840          */
4841         udelay(120);
4842
4843         /* Flush PCI posted writes.  The normal MMIO registers
4844          * are inaccessible at this time so this is the only
4845          * way to make this reliably (actually, this is no longer
4846          * the case, see above).  I tried to use indirect
4847          * register read/write but this upset some 5701 variants.
4848          */
4849         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4850
4851         udelay(120);
4852
4853         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4854                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4855                         int i;
4856                         u32 cfg_val;
4857
4858                         /* Wait for link training to complete.  */
4859                         for (i = 0; i < 5000; i++)
4860                                 udelay(100);
4861
4862                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4863                         pci_write_config_dword(tp->pdev, 0xc4,
4864                                                cfg_val | (1 << 15));
4865                 }
4866                 /* Set PCIE max payload size and clear error status.  */
4867                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4868         }
4869
4870         /* Re-enable indirect register accesses. */
4871         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4872                                tp->misc_host_ctrl);
4873
4874         /* Set MAX PCI retry to zero. */
4875         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4876         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4877             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4878                 val |= PCISTATE_RETRY_SAME_DMA;
4879         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4880
4881         pci_restore_state(tp->pdev);
4882
4883         /* Make sure PCI-X relaxed ordering bit is clear. */
4884         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4885         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4886         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4887
4888         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4889                 u32 val;
4890
4891                 /* Chip reset on 5780 will reset MSI enable bit,
4892                  * so need to restore it.
4893                  */
4894                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4895                         u16 ctrl;
4896
4897                         pci_read_config_word(tp->pdev,
4898                                              tp->msi_cap + PCI_MSI_FLAGS,
4899                                              &ctrl);
4900                         pci_write_config_word(tp->pdev,
4901                                               tp->msi_cap + PCI_MSI_FLAGS,
4902                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4903                         val = tr32(MSGINT_MODE);
4904                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4905                 }
4906
4907                 val = tr32(MEMARB_MODE);
4908                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4909
4910         } else
4911                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4912
4913         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4914                 tg3_stop_fw(tp);
4915                 tw32(0x5000, 0x400);
4916         }
4917
4918         tw32(GRC_MODE, tp->grc_mode);
4919
4920         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4921                 u32 val = tr32(0xc4);
4922
4923                 tw32(0xc4, val | (1 << 15));
4924         }
4925
4926         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4927             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4928                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4929                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4930                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4931                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4932         }
4933
4934         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4935                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4936                 tw32_f(MAC_MODE, tp->mac_mode);
4937         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4938                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4939                 tw32_f(MAC_MODE, tp->mac_mode);
4940         } else
4941                 tw32_f(MAC_MODE, 0);
4942         udelay(40);
4943
4944         err = tg3_poll_fw(tp);
4945         if (err)
4946                 return err;
4947
4948         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4949             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4950                 u32 val = tr32(0x7c00);
4951
4952                 tw32(0x7c00, val | (1 << 25));
4953         }
4954
4955         /* Reprobe ASF enable state.  */
4956         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4957         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4958         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4959         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4960                 u32 nic_cfg;
4961
4962                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4963                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4964                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4965                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4966                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4967                 }
4968         }
4969
4970         return 0;
4971 }
4972
4973 /* tp->lock is held. */
4974 static void tg3_stop_fw(struct tg3 *tp)
4975 {
4976         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4977                 u32 val;
4978                 int i;
4979
4980                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
4981                 val = tr32(GRC_RX_CPU_EVENT);
4982                 val |= (1 << 14);
4983                 tw32(GRC_RX_CPU_EVENT, val);
4984
4985                 /* Wait for RX cpu to ACK the event.  */
4986                 for (i = 0; i < 100; i++) {
4987                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
4988                                 break;
4989                         udelay(1);
4990                 }
4991         }
4992 }
4993
4994 /* tp->lock is held. */
4995 static int tg3_halt(struct tg3 *tp, int kind, int silent)
4996 {
4997         int err;
4998
4999         tg3_stop_fw(tp);
5000
5001         tg3_write_sig_pre_reset(tp, kind);
5002
5003         tg3_abort_hw(tp, silent);
5004         err = tg3_chip_reset(tp);
5005
5006         tg3_write_sig_legacy(tp, kind);
5007         tg3_write_sig_post_reset(tp, kind);
5008
5009         if (err)
5010                 return err;
5011
5012         return 0;
5013 }
5014
5015 #define TG3_FW_RELEASE_MAJOR    0x0
5016 #define TG3_FW_RELASE_MINOR     0x0
5017 #define TG3_FW_RELEASE_FIX      0x0
5018 #define TG3_FW_START_ADDR       0x08000000
5019 #define TG3_FW_TEXT_ADDR        0x08000000
5020 #define TG3_FW_TEXT_LEN         0x9c0
5021 #define TG3_FW_RODATA_ADDR      0x080009c0
5022 #define TG3_FW_RODATA_LEN       0x60
5023 #define TG3_FW_DATA_ADDR        0x08000a40
5024 #define TG3_FW_DATA_LEN         0x20
5025 #define TG3_FW_SBSS_ADDR        0x08000a60
5026 #define TG3_FW_SBSS_LEN         0xc
5027 #define TG3_FW_BSS_ADDR         0x08000a70
5028 #define TG3_FW_BSS_LEN          0x10
5029
5030 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5031         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5032         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5033         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5034         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5035         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5036         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5037         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5038         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5039         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5040         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5041         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5042         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5043         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5044         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5045         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5046         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5047         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5048         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5049         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5050         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5051         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5052         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5053         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5054         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5055         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5056         0, 0, 0, 0, 0, 0,
5057         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5058         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5059         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5060         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5061         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5062         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5063         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5064         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5065         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5066         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5067         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5068         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5069         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5070         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5071         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5072         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5073         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5074         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5075         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5076         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5077         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5078         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5079         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5080         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5081         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5082         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5083         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5084         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5085         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5086         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5087         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5088         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5089         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5090         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5091         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5092         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5093         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5094         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5095         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5096         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5097         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5098         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5099         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5100         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5101         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5102         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5103         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5104         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5105         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5106         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5107         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5108         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5109         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5110         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5111         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5112         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5113         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5114         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5115         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5116         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5117         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5118         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5119         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5120         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5121         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5122 };
5123
5124 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5125         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5126         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5127         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5128         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5129         0x00000000
5130 };
5131
5132 #if 0 /* All zeros, don't eat up space with it. */
5133 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5134         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5135         0x00000000, 0x00000000, 0x00000000, 0x00000000
5136 };
5137 #endif
5138
5139 #define RX_CPU_SCRATCH_BASE     0x30000
5140 #define RX_CPU_SCRATCH_SIZE     0x04000
5141 #define TX_CPU_SCRATCH_BASE     0x34000
5142 #define TX_CPU_SCRATCH_SIZE     0x04000
5143
5144 /* tp->lock is held. */
5145 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5146 {
5147         int i;
5148
5149         BUG_ON(offset == TX_CPU_BASE &&
5150             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5151
5152         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5153                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5154
5155                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5156                 return 0;
5157         }
5158         if (offset == RX_CPU_BASE) {
5159                 for (i = 0; i < 10000; i++) {
5160                         tw32(offset + CPU_STATE, 0xffffffff);
5161                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5162                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5163                                 break;
5164                 }
5165
5166                 tw32(offset + CPU_STATE, 0xffffffff);
5167                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5168                 udelay(10);
5169         } else {
5170                 for (i = 0; i < 10000; i++) {
5171                         tw32(offset + CPU_STATE, 0xffffffff);
5172                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5173                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5174                                 break;
5175                 }
5176         }
5177
5178         if (i >= 10000) {
5179                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5180                        "and %s CPU\n",
5181                        tp->dev->name,
5182                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5183                 return -ENODEV;
5184         }
5185
5186         /* Clear firmware's nvram arbitration. */
5187         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5188                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5189         return 0;
5190 }
5191
5192 struct fw_info {
5193         unsigned int text_base;
5194         unsigned int text_len;
5195         const u32 *text_data;
5196         unsigned int rodata_base;
5197         unsigned int rodata_len;
5198         const u32 *rodata_data;
5199         unsigned int data_base;
5200         unsigned int data_len;
5201         const u32 *data_data;
5202 };
5203
5204 /* tp->lock is held. */
5205 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5206                                  int cpu_scratch_size, struct fw_info *info)
5207 {
5208         int err, lock_err, i;
5209         void (*write_op)(struct tg3 *, u32, u32);
5210
5211         if (cpu_base == TX_CPU_BASE &&
5212             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5213                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5214                        "TX cpu firmware on %s which is 5705.\n",
5215                        tp->dev->name);
5216                 return -EINVAL;
5217         }
5218
5219         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5220                 write_op = tg3_write_mem;
5221         else
5222                 write_op = tg3_write_indirect_reg32;
5223
5224         /* It is possible that bootcode is still loading at this point.
5225          * Get the nvram lock first before halting the cpu.
5226          */
5227         lock_err = tg3_nvram_lock(tp);
5228         err = tg3_halt_cpu(tp, cpu_base);
5229         if (!lock_err)
5230                 tg3_nvram_unlock(tp);
5231         if (err)
5232                 goto out;
5233
5234         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5235                 write_op(tp, cpu_scratch_base + i, 0);
5236         tw32(cpu_base + CPU_STATE, 0xffffffff);
5237         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5238         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5239                 write_op(tp, (cpu_scratch_base +
5240                               (info->text_base & 0xffff) +
5241                               (i * sizeof(u32))),
5242                          (info->text_data ?
5243                           info->text_data[i] : 0));
5244         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5245                 write_op(tp, (cpu_scratch_base +
5246                               (info->rodata_base & 0xffff) +
5247                               (i * sizeof(u32))),
5248                          (info->rodata_data ?
5249                           info->rodata_data[i] : 0));
5250         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5251                 write_op(tp, (cpu_scratch_base +
5252                               (info->data_base & 0xffff) +
5253                               (i * sizeof(u32))),
5254                          (info->data_data ?
5255                           info->data_data[i] : 0));
5256
5257         err = 0;
5258
5259 out:
5260         return err;
5261 }
5262
5263 /* tp->lock is held. */
5264 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5265 {
5266         struct fw_info info;
5267         int err, i;
5268
5269         info.text_base = TG3_FW_TEXT_ADDR;
5270         info.text_len = TG3_FW_TEXT_LEN;
5271         info.text_data = &tg3FwText[0];
5272         info.rodata_base = TG3_FW_RODATA_ADDR;
5273         info.rodata_len = TG3_FW_RODATA_LEN;
5274         info.rodata_data = &tg3FwRodata[0];
5275         info.data_base = TG3_FW_DATA_ADDR;
5276         info.data_len = TG3_FW_DATA_LEN;
5277         info.data_data = NULL;
5278
5279         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5280                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5281                                     &info);
5282         if (err)
5283                 return err;
5284
5285         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5286                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5287                                     &info);
5288         if (err)
5289                 return err;
5290
5291         /* Now startup only the RX cpu. */
5292         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5293         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5294
5295         for (i = 0; i < 5; i++) {
5296                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5297                         break;
5298                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5299                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5300                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5301                 udelay(1000);
5302         }
5303         if (i >= 5) {
5304                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5305                        "to set RX CPU PC, is %08x should be %08x\n",
5306                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5307                        TG3_FW_TEXT_ADDR);
5308                 return -ENODEV;
5309         }
5310         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5311         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5312
5313         return 0;
5314 }
5315
5316 #if TG3_TSO_SUPPORT != 0
5317
5318 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5319 #define TG3_TSO_FW_RELASE_MINOR         0x6
5320 #define TG3_TSO_FW_RELEASE_FIX          0x0
5321 #define TG3_TSO_FW_START_ADDR           0x08000000
5322 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5323 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5324 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5325 #define TG3_TSO_FW_RODATA_LEN           0x60
5326 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5327 #define TG3_TSO_FW_DATA_LEN             0x30
5328 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5329 #define TG3_TSO_FW_SBSS_LEN             0x2c
5330 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5331 #define TG3_TSO_FW_BSS_LEN              0x894
5332
5333 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5334         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5335         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5336         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5337         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5338         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5339         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5340         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5341         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5342         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5343         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5344         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5345         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5346         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5347         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5348         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5349         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5350         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5351         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5352         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5353         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5354         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5355         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5356         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5357         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5358         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5359         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5360         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5361         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5362         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5363         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5364         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5365         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5366         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5367         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5368         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5369         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5370         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5371         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5372         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5373         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5374         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5375         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5376         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5377         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5378         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5379         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5380         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5381         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5382         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5383         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5384         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5385         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5386         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5387         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5388         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5389         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5390         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5391         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5392         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5393         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5394         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5395         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5396         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5397         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5398         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5399         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5400         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5401         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5402         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5403         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5404         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5405         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5406         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5407         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5408         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5409         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5410         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5411         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5412         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5413         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5414         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5415         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5416         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5417         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5418         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5419         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5420         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5421         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5422         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5423         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5424         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5425         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5426         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5427         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5428         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5429         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5430         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5431         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5432         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5433         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5434         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5435         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5436         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5437         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5438         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5439         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5440         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5441         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5442         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5443         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5444         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5445         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5446         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5447         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5448         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5449         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5450         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5451         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5452         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5453         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5454         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5455         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5456         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5457         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5458         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5459         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5460         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5461         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5462         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5463         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5464         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5465         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5466         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5467         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5468         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5469         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5470         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5471         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5472         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5473         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5474         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5475         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5476         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5477         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5478         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5479         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5480         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5481         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5482         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5483         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5484         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5485         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5486         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5487         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5488         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5489         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5490         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5491         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5492         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5493         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5494         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5495         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5496         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5497         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5498         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5499         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5500         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5501         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5502         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5503         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5504         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5505         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5506         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5507         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5508         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5509         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5510         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5511         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5512         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5513         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5514         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5515         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5516         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5517         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5518         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5519         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5520         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5521         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5522         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5523         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5524         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5525         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5526         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5527         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5528         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5529         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5530         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5531         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5532         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5533         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5534         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5535         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5536         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5537         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5538         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5539         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5540         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5541         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5542         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5543         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5544         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5545         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5546         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5547         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5548         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5549         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5550         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5551         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5552         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5553         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5554         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5555         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5556         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5557         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5558         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5559         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5560         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5561         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5562         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5563         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5564         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5565         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5566         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5567         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5568         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5569         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5570         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5571         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5572         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5573         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5574         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5575         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5576         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5577         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5578         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5579         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5580         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5581         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5582         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5583         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5584         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5585         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5586         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5587         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5588         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5589         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5590         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5591         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5592         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5593         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5594         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5595         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5596         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5597         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5598         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5599         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5600         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5601         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5602         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5603         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5604         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5605         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5606         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5607         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5608         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5609         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5610         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5611         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5612         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5613         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5614         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5615         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5616         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5617         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5618 };
5619
5620 static const u32 tg3TsoFwRodata[] = {
5621         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5622         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5623         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5624         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5625         0x00000000,
5626 };
5627
5628 static const u32 tg3TsoFwData[] = {
5629         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5630         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5631         0x00000000,
5632 };
5633
5634 /* 5705 needs a special version of the TSO firmware.  */
5635 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5636 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5637 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5638 #define TG3_TSO5_FW_START_ADDR          0x00010000
5639 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5640 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5641 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5642 #define TG3_TSO5_FW_RODATA_LEN          0x50
5643 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5644 #define TG3_TSO5_FW_DATA_LEN            0x20
5645 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5646 #define TG3_TSO5_FW_SBSS_LEN            0x28
5647 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5648 #define TG3_TSO5_FW_BSS_LEN             0x88
5649
5650 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5651         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5652         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5653         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5654         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5655         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5656         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5657         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5658         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5659         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5660         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5661         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5662         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5663         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5664         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5665         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5666         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5667         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5668         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5669         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5670         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5671         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5672         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5673         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5674         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5675         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5676         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5677         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5678         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5679         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5680         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5681         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5682         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5683         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5684         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5685         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5686         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5687         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5688         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5689         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5690         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5691         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5692         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5693         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5694         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5695         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5696         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5697         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5698         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5699         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5700         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5701         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5702         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5703         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5704         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5705         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5706         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5707         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5708         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5709         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5710         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5711         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5712         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5713         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5714         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5715         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5716         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5717         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5718         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5719         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5720         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5721         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5722         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5723         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5724         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5725         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5726         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5727         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5728         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5729         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5730         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5731         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5732         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5733         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5734         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5735         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5736         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5737         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5738         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5739         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5740         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5741         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5742         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5743         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5744         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5745         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5746         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5747         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5748         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5749         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5750         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5751         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5752         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5753         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5754         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5755         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5756         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5757         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5758         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5759         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5760         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5761         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5762         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5763         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5764         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5765         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5766         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5767         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5768         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5769         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5770         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5771         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5772         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5773         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5774         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5775         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5776         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5777         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5778         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5779         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5780         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5781         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5782         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5783         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5784         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5785         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5786         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5787         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5788         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5789         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5790         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5791         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5792         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5793         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5794         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5795         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5796         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5797         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5798         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5799         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5800         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5801         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5802         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5803         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5804         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5805         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5806         0x00000000, 0x00000000, 0x00000000,
5807 };
5808
5809 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5810         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5811         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5812         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5813         0x00000000, 0x00000000, 0x00000000,
5814 };
5815
5816 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5817         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5818         0x00000000, 0x00000000, 0x00000000,
5819 };
5820
5821 /* tp->lock is held. */
5822 static int tg3_load_tso_firmware(struct tg3 *tp)
5823 {
5824         struct fw_info info;
5825         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5826         int err, i;
5827
5828         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5829                 return 0;
5830
5831         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5832                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5833                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5834                 info.text_data = &tg3Tso5FwText[0];
5835                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5836                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5837                 info.rodata_data = &tg3Tso5FwRodata[0];
5838                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5839                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5840                 info.data_data = &tg3Tso5FwData[0];
5841                 cpu_base = RX_CPU_BASE;
5842                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5843                 cpu_scratch_size = (info.text_len +
5844                                     info.rodata_len +
5845                                     info.data_len +
5846                                     TG3_TSO5_FW_SBSS_LEN +
5847                                     TG3_TSO5_FW_BSS_LEN);
5848         } else {
5849                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5850                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5851                 info.text_data = &tg3TsoFwText[0];
5852                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5853                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5854                 info.rodata_data = &tg3TsoFwRodata[0];
5855                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5856                 info.data_len = TG3_TSO_FW_DATA_LEN;
5857                 info.data_data = &tg3TsoFwData[0];
5858                 cpu_base = TX_CPU_BASE;
5859                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5860                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5861         }
5862
5863         err = tg3_load_firmware_cpu(tp, cpu_base,
5864                                     cpu_scratch_base, cpu_scratch_size,
5865                                     &info);
5866         if (err)
5867                 return err;
5868
5869         /* Now startup the cpu. */
5870         tw32(cpu_base + CPU_STATE, 0xffffffff);
5871         tw32_f(cpu_base + CPU_PC,    info.text_base);
5872
5873         for (i = 0; i < 5; i++) {
5874                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5875                         break;
5876                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5877                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5878                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5879                 udelay(1000);
5880         }
5881         if (i >= 5) {
5882                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5883                        "to set CPU PC, is %08x should be %08x\n",
5884                        tp->dev->name, tr32(cpu_base + CPU_PC),
5885                        info.text_base);
5886                 return -ENODEV;
5887         }
5888         tw32(cpu_base + CPU_STATE, 0xffffffff);
5889         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5890         return 0;
5891 }
5892
5893 #endif /* TG3_TSO_SUPPORT != 0 */
5894
5895 /* tp->lock is held. */
5896 static void __tg3_set_mac_addr(struct tg3 *tp)
5897 {
5898         u32 addr_high, addr_low;
5899         int i;
5900
5901         addr_high = ((tp->dev->dev_addr[0] << 8) |
5902                      tp->dev->dev_addr[1]);
5903         addr_low = ((tp->dev->dev_addr[2] << 24) |
5904                     (tp->dev->dev_addr[3] << 16) |
5905                     (tp->dev->dev_addr[4] <<  8) |
5906                     (tp->dev->dev_addr[5] <<  0));
5907         for (i = 0; i < 4; i++) {
5908                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5909                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5910         }
5911
5912         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5913             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5914                 for (i = 0; i < 12; i++) {
5915                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5916                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5917                 }
5918         }
5919
5920         addr_high = (tp->dev->dev_addr[0] +
5921                      tp->dev->dev_addr[1] +
5922                      tp->dev->dev_addr[2] +
5923                      tp->dev->dev_addr[3] +
5924                      tp->dev->dev_addr[4] +
5925                      tp->dev->dev_addr[5]) &
5926                 TX_BACKOFF_SEED_MASK;
5927         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5928 }
5929
5930 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5931 {
5932         struct tg3 *tp = netdev_priv(dev);
5933         struct sockaddr *addr = p;
5934         int err = 0;
5935
5936         if (!is_valid_ether_addr(addr->sa_data))
5937                 return -EINVAL;
5938
5939         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5940
5941         if (!netif_running(dev))
5942                 return 0;
5943
5944         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5945                 /* Reset chip so that ASF can re-init any MAC addresses it
5946                  * needs.
5947                  */
5948                 tg3_netif_stop(tp);
5949                 tg3_full_lock(tp, 1);
5950
5951                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5952                 err = tg3_restart_hw(tp, 0);
5953                 if (!err)
5954                         tg3_netif_start(tp);
5955                 tg3_full_unlock(tp);
5956         } else {
5957                 spin_lock_bh(&tp->lock);
5958                 __tg3_set_mac_addr(tp);
5959                 spin_unlock_bh(&tp->lock);
5960         }
5961
5962         return err;
5963 }
5964
5965 /* tp->lock is held. */
5966 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5967                            dma_addr_t mapping, u32 maxlen_flags,
5968                            u32 nic_addr)
5969 {
5970         tg3_write_mem(tp,
5971                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5972                       ((u64) mapping >> 32));
5973         tg3_write_mem(tp,
5974                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5975                       ((u64) mapping & 0xffffffff));
5976         tg3_write_mem(tp,
5977                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5978                        maxlen_flags);
5979
5980         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
5981                 tg3_write_mem(tp,
5982                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
5983                               nic_addr);
5984 }
5985
5986 static void __tg3_set_rx_mode(struct net_device *);
5987 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
5988 {
5989         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
5990         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
5991         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
5992         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
5993         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5994                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
5995                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
5996         }
5997         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
5998         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
5999         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6000                 u32 val = ec->stats_block_coalesce_usecs;
6001
6002                 if (!netif_carrier_ok(tp->dev))
6003                         val = 0;
6004
6005                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6006         }
6007 }
6008
6009 /* tp->lock is held. */
6010 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6011 {
6012         u32 val, rdmac_mode;
6013         int i, err, limit;
6014
6015         tg3_disable_ints(tp);
6016
6017         tg3_stop_fw(tp);
6018
6019         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6020
6021         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6022                 tg3_abort_hw(tp, 1);
6023         }
6024
6025         if (reset_phy)
6026                 tg3_phy_reset(tp);
6027
6028         err = tg3_chip_reset(tp);
6029         if (err)
6030                 return err;
6031
6032         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6033
6034         /* This works around an issue with Athlon chipsets on
6035          * B3 tigon3 silicon.  This bit has no effect on any
6036          * other revision.  But do not set this on PCI Express
6037          * chips.
6038          */
6039         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6040                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6041         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6042
6043         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6044             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6045                 val = tr32(TG3PCI_PCISTATE);
6046                 val |= PCISTATE_RETRY_SAME_DMA;
6047                 tw32(TG3PCI_PCISTATE, val);
6048         }
6049
6050         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6051                 /* Enable some hw fixes.  */
6052                 val = tr32(TG3PCI_MSI_DATA);
6053                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6054                 tw32(TG3PCI_MSI_DATA, val);
6055         }
6056
6057         /* Descriptor ring init may make accesses to the
6058          * NIC SRAM area to setup the TX descriptors, so we
6059          * can only do this after the hardware has been
6060          * successfully reset.
6061          */
6062         err = tg3_init_rings(tp);
6063         if (err)
6064                 return err;
6065
6066         /* This value is determined during the probe time DMA
6067          * engine test, tg3_test_dma.
6068          */
6069         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6070
6071         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6072                           GRC_MODE_4X_NIC_SEND_RINGS |
6073                           GRC_MODE_NO_TX_PHDR_CSUM |
6074                           GRC_MODE_NO_RX_PHDR_CSUM);
6075         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6076
6077         /* Pseudo-header checksum is done by hardware logic and not
6078          * the offload processers, so make the chip do the pseudo-
6079          * header checksums on receive.  For transmit it is more
6080          * convenient to do the pseudo-header checksum in software
6081          * as Linux does that on transmit for us in all cases.
6082          */
6083         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6084
6085         tw32(GRC_MODE,
6086              tp->grc_mode |
6087              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6088
6089         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6090         val = tr32(GRC_MISC_CFG);
6091         val &= ~0xff;
6092         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6093         tw32(GRC_MISC_CFG, val);
6094
6095         /* Initialize MBUF/DESC pool. */
6096         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6097                 /* Do nothing.  */
6098         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6099                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6100                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6101                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6102                 else
6103                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6104                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6105                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6106         }
6107 #if TG3_TSO_SUPPORT != 0
6108         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6109                 int fw_len;
6110
6111                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6112                           TG3_TSO5_FW_RODATA_LEN +
6113                           TG3_TSO5_FW_DATA_LEN +
6114                           TG3_TSO5_FW_SBSS_LEN +
6115                           TG3_TSO5_FW_BSS_LEN);
6116                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6117                 tw32(BUFMGR_MB_POOL_ADDR,
6118                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6119                 tw32(BUFMGR_MB_POOL_SIZE,
6120                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6121         }
6122 #endif
6123
6124         if (tp->dev->mtu <= ETH_DATA_LEN) {
6125                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6126                      tp->bufmgr_config.mbuf_read_dma_low_water);
6127                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6128                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6129                 tw32(BUFMGR_MB_HIGH_WATER,
6130                      tp->bufmgr_config.mbuf_high_water);
6131         } else {
6132                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6133                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6134                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6135                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6136                 tw32(BUFMGR_MB_HIGH_WATER,
6137                      tp->bufmgr_config.mbuf_high_water_jumbo);
6138         }
6139         tw32(BUFMGR_DMA_LOW_WATER,
6140              tp->bufmgr_config.dma_low_water);
6141         tw32(BUFMGR_DMA_HIGH_WATER,
6142              tp->bufmgr_config.dma_high_water);
6143
6144         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6145         for (i = 0; i < 2000; i++) {
6146                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6147                         break;
6148                 udelay(10);
6149         }
6150         if (i >= 2000) {
6151                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6152                        tp->dev->name);
6153                 return -ENODEV;
6154         }
6155
6156         /* Setup replenish threshold. */
6157         val = tp->rx_pending / 8;
6158         if (val == 0)
6159                 val = 1;
6160         else if (val > tp->rx_std_max_post)
6161                 val = tp->rx_std_max_post;
6162         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6163                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6164                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6165
6166                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6167                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6168         }
6169
6170         tw32(RCVBDI_STD_THRESH, val);
6171
6172         /* Initialize TG3_BDINFO's at:
6173          *  RCVDBDI_STD_BD:     standard eth size rx ring
6174          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6175          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6176          *
6177          * like so:
6178          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6179          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6180          *                              ring attribute flags
6181          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6182          *
6183          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6184          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6185          *
6186          * The size of each ring is fixed in the firmware, but the location is
6187          * configurable.
6188          */
6189         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6190              ((u64) tp->rx_std_mapping >> 32));
6191         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6192              ((u64) tp->rx_std_mapping & 0xffffffff));
6193         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6194              NIC_SRAM_RX_BUFFER_DESC);
6195
6196         /* Don't even try to program the JUMBO/MINI buffer descriptor
6197          * configs on 5705.
6198          */
6199         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6200                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6201                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6202         } else {
6203                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6204                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6205
6206                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6207                      BDINFO_FLAGS_DISABLED);
6208
6209                 /* Setup replenish threshold. */
6210                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6211
6212                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6213                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6214                              ((u64) tp->rx_jumbo_mapping >> 32));
6215                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6216                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6217                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6218                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6219                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6220                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6221                 } else {
6222                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6223                              BDINFO_FLAGS_DISABLED);
6224                 }
6225
6226         }
6227
6228         /* There is only one send ring on 5705/5750, no need to explicitly
6229          * disable the others.
6230          */
6231         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6232                 /* Clear out send RCB ring in SRAM. */
6233                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6234                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6235                                       BDINFO_FLAGS_DISABLED);
6236         }
6237
6238         tp->tx_prod = 0;
6239         tp->tx_cons = 0;
6240         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6241         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6242
6243         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6244                        tp->tx_desc_mapping,
6245                        (TG3_TX_RING_SIZE <<
6246                         BDINFO_FLAGS_MAXLEN_SHIFT),
6247                        NIC_SRAM_TX_BUFFER_DESC);
6248
6249         /* There is only one receive return ring on 5705/5750, no need
6250          * to explicitly disable the others.
6251          */
6252         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6253                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6254                      i += TG3_BDINFO_SIZE) {
6255                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6256                                       BDINFO_FLAGS_DISABLED);
6257                 }
6258         }
6259
6260         tp->rx_rcb_ptr = 0;
6261         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6262
6263         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6264                        tp->rx_rcb_mapping,
6265                        (TG3_RX_RCB_RING_SIZE(tp) <<
6266                         BDINFO_FLAGS_MAXLEN_SHIFT),
6267                        0);
6268
6269         tp->rx_std_ptr = tp->rx_pending;
6270         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6271                      tp->rx_std_ptr);
6272
6273         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6274                                                 tp->rx_jumbo_pending : 0;
6275         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6276                      tp->rx_jumbo_ptr);
6277
6278         /* Initialize MAC address and backoff seed. */
6279         __tg3_set_mac_addr(tp);
6280
6281         /* MTU + ethernet header + FCS + optional VLAN tag */
6282         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6283
6284         /* The slot time is changed by tg3_setup_phy if we
6285          * run at gigabit with half duplex.
6286          */
6287         tw32(MAC_TX_LENGTHS,
6288              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6289              (6 << TX_LENGTHS_IPG_SHIFT) |
6290              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6291
6292         /* Receive rules. */
6293         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6294         tw32(RCVLPC_CONFIG, 0x0181);
6295
6296         /* Calculate RDMAC_MODE setting early, we need it to determine
6297          * the RCVLPC_STATE_ENABLE mask.
6298          */
6299         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6300                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6301                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6302                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6303                       RDMAC_MODE_LNGREAD_ENAB);
6304         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6305                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6306
6307         /* If statement applies to 5705 and 5750 PCI devices only */
6308         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6309              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6310             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6311                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6312                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6313                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6314                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6315                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6316                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6317                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6318                 }
6319         }
6320
6321         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6322                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6323
6324 #if TG3_TSO_SUPPORT != 0
6325         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6326                 rdmac_mode |= (1 << 27);
6327 #endif
6328
6329         /* Receive/send statistics. */
6330         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6331                 val = tr32(RCVLPC_STATS_ENABLE);
6332                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6333                 tw32(RCVLPC_STATS_ENABLE, val);
6334         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6335                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6336                 val = tr32(RCVLPC_STATS_ENABLE);
6337                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6338                 tw32(RCVLPC_STATS_ENABLE, val);
6339         } else {
6340                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6341         }
6342         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6343         tw32(SNDDATAI_STATSENAB, 0xffffff);
6344         tw32(SNDDATAI_STATSCTRL,
6345              (SNDDATAI_SCTRL_ENABLE |
6346               SNDDATAI_SCTRL_FASTUPD));
6347
6348         /* Setup host coalescing engine. */
6349         tw32(HOSTCC_MODE, 0);
6350         for (i = 0; i < 2000; i++) {
6351                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6352                         break;
6353                 udelay(10);
6354         }
6355
6356         __tg3_set_coalesce(tp, &tp->coal);
6357
6358         /* set status block DMA address */
6359         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6360              ((u64) tp->status_mapping >> 32));
6361         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6362              ((u64) tp->status_mapping & 0xffffffff));
6363
6364         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6365                 /* Status/statistics block address.  See tg3_timer,
6366                  * the tg3_periodic_fetch_stats call there, and
6367                  * tg3_get_stats to see how this works for 5705/5750 chips.
6368                  */
6369                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6370                      ((u64) tp->stats_mapping >> 32));
6371                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6372                      ((u64) tp->stats_mapping & 0xffffffff));
6373                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6374                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6375         }
6376
6377         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6378
6379         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6380         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6381         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6382                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6383
6384         /* Clear statistics/status block in chip, and status block in ram. */
6385         for (i = NIC_SRAM_STATS_BLK;
6386              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6387              i += sizeof(u32)) {
6388                 tg3_write_mem(tp, i, 0);
6389                 udelay(40);
6390         }
6391         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6392
6393         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6394                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6395                 /* reset to prevent losing 1st rx packet intermittently */
6396                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6397                 udelay(10);
6398         }
6399
6400         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6401                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6402         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6403         udelay(40);
6404
6405         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6406          * If TG3_FLG2_IS_NIC is zero, we should read the
6407          * register to preserve the GPIO settings for LOMs. The GPIOs,
6408          * whether used as inputs or outputs, are set by boot code after
6409          * reset.
6410          */
6411         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6412                 u32 gpio_mask;
6413
6414                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6415                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6416                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6417
6418                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6419                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6420                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6421
6422                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6423                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6424
6425                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6426
6427                 /* GPIO1 must be driven high for eeprom write protect */
6428                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6429                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6430                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6431         }
6432         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6433         udelay(100);
6434
6435         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6436         tp->last_tag = 0;
6437
6438         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6439                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6440                 udelay(40);
6441         }
6442
6443         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6444                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6445                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6446                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6447                WDMAC_MODE_LNGREAD_ENAB);
6448
6449         /* If statement applies to 5705 and 5750 PCI devices only */
6450         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6451              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6452             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6453                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6454                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6455                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6456                         /* nothing */
6457                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6458                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6459                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6460                         val |= WDMAC_MODE_RX_ACCEL;
6461                 }
6462         }
6463
6464         /* Enable host coalescing bug fix */
6465         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6466             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6467                 val |= (1 << 29);
6468
6469         tw32_f(WDMAC_MODE, val);
6470         udelay(40);
6471
6472         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6473                 val = tr32(TG3PCI_X_CAPS);
6474                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6475                         val &= ~PCIX_CAPS_BURST_MASK;
6476                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6477                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6478                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6479                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6480                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6481                                 val |= (tp->split_mode_max_reqs <<
6482                                         PCIX_CAPS_SPLIT_SHIFT);
6483                 }
6484                 tw32(TG3PCI_X_CAPS, val);
6485         }
6486
6487         tw32_f(RDMAC_MODE, rdmac_mode);
6488         udelay(40);
6489
6490         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6491         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6492                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6493         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6494         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6495         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6496         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6497         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6498 #if TG3_TSO_SUPPORT != 0
6499         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6500                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6501 #endif
6502         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6503         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6504
6505         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6506                 err = tg3_load_5701_a0_firmware_fix(tp);
6507                 if (err)
6508                         return err;
6509         }
6510
6511 #if TG3_TSO_SUPPORT != 0
6512         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6513                 err = tg3_load_tso_firmware(tp);
6514                 if (err)
6515                         return err;
6516         }
6517 #endif
6518
6519         tp->tx_mode = TX_MODE_ENABLE;
6520         tw32_f(MAC_TX_MODE, tp->tx_mode);
6521         udelay(100);
6522
6523         tp->rx_mode = RX_MODE_ENABLE;
6524         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6525                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6526
6527         tw32_f(MAC_RX_MODE, tp->rx_mode);
6528         udelay(10);
6529
6530         if (tp->link_config.phy_is_low_power) {
6531                 tp->link_config.phy_is_low_power = 0;
6532                 tp->link_config.speed = tp->link_config.orig_speed;
6533                 tp->link_config.duplex = tp->link_config.orig_duplex;
6534                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6535         }
6536
6537         tp->mi_mode = MAC_MI_MODE_BASE;
6538         tw32_f(MAC_MI_MODE, tp->mi_mode);
6539         udelay(80);
6540
6541         tw32(MAC_LED_CTRL, tp->led_ctrl);
6542
6543         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6544         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6545                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6546                 udelay(10);
6547         }
6548         tw32_f(MAC_RX_MODE, tp->rx_mode);
6549         udelay(10);
6550
6551         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6552                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6553                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6554                         /* Set drive transmission level to 1.2V  */
6555                         /* only if the signal pre-emphasis bit is not set  */
6556                         val = tr32(MAC_SERDES_CFG);
6557                         val &= 0xfffff000;
6558                         val |= 0x880;
6559                         tw32(MAC_SERDES_CFG, val);
6560                 }
6561                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6562                         tw32(MAC_SERDES_CFG, 0x616000);
6563         }
6564
6565         /* Prevent chip from dropping frames when flow control
6566          * is enabled.
6567          */
6568         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6569
6570         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6571             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6572                 /* Use hardware link auto-negotiation */
6573                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6574         }
6575
6576         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6577             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6578                 u32 tmp;
6579
6580                 tmp = tr32(SERDES_RX_CTRL);
6581                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6582                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6583                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6584                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6585         }
6586
6587         err = tg3_setup_phy(tp, 0);
6588         if (err)
6589                 return err;
6590
6591         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6592             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6593                 u32 tmp;
6594
6595                 /* Clear CRC stats. */
6596                 if (!tg3_readphy(tp, 0x1e, &tmp)) {
6597                         tg3_writephy(tp, 0x1e, tmp | 0x8000);
6598                         tg3_readphy(tp, 0x14, &tmp);
6599                 }
6600         }
6601
6602         __tg3_set_rx_mode(tp->dev);
6603
6604         /* Initialize receive rules. */
6605         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6606         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6607         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6608         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6609
6610         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6611             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6612                 limit = 8;
6613         else
6614                 limit = 16;
6615         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6616                 limit -= 4;
6617         switch (limit) {
6618         case 16:
6619                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6620         case 15:
6621                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6622         case 14:
6623                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6624         case 13:
6625                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6626         case 12:
6627                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6628         case 11:
6629                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6630         case 10:
6631                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6632         case 9:
6633                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6634         case 8:
6635                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6636         case 7:
6637                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6638         case 6:
6639                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6640         case 5:
6641                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6642         case 4:
6643                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6644         case 3:
6645                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6646         case 2:
6647         case 1:
6648
6649         default:
6650                 break;
6651         };
6652
6653         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6654
6655         return 0;
6656 }
6657
6658 /* Called at device open time to get the chip ready for
6659  * packet processing.  Invoked with tp->lock held.
6660  */
6661 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6662 {
6663         int err;
6664
6665         /* Force the chip into D0. */
6666         err = tg3_set_power_state(tp, PCI_D0);
6667         if (err)
6668                 goto out;
6669
6670         tg3_switch_clocks(tp);
6671
6672         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6673
6674         err = tg3_reset_hw(tp, reset_phy);
6675
6676 out:
6677         return err;
6678 }
6679
6680 #define TG3_STAT_ADD32(PSTAT, REG) \
6681 do {    u32 __val = tr32(REG); \
6682         (PSTAT)->low += __val; \
6683         if ((PSTAT)->low < __val) \
6684                 (PSTAT)->high += 1; \
6685 } while (0)
6686
6687 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6688 {
6689         struct tg3_hw_stats *sp = tp->hw_stats;
6690
6691         if (!netif_carrier_ok(tp->dev))
6692                 return;
6693
6694         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6695         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6696         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6697         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6698         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6699         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6700         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6701         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6702         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6703         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6704         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6705         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6706         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6707
6708         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6709         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6710         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6711         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6712         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6713         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6714         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6715         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6716         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6717         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6718         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6719         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6720         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6721         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6722
6723         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6724         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6725         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6726 }
6727
6728 static void tg3_timer(unsigned long __opaque)
6729 {
6730         struct tg3 *tp = (struct tg3 *) __opaque;
6731
6732         if (tp->irq_sync)
6733                 goto restart_timer;
6734
6735         spin_lock(&tp->lock);
6736
6737         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6738                 /* All of this garbage is because when using non-tagged
6739                  * IRQ status the mailbox/status_block protocol the chip
6740                  * uses with the cpu is race prone.
6741                  */
6742                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6743                         tw32(GRC_LOCAL_CTRL,
6744                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6745                 } else {
6746                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6747                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6748                 }
6749
6750                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6751                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6752                         spin_unlock(&tp->lock);
6753                         schedule_work(&tp->reset_task);
6754                         return;
6755                 }
6756         }
6757
6758         /* This part only runs once per second. */
6759         if (!--tp->timer_counter) {
6760                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6761                         tg3_periodic_fetch_stats(tp);
6762
6763                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6764                         u32 mac_stat;
6765                         int phy_event;
6766
6767                         mac_stat = tr32(MAC_STATUS);
6768
6769                         phy_event = 0;
6770                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6771                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6772                                         phy_event = 1;
6773                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6774                                 phy_event = 1;
6775
6776                         if (phy_event)
6777                                 tg3_setup_phy(tp, 0);
6778                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6779                         u32 mac_stat = tr32(MAC_STATUS);
6780                         int need_setup = 0;
6781
6782                         if (netif_carrier_ok(tp->dev) &&
6783                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6784                                 need_setup = 1;
6785                         }
6786                         if (! netif_carrier_ok(tp->dev) &&
6787                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6788                                          MAC_STATUS_SIGNAL_DET))) {
6789                                 need_setup = 1;
6790                         }
6791                         if (need_setup) {
6792                                 if (!tp->serdes_counter) {
6793                                         tw32_f(MAC_MODE,
6794                                              (tp->mac_mode &
6795                                               ~MAC_MODE_PORT_MODE_MASK));
6796                                         udelay(40);
6797                                         tw32_f(MAC_MODE, tp->mac_mode);
6798                                         udelay(40);
6799                                 }
6800                                 tg3_setup_phy(tp, 0);
6801                         }
6802                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6803                         tg3_serdes_parallel_detect(tp);
6804
6805                 tp->timer_counter = tp->timer_multiplier;
6806         }
6807
6808         /* Heartbeat is only sent once every 2 seconds.
6809          *
6810          * The heartbeat is to tell the ASF firmware that the host
6811          * driver is still alive.  In the event that the OS crashes,
6812          * ASF needs to reset the hardware to free up the FIFO space
6813          * that may be filled with rx packets destined for the host.
6814          * If the FIFO is full, ASF will no longer function properly.
6815          *
6816          * Unintended resets have been reported on real time kernels
6817          * where the timer doesn't run on time.  Netpoll will also have
6818          * same problem.
6819          *
6820          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6821          * to check the ring condition when the heartbeat is expiring
6822          * before doing the reset.  This will prevent most unintended
6823          * resets.
6824          */
6825         if (!--tp->asf_counter) {
6826                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6827                         u32 val;
6828
6829                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6830                                       FWCMD_NICDRV_ALIVE3);
6831                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6832                         /* 5 seconds timeout */
6833                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6834                         val = tr32(GRC_RX_CPU_EVENT);
6835                         val |= (1 << 14);
6836                         tw32(GRC_RX_CPU_EVENT, val);
6837                 }
6838                 tp->asf_counter = tp->asf_multiplier;
6839         }
6840
6841         spin_unlock(&tp->lock);
6842
6843 restart_timer:
6844         tp->timer.expires = jiffies + tp->timer_offset;
6845         add_timer(&tp->timer);
6846 }
6847
6848 static int tg3_request_irq(struct tg3 *tp)
6849 {
6850         irq_handler_t fn;
6851         unsigned long flags;
6852         struct net_device *dev = tp->dev;
6853
6854         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6855                 fn = tg3_msi;
6856                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6857                         fn = tg3_msi_1shot;
6858                 flags = IRQF_SAMPLE_RANDOM;
6859         } else {
6860                 fn = tg3_interrupt;
6861                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6862                         fn = tg3_interrupt_tagged;
6863                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6864         }
6865         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6866 }
6867
6868 static int tg3_test_interrupt(struct tg3 *tp)
6869 {
6870         struct net_device *dev = tp->dev;
6871         int err, i, intr_ok = 0;
6872
6873         if (!netif_running(dev))
6874                 return -ENODEV;
6875
6876         tg3_disable_ints(tp);
6877
6878         free_irq(tp->pdev->irq, dev);
6879
6880         err = request_irq(tp->pdev->irq, tg3_test_isr,
6881                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6882         if (err)
6883                 return err;
6884
6885         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6886         tg3_enable_ints(tp);
6887
6888         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6889                HOSTCC_MODE_NOW);
6890
6891         for (i = 0; i < 5; i++) {
6892                 u32 int_mbox, misc_host_ctrl;
6893
6894                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6895                                         TG3_64BIT_REG_LOW);
6896                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6897
6898                 if ((int_mbox != 0) ||
6899                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6900                         intr_ok = 1;
6901                         break;
6902                 }
6903
6904                 msleep(10);
6905         }
6906
6907         tg3_disable_ints(tp);
6908
6909         free_irq(tp->pdev->irq, dev);
6910
6911         err = tg3_request_irq(tp);
6912
6913         if (err)
6914                 return err;
6915
6916         if (intr_ok)
6917                 return 0;
6918
6919         return -EIO;
6920 }
6921
6922 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6923  * successfully restored
6924  */
6925 static int tg3_test_msi(struct tg3 *tp)
6926 {
6927         struct net_device *dev = tp->dev;
6928         int err;
6929         u16 pci_cmd;
6930
6931         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6932                 return 0;
6933
6934         /* Turn off SERR reporting in case MSI terminates with Master
6935          * Abort.
6936          */
6937         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6938         pci_write_config_word(tp->pdev, PCI_COMMAND,
6939                               pci_cmd & ~PCI_COMMAND_SERR);
6940
6941         err = tg3_test_interrupt(tp);
6942
6943         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6944
6945         if (!err)
6946                 return 0;
6947
6948         /* other failures */
6949         if (err != -EIO)
6950                 return err;
6951
6952         /* MSI test failed, go back to INTx mode */
6953         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6954                "switching to INTx mode. Please report this failure to "
6955                "the PCI maintainer and include system chipset information.\n",
6956                        tp->dev->name);
6957
6958         free_irq(tp->pdev->irq, dev);
6959         pci_disable_msi(tp->pdev);
6960
6961         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6962
6963         err = tg3_request_irq(tp);
6964         if (err)
6965                 return err;
6966
6967         /* Need to reset the chip because the MSI cycle may have terminated
6968          * with Master Abort.
6969          */
6970         tg3_full_lock(tp, 1);
6971
6972         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6973         err = tg3_init_hw(tp, 1);
6974
6975         tg3_full_unlock(tp);
6976
6977         if (err)
6978                 free_irq(tp->pdev->irq, dev);
6979
6980         return err;
6981 }
6982
6983 static int tg3_open(struct net_device *dev)
6984 {
6985         struct tg3 *tp = netdev_priv(dev);
6986         int err;
6987
6988         tg3_full_lock(tp, 0);
6989
6990         err = tg3_set_power_state(tp, PCI_D0);
6991         if (err) {
6992                 tg3_full_unlock(tp);
6993                 return err;
6994         }
6995
6996         tg3_disable_ints(tp);
6997         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
6998
6999         tg3_full_unlock(tp);
7000
7001         /* The placement of this call is tied
7002          * to the setup and use of Host TX descriptors.
7003          */
7004         err = tg3_alloc_consistent(tp);
7005         if (err)
7006                 return err;
7007
7008         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7009             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7010             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7011             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7012               (tp->pdev_peer == tp->pdev))) {
7013                 /* All MSI supporting chips should support tagged
7014                  * status.  Assert that this is the case.
7015                  */
7016                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7017                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7018                                "Not using MSI.\n", tp->dev->name);
7019                 } else if (pci_enable_msi(tp->pdev) == 0) {
7020                         u32 msi_mode;
7021
7022                         msi_mode = tr32(MSGINT_MODE);
7023                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7024                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7025                 }
7026         }
7027         err = tg3_request_irq(tp);
7028
7029         if (err) {
7030                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7031                         pci_disable_msi(tp->pdev);
7032                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7033                 }
7034                 tg3_free_consistent(tp);
7035                 return err;
7036         }
7037
7038         tg3_full_lock(tp, 0);
7039
7040         err = tg3_init_hw(tp, 1);
7041         if (err) {
7042                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7043                 tg3_free_rings(tp);
7044         } else {
7045                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7046                         tp->timer_offset = HZ;
7047                 else
7048                         tp->timer_offset = HZ / 10;
7049
7050                 BUG_ON(tp->timer_offset > HZ);
7051                 tp->timer_counter = tp->timer_multiplier =
7052                         (HZ / tp->timer_offset);
7053                 tp->asf_counter = tp->asf_multiplier =
7054                         ((HZ / tp->timer_offset) * 2);
7055
7056                 init_timer(&tp->timer);
7057                 tp->timer.expires = jiffies + tp->timer_offset;
7058                 tp->timer.data = (unsigned long) tp;
7059                 tp->timer.function = tg3_timer;
7060         }
7061
7062         tg3_full_unlock(tp);
7063
7064         if (err) {
7065                 free_irq(tp->pdev->irq, dev);
7066                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7067                         pci_disable_msi(tp->pdev);
7068                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7069                 }
7070                 tg3_free_consistent(tp);
7071                 return err;
7072         }
7073
7074         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7075                 err = tg3_test_msi(tp);
7076
7077                 if (err) {
7078                         tg3_full_lock(tp, 0);
7079
7080                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7081                                 pci_disable_msi(tp->pdev);
7082                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7083                         }
7084                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7085                         tg3_free_rings(tp);
7086                         tg3_free_consistent(tp);
7087
7088                         tg3_full_unlock(tp);
7089
7090                         return err;
7091                 }
7092
7093                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7094                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7095                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7096
7097                                 tw32(PCIE_TRANSACTION_CFG,
7098                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7099                         }
7100                 }
7101         }
7102
7103         tg3_full_lock(tp, 0);
7104
7105         add_timer(&tp->timer);
7106         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7107         tg3_enable_ints(tp);
7108
7109         tg3_full_unlock(tp);
7110
7111         netif_start_queue(dev);
7112
7113         return 0;
7114 }
7115
7116 #if 0
7117 /*static*/ void tg3_dump_state(struct tg3 *tp)
7118 {
7119         u32 val32, val32_2, val32_3, val32_4, val32_5;
7120         u16 val16;
7121         int i;
7122
7123         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7124         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7125         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7126                val16, val32);
7127
7128         /* MAC block */
7129         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7130                tr32(MAC_MODE), tr32(MAC_STATUS));
7131         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7132                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7133         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7134                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7135         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7136                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7137
7138         /* Send data initiator control block */
7139         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7140                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7141         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7142                tr32(SNDDATAI_STATSCTRL));
7143
7144         /* Send data completion control block */
7145         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7146
7147         /* Send BD ring selector block */
7148         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7149                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7150
7151         /* Send BD initiator control block */
7152         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7153                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7154
7155         /* Send BD completion control block */
7156         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7157
7158         /* Receive list placement control block */
7159         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7160                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7161         printk("       RCVLPC_STATSCTRL[%08x]\n",
7162                tr32(RCVLPC_STATSCTRL));
7163
7164         /* Receive data and receive BD initiator control block */
7165         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7166                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7167
7168         /* Receive data completion control block */
7169         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7170                tr32(RCVDCC_MODE));
7171
7172         /* Receive BD initiator control block */
7173         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7174                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7175
7176         /* Receive BD completion control block */
7177         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7178                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7179
7180         /* Receive list selector control block */
7181         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7182                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7183
7184         /* Mbuf cluster free block */
7185         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7186                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7187
7188         /* Host coalescing control block */
7189         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7190                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7191         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7192                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7193                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7194         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7195                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7196                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7197         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7198                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7199         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7200                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7201
7202         /* Memory arbiter control block */
7203         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7204                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7205
7206         /* Buffer manager control block */
7207         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7208                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7209         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7210                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7211         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7212                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7213                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7214                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7215
7216         /* Read DMA control block */
7217         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7218                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7219
7220         /* Write DMA control block */
7221         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7222                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7223
7224         /* DMA completion block */
7225         printk("DEBUG: DMAC_MODE[%08x]\n",
7226                tr32(DMAC_MODE));
7227
7228         /* GRC block */
7229         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7230                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7231         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7232                tr32(GRC_LOCAL_CTRL));
7233
7234         /* TG3_BDINFOs */
7235         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7236                tr32(RCVDBDI_JUMBO_BD + 0x0),
7237                tr32(RCVDBDI_JUMBO_BD + 0x4),
7238                tr32(RCVDBDI_JUMBO_BD + 0x8),
7239                tr32(RCVDBDI_JUMBO_BD + 0xc));
7240         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7241                tr32(RCVDBDI_STD_BD + 0x0),
7242                tr32(RCVDBDI_STD_BD + 0x4),
7243                tr32(RCVDBDI_STD_BD + 0x8),
7244                tr32(RCVDBDI_STD_BD + 0xc));
7245         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7246                tr32(RCVDBDI_MINI_BD + 0x0),
7247                tr32(RCVDBDI_MINI_BD + 0x4),
7248                tr32(RCVDBDI_MINI_BD + 0x8),
7249                tr32(RCVDBDI_MINI_BD + 0xc));
7250
7251         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7252         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7253         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7254         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7255         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7256                val32, val32_2, val32_3, val32_4);
7257
7258         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7259         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7260         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7261         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7262         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7263                val32, val32_2, val32_3, val32_4);
7264
7265         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7266         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7267         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7268         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7269         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7270         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7271                val32, val32_2, val32_3, val32_4, val32_5);
7272
7273         /* SW status block */
7274         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7275                tp->hw_status->status,
7276                tp->hw_status->status_tag,
7277                tp->hw_status->rx_jumbo_consumer,
7278                tp->hw_status->rx_consumer,
7279                tp->hw_status->rx_mini_consumer,
7280                tp->hw_status->idx[0].rx_producer,
7281                tp->hw_status->idx[0].tx_consumer);
7282
7283         /* SW statistics block */
7284         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7285                ((u32 *)tp->hw_stats)[0],
7286                ((u32 *)tp->hw_stats)[1],
7287                ((u32 *)tp->hw_stats)[2],
7288                ((u32 *)tp->hw_stats)[3]);
7289
7290         /* Mailboxes */
7291         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7292                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7293                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7294                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7295                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7296
7297         /* NIC side send descriptors. */
7298         for (i = 0; i < 6; i++) {
7299                 unsigned long txd;
7300
7301                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7302                         + (i * sizeof(struct tg3_tx_buffer_desc));
7303                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7304                        i,
7305                        readl(txd + 0x0), readl(txd + 0x4),
7306                        readl(txd + 0x8), readl(txd + 0xc));
7307         }
7308
7309         /* NIC side RX descriptors. */
7310         for (i = 0; i < 6; i++) {
7311                 unsigned long rxd;
7312
7313                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7314                         + (i * sizeof(struct tg3_rx_buffer_desc));
7315                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7316                        i,
7317                        readl(rxd + 0x0), readl(rxd + 0x4),
7318                        readl(rxd + 0x8), readl(rxd + 0xc));
7319                 rxd += (4 * sizeof(u32));
7320                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7321                        i,
7322                        readl(rxd + 0x0), readl(rxd + 0x4),
7323                        readl(rxd + 0x8), readl(rxd + 0xc));
7324         }
7325
7326         for (i = 0; i < 6; i++) {
7327                 unsigned long rxd;
7328
7329                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7330                         + (i * sizeof(struct tg3_rx_buffer_desc));
7331                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7332                        i,
7333                        readl(rxd + 0x0), readl(rxd + 0x4),
7334                        readl(rxd + 0x8), readl(rxd + 0xc));
7335                 rxd += (4 * sizeof(u32));
7336                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7337                        i,
7338                        readl(rxd + 0x0), readl(rxd + 0x4),
7339                        readl(rxd + 0x8), readl(rxd + 0xc));
7340         }
7341 }
7342 #endif
7343
7344 static struct net_device_stats *tg3_get_stats(struct net_device *);
7345 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7346
7347 static int tg3_close(struct net_device *dev)
7348 {
7349         struct tg3 *tp = netdev_priv(dev);
7350
7351         /* Calling flush_scheduled_work() may deadlock because
7352          * linkwatch_event() may be on the workqueue and it will try to get
7353          * the rtnl_lock which we are holding.
7354          */
7355         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7356                 msleep(1);
7357
7358         netif_stop_queue(dev);
7359
7360         del_timer_sync(&tp->timer);
7361
7362         tg3_full_lock(tp, 1);
7363 #if 0
7364         tg3_dump_state(tp);
7365 #endif
7366
7367         tg3_disable_ints(tp);
7368
7369         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7370         tg3_free_rings(tp);
7371         tp->tg3_flags &=
7372                 ~(TG3_FLAG_INIT_COMPLETE |
7373                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7374
7375         tg3_full_unlock(tp);
7376
7377         free_irq(tp->pdev->irq, dev);
7378         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7379                 pci_disable_msi(tp->pdev);
7380                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7381         }
7382
7383         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7384                sizeof(tp->net_stats_prev));
7385         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7386                sizeof(tp->estats_prev));
7387
7388         tg3_free_consistent(tp);
7389
7390         tg3_set_power_state(tp, PCI_D3hot);
7391
7392         netif_carrier_off(tp->dev);
7393
7394         return 0;
7395 }
7396
7397 static inline unsigned long get_stat64(tg3_stat64_t *val)
7398 {
7399         unsigned long ret;
7400
7401 #if (BITS_PER_LONG == 32)
7402         ret = val->low;
7403 #else
7404         ret = ((u64)val->high << 32) | ((u64)val->low);
7405 #endif
7406         return ret;
7407 }
7408
7409 static unsigned long calc_crc_errors(struct tg3 *tp)
7410 {
7411         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7412
7413         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7414             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7415              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7416                 u32 val;
7417
7418                 spin_lock_bh(&tp->lock);
7419                 if (!tg3_readphy(tp, 0x1e, &val)) {
7420                         tg3_writephy(tp, 0x1e, val | 0x8000);
7421                         tg3_readphy(tp, 0x14, &val);
7422                 } else
7423                         val = 0;
7424                 spin_unlock_bh(&tp->lock);
7425
7426                 tp->phy_crc_errors += val;
7427
7428                 return tp->phy_crc_errors;
7429         }
7430
7431         return get_stat64(&hw_stats->rx_fcs_errors);
7432 }
7433
7434 #define ESTAT_ADD(member) \
7435         estats->member =        old_estats->member + \
7436                                 get_stat64(&hw_stats->member)
7437
7438 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7439 {
7440         struct tg3_ethtool_stats *estats = &tp->estats;
7441         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7442         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7443
7444         if (!hw_stats)
7445                 return old_estats;
7446
7447         ESTAT_ADD(rx_octets);
7448         ESTAT_ADD(rx_fragments);
7449         ESTAT_ADD(rx_ucast_packets);
7450         ESTAT_ADD(rx_mcast_packets);
7451         ESTAT_ADD(rx_bcast_packets);
7452         ESTAT_ADD(rx_fcs_errors);
7453         ESTAT_ADD(rx_align_errors);
7454         ESTAT_ADD(rx_xon_pause_rcvd);
7455         ESTAT_ADD(rx_xoff_pause_rcvd);
7456         ESTAT_ADD(rx_mac_ctrl_rcvd);
7457         ESTAT_ADD(rx_xoff_entered);
7458         ESTAT_ADD(rx_frame_too_long_errors);
7459         ESTAT_ADD(rx_jabbers);
7460         ESTAT_ADD(rx_undersize_packets);
7461         ESTAT_ADD(rx_in_length_errors);
7462         ESTAT_ADD(rx_out_length_errors);
7463         ESTAT_ADD(rx_64_or_less_octet_packets);
7464         ESTAT_ADD(rx_65_to_127_octet_packets);
7465         ESTAT_ADD(rx_128_to_255_octet_packets);
7466         ESTAT_ADD(rx_256_to_511_octet_packets);
7467         ESTAT_ADD(rx_512_to_1023_octet_packets);
7468         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7469         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7470         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7471         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7472         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7473
7474         ESTAT_ADD(tx_octets);
7475         ESTAT_ADD(tx_collisions);
7476         ESTAT_ADD(tx_xon_sent);
7477         ESTAT_ADD(tx_xoff_sent);
7478         ESTAT_ADD(tx_flow_control);
7479         ESTAT_ADD(tx_mac_errors);
7480         ESTAT_ADD(tx_single_collisions);
7481         ESTAT_ADD(tx_mult_collisions);
7482         ESTAT_ADD(tx_deferred);
7483         ESTAT_ADD(tx_excessive_collisions);
7484         ESTAT_ADD(tx_late_collisions);
7485         ESTAT_ADD(tx_collide_2times);
7486         ESTAT_ADD(tx_collide_3times);
7487         ESTAT_ADD(tx_collide_4times);
7488         ESTAT_ADD(tx_collide_5times);
7489         ESTAT_ADD(tx_collide_6times);
7490         ESTAT_ADD(tx_collide_7times);
7491         ESTAT_ADD(tx_collide_8times);
7492         ESTAT_ADD(tx_collide_9times);
7493         ESTAT_ADD(tx_collide_10times);
7494         ESTAT_ADD(tx_collide_11times);
7495         ESTAT_ADD(tx_collide_12times);
7496         ESTAT_ADD(tx_collide_13times);
7497         ESTAT_ADD(tx_collide_14times);
7498         ESTAT_ADD(tx_collide_15times);
7499         ESTAT_ADD(tx_ucast_packets);
7500         ESTAT_ADD(tx_mcast_packets);
7501         ESTAT_ADD(tx_bcast_packets);
7502         ESTAT_ADD(tx_carrier_sense_errors);
7503         ESTAT_ADD(tx_discards);
7504         ESTAT_ADD(tx_errors);
7505
7506         ESTAT_ADD(dma_writeq_full);
7507         ESTAT_ADD(dma_write_prioq_full);
7508         ESTAT_ADD(rxbds_empty);
7509         ESTAT_ADD(rx_discards);
7510         ESTAT_ADD(rx_errors);
7511         ESTAT_ADD(rx_threshold_hit);
7512
7513         ESTAT_ADD(dma_readq_full);
7514         ESTAT_ADD(dma_read_prioq_full);
7515         ESTAT_ADD(tx_comp_queue_full);
7516
7517         ESTAT_ADD(ring_set_send_prod_index);
7518         ESTAT_ADD(ring_status_update);
7519         ESTAT_ADD(nic_irqs);
7520         ESTAT_ADD(nic_avoided_irqs);
7521         ESTAT_ADD(nic_tx_threshold_hit);
7522
7523         return estats;
7524 }
7525
7526 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7527 {
7528         struct tg3 *tp = netdev_priv(dev);
7529         struct net_device_stats *stats = &tp->net_stats;
7530         struct net_device_stats *old_stats = &tp->net_stats_prev;
7531         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7532
7533         if (!hw_stats)
7534                 return old_stats;
7535
7536         stats->rx_packets = old_stats->rx_packets +
7537                 get_stat64(&hw_stats->rx_ucast_packets) +
7538                 get_stat64(&hw_stats->rx_mcast_packets) +
7539                 get_stat64(&hw_stats->rx_bcast_packets);
7540
7541         stats->tx_packets = old_stats->tx_packets +
7542                 get_stat64(&hw_stats->tx_ucast_packets) +
7543                 get_stat64(&hw_stats->tx_mcast_packets) +
7544                 get_stat64(&hw_stats->tx_bcast_packets);
7545
7546         stats->rx_bytes = old_stats->rx_bytes +
7547                 get_stat64(&hw_stats->rx_octets);
7548         stats->tx_bytes = old_stats->tx_bytes +
7549                 get_stat64(&hw_stats->tx_octets);
7550
7551         stats->rx_errors = old_stats->rx_errors +
7552                 get_stat64(&hw_stats->rx_errors);
7553         stats->tx_errors = old_stats->tx_errors +
7554                 get_stat64(&hw_stats->tx_errors) +
7555                 get_stat64(&hw_stats->tx_mac_errors) +
7556                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7557                 get_stat64(&hw_stats->tx_discards);
7558
7559         stats->multicast = old_stats->multicast +
7560                 get_stat64(&hw_stats->rx_mcast_packets);
7561         stats->collisions = old_stats->collisions +
7562                 get_stat64(&hw_stats->tx_collisions);
7563
7564         stats->rx_length_errors = old_stats->rx_length_errors +
7565                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7566                 get_stat64(&hw_stats->rx_undersize_packets);
7567
7568         stats->rx_over_errors = old_stats->rx_over_errors +
7569                 get_stat64(&hw_stats->rxbds_empty);
7570         stats->rx_frame_errors = old_stats->rx_frame_errors +
7571                 get_stat64(&hw_stats->rx_align_errors);
7572         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7573                 get_stat64(&hw_stats->tx_discards);
7574         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7575                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7576
7577         stats->rx_crc_errors = old_stats->rx_crc_errors +
7578                 calc_crc_errors(tp);
7579
7580         stats->rx_missed_errors = old_stats->rx_missed_errors +
7581                 get_stat64(&hw_stats->rx_discards);
7582
7583         return stats;
7584 }
7585
7586 static inline u32 calc_crc(unsigned char *buf, int len)
7587 {
7588         u32 reg;
7589         u32 tmp;
7590         int j, k;
7591
7592         reg = 0xffffffff;
7593
7594         for (j = 0; j < len; j++) {
7595                 reg ^= buf[j];
7596
7597                 for (k = 0; k < 8; k++) {
7598                         tmp = reg & 0x01;
7599
7600                         reg >>= 1;
7601
7602                         if (tmp) {
7603                                 reg ^= 0xedb88320;
7604                         }
7605                 }
7606         }
7607
7608         return ~reg;
7609 }
7610
7611 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7612 {
7613         /* accept or reject all multicast frames */
7614         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7615         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7616         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7617         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7618 }
7619
7620 static void __tg3_set_rx_mode(struct net_device *dev)
7621 {
7622         struct tg3 *tp = netdev_priv(dev);
7623         u32 rx_mode;
7624
7625         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7626                                   RX_MODE_KEEP_VLAN_TAG);
7627
7628         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7629          * flag clear.
7630          */
7631 #if TG3_VLAN_TAG_USED
7632         if (!tp->vlgrp &&
7633             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7634                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7635 #else
7636         /* By definition, VLAN is disabled always in this
7637          * case.
7638          */
7639         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7640                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7641 #endif
7642
7643         if (dev->flags & IFF_PROMISC) {
7644                 /* Promiscuous mode. */
7645                 rx_mode |= RX_MODE_PROMISC;
7646         } else if (dev->flags & IFF_ALLMULTI) {
7647                 /* Accept all multicast. */
7648                 tg3_set_multi (tp, 1);
7649         } else if (dev->mc_count < 1) {
7650                 /* Reject all multicast. */
7651                 tg3_set_multi (tp, 0);
7652         } else {
7653                 /* Accept one or more multicast(s). */
7654                 struct dev_mc_list *mclist;
7655                 unsigned int i;
7656                 u32 mc_filter[4] = { 0, };
7657                 u32 regidx;
7658                 u32 bit;
7659                 u32 crc;
7660
7661                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7662                      i++, mclist = mclist->next) {
7663
7664                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7665                         bit = ~crc & 0x7f;
7666                         regidx = (bit & 0x60) >> 5;
7667                         bit &= 0x1f;
7668                         mc_filter[regidx] |= (1 << bit);
7669                 }
7670
7671                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7672                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7673                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7674                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7675         }
7676
7677         if (rx_mode != tp->rx_mode) {
7678                 tp->rx_mode = rx_mode;
7679                 tw32_f(MAC_RX_MODE, rx_mode);
7680                 udelay(10);
7681         }
7682 }
7683
7684 static void tg3_set_rx_mode(struct net_device *dev)
7685 {
7686         struct tg3 *tp = netdev_priv(dev);
7687
7688         if (!netif_running(dev))
7689                 return;
7690
7691         tg3_full_lock(tp, 0);
7692         __tg3_set_rx_mode(dev);
7693         tg3_full_unlock(tp);
7694 }
7695
7696 #define TG3_REGDUMP_LEN         (32 * 1024)
7697
7698 static int tg3_get_regs_len(struct net_device *dev)
7699 {
7700         return TG3_REGDUMP_LEN;
7701 }
7702
7703 static void tg3_get_regs(struct net_device *dev,
7704                 struct ethtool_regs *regs, void *_p)
7705 {
7706         u32 *p = _p;
7707         struct tg3 *tp = netdev_priv(dev);
7708         u8 *orig_p = _p;
7709         int i;
7710
7711         regs->version = 0;
7712
7713         memset(p, 0, TG3_REGDUMP_LEN);
7714
7715         if (tp->link_config.phy_is_low_power)
7716                 return;
7717
7718         tg3_full_lock(tp, 0);
7719
7720 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7721 #define GET_REG32_LOOP(base,len)                \
7722 do {    p = (u32 *)(orig_p + (base));           \
7723         for (i = 0; i < len; i += 4)            \
7724                 __GET_REG32((base) + i);        \
7725 } while (0)
7726 #define GET_REG32_1(reg)                        \
7727 do {    p = (u32 *)(orig_p + (reg));            \
7728         __GET_REG32((reg));                     \
7729 } while (0)
7730
7731         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7732         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7733         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7734         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7735         GET_REG32_1(SNDDATAC_MODE);
7736         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7737         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7738         GET_REG32_1(SNDBDC_MODE);
7739         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7740         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7741         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7742         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7743         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7744         GET_REG32_1(RCVDCC_MODE);
7745         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7746         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7747         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7748         GET_REG32_1(MBFREE_MODE);
7749         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7750         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7751         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7752         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7753         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7754         GET_REG32_1(RX_CPU_MODE);
7755         GET_REG32_1(RX_CPU_STATE);
7756         GET_REG32_1(RX_CPU_PGMCTR);
7757         GET_REG32_1(RX_CPU_HWBKPT);
7758         GET_REG32_1(TX_CPU_MODE);
7759         GET_REG32_1(TX_CPU_STATE);
7760         GET_REG32_1(TX_CPU_PGMCTR);
7761         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7762         GET_REG32_LOOP(FTQ_RESET, 0x120);
7763         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7764         GET_REG32_1(DMAC_MODE);
7765         GET_REG32_LOOP(GRC_MODE, 0x4c);
7766         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7767                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7768
7769 #undef __GET_REG32
7770 #undef GET_REG32_LOOP
7771 #undef GET_REG32_1
7772
7773         tg3_full_unlock(tp);
7774 }
7775
7776 static int tg3_get_eeprom_len(struct net_device *dev)
7777 {
7778         struct tg3 *tp = netdev_priv(dev);
7779
7780         return tp->nvram_size;
7781 }
7782
7783 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7784 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7785
7786 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7787 {
7788         struct tg3 *tp = netdev_priv(dev);
7789         int ret;
7790         u8  *pd;
7791         u32 i, offset, len, val, b_offset, b_count;
7792
7793         if (tp->link_config.phy_is_low_power)
7794                 return -EAGAIN;
7795
7796         offset = eeprom->offset;
7797         len = eeprom->len;
7798         eeprom->len = 0;
7799
7800         eeprom->magic = TG3_EEPROM_MAGIC;
7801
7802         if (offset & 3) {
7803                 /* adjustments to start on required 4 byte boundary */
7804                 b_offset = offset & 3;
7805                 b_count = 4 - b_offset;
7806                 if (b_count > len) {
7807                         /* i.e. offset=1 len=2 */
7808                         b_count = len;
7809                 }
7810                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7811                 if (ret)
7812                         return ret;
7813                 val = cpu_to_le32(val);
7814                 memcpy(data, ((char*)&val) + b_offset, b_count);
7815                 len -= b_count;
7816                 offset += b_count;
7817                 eeprom->len += b_count;
7818         }
7819
7820         /* read bytes upto the last 4 byte boundary */
7821         pd = &data[eeprom->len];
7822         for (i = 0; i < (len - (len & 3)); i += 4) {
7823                 ret = tg3_nvram_read(tp, offset + i, &val);
7824                 if (ret) {
7825                         eeprom->len += i;
7826                         return ret;
7827                 }
7828                 val = cpu_to_le32(val);
7829                 memcpy(pd + i, &val, 4);
7830         }
7831         eeprom->len += i;
7832
7833         if (len & 3) {
7834                 /* read last bytes not ending on 4 byte boundary */
7835                 pd = &data[eeprom->len];
7836                 b_count = len & 3;
7837                 b_offset = offset + len - b_count;
7838                 ret = tg3_nvram_read(tp, b_offset, &val);
7839                 if (ret)
7840                         return ret;
7841                 val = cpu_to_le32(val);
7842                 memcpy(pd, ((char*)&val), b_count);
7843                 eeprom->len += b_count;
7844         }
7845         return 0;
7846 }
7847
7848 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7849
7850 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7851 {
7852         struct tg3 *tp = netdev_priv(dev);
7853         int ret;
7854         u32 offset, len, b_offset, odd_len, start, end;
7855         u8 *buf;
7856
7857         if (tp->link_config.phy_is_low_power)
7858                 return -EAGAIN;
7859
7860         if (eeprom->magic != TG3_EEPROM_MAGIC)
7861                 return -EINVAL;
7862
7863         offset = eeprom->offset;
7864         len = eeprom->len;
7865
7866         if ((b_offset = (offset & 3))) {
7867                 /* adjustments to start on required 4 byte boundary */
7868                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7869                 if (ret)
7870                         return ret;
7871                 start = cpu_to_le32(start);
7872                 len += b_offset;
7873                 offset &= ~3;
7874                 if (len < 4)
7875                         len = 4;
7876         }
7877
7878         odd_len = 0;
7879         if (len & 3) {
7880                 /* adjustments to end on required 4 byte boundary */
7881                 odd_len = 1;
7882                 len = (len + 3) & ~3;
7883                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7884                 if (ret)
7885                         return ret;
7886                 end = cpu_to_le32(end);
7887         }
7888
7889         buf = data;
7890         if (b_offset || odd_len) {
7891                 buf = kmalloc(len, GFP_KERNEL);
7892                 if (buf == 0)
7893                         return -ENOMEM;
7894                 if (b_offset)
7895                         memcpy(buf, &start, 4);
7896                 if (odd_len)
7897                         memcpy(buf+len-4, &end, 4);
7898                 memcpy(buf + b_offset, data, eeprom->len);
7899         }
7900
7901         ret = tg3_nvram_write_block(tp, offset, len, buf);
7902
7903         if (buf != data)
7904                 kfree(buf);
7905
7906         return ret;
7907 }
7908
7909 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7910 {
7911         struct tg3 *tp = netdev_priv(dev);
7912
7913         cmd->supported = (SUPPORTED_Autoneg);
7914
7915         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7916                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7917                                    SUPPORTED_1000baseT_Full);
7918
7919         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7920                 cmd->supported |= (SUPPORTED_100baseT_Half |
7921                                   SUPPORTED_100baseT_Full |
7922                                   SUPPORTED_10baseT_Half |
7923                                   SUPPORTED_10baseT_Full |
7924                                   SUPPORTED_MII);
7925                 cmd->port = PORT_TP;
7926         } else {
7927                 cmd->supported |= SUPPORTED_FIBRE;
7928                 cmd->port = PORT_FIBRE;
7929         }
7930
7931         cmd->advertising = tp->link_config.advertising;
7932         if (netif_running(dev)) {
7933                 cmd->speed = tp->link_config.active_speed;
7934                 cmd->duplex = tp->link_config.active_duplex;
7935         }
7936         cmd->phy_address = PHY_ADDR;
7937         cmd->transceiver = 0;
7938         cmd->autoneg = tp->link_config.autoneg;
7939         cmd->maxtxpkt = 0;
7940         cmd->maxrxpkt = 0;
7941         return 0;
7942 }
7943
7944 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7945 {
7946         struct tg3 *tp = netdev_priv(dev);
7947
7948         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7949                 /* These are the only valid advertisement bits allowed.  */
7950                 if (cmd->autoneg == AUTONEG_ENABLE &&
7951                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7952                                           ADVERTISED_1000baseT_Full |
7953                                           ADVERTISED_Autoneg |
7954                                           ADVERTISED_FIBRE)))
7955                         return -EINVAL;
7956                 /* Fiber can only do SPEED_1000.  */
7957                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7958                          (cmd->speed != SPEED_1000))
7959                         return -EINVAL;
7960         /* Copper cannot force SPEED_1000.  */
7961         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7962                    (cmd->speed == SPEED_1000))
7963                 return -EINVAL;
7964         else if ((cmd->speed == SPEED_1000) &&
7965                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7966                 return -EINVAL;
7967
7968         tg3_full_lock(tp, 0);
7969
7970         tp->link_config.autoneg = cmd->autoneg;
7971         if (cmd->autoneg == AUTONEG_ENABLE) {
7972                 tp->link_config.advertising = cmd->advertising;
7973                 tp->link_config.speed = SPEED_INVALID;
7974                 tp->link_config.duplex = DUPLEX_INVALID;
7975         } else {
7976                 tp->link_config.advertising = 0;
7977                 tp->link_config.speed = cmd->speed;
7978                 tp->link_config.duplex = cmd->duplex;
7979         }
7980
7981         if (netif_running(dev))
7982                 tg3_setup_phy(tp, 1);
7983
7984         tg3_full_unlock(tp);
7985
7986         return 0;
7987 }
7988
7989 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
7990 {
7991         struct tg3 *tp = netdev_priv(dev);
7992
7993         strcpy(info->driver, DRV_MODULE_NAME);
7994         strcpy(info->version, DRV_MODULE_VERSION);
7995         strcpy(info->fw_version, tp->fw_ver);
7996         strcpy(info->bus_info, pci_name(tp->pdev));
7997 }
7998
7999 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8000 {
8001         struct tg3 *tp = netdev_priv(dev);
8002
8003         wol->supported = WAKE_MAGIC;
8004         wol->wolopts = 0;
8005         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8006                 wol->wolopts = WAKE_MAGIC;
8007         memset(&wol->sopass, 0, sizeof(wol->sopass));
8008 }
8009
8010 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8011 {
8012         struct tg3 *tp = netdev_priv(dev);
8013
8014         if (wol->wolopts & ~WAKE_MAGIC)
8015                 return -EINVAL;
8016         if ((wol->wolopts & WAKE_MAGIC) &&
8017             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8018             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8019                 return -EINVAL;
8020
8021         spin_lock_bh(&tp->lock);
8022         if (wol->wolopts & WAKE_MAGIC)
8023                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8024         else
8025                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8026         spin_unlock_bh(&tp->lock);
8027
8028         return 0;
8029 }
8030
8031 static u32 tg3_get_msglevel(struct net_device *dev)
8032 {
8033         struct tg3 *tp = netdev_priv(dev);
8034         return tp->msg_enable;
8035 }
8036
8037 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8038 {
8039         struct tg3 *tp = netdev_priv(dev);
8040         tp->msg_enable = value;
8041 }
8042
8043 #if TG3_TSO_SUPPORT != 0
8044 static int tg3_set_tso(struct net_device *dev, u32 value)
8045 {
8046         struct tg3 *tp = netdev_priv(dev);
8047
8048         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8049                 if (value)
8050                         return -EINVAL;
8051                 return 0;
8052         }
8053         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8054             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8055                 if (value)
8056                         dev->features |= NETIF_F_TSO6;
8057                 else
8058                         dev->features &= ~NETIF_F_TSO6;
8059         }
8060         return ethtool_op_set_tso(dev, value);
8061 }
8062 #endif
8063
8064 static int tg3_nway_reset(struct net_device *dev)
8065 {
8066         struct tg3 *tp = netdev_priv(dev);
8067         u32 bmcr;
8068         int r;
8069
8070         if (!netif_running(dev))
8071                 return -EAGAIN;
8072
8073         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8074                 return -EINVAL;
8075
8076         spin_lock_bh(&tp->lock);
8077         r = -EINVAL;
8078         tg3_readphy(tp, MII_BMCR, &bmcr);
8079         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8080             ((bmcr & BMCR_ANENABLE) ||
8081              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8082                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8083                                            BMCR_ANENABLE);
8084                 r = 0;
8085         }
8086         spin_unlock_bh(&tp->lock);
8087
8088         return r;
8089 }
8090
8091 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8092 {
8093         struct tg3 *tp = netdev_priv(dev);
8094
8095         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8096         ering->rx_mini_max_pending = 0;
8097         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8098                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8099         else
8100                 ering->rx_jumbo_max_pending = 0;
8101
8102         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8103
8104         ering->rx_pending = tp->rx_pending;
8105         ering->rx_mini_pending = 0;
8106         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8107                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8108         else
8109                 ering->rx_jumbo_pending = 0;
8110
8111         ering->tx_pending = tp->tx_pending;
8112 }
8113
8114 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8115 {
8116         struct tg3 *tp = netdev_priv(dev);
8117         int irq_sync = 0, err = 0;
8118
8119         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8120             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8121             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8122             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8123             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8124              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8125                 return -EINVAL;
8126
8127         if (netif_running(dev)) {
8128                 tg3_netif_stop(tp);
8129                 irq_sync = 1;
8130         }
8131
8132         tg3_full_lock(tp, irq_sync);
8133
8134         tp->rx_pending = ering->rx_pending;
8135
8136         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8137             tp->rx_pending > 63)
8138                 tp->rx_pending = 63;
8139         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8140         tp->tx_pending = ering->tx_pending;
8141
8142         if (netif_running(dev)) {
8143                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8144                 err = tg3_restart_hw(tp, 1);
8145                 if (!err)
8146                         tg3_netif_start(tp);
8147         }
8148
8149         tg3_full_unlock(tp);
8150
8151         return err;
8152 }
8153
8154 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8155 {
8156         struct tg3 *tp = netdev_priv(dev);
8157
8158         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8159         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8160         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8161 }
8162
8163 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8164 {
8165         struct tg3 *tp = netdev_priv(dev);
8166         int irq_sync = 0, err = 0;
8167
8168         if (netif_running(dev)) {
8169                 tg3_netif_stop(tp);
8170                 irq_sync = 1;
8171         }
8172
8173         tg3_full_lock(tp, irq_sync);
8174
8175         if (epause->autoneg)
8176                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8177         else
8178                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8179         if (epause->rx_pause)
8180                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8181         else
8182                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8183         if (epause->tx_pause)
8184                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8185         else
8186                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8187
8188         if (netif_running(dev)) {
8189                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8190                 err = tg3_restart_hw(tp, 1);
8191                 if (!err)
8192                         tg3_netif_start(tp);
8193         }
8194
8195         tg3_full_unlock(tp);
8196
8197         return err;
8198 }
8199
8200 static u32 tg3_get_rx_csum(struct net_device *dev)
8201 {
8202         struct tg3 *tp = netdev_priv(dev);
8203         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8204 }
8205
8206 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8207 {
8208         struct tg3 *tp = netdev_priv(dev);
8209
8210         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8211                 if (data != 0)
8212                         return -EINVAL;
8213                 return 0;
8214         }
8215
8216         spin_lock_bh(&tp->lock);
8217         if (data)
8218                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8219         else
8220                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8221         spin_unlock_bh(&tp->lock);
8222
8223         return 0;
8224 }
8225
8226 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8227 {
8228         struct tg3 *tp = netdev_priv(dev);
8229
8230         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8231                 if (data != 0)
8232                         return -EINVAL;
8233                 return 0;
8234         }
8235
8236         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8237             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8238                 ethtool_op_set_tx_hw_csum(dev, data);
8239         else
8240                 ethtool_op_set_tx_csum(dev, data);
8241
8242         return 0;
8243 }
8244
8245 static int tg3_get_stats_count (struct net_device *dev)
8246 {
8247         return TG3_NUM_STATS;
8248 }
8249
8250 static int tg3_get_test_count (struct net_device *dev)
8251 {
8252         return TG3_NUM_TEST;
8253 }
8254
8255 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8256 {
8257         switch (stringset) {
8258         case ETH_SS_STATS:
8259                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8260                 break;
8261         case ETH_SS_TEST:
8262                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8263                 break;
8264         default:
8265                 WARN_ON(1);     /* we need a WARN() */
8266                 break;
8267         }
8268 }
8269
8270 static int tg3_phys_id(struct net_device *dev, u32 data)
8271 {
8272         struct tg3 *tp = netdev_priv(dev);
8273         int i;
8274
8275         if (!netif_running(tp->dev))
8276                 return -EAGAIN;
8277
8278         if (data == 0)
8279                 data = 2;
8280
8281         for (i = 0; i < (data * 2); i++) {
8282                 if ((i % 2) == 0)
8283                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8284                                            LED_CTRL_1000MBPS_ON |
8285                                            LED_CTRL_100MBPS_ON |
8286                                            LED_CTRL_10MBPS_ON |
8287                                            LED_CTRL_TRAFFIC_OVERRIDE |
8288                                            LED_CTRL_TRAFFIC_BLINK |
8289                                            LED_CTRL_TRAFFIC_LED);
8290
8291                 else
8292                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8293                                            LED_CTRL_TRAFFIC_OVERRIDE);
8294
8295                 if (msleep_interruptible(500))
8296                         break;
8297         }
8298         tw32(MAC_LED_CTRL, tp->led_ctrl);
8299         return 0;
8300 }
8301
8302 static void tg3_get_ethtool_stats (struct net_device *dev,
8303                                    struct ethtool_stats *estats, u64 *tmp_stats)
8304 {
8305         struct tg3 *tp = netdev_priv(dev);
8306         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8307 }
8308
8309 #define NVRAM_TEST_SIZE 0x100
8310 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8311 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8312 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8313
8314 static int tg3_test_nvram(struct tg3 *tp)
8315 {
8316         u32 *buf, csum, magic;
8317         int i, j, err = 0, size;
8318
8319         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8320                 return -EIO;
8321
8322         if (magic == TG3_EEPROM_MAGIC)
8323                 size = NVRAM_TEST_SIZE;
8324         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8325                 if ((magic & 0xe00000) == 0x200000)
8326                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8327                 else
8328                         return 0;
8329         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8330                 size = NVRAM_SELFBOOT_HW_SIZE;
8331         else
8332                 return -EIO;
8333
8334         buf = kmalloc(size, GFP_KERNEL);
8335         if (buf == NULL)
8336                 return -ENOMEM;
8337
8338         err = -EIO;
8339         for (i = 0, j = 0; i < size; i += 4, j++) {
8340                 u32 val;
8341
8342                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8343                         break;
8344                 buf[j] = cpu_to_le32(val);
8345         }
8346         if (i < size)
8347                 goto out;
8348
8349         /* Selfboot format */
8350         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8351             TG3_EEPROM_MAGIC_FW) {
8352                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8353
8354                 for (i = 0; i < size; i++)
8355                         csum8 += buf8[i];
8356
8357                 if (csum8 == 0) {
8358                         err = 0;
8359                         goto out;
8360                 }
8361
8362                 err = -EIO;
8363                 goto out;
8364         }
8365
8366         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8367             TG3_EEPROM_MAGIC_HW) {
8368                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8369                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8370                 u8 *buf8 = (u8 *) buf;
8371                 int j, k;
8372
8373                 /* Separate the parity bits and the data bytes.  */
8374                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8375                         if ((i == 0) || (i == 8)) {
8376                                 int l;
8377                                 u8 msk;
8378
8379                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8380                                         parity[k++] = buf8[i] & msk;
8381                                 i++;
8382                         }
8383                         else if (i == 16) {
8384                                 int l;
8385                                 u8 msk;
8386
8387                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8388                                         parity[k++] = buf8[i] & msk;
8389                                 i++;
8390
8391                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8392                                         parity[k++] = buf8[i] & msk;
8393                                 i++;
8394                         }
8395                         data[j++] = buf8[i];
8396                 }
8397
8398                 err = -EIO;
8399                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8400                         u8 hw8 = hweight8(data[i]);
8401
8402                         if ((hw8 & 0x1) && parity[i])
8403                                 goto out;
8404                         else if (!(hw8 & 0x1) && !parity[i])
8405                                 goto out;
8406                 }
8407                 err = 0;
8408                 goto out;
8409         }
8410
8411         /* Bootstrap checksum at offset 0x10 */
8412         csum = calc_crc((unsigned char *) buf, 0x10);
8413         if(csum != cpu_to_le32(buf[0x10/4]))
8414                 goto out;
8415
8416         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8417         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8418         if (csum != cpu_to_le32(buf[0xfc/4]))
8419                  goto out;
8420
8421         err = 0;
8422
8423 out:
8424         kfree(buf);
8425         return err;
8426 }
8427
8428 #define TG3_SERDES_TIMEOUT_SEC  2
8429 #define TG3_COPPER_TIMEOUT_SEC  6
8430
8431 static int tg3_test_link(struct tg3 *tp)
8432 {
8433         int i, max;
8434
8435         if (!netif_running(tp->dev))
8436                 return -ENODEV;
8437
8438         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8439                 max = TG3_SERDES_TIMEOUT_SEC;
8440         else
8441                 max = TG3_COPPER_TIMEOUT_SEC;
8442
8443         for (i = 0; i < max; i++) {
8444                 if (netif_carrier_ok(tp->dev))
8445                         return 0;
8446
8447                 if (msleep_interruptible(1000))
8448                         break;
8449         }
8450
8451         return -EIO;
8452 }
8453
8454 /* Only test the commonly used registers */
8455 static int tg3_test_registers(struct tg3 *tp)
8456 {
8457         int i, is_5705, is_5750;
8458         u32 offset, read_mask, write_mask, val, save_val, read_val;
8459         static struct {
8460                 u16 offset;
8461                 u16 flags;
8462 #define TG3_FL_5705     0x1
8463 #define TG3_FL_NOT_5705 0x2
8464 #define TG3_FL_NOT_5788 0x4
8465 #define TG3_FL_NOT_5750 0x8
8466                 u32 read_mask;
8467                 u32 write_mask;
8468         } reg_tbl[] = {
8469                 /* MAC Control Registers */
8470                 { MAC_MODE, TG3_FL_NOT_5705,
8471                         0x00000000, 0x00ef6f8c },
8472                 { MAC_MODE, TG3_FL_5705,
8473                         0x00000000, 0x01ef6b8c },
8474                 { MAC_STATUS, TG3_FL_NOT_5705,
8475                         0x03800107, 0x00000000 },
8476                 { MAC_STATUS, TG3_FL_5705,
8477                         0x03800100, 0x00000000 },
8478                 { MAC_ADDR_0_HIGH, 0x0000,
8479                         0x00000000, 0x0000ffff },
8480                 { MAC_ADDR_0_LOW, 0x0000,
8481                         0x00000000, 0xffffffff },
8482                 { MAC_RX_MTU_SIZE, 0x0000,
8483                         0x00000000, 0x0000ffff },
8484                 { MAC_TX_MODE, 0x0000,
8485                         0x00000000, 0x00000070 },
8486                 { MAC_TX_LENGTHS, 0x0000,
8487                         0x00000000, 0x00003fff },
8488                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8489                         0x00000000, 0x000007fc },
8490                 { MAC_RX_MODE, TG3_FL_5705,
8491                         0x00000000, 0x000007dc },
8492                 { MAC_HASH_REG_0, 0x0000,
8493                         0x00000000, 0xffffffff },
8494                 { MAC_HASH_REG_1, 0x0000,
8495                         0x00000000, 0xffffffff },
8496                 { MAC_HASH_REG_2, 0x0000,
8497                         0x00000000, 0xffffffff },
8498                 { MAC_HASH_REG_3, 0x0000,
8499                         0x00000000, 0xffffffff },
8500
8501                 /* Receive Data and Receive BD Initiator Control Registers. */
8502                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8503                         0x00000000, 0xffffffff },
8504                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8505                         0x00000000, 0xffffffff },
8506                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8507                         0x00000000, 0x00000003 },
8508                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8509                         0x00000000, 0xffffffff },
8510                 { RCVDBDI_STD_BD+0, 0x0000,
8511                         0x00000000, 0xffffffff },
8512                 { RCVDBDI_STD_BD+4, 0x0000,
8513                         0x00000000, 0xffffffff },
8514                 { RCVDBDI_STD_BD+8, 0x0000,
8515                         0x00000000, 0xffff0002 },
8516                 { RCVDBDI_STD_BD+0xc, 0x0000,
8517                         0x00000000, 0xffffffff },
8518
8519                 /* Receive BD Initiator Control Registers. */
8520                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8521                         0x00000000, 0xffffffff },
8522                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8523                         0x00000000, 0x000003ff },
8524                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8525                         0x00000000, 0xffffffff },
8526
8527                 /* Host Coalescing Control Registers. */
8528                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8529                         0x00000000, 0x00000004 },
8530                 { HOSTCC_MODE, TG3_FL_5705,
8531                         0x00000000, 0x000000f6 },
8532                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8533                         0x00000000, 0xffffffff },
8534                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8535                         0x00000000, 0x000003ff },
8536                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8537                         0x00000000, 0xffffffff },
8538                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8539                         0x00000000, 0x000003ff },
8540                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8541                         0x00000000, 0xffffffff },
8542                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8543                         0x00000000, 0x000000ff },
8544                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8545                         0x00000000, 0xffffffff },
8546                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8547                         0x00000000, 0x000000ff },
8548                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8549                         0x00000000, 0xffffffff },
8550                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8551                         0x00000000, 0xffffffff },
8552                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8553                         0x00000000, 0xffffffff },
8554                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8555                         0x00000000, 0x000000ff },
8556                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8557                         0x00000000, 0xffffffff },
8558                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8559                         0x00000000, 0x000000ff },
8560                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8561                         0x00000000, 0xffffffff },
8562                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8563                         0x00000000, 0xffffffff },
8564                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8565                         0x00000000, 0xffffffff },
8566                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8567                         0x00000000, 0xffffffff },
8568                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8569                         0x00000000, 0xffffffff },
8570                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8571                         0xffffffff, 0x00000000 },
8572                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8573                         0xffffffff, 0x00000000 },
8574
8575                 /* Buffer Manager Control Registers. */
8576                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8577                         0x00000000, 0x007fff80 },
8578                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8579                         0x00000000, 0x007fffff },
8580                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8581                         0x00000000, 0x0000003f },
8582                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8583                         0x00000000, 0x000001ff },
8584                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8585                         0x00000000, 0x000001ff },
8586                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8587                         0xffffffff, 0x00000000 },
8588                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8589                         0xffffffff, 0x00000000 },
8590
8591                 /* Mailbox Registers */
8592                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8593                         0x00000000, 0x000001ff },
8594                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8595                         0x00000000, 0x000001ff },
8596                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8597                         0x00000000, 0x000007ff },
8598                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8599                         0x00000000, 0x000001ff },
8600
8601                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8602         };
8603
8604         is_5705 = is_5750 = 0;
8605         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8606                 is_5705 = 1;
8607                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8608                         is_5750 = 1;
8609         }
8610
8611         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8612                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8613                         continue;
8614
8615                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8616                         continue;
8617
8618                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8619                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8620                         continue;
8621
8622                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8623                         continue;
8624
8625                 offset = (u32) reg_tbl[i].offset;
8626                 read_mask = reg_tbl[i].read_mask;
8627                 write_mask = reg_tbl[i].write_mask;
8628
8629                 /* Save the original register content */
8630                 save_val = tr32(offset);
8631
8632                 /* Determine the read-only value. */
8633                 read_val = save_val & read_mask;
8634
8635                 /* Write zero to the register, then make sure the read-only bits
8636                  * are not changed and the read/write bits are all zeros.
8637                  */
8638                 tw32(offset, 0);
8639
8640                 val = tr32(offset);
8641
8642                 /* Test the read-only and read/write bits. */
8643                 if (((val & read_mask) != read_val) || (val & write_mask))
8644                         goto out;
8645
8646                 /* Write ones to all the bits defined by RdMask and WrMask, then
8647                  * make sure the read-only bits are not changed and the
8648                  * read/write bits are all ones.
8649                  */
8650                 tw32(offset, read_mask | write_mask);
8651
8652                 val = tr32(offset);
8653
8654                 /* Test the read-only bits. */
8655                 if ((val & read_mask) != read_val)
8656                         goto out;
8657
8658                 /* Test the read/write bits. */
8659                 if ((val & write_mask) != write_mask)
8660                         goto out;
8661
8662                 tw32(offset, save_val);
8663         }
8664
8665         return 0;
8666
8667 out:
8668         printk(KERN_ERR PFX "Register test failed at offset %x\n", offset);
8669         tw32(offset, save_val);
8670         return -EIO;
8671 }
8672
8673 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8674 {
8675         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8676         int i;
8677         u32 j;
8678
8679         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8680                 for (j = 0; j < len; j += 4) {
8681                         u32 val;
8682
8683                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8684                         tg3_read_mem(tp, offset + j, &val);
8685                         if (val != test_pattern[i])
8686                                 return -EIO;
8687                 }
8688         }
8689         return 0;
8690 }
8691
8692 static int tg3_test_memory(struct tg3 *tp)
8693 {
8694         static struct mem_entry {
8695                 u32 offset;
8696                 u32 len;
8697         } mem_tbl_570x[] = {
8698                 { 0x00000000, 0x00b50},
8699                 { 0x00002000, 0x1c000},
8700                 { 0xffffffff, 0x00000}
8701         }, mem_tbl_5705[] = {
8702                 { 0x00000100, 0x0000c},
8703                 { 0x00000200, 0x00008},
8704                 { 0x00004000, 0x00800},
8705                 { 0x00006000, 0x01000},
8706                 { 0x00008000, 0x02000},
8707                 { 0x00010000, 0x0e000},
8708                 { 0xffffffff, 0x00000}
8709         }, mem_tbl_5755[] = {
8710                 { 0x00000200, 0x00008},
8711                 { 0x00004000, 0x00800},
8712                 { 0x00006000, 0x00800},
8713                 { 0x00008000, 0x02000},
8714                 { 0x00010000, 0x0c000},
8715                 { 0xffffffff, 0x00000}
8716         }, mem_tbl_5906[] = {
8717                 { 0x00000200, 0x00008},
8718                 { 0x00004000, 0x00400},
8719                 { 0x00006000, 0x00400},
8720                 { 0x00008000, 0x01000},
8721                 { 0x00010000, 0x01000},
8722                 { 0xffffffff, 0x00000}
8723         };
8724         struct mem_entry *mem_tbl;
8725         int err = 0;
8726         int i;
8727
8728         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8729                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8730                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8731                         mem_tbl = mem_tbl_5755;
8732                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8733                         mem_tbl = mem_tbl_5906;
8734                 else
8735                         mem_tbl = mem_tbl_5705;
8736         } else
8737                 mem_tbl = mem_tbl_570x;
8738
8739         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8740                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8741                     mem_tbl[i].len)) != 0)
8742                         break;
8743         }
8744
8745         return err;
8746 }
8747
8748 #define TG3_MAC_LOOPBACK        0
8749 #define TG3_PHY_LOOPBACK        1
8750
8751 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8752 {
8753         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8754         u32 desc_idx;
8755         struct sk_buff *skb, *rx_skb;
8756         u8 *tx_data;
8757         dma_addr_t map;
8758         int num_pkts, tx_len, rx_len, i, err;
8759         struct tg3_rx_buffer_desc *desc;
8760
8761         if (loopback_mode == TG3_MAC_LOOPBACK) {
8762                 /* HW errata - mac loopback fails in some cases on 5780.
8763                  * Normal traffic and PHY loopback are not affected by
8764                  * errata.
8765                  */
8766                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8767                         return 0;
8768
8769                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8770                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8771                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8772                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8773                 else
8774                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8775                 tw32(MAC_MODE, mac_mode);
8776         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8777                 u32 val;
8778
8779                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8780                         u32 phytest;
8781
8782                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8783                                 u32 phy;
8784
8785                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8786                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8787                                 if (!tg3_readphy(tp, 0x1b, &phy))
8788                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8789                                 if (!tg3_readphy(tp, 0x10, &phy))
8790                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8791                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8792                         }
8793                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8794                 } else
8795                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8796
8797                 tg3_writephy(tp, MII_BMCR, val);
8798                 udelay(40);
8799
8800                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8801                            MAC_MODE_LINK_POLARITY;
8802                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8803                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8804                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8805                 } else
8806                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8807
8808                 /* reset to prevent losing 1st rx packet intermittently */
8809                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8810                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8811                         udelay(10);
8812                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8813                 }
8814                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8815                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8816                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8817                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8818                 }
8819                 tw32(MAC_MODE, mac_mode);
8820         }
8821         else
8822                 return -EINVAL;
8823
8824         err = -EIO;
8825
8826         tx_len = 1514;
8827         skb = netdev_alloc_skb(tp->dev, tx_len);
8828         if (!skb)
8829                 return -ENOMEM;
8830
8831         tx_data = skb_put(skb, tx_len);
8832         memcpy(tx_data, tp->dev->dev_addr, 6);
8833         memset(tx_data + 6, 0x0, 8);
8834
8835         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8836
8837         for (i = 14; i < tx_len; i++)
8838                 tx_data[i] = (u8) (i & 0xff);
8839
8840         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8841
8842         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8843              HOSTCC_MODE_NOW);
8844
8845         udelay(10);
8846
8847         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8848
8849         num_pkts = 0;
8850
8851         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8852
8853         tp->tx_prod++;
8854         num_pkts++;
8855
8856         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8857                      tp->tx_prod);
8858         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8859
8860         udelay(10);
8861
8862         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8863         for (i = 0; i < 25; i++) {
8864                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8865                        HOSTCC_MODE_NOW);
8866
8867                 udelay(10);
8868
8869                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8870                 rx_idx = tp->hw_status->idx[0].rx_producer;
8871                 if ((tx_idx == tp->tx_prod) &&
8872                     (rx_idx == (rx_start_idx + num_pkts)))
8873                         break;
8874         }
8875
8876         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8877         dev_kfree_skb(skb);
8878
8879         if (tx_idx != tp->tx_prod)
8880                 goto out;
8881
8882         if (rx_idx != rx_start_idx + num_pkts)
8883                 goto out;
8884
8885         desc = &tp->rx_rcb[rx_start_idx];
8886         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8887         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8888         if (opaque_key != RXD_OPAQUE_RING_STD)
8889                 goto out;
8890
8891         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8892             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8893                 goto out;
8894
8895         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8896         if (rx_len != tx_len)
8897                 goto out;
8898
8899         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8900
8901         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8902         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8903
8904         for (i = 14; i < tx_len; i++) {
8905                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8906                         goto out;
8907         }
8908         err = 0;
8909
8910         /* tg3_free_rings will unmap and free the rx_skb */
8911 out:
8912         return err;
8913 }
8914
8915 #define TG3_MAC_LOOPBACK_FAILED         1
8916 #define TG3_PHY_LOOPBACK_FAILED         2
8917 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8918                                          TG3_PHY_LOOPBACK_FAILED)
8919
8920 static int tg3_test_loopback(struct tg3 *tp)
8921 {
8922         int err = 0;
8923
8924         if (!netif_running(tp->dev))
8925                 return TG3_LOOPBACK_FAILED;
8926
8927         err = tg3_reset_hw(tp, 1);
8928         if (err)
8929                 return TG3_LOOPBACK_FAILED;
8930
8931         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8932                 err |= TG3_MAC_LOOPBACK_FAILED;
8933         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8934                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8935                         err |= TG3_PHY_LOOPBACK_FAILED;
8936         }
8937
8938         return err;
8939 }
8940
8941 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8942                           u64 *data)
8943 {
8944         struct tg3 *tp = netdev_priv(dev);
8945
8946         if (tp->link_config.phy_is_low_power)
8947                 tg3_set_power_state(tp, PCI_D0);
8948
8949         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8950
8951         if (tg3_test_nvram(tp) != 0) {
8952                 etest->flags |= ETH_TEST_FL_FAILED;
8953                 data[0] = 1;
8954         }
8955         if (tg3_test_link(tp) != 0) {
8956                 etest->flags |= ETH_TEST_FL_FAILED;
8957                 data[1] = 1;
8958         }
8959         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8960                 int err, irq_sync = 0;
8961
8962                 if (netif_running(dev)) {
8963                         tg3_netif_stop(tp);
8964                         irq_sync = 1;
8965                 }
8966
8967                 tg3_full_lock(tp, irq_sync);
8968
8969                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8970                 err = tg3_nvram_lock(tp);
8971                 tg3_halt_cpu(tp, RX_CPU_BASE);
8972                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8973                         tg3_halt_cpu(tp, TX_CPU_BASE);
8974                 if (!err)
8975                         tg3_nvram_unlock(tp);
8976
8977                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8978                         tg3_phy_reset(tp);
8979
8980                 if (tg3_test_registers(tp) != 0) {
8981                         etest->flags |= ETH_TEST_FL_FAILED;
8982                         data[2] = 1;
8983                 }
8984                 if (tg3_test_memory(tp) != 0) {
8985                         etest->flags |= ETH_TEST_FL_FAILED;
8986                         data[3] = 1;
8987                 }
8988                 if ((data[4] = tg3_test_loopback(tp)) != 0)
8989                         etest->flags |= ETH_TEST_FL_FAILED;
8990
8991                 tg3_full_unlock(tp);
8992
8993                 if (tg3_test_interrupt(tp) != 0) {
8994                         etest->flags |= ETH_TEST_FL_FAILED;
8995                         data[5] = 1;
8996                 }
8997
8998                 tg3_full_lock(tp, 0);
8999
9000                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9001                 if (netif_running(dev)) {
9002                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9003                         if (!tg3_restart_hw(tp, 1))
9004                                 tg3_netif_start(tp);
9005                 }
9006
9007                 tg3_full_unlock(tp);
9008         }
9009         if (tp->link_config.phy_is_low_power)
9010                 tg3_set_power_state(tp, PCI_D3hot);
9011
9012 }
9013
9014 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9015 {
9016         struct mii_ioctl_data *data = if_mii(ifr);
9017         struct tg3 *tp = netdev_priv(dev);
9018         int err;
9019
9020         switch(cmd) {
9021         case SIOCGMIIPHY:
9022                 data->phy_id = PHY_ADDR;
9023
9024                 /* fallthru */
9025         case SIOCGMIIREG: {
9026                 u32 mii_regval;
9027
9028                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9029                         break;                  /* We have no PHY */
9030
9031                 if (tp->link_config.phy_is_low_power)
9032                         return -EAGAIN;
9033
9034                 spin_lock_bh(&tp->lock);
9035                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9036                 spin_unlock_bh(&tp->lock);
9037
9038                 data->val_out = mii_regval;
9039
9040                 return err;
9041         }
9042
9043         case SIOCSMIIREG:
9044                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9045                         break;                  /* We have no PHY */
9046
9047                 if (!capable(CAP_NET_ADMIN))
9048                         return -EPERM;
9049
9050                 if (tp->link_config.phy_is_low_power)
9051                         return -EAGAIN;
9052
9053                 spin_lock_bh(&tp->lock);
9054                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9055                 spin_unlock_bh(&tp->lock);
9056
9057                 return err;
9058
9059         default:
9060                 /* do nothing */
9061                 break;
9062         }
9063         return -EOPNOTSUPP;
9064 }
9065
9066 #if TG3_VLAN_TAG_USED
9067 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9068 {
9069         struct tg3 *tp = netdev_priv(dev);
9070
9071         if (netif_running(dev))
9072                 tg3_netif_stop(tp);
9073
9074         tg3_full_lock(tp, 0);
9075
9076         tp->vlgrp = grp;
9077
9078         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9079         __tg3_set_rx_mode(dev);
9080
9081         tg3_full_unlock(tp);
9082
9083         if (netif_running(dev))
9084                 tg3_netif_start(tp);
9085 }
9086
9087 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9088 {
9089         struct tg3 *tp = netdev_priv(dev);
9090
9091         if (netif_running(dev))
9092                 tg3_netif_stop(tp);
9093
9094         tg3_full_lock(tp, 0);
9095         if (tp->vlgrp)
9096                 tp->vlgrp->vlan_devices[vid] = NULL;
9097         tg3_full_unlock(tp);
9098
9099         if (netif_running(dev))
9100                 tg3_netif_start(tp);
9101 }
9102 #endif
9103
9104 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9105 {
9106         struct tg3 *tp = netdev_priv(dev);
9107
9108         memcpy(ec, &tp->coal, sizeof(*ec));
9109         return 0;
9110 }
9111
9112 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9113 {
9114         struct tg3 *tp = netdev_priv(dev);
9115         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9116         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9117
9118         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9119                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9120                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9121                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9122                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9123         }
9124
9125         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9126             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9127             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9128             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9129             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9130             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9131             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9132             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9133             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9134             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9135                 return -EINVAL;
9136
9137         /* No rx interrupts will be generated if both are zero */
9138         if ((ec->rx_coalesce_usecs == 0) &&
9139             (ec->rx_max_coalesced_frames == 0))
9140                 return -EINVAL;
9141
9142         /* No tx interrupts will be generated if both are zero */
9143         if ((ec->tx_coalesce_usecs == 0) &&
9144             (ec->tx_max_coalesced_frames == 0))
9145                 return -EINVAL;
9146
9147         /* Only copy relevant parameters, ignore all others. */
9148         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9149         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9150         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9151         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9152         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9153         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9154         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9155         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9156         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9157
9158         if (netif_running(dev)) {
9159                 tg3_full_lock(tp, 0);
9160                 __tg3_set_coalesce(tp, &tp->coal);
9161                 tg3_full_unlock(tp);
9162         }
9163         return 0;
9164 }
9165
9166 static const struct ethtool_ops tg3_ethtool_ops = {
9167         .get_settings           = tg3_get_settings,
9168         .set_settings           = tg3_set_settings,
9169         .get_drvinfo            = tg3_get_drvinfo,
9170         .get_regs_len           = tg3_get_regs_len,
9171         .get_regs               = tg3_get_regs,
9172         .get_wol                = tg3_get_wol,
9173         .set_wol                = tg3_set_wol,
9174         .get_msglevel           = tg3_get_msglevel,
9175         .set_msglevel           = tg3_set_msglevel,
9176         .nway_reset             = tg3_nway_reset,
9177         .get_link               = ethtool_op_get_link,
9178         .get_eeprom_len         = tg3_get_eeprom_len,
9179         .get_eeprom             = tg3_get_eeprom,
9180         .set_eeprom             = tg3_set_eeprom,
9181         .get_ringparam          = tg3_get_ringparam,
9182         .set_ringparam          = tg3_set_ringparam,
9183         .get_pauseparam         = tg3_get_pauseparam,
9184         .set_pauseparam         = tg3_set_pauseparam,
9185         .get_rx_csum            = tg3_get_rx_csum,
9186         .set_rx_csum            = tg3_set_rx_csum,
9187         .get_tx_csum            = ethtool_op_get_tx_csum,
9188         .set_tx_csum            = tg3_set_tx_csum,
9189         .get_sg                 = ethtool_op_get_sg,
9190         .set_sg                 = ethtool_op_set_sg,
9191 #if TG3_TSO_SUPPORT != 0
9192         .get_tso                = ethtool_op_get_tso,
9193         .set_tso                = tg3_set_tso,
9194 #endif
9195         .self_test_count        = tg3_get_test_count,
9196         .self_test              = tg3_self_test,
9197         .get_strings            = tg3_get_strings,
9198         .phys_id                = tg3_phys_id,
9199         .get_stats_count        = tg3_get_stats_count,
9200         .get_ethtool_stats      = tg3_get_ethtool_stats,
9201         .get_coalesce           = tg3_get_coalesce,
9202         .set_coalesce           = tg3_set_coalesce,
9203         .get_perm_addr          = ethtool_op_get_perm_addr,
9204 };
9205
9206 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9207 {
9208         u32 cursize, val, magic;
9209
9210         tp->nvram_size = EEPROM_CHIP_SIZE;
9211
9212         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9213                 return;
9214
9215         if ((magic != TG3_EEPROM_MAGIC) &&
9216             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9217             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9218                 return;
9219
9220         /*
9221          * Size the chip by reading offsets at increasing powers of two.
9222          * When we encounter our validation signature, we know the addressing
9223          * has wrapped around, and thus have our chip size.
9224          */
9225         cursize = 0x10;
9226
9227         while (cursize < tp->nvram_size) {
9228                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9229                         return;
9230
9231                 if (val == magic)
9232                         break;
9233
9234                 cursize <<= 1;
9235         }
9236
9237         tp->nvram_size = cursize;
9238 }
9239
9240 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9241 {
9242         u32 val;
9243
9244         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9245                 return;
9246
9247         /* Selfboot format */
9248         if (val != TG3_EEPROM_MAGIC) {
9249                 tg3_get_eeprom_size(tp);
9250                 return;
9251         }
9252
9253         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9254                 if (val != 0) {
9255                         tp->nvram_size = (val >> 16) * 1024;
9256                         return;
9257                 }
9258         }
9259         tp->nvram_size = 0x20000;
9260 }
9261
9262 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9263 {
9264         u32 nvcfg1;
9265
9266         nvcfg1 = tr32(NVRAM_CFG1);
9267         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9268                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9269         }
9270         else {
9271                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9272                 tw32(NVRAM_CFG1, nvcfg1);
9273         }
9274
9275         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9276             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9277                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9278                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9279                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9280                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9281                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9282                                 break;
9283                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9284                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9285                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9286                                 break;
9287                         case FLASH_VENDOR_ATMEL_EEPROM:
9288                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9289                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9290                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9291                                 break;
9292                         case FLASH_VENDOR_ST:
9293                                 tp->nvram_jedecnum = JEDEC_ST;
9294                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9295                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9296                                 break;
9297                         case FLASH_VENDOR_SAIFUN:
9298                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9299                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9300                                 break;
9301                         case FLASH_VENDOR_SST_SMALL:
9302                         case FLASH_VENDOR_SST_LARGE:
9303                                 tp->nvram_jedecnum = JEDEC_SST;
9304                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9305                                 break;
9306                 }
9307         }
9308         else {
9309                 tp->nvram_jedecnum = JEDEC_ATMEL;
9310                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9311                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9312         }
9313 }
9314
9315 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9316 {
9317         u32 nvcfg1;
9318
9319         nvcfg1 = tr32(NVRAM_CFG1);
9320
9321         /* NVRAM protection for TPM */
9322         if (nvcfg1 & (1 << 27))
9323                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9324
9325         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9326                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9327                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9328                         tp->nvram_jedecnum = JEDEC_ATMEL;
9329                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9330                         break;
9331                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9332                         tp->nvram_jedecnum = JEDEC_ATMEL;
9333                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9334                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9335                         break;
9336                 case FLASH_5752VENDOR_ST_M45PE10:
9337                 case FLASH_5752VENDOR_ST_M45PE20:
9338                 case FLASH_5752VENDOR_ST_M45PE40:
9339                         tp->nvram_jedecnum = JEDEC_ST;
9340                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9341                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9342                         break;
9343         }
9344
9345         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9346                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9347                         case FLASH_5752PAGE_SIZE_256:
9348                                 tp->nvram_pagesize = 256;
9349                                 break;
9350                         case FLASH_5752PAGE_SIZE_512:
9351                                 tp->nvram_pagesize = 512;
9352                                 break;
9353                         case FLASH_5752PAGE_SIZE_1K:
9354                                 tp->nvram_pagesize = 1024;
9355                                 break;
9356                         case FLASH_5752PAGE_SIZE_2K:
9357                                 tp->nvram_pagesize = 2048;
9358                                 break;
9359                         case FLASH_5752PAGE_SIZE_4K:
9360                                 tp->nvram_pagesize = 4096;
9361                                 break;
9362                         case FLASH_5752PAGE_SIZE_264:
9363                                 tp->nvram_pagesize = 264;
9364                                 break;
9365                 }
9366         }
9367         else {
9368                 /* For eeprom, set pagesize to maximum eeprom size */
9369                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9370
9371                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9372                 tw32(NVRAM_CFG1, nvcfg1);
9373         }
9374 }
9375
9376 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9377 {
9378         u32 nvcfg1;
9379
9380         nvcfg1 = tr32(NVRAM_CFG1);
9381
9382         /* NVRAM protection for TPM */
9383         if (nvcfg1 & (1 << 27))
9384                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9385
9386         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9387                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9388                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9389                         tp->nvram_jedecnum = JEDEC_ATMEL;
9390                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9391                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9392
9393                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9394                         tw32(NVRAM_CFG1, nvcfg1);
9395                         break;
9396                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9397                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9398                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9399                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9400                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9401                         tp->nvram_jedecnum = JEDEC_ATMEL;
9402                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9403                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9404                         tp->nvram_pagesize = 264;
9405                         break;
9406                 case FLASH_5752VENDOR_ST_M45PE10:
9407                 case FLASH_5752VENDOR_ST_M45PE20:
9408                 case FLASH_5752VENDOR_ST_M45PE40:
9409                         tp->nvram_jedecnum = JEDEC_ST;
9410                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9411                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9412                         tp->nvram_pagesize = 256;
9413                         break;
9414         }
9415 }
9416
9417 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9418 {
9419         u32 nvcfg1;
9420
9421         nvcfg1 = tr32(NVRAM_CFG1);
9422
9423         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9424                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9425                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9426                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9427                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9428                         tp->nvram_jedecnum = JEDEC_ATMEL;
9429                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9430                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9431
9432                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9433                         tw32(NVRAM_CFG1, nvcfg1);
9434                         break;
9435                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9436                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9437                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9438                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9439                         tp->nvram_jedecnum = JEDEC_ATMEL;
9440                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9441                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9442                         tp->nvram_pagesize = 264;
9443                         break;
9444                 case FLASH_5752VENDOR_ST_M45PE10:
9445                 case FLASH_5752VENDOR_ST_M45PE20:
9446                 case FLASH_5752VENDOR_ST_M45PE40:
9447                         tp->nvram_jedecnum = JEDEC_ST;
9448                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9449                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9450                         tp->nvram_pagesize = 256;
9451                         break;
9452         }
9453 }
9454
9455 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9456 {
9457         tp->nvram_jedecnum = JEDEC_ATMEL;
9458         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9459         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9460 }
9461
9462 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9463 static void __devinit tg3_nvram_init(struct tg3 *tp)
9464 {
9465         int j;
9466
9467         tw32_f(GRC_EEPROM_ADDR,
9468              (EEPROM_ADDR_FSM_RESET |
9469               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9470                EEPROM_ADDR_CLKPERD_SHIFT)));
9471
9472         /* XXX schedule_timeout() ... */
9473         for (j = 0; j < 100; j++)
9474                 udelay(10);
9475
9476         /* Enable seeprom accesses. */
9477         tw32_f(GRC_LOCAL_CTRL,
9478              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9479         udelay(100);
9480
9481         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9482             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9483                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9484
9485                 if (tg3_nvram_lock(tp)) {
9486                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9487                                "tg3_nvram_init failed.\n", tp->dev->name);
9488                         return;
9489                 }
9490                 tg3_enable_nvram_access(tp);
9491
9492                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9493                         tg3_get_5752_nvram_info(tp);
9494                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9495                         tg3_get_5755_nvram_info(tp);
9496                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9497                         tg3_get_5787_nvram_info(tp);
9498                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9499                         tg3_get_5906_nvram_info(tp);
9500                 else
9501                         tg3_get_nvram_info(tp);
9502
9503                 tg3_get_nvram_size(tp);
9504
9505                 tg3_disable_nvram_access(tp);
9506                 tg3_nvram_unlock(tp);
9507
9508         } else {
9509                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9510
9511                 tg3_get_eeprom_size(tp);
9512         }
9513 }
9514
9515 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9516                                         u32 offset, u32 *val)
9517 {
9518         u32 tmp;
9519         int i;
9520
9521         if (offset > EEPROM_ADDR_ADDR_MASK ||
9522             (offset % 4) != 0)
9523                 return -EINVAL;
9524
9525         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9526                                         EEPROM_ADDR_DEVID_MASK |
9527                                         EEPROM_ADDR_READ);
9528         tw32(GRC_EEPROM_ADDR,
9529              tmp |
9530              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9531              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9532               EEPROM_ADDR_ADDR_MASK) |
9533              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9534
9535         for (i = 0; i < 10000; i++) {
9536                 tmp = tr32(GRC_EEPROM_ADDR);
9537
9538                 if (tmp & EEPROM_ADDR_COMPLETE)
9539                         break;
9540                 udelay(100);
9541         }
9542         if (!(tmp & EEPROM_ADDR_COMPLETE))
9543                 return -EBUSY;
9544
9545         *val = tr32(GRC_EEPROM_DATA);
9546         return 0;
9547 }
9548
9549 #define NVRAM_CMD_TIMEOUT 10000
9550
9551 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9552 {
9553         int i;
9554
9555         tw32(NVRAM_CMD, nvram_cmd);
9556         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9557                 udelay(10);
9558                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9559                         udelay(10);
9560                         break;
9561                 }
9562         }
9563         if (i == NVRAM_CMD_TIMEOUT) {
9564                 return -EBUSY;
9565         }
9566         return 0;
9567 }
9568
9569 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9570 {
9571         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9572             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9573             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9574             (tp->nvram_jedecnum == JEDEC_ATMEL))
9575
9576                 addr = ((addr / tp->nvram_pagesize) <<
9577                         ATMEL_AT45DB0X1B_PAGE_POS) +
9578                        (addr % tp->nvram_pagesize);
9579
9580         return addr;
9581 }
9582
9583 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9584 {
9585         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9586             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9587             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9588             (tp->nvram_jedecnum == JEDEC_ATMEL))
9589
9590                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9591                         tp->nvram_pagesize) +
9592                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9593
9594         return addr;
9595 }
9596
9597 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9598 {
9599         int ret;
9600
9601         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9602                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9603
9604         offset = tg3_nvram_phys_addr(tp, offset);
9605
9606         if (offset > NVRAM_ADDR_MSK)
9607                 return -EINVAL;
9608
9609         ret = tg3_nvram_lock(tp);
9610         if (ret)
9611                 return ret;
9612
9613         tg3_enable_nvram_access(tp);
9614
9615         tw32(NVRAM_ADDR, offset);
9616         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9617                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9618
9619         if (ret == 0)
9620                 *val = swab32(tr32(NVRAM_RDDATA));
9621
9622         tg3_disable_nvram_access(tp);
9623
9624         tg3_nvram_unlock(tp);
9625
9626         return ret;
9627 }
9628
9629 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9630 {
9631         int err;
9632         u32 tmp;
9633
9634         err = tg3_nvram_read(tp, offset, &tmp);
9635         *val = swab32(tmp);
9636         return err;
9637 }
9638
9639 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9640                                     u32 offset, u32 len, u8 *buf)
9641 {
9642         int i, j, rc = 0;
9643         u32 val;
9644
9645         for (i = 0; i < len; i += 4) {
9646                 u32 addr, data;
9647
9648                 addr = offset + i;
9649
9650                 memcpy(&data, buf + i, 4);
9651
9652                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9653
9654                 val = tr32(GRC_EEPROM_ADDR);
9655                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9656
9657                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9658                         EEPROM_ADDR_READ);
9659                 tw32(GRC_EEPROM_ADDR, val |
9660                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9661                         (addr & EEPROM_ADDR_ADDR_MASK) |
9662                         EEPROM_ADDR_START |
9663                         EEPROM_ADDR_WRITE);
9664
9665                 for (j = 0; j < 10000; j++) {
9666                         val = tr32(GRC_EEPROM_ADDR);
9667
9668                         if (val & EEPROM_ADDR_COMPLETE)
9669                                 break;
9670                         udelay(100);
9671                 }
9672                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9673                         rc = -EBUSY;
9674                         break;
9675                 }
9676         }
9677
9678         return rc;
9679 }
9680
9681 /* offset and length are dword aligned */
9682 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9683                 u8 *buf)
9684 {
9685         int ret = 0;
9686         u32 pagesize = tp->nvram_pagesize;
9687         u32 pagemask = pagesize - 1;
9688         u32 nvram_cmd;
9689         u8 *tmp;
9690
9691         tmp = kmalloc(pagesize, GFP_KERNEL);
9692         if (tmp == NULL)
9693                 return -ENOMEM;
9694
9695         while (len) {
9696                 int j;
9697                 u32 phy_addr, page_off, size;
9698
9699                 phy_addr = offset & ~pagemask;
9700
9701                 for (j = 0; j < pagesize; j += 4) {
9702                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9703                                                 (u32 *) (tmp + j))))
9704                                 break;
9705                 }
9706                 if (ret)
9707                         break;
9708
9709                 page_off = offset & pagemask;
9710                 size = pagesize;
9711                 if (len < size)
9712                         size = len;
9713
9714                 len -= size;
9715
9716                 memcpy(tmp + page_off, buf, size);
9717
9718                 offset = offset + (pagesize - page_off);
9719
9720                 tg3_enable_nvram_access(tp);
9721
9722                 /*
9723                  * Before we can erase the flash page, we need
9724                  * to issue a special "write enable" command.
9725                  */
9726                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9727
9728                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9729                         break;
9730
9731                 /* Erase the target page */
9732                 tw32(NVRAM_ADDR, phy_addr);
9733
9734                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9735                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9736
9737                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9738                         break;
9739
9740                 /* Issue another write enable to start the write. */
9741                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9742
9743                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9744                         break;
9745
9746                 for (j = 0; j < pagesize; j += 4) {
9747                         u32 data;
9748
9749                         data = *((u32 *) (tmp + j));
9750                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9751
9752                         tw32(NVRAM_ADDR, phy_addr + j);
9753
9754                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9755                                 NVRAM_CMD_WR;
9756
9757                         if (j == 0)
9758                                 nvram_cmd |= NVRAM_CMD_FIRST;
9759                         else if (j == (pagesize - 4))
9760                                 nvram_cmd |= NVRAM_CMD_LAST;
9761
9762                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9763                                 break;
9764                 }
9765                 if (ret)
9766                         break;
9767         }
9768
9769         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9770         tg3_nvram_exec_cmd(tp, nvram_cmd);
9771
9772         kfree(tmp);
9773
9774         return ret;
9775 }
9776
9777 /* offset and length are dword aligned */
9778 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9779                 u8 *buf)
9780 {
9781         int i, ret = 0;
9782
9783         for (i = 0; i < len; i += 4, offset += 4) {
9784                 u32 data, page_off, phy_addr, nvram_cmd;
9785
9786                 memcpy(&data, buf + i, 4);
9787                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9788
9789                 page_off = offset % tp->nvram_pagesize;
9790
9791                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9792
9793                 tw32(NVRAM_ADDR, phy_addr);
9794
9795                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9796
9797                 if ((page_off == 0) || (i == 0))
9798                         nvram_cmd |= NVRAM_CMD_FIRST;
9799                 if (page_off == (tp->nvram_pagesize - 4))
9800                         nvram_cmd |= NVRAM_CMD_LAST;
9801
9802                 if (i == (len - 4))
9803                         nvram_cmd |= NVRAM_CMD_LAST;
9804
9805                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9806                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9807                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9808                     (tp->nvram_jedecnum == JEDEC_ST) &&
9809                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9810
9811                         if ((ret = tg3_nvram_exec_cmd(tp,
9812                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9813                                 NVRAM_CMD_DONE)))
9814
9815                                 break;
9816                 }
9817                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9818                         /* We always do complete word writes to eeprom. */
9819                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9820                 }
9821
9822                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9823                         break;
9824         }
9825         return ret;
9826 }
9827
9828 /* offset and length are dword aligned */
9829 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9830 {
9831         int ret;
9832
9833         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9834                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9835                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9836                 udelay(40);
9837         }
9838
9839         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9840                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9841         }
9842         else {
9843                 u32 grc_mode;
9844
9845                 ret = tg3_nvram_lock(tp);
9846                 if (ret)
9847                         return ret;
9848
9849                 tg3_enable_nvram_access(tp);
9850                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9851                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9852                         tw32(NVRAM_WRITE1, 0x406);
9853
9854                 grc_mode = tr32(GRC_MODE);
9855                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9856
9857                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9858                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9859
9860                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9861                                 buf);
9862                 }
9863                 else {
9864                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9865                                 buf);
9866                 }
9867
9868                 grc_mode = tr32(GRC_MODE);
9869                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9870
9871                 tg3_disable_nvram_access(tp);
9872                 tg3_nvram_unlock(tp);
9873         }
9874
9875         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9876                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9877                 udelay(40);
9878         }
9879
9880         return ret;
9881 }
9882
9883 struct subsys_tbl_ent {
9884         u16 subsys_vendor, subsys_devid;
9885         u32 phy_id;
9886 };
9887
9888 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9889         /* Broadcom boards. */
9890         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9891         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9892         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9893         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9894         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9895         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9896         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9897         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9898         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9899         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9900         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9901
9902         /* 3com boards. */
9903         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9904         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9905         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9906         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9907         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9908
9909         /* DELL boards. */
9910         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9911         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9912         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9913         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9914
9915         /* Compaq boards. */
9916         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9917         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9918         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9919         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9920         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9921
9922         /* IBM boards. */
9923         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9924 };
9925
9926 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9927 {
9928         int i;
9929
9930         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9931                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9932                      tp->pdev->subsystem_vendor) &&
9933                     (subsys_id_to_phy_id[i].subsys_devid ==
9934                      tp->pdev->subsystem_device))
9935                         return &subsys_id_to_phy_id[i];
9936         }
9937         return NULL;
9938 }
9939
9940 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9941 {
9942         u32 val;
9943         u16 pmcsr;
9944
9945         /* On some early chips the SRAM cannot be accessed in D3hot state,
9946          * so need make sure we're in D0.
9947          */
9948         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9949         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9950         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9951         msleep(1);
9952
9953         /* Make sure register accesses (indirect or otherwise)
9954          * will function correctly.
9955          */
9956         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9957                                tp->misc_host_ctrl);
9958
9959         /* The memory arbiter has to be enabled in order for SRAM accesses
9960          * to succeed.  Normally on powerup the tg3 chip firmware will make
9961          * sure it is enabled, but other entities such as system netboot
9962          * code might disable it.
9963          */
9964         val = tr32(MEMARB_MODE);
9965         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9966
9967         tp->phy_id = PHY_ID_INVALID;
9968         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9969
9970         /* Assume an onboard device by default.  */
9971         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9972
9973         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9974                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
9975                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9976                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9977                 }
9978                 return;
9979         }
9980
9981         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9982         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9983                 u32 nic_cfg, led_cfg;
9984                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9985                 int eeprom_phy_serdes = 0;
9986
9987                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
9988                 tp->nic_sram_data_cfg = nic_cfg;
9989
9990                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
9991                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
9992                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
9993                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
9994                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
9995                     (ver > 0) && (ver < 0x100))
9996                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
9997
9998                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
9999                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10000                         eeprom_phy_serdes = 1;
10001
10002                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10003                 if (nic_phy_id != 0) {
10004                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10005                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10006
10007                         eeprom_phy_id  = (id1 >> 16) << 10;
10008                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10009                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10010                 } else
10011                         eeprom_phy_id = 0;
10012
10013                 tp->phy_id = eeprom_phy_id;
10014                 if (eeprom_phy_serdes) {
10015                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10016                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10017                         else
10018                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10019                 }
10020
10021                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10022                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10023                                     SHASTA_EXT_LED_MODE_MASK);
10024                 else
10025                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10026
10027                 switch (led_cfg) {
10028                 default:
10029                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10030                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10031                         break;
10032
10033                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10034                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10035                         break;
10036
10037                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10038                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10039
10040                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10041                          * read on some older 5700/5701 bootcode.
10042                          */
10043                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10044                             ASIC_REV_5700 ||
10045                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10046                             ASIC_REV_5701)
10047                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10048
10049                         break;
10050
10051                 case SHASTA_EXT_LED_SHARED:
10052                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10053                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10054                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10055                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10056                                                  LED_CTRL_MODE_PHY_2);
10057                         break;
10058
10059                 case SHASTA_EXT_LED_MAC:
10060                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10061                         break;
10062
10063                 case SHASTA_EXT_LED_COMBO:
10064                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10065                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10066                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10067                                                  LED_CTRL_MODE_PHY_2);
10068                         break;
10069
10070                 };
10071
10072                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10073                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10074                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10075                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10076
10077                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10078                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10079                         if ((tp->pdev->subsystem_vendor ==
10080                              PCI_VENDOR_ID_ARIMA) &&
10081                             (tp->pdev->subsystem_device == 0x205a ||
10082                              tp->pdev->subsystem_device == 0x2063))
10083                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10084                 } else {
10085                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10086                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10087                 }
10088
10089                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10090                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10091                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10092                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10093                 }
10094                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10095                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10096
10097                 if (cfg2 & (1 << 17))
10098                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10099
10100                 /* serdes signal pre-emphasis in register 0x590 set by */
10101                 /* bootcode if bit 18 is set */
10102                 if (cfg2 & (1 << 18))
10103                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10104         }
10105 }
10106
10107 static int __devinit tg3_phy_probe(struct tg3 *tp)
10108 {
10109         u32 hw_phy_id_1, hw_phy_id_2;
10110         u32 hw_phy_id, hw_phy_id_masked;
10111         int err;
10112
10113         /* Reading the PHY ID register can conflict with ASF
10114          * firwmare access to the PHY hardware.
10115          */
10116         err = 0;
10117         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10118                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10119         } else {
10120                 /* Now read the physical PHY_ID from the chip and verify
10121                  * that it is sane.  If it doesn't look good, we fall back
10122                  * to either the hard-coded table based PHY_ID and failing
10123                  * that the value found in the eeprom area.
10124                  */
10125                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10126                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10127
10128                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10129                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10130                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10131
10132                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10133         }
10134
10135         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10136                 tp->phy_id = hw_phy_id;
10137                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10138                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10139                 else
10140                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10141         } else {
10142                 if (tp->phy_id != PHY_ID_INVALID) {
10143                         /* Do nothing, phy ID already set up in
10144                          * tg3_get_eeprom_hw_cfg().
10145                          */
10146                 } else {
10147                         struct subsys_tbl_ent *p;
10148
10149                         /* No eeprom signature?  Try the hardcoded
10150                          * subsys device table.
10151                          */
10152                         p = lookup_by_subsys(tp);
10153                         if (!p)
10154                                 return -ENODEV;
10155
10156                         tp->phy_id = p->phy_id;
10157                         if (!tp->phy_id ||
10158                             tp->phy_id == PHY_ID_BCM8002)
10159                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10160                 }
10161         }
10162
10163         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10164             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10165                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10166
10167                 tg3_readphy(tp, MII_BMSR, &bmsr);
10168                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10169                     (bmsr & BMSR_LSTATUS))
10170                         goto skip_phy_reset;
10171
10172                 err = tg3_phy_reset(tp);
10173                 if (err)
10174                         return err;
10175
10176                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10177                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10178                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10179                 tg3_ctrl = 0;
10180                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10181                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10182                                     MII_TG3_CTRL_ADV_1000_FULL);
10183                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10184                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10185                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10186                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10187                 }
10188
10189                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10190                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10191                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10192                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10193                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10194
10195                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10196                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10197
10198                         tg3_writephy(tp, MII_BMCR,
10199                                      BMCR_ANENABLE | BMCR_ANRESTART);
10200                 }
10201                 tg3_phy_set_wirespeed(tp);
10202
10203                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10204                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10205                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10206         }
10207
10208 skip_phy_reset:
10209         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10210                 err = tg3_init_5401phy_dsp(tp);
10211                 if (err)
10212                         return err;
10213         }
10214
10215         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10216                 err = tg3_init_5401phy_dsp(tp);
10217         }
10218
10219         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10220                 tp->link_config.advertising =
10221                         (ADVERTISED_1000baseT_Half |
10222                          ADVERTISED_1000baseT_Full |
10223                          ADVERTISED_Autoneg |
10224                          ADVERTISED_FIBRE);
10225         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10226                 tp->link_config.advertising &=
10227                         ~(ADVERTISED_1000baseT_Half |
10228                           ADVERTISED_1000baseT_Full);
10229
10230         return err;
10231 }
10232
10233 static void __devinit tg3_read_partno(struct tg3 *tp)
10234 {
10235         unsigned char vpd_data[256];
10236         unsigned int i;
10237         u32 magic;
10238
10239         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10240                 goto out_not_found;
10241
10242         if (magic == TG3_EEPROM_MAGIC) {
10243                 for (i = 0; i < 256; i += 4) {
10244                         u32 tmp;
10245
10246                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10247                                 goto out_not_found;
10248
10249                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10250                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10251                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10252                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10253                 }
10254         } else {
10255                 int vpd_cap;
10256
10257                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10258                 for (i = 0; i < 256; i += 4) {
10259                         u32 tmp, j = 0;
10260                         u16 tmp16;
10261
10262                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10263                                               i);
10264                         while (j++ < 100) {
10265                                 pci_read_config_word(tp->pdev, vpd_cap +
10266                                                      PCI_VPD_ADDR, &tmp16);
10267                                 if (tmp16 & 0x8000)
10268                                         break;
10269                                 msleep(1);
10270                         }
10271                         if (!(tmp16 & 0x8000))
10272                                 goto out_not_found;
10273
10274                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10275                                               &tmp);
10276                         tmp = cpu_to_le32(tmp);
10277                         memcpy(&vpd_data[i], &tmp, 4);
10278                 }
10279         }
10280
10281         /* Now parse and find the part number. */
10282         for (i = 0; i < 254; ) {
10283                 unsigned char val = vpd_data[i];
10284                 unsigned int block_end;
10285
10286                 if (val == 0x82 || val == 0x91) {
10287                         i = (i + 3 +
10288                              (vpd_data[i + 1] +
10289                               (vpd_data[i + 2] << 8)));
10290                         continue;
10291                 }
10292
10293                 if (val != 0x90)
10294                         goto out_not_found;
10295
10296                 block_end = (i + 3 +
10297                              (vpd_data[i + 1] +
10298                               (vpd_data[i + 2] << 8)));
10299                 i += 3;
10300
10301                 if (block_end > 256)
10302                         goto out_not_found;
10303
10304                 while (i < (block_end - 2)) {
10305                         if (vpd_data[i + 0] == 'P' &&
10306                             vpd_data[i + 1] == 'N') {
10307                                 int partno_len = vpd_data[i + 2];
10308
10309                                 i += 3;
10310                                 if (partno_len > 24 || (partno_len + i) > 256)
10311                                         goto out_not_found;
10312
10313                                 memcpy(tp->board_part_number,
10314                                        &vpd_data[i], partno_len);
10315
10316                                 /* Success. */
10317                                 return;
10318                         }
10319                         i += 3 + vpd_data[i + 2];
10320                 }
10321
10322                 /* Part number not found. */
10323                 goto out_not_found;
10324         }
10325
10326 out_not_found:
10327         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10328                 strcpy(tp->board_part_number, "BCM95906");
10329         else
10330                 strcpy(tp->board_part_number, "none");
10331 }
10332
10333 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10334 {
10335         u32 val, offset, start;
10336
10337         if (tg3_nvram_read_swab(tp, 0, &val))
10338                 return;
10339
10340         if (val != TG3_EEPROM_MAGIC)
10341                 return;
10342
10343         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10344             tg3_nvram_read_swab(tp, 0x4, &start))
10345                 return;
10346
10347         offset = tg3_nvram_logical_addr(tp, offset);
10348         if (tg3_nvram_read_swab(tp, offset, &val))
10349                 return;
10350
10351         if ((val & 0xfc000000) == 0x0c000000) {
10352                 u32 ver_offset, addr;
10353                 int i;
10354
10355                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10356                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10357                         return;
10358
10359                 if (val != 0)
10360                         return;
10361
10362                 addr = offset + ver_offset - start;
10363                 for (i = 0; i < 16; i += 4) {
10364                         if (tg3_nvram_read(tp, addr + i, &val))
10365                                 return;
10366
10367                         val = cpu_to_le32(val);
10368                         memcpy(tp->fw_ver + i, &val, 4);
10369                 }
10370         }
10371 }
10372
10373 static int __devinit tg3_get_invariants(struct tg3 *tp)
10374 {
10375         static struct pci_device_id write_reorder_chipsets[] = {
10376                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10377                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10378                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10379                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10380                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10381                              PCI_DEVICE_ID_VIA_8385_0) },
10382                 { },
10383         };
10384         u32 misc_ctrl_reg;
10385         u32 cacheline_sz_reg;
10386         u32 pci_state_reg, grc_misc_cfg;
10387         u32 val;
10388         u16 pci_cmd;
10389         int err, pcie_cap;
10390
10391         /* Force memory write invalidate off.  If we leave it on,
10392          * then on 5700_BX chips we have to enable a workaround.
10393          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10394          * to match the cacheline size.  The Broadcom driver have this
10395          * workaround but turns MWI off all the times so never uses
10396          * it.  This seems to suggest that the workaround is insufficient.
10397          */
10398         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10399         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10400         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10401
10402         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10403          * has the register indirect write enable bit set before
10404          * we try to access any of the MMIO registers.  It is also
10405          * critical that the PCI-X hw workaround situation is decided
10406          * before that as well.
10407          */
10408         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10409                               &misc_ctrl_reg);
10410
10411         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10412                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10413
10414         /* Wrong chip ID in 5752 A0. This code can be removed later
10415          * as A0 is not in production.
10416          */
10417         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10418                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10419
10420         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10421          * we need to disable memory and use config. cycles
10422          * only to access all registers. The 5702/03 chips
10423          * can mistakenly decode the special cycles from the
10424          * ICH chipsets as memory write cycles, causing corruption
10425          * of register and memory space. Only certain ICH bridges
10426          * will drive special cycles with non-zero data during the
10427          * address phase which can fall within the 5703's address
10428          * range. This is not an ICH bug as the PCI spec allows
10429          * non-zero address during special cycles. However, only
10430          * these ICH bridges are known to drive non-zero addresses
10431          * during special cycles.
10432          *
10433          * Since special cycles do not cross PCI bridges, we only
10434          * enable this workaround if the 5703 is on the secondary
10435          * bus of these ICH bridges.
10436          */
10437         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10438             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10439                 static struct tg3_dev_id {
10440                         u32     vendor;
10441                         u32     device;
10442                         u32     rev;
10443                 } ich_chipsets[] = {
10444                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10445                           PCI_ANY_ID },
10446                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10447                           PCI_ANY_ID },
10448                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10449                           0xa },
10450                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10451                           PCI_ANY_ID },
10452                         { },
10453                 };
10454                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10455                 struct pci_dev *bridge = NULL;
10456
10457                 while (pci_id->vendor != 0) {
10458                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10459                                                 bridge);
10460                         if (!bridge) {
10461                                 pci_id++;
10462                                 continue;
10463                         }
10464                         if (pci_id->rev != PCI_ANY_ID) {
10465                                 u8 rev;
10466
10467                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10468                                                      &rev);
10469                                 if (rev > pci_id->rev)
10470                                         continue;
10471                         }
10472                         if (bridge->subordinate &&
10473                             (bridge->subordinate->number ==
10474                              tp->pdev->bus->number)) {
10475
10476                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10477                                 pci_dev_put(bridge);
10478                                 break;
10479                         }
10480                 }
10481         }
10482
10483         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10484          * DMA addresses > 40-bit. This bridge may have other additional
10485          * 57xx devices behind it in some 4-port NIC designs for example.
10486          * Any tg3 device found behind the bridge will also need the 40-bit
10487          * DMA workaround.
10488          */
10489         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10490             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10491                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10492                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10493                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10494         }
10495         else {
10496                 struct pci_dev *bridge = NULL;
10497
10498                 do {
10499                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10500                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10501                                                 bridge);
10502                         if (bridge && bridge->subordinate &&
10503                             (bridge->subordinate->number <=
10504                              tp->pdev->bus->number) &&
10505                             (bridge->subordinate->subordinate >=
10506                              tp->pdev->bus->number)) {
10507                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10508                                 pci_dev_put(bridge);
10509                                 break;
10510                         }
10511                 } while (bridge);
10512         }
10513
10514         /* Initialize misc host control in PCI block. */
10515         tp->misc_host_ctrl |= (misc_ctrl_reg &
10516                                MISC_HOST_CTRL_CHIPREV);
10517         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10518                                tp->misc_host_ctrl);
10519
10520         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10521                               &cacheline_sz_reg);
10522
10523         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10524         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10525         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10526         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10527
10528         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10529             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10530             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10531             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10532             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10533             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10534                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10535
10536         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10537             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10538                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10539
10540         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10541                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10542                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10543                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10544                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10545                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10546                 } else {
10547                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10548                                           TG3_FLG2_HW_TSO_1_BUG;
10549                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10550                                 ASIC_REV_5750 &&
10551                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10552                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10553                 }
10554         }
10555
10556         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10557             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10558             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10559             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10560             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10561             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10562                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10563
10564         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10565         if (pcie_cap != 0) {
10566                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10567                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10568                         u16 lnkctl;
10569
10570                         pci_read_config_word(tp->pdev,
10571                                              pcie_cap + PCI_EXP_LNKCTL,
10572                                              &lnkctl);
10573                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10574                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10575                 }
10576         }
10577
10578         /* If we have an AMD 762 or VIA K8T800 chipset, write
10579          * reordering to the mailbox registers done by the host
10580          * controller can cause major troubles.  We read back from
10581          * every mailbox register write to force the writes to be
10582          * posted to the chip in order.
10583          */
10584         if (pci_dev_present(write_reorder_chipsets) &&
10585             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10586                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10587
10588         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10589             tp->pci_lat_timer < 64) {
10590                 tp->pci_lat_timer = 64;
10591
10592                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10593                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10594                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10595                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10596
10597                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10598                                        cacheline_sz_reg);
10599         }
10600
10601         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10602                               &pci_state_reg);
10603
10604         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10605                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10606
10607                 /* If this is a 5700 BX chipset, and we are in PCI-X
10608                  * mode, enable register write workaround.
10609                  *
10610                  * The workaround is to use indirect register accesses
10611                  * for all chip writes not to mailbox registers.
10612                  */
10613                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10614                         u32 pm_reg;
10615                         u16 pci_cmd;
10616
10617                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10618
10619                         /* The chip can have it's power management PCI config
10620                          * space registers clobbered due to this bug.
10621                          * So explicitly force the chip into D0 here.
10622                          */
10623                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10624                                               &pm_reg);
10625                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10626                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10627                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10628                                                pm_reg);
10629
10630                         /* Also, force SERR#/PERR# in PCI command. */
10631                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10632                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10633                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10634                 }
10635         }
10636
10637         /* 5700 BX chips need to have their TX producer index mailboxes
10638          * written twice to workaround a bug.
10639          */
10640         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10641                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10642
10643         /* Back to back register writes can cause problems on this chip,
10644          * the workaround is to read back all reg writes except those to
10645          * mailbox regs.  See tg3_write_indirect_reg32().
10646          *
10647          * PCI Express 5750_A0 rev chips need this workaround too.
10648          */
10649         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10650             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10651              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10652                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10653
10654         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10655                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10656         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10657                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10658
10659         /* Chip-specific fixup from Broadcom driver */
10660         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10661             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10662                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10663                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10664         }
10665
10666         /* Default fast path register access methods */
10667         tp->read32 = tg3_read32;
10668         tp->write32 = tg3_write32;
10669         tp->read32_mbox = tg3_read32;
10670         tp->write32_mbox = tg3_write32;
10671         tp->write32_tx_mbox = tg3_write32;
10672         tp->write32_rx_mbox = tg3_write32;
10673
10674         /* Various workaround register access methods */
10675         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10676                 tp->write32 = tg3_write_indirect_reg32;
10677         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10678                 tp->write32 = tg3_write_flush_reg32;
10679
10680         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10681             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10682                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10683                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10684                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10685         }
10686
10687         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10688                 tp->read32 = tg3_read_indirect_reg32;
10689                 tp->write32 = tg3_write_indirect_reg32;
10690                 tp->read32_mbox = tg3_read_indirect_mbox;
10691                 tp->write32_mbox = tg3_write_indirect_mbox;
10692                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10693                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10694
10695                 iounmap(tp->regs);
10696                 tp->regs = NULL;
10697
10698                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10699                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10700                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10701         }
10702         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10703                 tp->read32_mbox = tg3_read32_mbox_5906;
10704                 tp->write32_mbox = tg3_write32_mbox_5906;
10705                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10706                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10707         }
10708
10709         if (tp->write32 == tg3_write_indirect_reg32 ||
10710             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10711              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10712               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10713                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10714
10715         /* Get eeprom hw config before calling tg3_set_power_state().
10716          * In particular, the TG3_FLG2_IS_NIC flag must be
10717          * determined before calling tg3_set_power_state() so that
10718          * we know whether or not to switch out of Vaux power.
10719          * When the flag is set, it means that GPIO1 is used for eeprom
10720          * write protect and also implies that it is a LOM where GPIOs
10721          * are not used to switch power.
10722          */
10723         tg3_get_eeprom_hw_cfg(tp);
10724
10725         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10726          * GPIO1 driven high will bring 5700's external PHY out of reset.
10727          * It is also used as eeprom write protect on LOMs.
10728          */
10729         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10730         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10731             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10732                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10733                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10734         /* Unused GPIO3 must be driven as output on 5752 because there
10735          * are no pull-up resistors on unused GPIO pins.
10736          */
10737         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10738                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10739
10740         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10741                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10742
10743         /* Force the chip into D0. */
10744         err = tg3_set_power_state(tp, PCI_D0);
10745         if (err) {
10746                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10747                        pci_name(tp->pdev));
10748                 return err;
10749         }
10750
10751         /* 5700 B0 chips do not support checksumming correctly due
10752          * to hardware bugs.
10753          */
10754         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10755                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10756
10757         /* Derive initial jumbo mode from MTU assigned in
10758          * ether_setup() via the alloc_etherdev() call
10759          */
10760         if (tp->dev->mtu > ETH_DATA_LEN &&
10761             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10762                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10763
10764         /* Determine WakeOnLan speed to use. */
10765         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10766             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10767             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10768             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10769                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10770         } else {
10771                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10772         }
10773
10774         /* A few boards don't want Ethernet@WireSpeed phy feature */
10775         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10776             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10777              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10778              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10779             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10780             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10781                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10782
10783         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10784             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10785                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10786         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10787                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10788
10789         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10790                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10791                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10792                         tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10793                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10794                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10795         }
10796
10797         tp->coalesce_mode = 0;
10798         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10799             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10800                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10801
10802         /* Initialize MAC MI mode, polling disabled. */
10803         tw32_f(MAC_MI_MODE, tp->mi_mode);
10804         udelay(80);
10805
10806         /* Initialize data/descriptor byte/word swapping. */
10807         val = tr32(GRC_MODE);
10808         val &= GRC_MODE_HOST_STACKUP;
10809         tw32(GRC_MODE, val | tp->grc_mode);
10810
10811         tg3_switch_clocks(tp);
10812
10813         /* Clear this out for sanity. */
10814         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10815
10816         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10817                               &pci_state_reg);
10818         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10819             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10820                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10821
10822                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10823                     chiprevid == CHIPREV_ID_5701_B0 ||
10824                     chiprevid == CHIPREV_ID_5701_B2 ||
10825                     chiprevid == CHIPREV_ID_5701_B5) {
10826                         void __iomem *sram_base;
10827
10828                         /* Write some dummy words into the SRAM status block
10829                          * area, see if it reads back correctly.  If the return
10830                          * value is bad, force enable the PCIX workaround.
10831                          */
10832                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10833
10834                         writel(0x00000000, sram_base);
10835                         writel(0x00000000, sram_base + 4);
10836                         writel(0xffffffff, sram_base + 4);
10837                         if (readl(sram_base) != 0x00000000)
10838                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10839                 }
10840         }
10841
10842         udelay(50);
10843         tg3_nvram_init(tp);
10844
10845         grc_misc_cfg = tr32(GRC_MISC_CFG);
10846         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10847
10848         /* Broadcom's driver says that CIOBE multisplit has a bug */
10849 #if 0
10850         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10851             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10852                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10853                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10854         }
10855 #endif
10856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10857             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10858              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10859                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10860
10861         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10862             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10863                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10864         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10865                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10866                                       HOSTCC_MODE_CLRTICK_TXBD);
10867
10868                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10869                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10870                                        tp->misc_host_ctrl);
10871         }
10872
10873         /* these are limited to 10/100 only */
10874         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10875              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10876             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10877              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10878              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10879               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10880               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10881             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10882              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10883               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10884               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10885             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10886                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10887
10888         err = tg3_phy_probe(tp);
10889         if (err) {
10890                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10891                        pci_name(tp->pdev), err);
10892                 /* ... but do not return immediately ... */
10893         }
10894
10895         tg3_read_partno(tp);
10896         tg3_read_fw_ver(tp);
10897
10898         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10899                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10900         } else {
10901                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10902                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10903                 else
10904                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10905         }
10906
10907         /* 5700 {AX,BX} chips have a broken status block link
10908          * change bit implementation, so we must use the
10909          * status register in those cases.
10910          */
10911         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10912                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10913         else
10914                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10915
10916         /* The led_ctrl is set during tg3_phy_probe, here we might
10917          * have to force the link status polling mechanism based
10918          * upon subsystem IDs.
10919          */
10920         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10921             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10922                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10923                                   TG3_FLAG_USE_LINKCHG_REG);
10924         }
10925
10926         /* For all SERDES we poll the MAC status register. */
10927         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10928                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10929         else
10930                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10931
10932         /* All chips before 5787 can get confused if TX buffers
10933          * straddle the 4GB address boundary in some cases.
10934          */
10935         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10936             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10937             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10938                 tp->dev->hard_start_xmit = tg3_start_xmit;
10939         else
10940                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10941
10942         tp->rx_offset = 2;
10943         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10944             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10945                 tp->rx_offset = 0;
10946
10947         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10948
10949         /* Increment the rx prod index on the rx std ring by at most
10950          * 8 for these chips to workaround hw errata.
10951          */
10952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10953             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10954             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10955                 tp->rx_std_max_post = 8;
10956
10957         /* By default, disable wake-on-lan.  User can change this
10958          * using ETHTOOL_SWOL.
10959          */
10960         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10961
10962         return err;
10963 }
10964
10965 #ifdef CONFIG_SPARC64
10966 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10967 {
10968         struct net_device *dev = tp->dev;
10969         struct pci_dev *pdev = tp->pdev;
10970         struct pcidev_cookie *pcp = pdev->sysdata;
10971
10972         if (pcp != NULL) {
10973                 unsigned char *addr;
10974                 int len;
10975
10976                 addr = of_get_property(pcp->prom_node, "local-mac-address",
10977                                         &len);
10978                 if (addr && len == 6) {
10979                         memcpy(dev->dev_addr, addr, 6);
10980                         memcpy(dev->perm_addr, dev->dev_addr, 6);
10981                         return 0;
10982                 }
10983         }
10984         return -ENODEV;
10985 }
10986
10987 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
10988 {
10989         struct net_device *dev = tp->dev;
10990
10991         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
10992         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
10993         return 0;
10994 }
10995 #endif
10996
10997 static int __devinit tg3_get_device_address(struct tg3 *tp)
10998 {
10999         struct net_device *dev = tp->dev;
11000         u32 hi, lo, mac_offset;
11001         int addr_ok = 0;
11002
11003 #ifdef CONFIG_SPARC64
11004         if (!tg3_get_macaddr_sparc(tp))
11005                 return 0;
11006 #endif
11007
11008         mac_offset = 0x7c;
11009         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11010             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11011                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11012                         mac_offset = 0xcc;
11013                 if (tg3_nvram_lock(tp))
11014                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11015                 else
11016                         tg3_nvram_unlock(tp);
11017         }
11018         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11019                 mac_offset = 0x10;
11020
11021         /* First try to get it from MAC address mailbox. */
11022         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11023         if ((hi >> 16) == 0x484b) {
11024                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11025                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11026
11027                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11028                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11029                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11030                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11031                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11032
11033                 /* Some old bootcode may report a 0 MAC address in SRAM */
11034                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11035         }
11036         if (!addr_ok) {
11037                 /* Next, try NVRAM. */
11038                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11039                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11040                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11041                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11042                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11043                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11044                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11045                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11046                 }
11047                 /* Finally just fetch it out of the MAC control regs. */
11048                 else {
11049                         hi = tr32(MAC_ADDR_0_HIGH);
11050                         lo = tr32(MAC_ADDR_0_LOW);
11051
11052                         dev->dev_addr[5] = lo & 0xff;
11053                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11054                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11055                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11056                         dev->dev_addr[1] = hi & 0xff;
11057                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11058                 }
11059         }
11060
11061         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11062 #ifdef CONFIG_SPARC64
11063                 if (!tg3_get_default_macaddr_sparc(tp))
11064                         return 0;
11065 #endif
11066                 return -EINVAL;
11067         }
11068         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11069         return 0;
11070 }
11071
11072 #define BOUNDARY_SINGLE_CACHELINE       1
11073 #define BOUNDARY_MULTI_CACHELINE        2
11074
11075 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11076 {
11077         int cacheline_size;
11078         u8 byte;
11079         int goal;
11080
11081         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11082         if (byte == 0)
11083                 cacheline_size = 1024;
11084         else
11085                 cacheline_size = (int) byte * 4;
11086
11087         /* On 5703 and later chips, the boundary bits have no
11088          * effect.
11089          */
11090         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11091             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11092             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11093                 goto out;
11094
11095 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11096         goal = BOUNDARY_MULTI_CACHELINE;
11097 #else
11098 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11099         goal = BOUNDARY_SINGLE_CACHELINE;
11100 #else
11101         goal = 0;
11102 #endif
11103 #endif
11104
11105         if (!goal)
11106                 goto out;
11107
11108         /* PCI controllers on most RISC systems tend to disconnect
11109          * when a device tries to burst across a cache-line boundary.
11110          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11111          *
11112          * Unfortunately, for PCI-E there are only limited
11113          * write-side controls for this, and thus for reads
11114          * we will still get the disconnects.  We'll also waste
11115          * these PCI cycles for both read and write for chips
11116          * other than 5700 and 5701 which do not implement the
11117          * boundary bits.
11118          */
11119         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11120             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11121                 switch (cacheline_size) {
11122                 case 16:
11123                 case 32:
11124                 case 64:
11125                 case 128:
11126                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11127                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11128                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11129                         } else {
11130                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11131                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11132                         }
11133                         break;
11134
11135                 case 256:
11136                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11137                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11138                         break;
11139
11140                 default:
11141                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11142                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11143                         break;
11144                 };
11145         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11146                 switch (cacheline_size) {
11147                 case 16:
11148                 case 32:
11149                 case 64:
11150                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11151                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11152                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11153                                 break;
11154                         }
11155                         /* fallthrough */
11156                 case 128:
11157                 default:
11158                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11159                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11160                         break;
11161                 };
11162         } else {
11163                 switch (cacheline_size) {
11164                 case 16:
11165                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11166                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11167                                         DMA_RWCTRL_WRITE_BNDRY_16);
11168                                 break;
11169                         }
11170                         /* fallthrough */
11171                 case 32:
11172                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11173                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11174                                         DMA_RWCTRL_WRITE_BNDRY_32);
11175                                 break;
11176                         }
11177                         /* fallthrough */
11178                 case 64:
11179                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11180                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11181                                         DMA_RWCTRL_WRITE_BNDRY_64);
11182                                 break;
11183                         }
11184                         /* fallthrough */
11185                 case 128:
11186                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11187                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11188                                         DMA_RWCTRL_WRITE_BNDRY_128);
11189                                 break;
11190                         }
11191                         /* fallthrough */
11192                 case 256:
11193                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11194                                 DMA_RWCTRL_WRITE_BNDRY_256);
11195                         break;
11196                 case 512:
11197                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11198                                 DMA_RWCTRL_WRITE_BNDRY_512);
11199                         break;
11200                 case 1024:
11201                 default:
11202                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11203                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11204                         break;
11205                 };
11206         }
11207
11208 out:
11209         return val;
11210 }
11211
11212 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11213 {
11214         struct tg3_internal_buffer_desc test_desc;
11215         u32 sram_dma_descs;
11216         int i, ret;
11217
11218         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11219
11220         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11221         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11222         tw32(RDMAC_STATUS, 0);
11223         tw32(WDMAC_STATUS, 0);
11224
11225         tw32(BUFMGR_MODE, 0);
11226         tw32(FTQ_RESET, 0);
11227
11228         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11229         test_desc.addr_lo = buf_dma & 0xffffffff;
11230         test_desc.nic_mbuf = 0x00002100;
11231         test_desc.len = size;
11232
11233         /*
11234          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11235          * the *second* time the tg3 driver was getting loaded after an
11236          * initial scan.
11237          *
11238          * Broadcom tells me:
11239          *   ...the DMA engine is connected to the GRC block and a DMA
11240          *   reset may affect the GRC block in some unpredictable way...
11241          *   The behavior of resets to individual blocks has not been tested.
11242          *
11243          * Broadcom noted the GRC reset will also reset all sub-components.
11244          */
11245         if (to_device) {
11246                 test_desc.cqid_sqid = (13 << 8) | 2;
11247
11248                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11249                 udelay(40);
11250         } else {
11251                 test_desc.cqid_sqid = (16 << 8) | 7;
11252
11253                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11254                 udelay(40);
11255         }
11256         test_desc.flags = 0x00000005;
11257
11258         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11259                 u32 val;
11260
11261                 val = *(((u32 *)&test_desc) + i);
11262                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11263                                        sram_dma_descs + (i * sizeof(u32)));
11264                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11265         }
11266         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11267
11268         if (to_device) {
11269                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11270         } else {
11271                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11272         }
11273
11274         ret = -ENODEV;
11275         for (i = 0; i < 40; i++) {
11276                 u32 val;
11277
11278                 if (to_device)
11279                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11280                 else
11281                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11282                 if ((val & 0xffff) == sram_dma_descs) {
11283                         ret = 0;
11284                         break;
11285                 }
11286
11287                 udelay(100);
11288         }
11289
11290         return ret;
11291 }
11292
11293 #define TEST_BUFFER_SIZE        0x2000
11294
11295 static int __devinit tg3_test_dma(struct tg3 *tp)
11296 {
11297         dma_addr_t buf_dma;
11298         u32 *buf, saved_dma_rwctrl;
11299         int ret;
11300
11301         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11302         if (!buf) {
11303                 ret = -ENOMEM;
11304                 goto out_nofree;
11305         }
11306
11307         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11308                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11309
11310         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11311
11312         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11313                 /* DMA read watermark not used on PCIE */
11314                 tp->dma_rwctrl |= 0x00180000;
11315         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11316                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11317                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11318                         tp->dma_rwctrl |= 0x003f0000;
11319                 else
11320                         tp->dma_rwctrl |= 0x003f000f;
11321         } else {
11322                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11323                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11324                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11325
11326                         /* If the 5704 is behind the EPB bridge, we can
11327                          * do the less restrictive ONE_DMA workaround for
11328                          * better performance.
11329                          */
11330                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11331                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11332                                 tp->dma_rwctrl |= 0x8000;
11333                         else if (ccval == 0x6 || ccval == 0x7)
11334                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11335
11336                         /* Set bit 23 to enable PCIX hw bug fix */
11337                         tp->dma_rwctrl |= 0x009f0000;
11338                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11339                         /* 5780 always in PCIX mode */
11340                         tp->dma_rwctrl |= 0x00144000;
11341                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11342                         /* 5714 always in PCIX mode */
11343                         tp->dma_rwctrl |= 0x00148000;
11344                 } else {
11345                         tp->dma_rwctrl |= 0x001b000f;
11346                 }
11347         }
11348
11349         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11350             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11351                 tp->dma_rwctrl &= 0xfffffff0;
11352
11353         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11354             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11355                 /* Remove this if it causes problems for some boards. */
11356                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11357
11358                 /* On 5700/5701 chips, we need to set this bit.
11359                  * Otherwise the chip will issue cacheline transactions
11360                  * to streamable DMA memory with not all the byte
11361                  * enables turned on.  This is an error on several
11362                  * RISC PCI controllers, in particular sparc64.
11363                  *
11364                  * On 5703/5704 chips, this bit has been reassigned
11365                  * a different meaning.  In particular, it is used
11366                  * on those chips to enable a PCI-X workaround.
11367                  */
11368                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11369         }
11370
11371         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11372
11373 #if 0
11374         /* Unneeded, already done by tg3_get_invariants.  */
11375         tg3_switch_clocks(tp);
11376 #endif
11377
11378         ret = 0;
11379         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11380             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11381                 goto out;
11382
11383         /* It is best to perform DMA test with maximum write burst size
11384          * to expose the 5700/5701 write DMA bug.
11385          */
11386         saved_dma_rwctrl = tp->dma_rwctrl;
11387         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11388         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11389
11390         while (1) {
11391                 u32 *p = buf, i;
11392
11393                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11394                         p[i] = i;
11395
11396                 /* Send the buffer to the chip. */
11397                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11398                 if (ret) {
11399                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11400                         break;
11401                 }
11402
11403 #if 0
11404                 /* validate data reached card RAM correctly. */
11405                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11406                         u32 val;
11407                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11408                         if (le32_to_cpu(val) != p[i]) {
11409                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11410                                 /* ret = -ENODEV here? */
11411                         }
11412                         p[i] = 0;
11413                 }
11414 #endif
11415                 /* Now read it back. */
11416                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11417                 if (ret) {
11418                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11419
11420                         break;
11421                 }
11422
11423                 /* Verify it. */
11424                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11425                         if (p[i] == i)
11426                                 continue;
11427
11428                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11429                             DMA_RWCTRL_WRITE_BNDRY_16) {
11430                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11431                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11432                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11433                                 break;
11434                         } else {
11435                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11436                                 ret = -ENODEV;
11437                                 goto out;
11438                         }
11439                 }
11440
11441                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11442                         /* Success. */
11443                         ret = 0;
11444                         break;
11445                 }
11446         }
11447         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11448             DMA_RWCTRL_WRITE_BNDRY_16) {
11449                 static struct pci_device_id dma_wait_state_chipsets[] = {
11450                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11451                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11452                         { },
11453                 };
11454
11455                 /* DMA test passed without adjusting DMA boundary,
11456                  * now look for chipsets that are known to expose the
11457                  * DMA bug without failing the test.
11458                  */
11459                 if (pci_dev_present(dma_wait_state_chipsets)) {
11460                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11461                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11462                 }
11463                 else
11464                         /* Safe to use the calculated DMA boundary. */
11465                         tp->dma_rwctrl = saved_dma_rwctrl;
11466
11467                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11468         }
11469
11470 out:
11471         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11472 out_nofree:
11473         return ret;
11474 }
11475
11476 static void __devinit tg3_init_link_config(struct tg3 *tp)
11477 {
11478         tp->link_config.advertising =
11479                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11480                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11481                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11482                  ADVERTISED_Autoneg | ADVERTISED_MII);
11483         tp->link_config.speed = SPEED_INVALID;
11484         tp->link_config.duplex = DUPLEX_INVALID;
11485         tp->link_config.autoneg = AUTONEG_ENABLE;
11486         tp->link_config.active_speed = SPEED_INVALID;
11487         tp->link_config.active_duplex = DUPLEX_INVALID;
11488         tp->link_config.phy_is_low_power = 0;
11489         tp->link_config.orig_speed = SPEED_INVALID;
11490         tp->link_config.orig_duplex = DUPLEX_INVALID;
11491         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11492 }
11493
11494 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11495 {
11496         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11497                 tp->bufmgr_config.mbuf_read_dma_low_water =
11498                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11499                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11500                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11501                 tp->bufmgr_config.mbuf_high_water =
11502                         DEFAULT_MB_HIGH_WATER_5705;
11503                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11504                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11505                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11506                         tp->bufmgr_config.mbuf_high_water =
11507                                 DEFAULT_MB_HIGH_WATER_5906;
11508                 }
11509
11510                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11511                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11512                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11513                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11514                 tp->bufmgr_config.mbuf_high_water_jumbo =
11515                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11516         } else {
11517                 tp->bufmgr_config.mbuf_read_dma_low_water =
11518                         DEFAULT_MB_RDMA_LOW_WATER;
11519                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11520                         DEFAULT_MB_MACRX_LOW_WATER;
11521                 tp->bufmgr_config.mbuf_high_water =
11522                         DEFAULT_MB_HIGH_WATER;
11523
11524                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11525                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11526                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11527                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11528                 tp->bufmgr_config.mbuf_high_water_jumbo =
11529                         DEFAULT_MB_HIGH_WATER_JUMBO;
11530         }
11531
11532         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11533         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11534 }
11535
11536 static char * __devinit tg3_phy_string(struct tg3 *tp)
11537 {
11538         switch (tp->phy_id & PHY_ID_MASK) {
11539         case PHY_ID_BCM5400:    return "5400";
11540         case PHY_ID_BCM5401:    return "5401";
11541         case PHY_ID_BCM5411:    return "5411";
11542         case PHY_ID_BCM5701:    return "5701";
11543         case PHY_ID_BCM5703:    return "5703";
11544         case PHY_ID_BCM5704:    return "5704";
11545         case PHY_ID_BCM5705:    return "5705";
11546         case PHY_ID_BCM5750:    return "5750";
11547         case PHY_ID_BCM5752:    return "5752";
11548         case PHY_ID_BCM5714:    return "5714";
11549         case PHY_ID_BCM5780:    return "5780";
11550         case PHY_ID_BCM5755:    return "5755";
11551         case PHY_ID_BCM5787:    return "5787";
11552         case PHY_ID_BCM5756:    return "5722/5756";
11553         case PHY_ID_BCM5906:    return "5906";
11554         case PHY_ID_BCM8002:    return "8002/serdes";
11555         case 0:                 return "serdes";
11556         default:                return "unknown";
11557         };
11558 }
11559
11560 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11561 {
11562         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11563                 strcpy(str, "PCI Express");
11564                 return str;
11565         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11566                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11567
11568                 strcpy(str, "PCIX:");
11569
11570                 if ((clock_ctrl == 7) ||
11571                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11572                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11573                         strcat(str, "133MHz");
11574                 else if (clock_ctrl == 0)
11575                         strcat(str, "33MHz");
11576                 else if (clock_ctrl == 2)
11577                         strcat(str, "50MHz");
11578                 else if (clock_ctrl == 4)
11579                         strcat(str, "66MHz");
11580                 else if (clock_ctrl == 6)
11581                         strcat(str, "100MHz");
11582         } else {
11583                 strcpy(str, "PCI:");
11584                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11585                         strcat(str, "66MHz");
11586                 else
11587                         strcat(str, "33MHz");
11588         }
11589         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11590                 strcat(str, ":32-bit");
11591         else
11592                 strcat(str, ":64-bit");
11593         return str;
11594 }
11595
11596 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11597 {
11598         struct pci_dev *peer;
11599         unsigned int func, devnr = tp->pdev->devfn & ~7;
11600
11601         for (func = 0; func < 8; func++) {
11602                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11603                 if (peer && peer != tp->pdev)
11604                         break;
11605                 pci_dev_put(peer);
11606         }
11607         /* 5704 can be configured in single-port mode, set peer to
11608          * tp->pdev in that case.
11609          */
11610         if (!peer) {
11611                 peer = tp->pdev;
11612                 return peer;
11613         }
11614
11615         /*
11616          * We don't need to keep the refcount elevated; there's no way
11617          * to remove one half of this device without removing the other
11618          */
11619         pci_dev_put(peer);
11620
11621         return peer;
11622 }
11623
11624 static void __devinit tg3_init_coal(struct tg3 *tp)
11625 {
11626         struct ethtool_coalesce *ec = &tp->coal;
11627
11628         memset(ec, 0, sizeof(*ec));
11629         ec->cmd = ETHTOOL_GCOALESCE;
11630         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11631         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11632         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11633         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11634         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11635         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11636         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11637         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11638         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11639
11640         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11641                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11642                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11643                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11644                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11645                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11646         }
11647
11648         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11649                 ec->rx_coalesce_usecs_irq = 0;
11650                 ec->tx_coalesce_usecs_irq = 0;
11651                 ec->stats_block_coalesce_usecs = 0;
11652         }
11653 }
11654
11655 static int __devinit tg3_init_one(struct pci_dev *pdev,
11656                                   const struct pci_device_id *ent)
11657 {
11658         static int tg3_version_printed = 0;
11659         unsigned long tg3reg_base, tg3reg_len;
11660         struct net_device *dev;
11661         struct tg3 *tp;
11662         int i, err, pm_cap;
11663         char str[40];
11664         u64 dma_mask, persist_dma_mask;
11665
11666         if (tg3_version_printed++ == 0)
11667                 printk(KERN_INFO "%s", version);
11668
11669         err = pci_enable_device(pdev);
11670         if (err) {
11671                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11672                        "aborting.\n");
11673                 return err;
11674         }
11675
11676         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11677                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11678                        "base address, aborting.\n");
11679                 err = -ENODEV;
11680                 goto err_out_disable_pdev;
11681         }
11682
11683         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11684         if (err) {
11685                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11686                        "aborting.\n");
11687                 goto err_out_disable_pdev;
11688         }
11689
11690         pci_set_master(pdev);
11691
11692         /* Find power-management capability. */
11693         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11694         if (pm_cap == 0) {
11695                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11696                        "aborting.\n");
11697                 err = -EIO;
11698                 goto err_out_free_res;
11699         }
11700
11701         tg3reg_base = pci_resource_start(pdev, 0);
11702         tg3reg_len = pci_resource_len(pdev, 0);
11703
11704         dev = alloc_etherdev(sizeof(*tp));
11705         if (!dev) {
11706                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11707                 err = -ENOMEM;
11708                 goto err_out_free_res;
11709         }
11710
11711         SET_MODULE_OWNER(dev);
11712         SET_NETDEV_DEV(dev, &pdev->dev);
11713
11714 #if TG3_VLAN_TAG_USED
11715         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11716         dev->vlan_rx_register = tg3_vlan_rx_register;
11717         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11718 #endif
11719
11720         tp = netdev_priv(dev);
11721         tp->pdev = pdev;
11722         tp->dev = dev;
11723         tp->pm_cap = pm_cap;
11724         tp->mac_mode = TG3_DEF_MAC_MODE;
11725         tp->rx_mode = TG3_DEF_RX_MODE;
11726         tp->tx_mode = TG3_DEF_TX_MODE;
11727         tp->mi_mode = MAC_MI_MODE_BASE;
11728         if (tg3_debug > 0)
11729                 tp->msg_enable = tg3_debug;
11730         else
11731                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11732
11733         /* The word/byte swap controls here control register access byte
11734          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11735          * setting below.
11736          */
11737         tp->misc_host_ctrl =
11738                 MISC_HOST_CTRL_MASK_PCI_INT |
11739                 MISC_HOST_CTRL_WORD_SWAP |
11740                 MISC_HOST_CTRL_INDIR_ACCESS |
11741                 MISC_HOST_CTRL_PCISTATE_RW;
11742
11743         /* The NONFRM (non-frame) byte/word swap controls take effect
11744          * on descriptor entries, anything which isn't packet data.
11745          *
11746          * The StrongARM chips on the board (one for tx, one for rx)
11747          * are running in big-endian mode.
11748          */
11749         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11750                         GRC_MODE_WSWAP_NONFRM_DATA);
11751 #ifdef __BIG_ENDIAN
11752         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11753 #endif
11754         spin_lock_init(&tp->lock);
11755         spin_lock_init(&tp->indirect_lock);
11756         INIT_WORK(&tp->reset_task, tg3_reset_task);
11757
11758         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11759         if (tp->regs == 0UL) {
11760                 printk(KERN_ERR PFX "Cannot map device registers, "
11761                        "aborting.\n");
11762                 err = -ENOMEM;
11763                 goto err_out_free_dev;
11764         }
11765
11766         tg3_init_link_config(tp);
11767
11768         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11769         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11770         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11771
11772         dev->open = tg3_open;
11773         dev->stop = tg3_close;
11774         dev->get_stats = tg3_get_stats;
11775         dev->set_multicast_list = tg3_set_rx_mode;
11776         dev->set_mac_address = tg3_set_mac_addr;
11777         dev->do_ioctl = tg3_ioctl;
11778         dev->tx_timeout = tg3_tx_timeout;
11779         dev->poll = tg3_poll;
11780         dev->ethtool_ops = &tg3_ethtool_ops;
11781         dev->weight = 64;
11782         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11783         dev->change_mtu = tg3_change_mtu;
11784         dev->irq = pdev->irq;
11785 #ifdef CONFIG_NET_POLL_CONTROLLER
11786         dev->poll_controller = tg3_poll_controller;
11787 #endif
11788
11789         err = tg3_get_invariants(tp);
11790         if (err) {
11791                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11792                        "aborting.\n");
11793                 goto err_out_iounmap;
11794         }
11795
11796         /* The EPB bridge inside 5714, 5715, and 5780 and any
11797          * device behind the EPB cannot support DMA addresses > 40-bit.
11798          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11799          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11800          * do DMA address check in tg3_start_xmit().
11801          */
11802         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11803                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11804         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11805                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11806 #ifdef CONFIG_HIGHMEM
11807                 dma_mask = DMA_64BIT_MASK;
11808 #endif
11809         } else
11810                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11811
11812         /* Configure DMA attributes. */
11813         if (dma_mask > DMA_32BIT_MASK) {
11814                 err = pci_set_dma_mask(pdev, dma_mask);
11815                 if (!err) {
11816                         dev->features |= NETIF_F_HIGHDMA;
11817                         err = pci_set_consistent_dma_mask(pdev,
11818                                                           persist_dma_mask);
11819                         if (err < 0) {
11820                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11821                                        "DMA for consistent allocations\n");
11822                                 goto err_out_iounmap;
11823                         }
11824                 }
11825         }
11826         if (err || dma_mask == DMA_32BIT_MASK) {
11827                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11828                 if (err) {
11829                         printk(KERN_ERR PFX "No usable DMA configuration, "
11830                                "aborting.\n");
11831                         goto err_out_iounmap;
11832                 }
11833         }
11834
11835         tg3_init_bufmgr_config(tp);
11836
11837 #if TG3_TSO_SUPPORT != 0
11838         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11839                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11840         }
11841         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11842             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11843             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11844             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11845             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11846                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11847         } else {
11848                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11849         }
11850
11851         /* TSO is on by default on chips that support hardware TSO.
11852          * Firmware TSO on older chips gives lower performance, so it
11853          * is off by default, but can be enabled using ethtool.
11854          */
11855         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11856                 dev->features |= NETIF_F_TSO;
11857                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11858                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11859                         dev->features |= NETIF_F_TSO6;
11860         }
11861
11862 #endif
11863
11864         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11865             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11866             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11867                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11868                 tp->rx_pending = 63;
11869         }
11870
11871         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11872             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11873                 tp->pdev_peer = tg3_find_peer(tp);
11874
11875         err = tg3_get_device_address(tp);
11876         if (err) {
11877                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11878                        "aborting.\n");
11879                 goto err_out_iounmap;
11880         }
11881
11882         /*
11883          * Reset chip in case UNDI or EFI driver did not shutdown
11884          * DMA self test will enable WDMAC and we'll see (spurious)
11885          * pending DMA on the PCI bus at that point.
11886          */
11887         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11888             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11889                 pci_save_state(tp->pdev);
11890                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11891                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11892         }
11893
11894         err = tg3_test_dma(tp);
11895         if (err) {
11896                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11897                 goto err_out_iounmap;
11898         }
11899
11900         /* Tigon3 can do ipv4 only... and some chips have buggy
11901          * checksumming.
11902          */
11903         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11904                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11905                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11906                         dev->features |= NETIF_F_HW_CSUM;
11907                 else
11908                         dev->features |= NETIF_F_IP_CSUM;
11909                 dev->features |= NETIF_F_SG;
11910                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11911         } else
11912                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11913
11914         /* flow control autonegotiation is default behavior */
11915         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11916
11917         tg3_init_coal(tp);
11918
11919         /* Now that we have fully setup the chip, save away a snapshot
11920          * of the PCI config space.  We need to restore this after
11921          * GRC_MISC_CFG core clock resets and some resume events.
11922          */
11923         pci_save_state(tp->pdev);
11924
11925         err = register_netdev(dev);
11926         if (err) {
11927                 printk(KERN_ERR PFX "Cannot register net device, "
11928                        "aborting.\n");
11929                 goto err_out_iounmap;
11930         }
11931
11932         pci_set_drvdata(pdev, dev);
11933
11934         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %sBaseT Ethernet ",
11935                dev->name,
11936                tp->board_part_number,
11937                tp->pci_chip_rev_id,
11938                tg3_phy_string(tp),
11939                tg3_bus_string(tp, str),
11940                (tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100" : "10/100/1000");
11941
11942         for (i = 0; i < 6; i++)
11943                 printk("%2.2x%c", dev->dev_addr[i],
11944                        i == 5 ? '\n' : ':');
11945
11946         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11947                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11948                "TSOcap[%d] \n",
11949                dev->name,
11950                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11951                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11952                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11953                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11954                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11955                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11956                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11957         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11958                dev->name, tp->dma_rwctrl,
11959                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11960                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11961
11962         netif_carrier_off(tp->dev);
11963
11964         return 0;
11965
11966 err_out_iounmap:
11967         if (tp->regs) {
11968                 iounmap(tp->regs);
11969                 tp->regs = NULL;
11970         }
11971
11972 err_out_free_dev:
11973         free_netdev(dev);
11974
11975 err_out_free_res:
11976         pci_release_regions(pdev);
11977
11978 err_out_disable_pdev:
11979         pci_disable_device(pdev);
11980         pci_set_drvdata(pdev, NULL);
11981         return err;
11982 }
11983
11984 static void __devexit tg3_remove_one(struct pci_dev *pdev)
11985 {
11986         struct net_device *dev = pci_get_drvdata(pdev);
11987
11988         if (dev) {
11989                 struct tg3 *tp = netdev_priv(dev);
11990
11991                 flush_scheduled_work();
11992                 unregister_netdev(dev);
11993                 if (tp->regs) {
11994                         iounmap(tp->regs);
11995                         tp->regs = NULL;
11996                 }
11997                 free_netdev(dev);
11998                 pci_release_regions(pdev);
11999                 pci_disable_device(pdev);
12000                 pci_set_drvdata(pdev, NULL);
12001         }
12002 }
12003
12004 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12005 {
12006         struct net_device *dev = pci_get_drvdata(pdev);
12007         struct tg3 *tp = netdev_priv(dev);
12008         int err;
12009
12010         if (!netif_running(dev))
12011                 return 0;
12012
12013         flush_scheduled_work();
12014         tg3_netif_stop(tp);
12015
12016         del_timer_sync(&tp->timer);
12017
12018         tg3_full_lock(tp, 1);
12019         tg3_disable_ints(tp);
12020         tg3_full_unlock(tp);
12021
12022         netif_device_detach(dev);
12023
12024         tg3_full_lock(tp, 0);
12025         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12026         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12027         tg3_full_unlock(tp);
12028
12029         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12030         if (err) {
12031                 tg3_full_lock(tp, 0);
12032
12033                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12034                 if (tg3_restart_hw(tp, 1))
12035                         goto out;
12036
12037                 tp->timer.expires = jiffies + tp->timer_offset;
12038                 add_timer(&tp->timer);
12039
12040                 netif_device_attach(dev);
12041                 tg3_netif_start(tp);
12042
12043 out:
12044                 tg3_full_unlock(tp);
12045         }
12046
12047         return err;
12048 }
12049
12050 static int tg3_resume(struct pci_dev *pdev)
12051 {
12052         struct net_device *dev = pci_get_drvdata(pdev);
12053         struct tg3 *tp = netdev_priv(dev);
12054         int err;
12055
12056         if (!netif_running(dev))
12057                 return 0;
12058
12059         pci_restore_state(tp->pdev);
12060
12061         err = tg3_set_power_state(tp, PCI_D0);
12062         if (err)
12063                 return err;
12064
12065         netif_device_attach(dev);
12066
12067         tg3_full_lock(tp, 0);
12068
12069         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12070         err = tg3_restart_hw(tp, 1);
12071         if (err)
12072                 goto out;
12073
12074         tp->timer.expires = jiffies + tp->timer_offset;
12075         add_timer(&tp->timer);
12076
12077         tg3_netif_start(tp);
12078
12079 out:
12080         tg3_full_unlock(tp);
12081
12082         return err;
12083 }
12084
12085 static struct pci_driver tg3_driver = {
12086         .name           = DRV_MODULE_NAME,
12087         .id_table       = tg3_pci_tbl,
12088         .probe          = tg3_init_one,
12089         .remove         = __devexit_p(tg3_remove_one),
12090         .suspend        = tg3_suspend,
12091         .resume         = tg3_resume
12092 };
12093
12094 static int __init tg3_init(void)
12095 {
12096         return pci_register_driver(&tg3_driver);
12097 }
12098
12099 static void __exit tg3_cleanup(void)
12100 {
12101         pci_unregister_driver(&tg3_driver);
12102 }
12103
12104 module_init(tg3_init);
12105 module_exit(tg3_cleanup);