2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/config.h>
32 #include <linux/crc32.h>
33 #include <linux/kernel.h>
34 #include <linux/version.h>
35 #include <linux/module.h>
36 #include <linux/netdevice.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/etherdevice.h>
39 #include <linux/ethtool.h>
40 #include <linux/pci.h>
42 #include <linux/tcp.h>
44 #include <linux/delay.h>
45 #include <linux/workqueue.h>
46 #include <linux/if_vlan.h>
47 #include <linux/prefetch.h>
48 #include <linux/mii.h>
52 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53 #define SKY2_VLAN_TAG_USED 1
58 #define DRV_NAME "sky2"
59 #define DRV_VERSION "0.13"
60 #define PFX DRV_NAME " "
63 * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 * that are organized into three (receive, transmit, status) different rings
65 * similar to Tigon3. A transmit can require several elements;
66 * a receive requires one (or two if using 64 bit dma).
69 #define is_ec_a1(hw) \
70 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
71 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
73 #define RX_LE_SIZE 512
74 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
75 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
76 #define RX_DEF_PENDING RX_MAX_PENDING
77 #define RX_SKB_ALIGN 8
79 #define TX_RING_SIZE 512
80 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
81 #define TX_MIN_PENDING 64
82 #define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
84 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
85 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
86 #define ETH_JUMBO_MTU 9000
87 #define TX_WATCHDOG (5 * HZ)
88 #define NAPI_WEIGHT 64
89 #define PHY_RETRIES 1000
91 static const u32 default_msg =
92 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
93 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
94 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
96 static int debug = -1; /* defaults above */
97 module_param(debug, int, 0);
98 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
100 static int copybreak __read_mostly = 256;
101 module_param(copybreak, int, 0);
102 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
104 static const struct pci_device_id sky2_id_table[] = {
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
127 MODULE_DEVICE_TABLE(pci, sky2_id_table);
129 /* Avoid conditionals by using array */
130 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
131 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
133 /* This driver supports yukon2 chipset only */
134 static const char *yukon2_name[] = {
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
142 /* Access to external PHY */
143 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151 for (i = 0; i < PHY_RETRIES; i++) {
152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
161 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
165 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
166 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168 for (i = 0; i < PHY_RETRIES; i++) {
169 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 *val = gma_read16(hw, port, GM_SMI_DATA);
180 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
184 if (__gm_phy_read(hw, port, reg, &v) != 0)
185 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
189 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
199 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
200 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
201 (power_control & PCI_PM_CAP_PME_D3cold);
203 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
226 /* Turn off phy power saving */
227 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230 /* looks like this XL is back asswards .. */
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
234 reg1 |= PCI_Y2_PHY2_COMA;
236 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
241 /* Turn on phy power saving */
242 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1);
243 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
244 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
247 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
249 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
250 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
252 /* enable bits are inverted */
253 sky2_write8(hw, B2_Y2_CLK_GATE,
254 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
255 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
256 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
258 /* switch power to VAUX */
259 if (vaux && state != PCI_D3cold)
260 sky2_write8(hw, B0_POWER_CTRL,
261 (PC_VAUX_ENA | PC_VCC_ENA |
262 PC_VAUX_ON | PC_VCC_OFF));
265 printk(KERN_ERR PFX "Unknown power state %d\n", state);
269 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
270 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
274 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
278 /* disable all GMAC IRQ's */
279 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
280 /* disable PHY IRQs */
281 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
283 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
284 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
286 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
288 reg = gma_read16(hw, port, GM_RX_CTRL);
289 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
290 gma_write16(hw, port, GM_RX_CTRL, reg);
293 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
296 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
298 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
299 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
301 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
303 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
305 if (hw->chip_id == CHIP_ID_YUKON_EC)
306 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
308 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
310 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
313 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
315 if (hw->chip_id == CHIP_ID_YUKON_FE) {
316 /* enable automatic crossover */
317 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
319 /* disable energy detect */
320 ctrl &= ~PHY_M_PC_EN_DET_MSK;
322 /* enable automatic crossover */
323 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
325 if (sky2->autoneg == AUTONEG_ENABLE &&
326 hw->chip_id == CHIP_ID_YUKON_XL) {
327 ctrl &= ~PHY_M_PC_DSC_MSK;
328 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
331 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
333 /* workaround for deviation #4.88 (CRC errors) */
334 /* disable Automatic Crossover */
336 ctrl &= ~PHY_M_PC_MDIX_MSK;
337 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
339 if (hw->chip_id == CHIP_ID_YUKON_XL) {
340 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
341 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
342 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
343 ctrl &= ~PHY_M_MAC_MD_MSK;
344 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
345 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
353 if (sky2->autoneg == AUTONEG_DISABLE)
358 ctrl |= PHY_CT_RESET;
359 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
365 if (sky2->autoneg == AUTONEG_ENABLE) {
367 if (sky2->advertising & ADVERTISED_1000baseT_Full)
368 ct1000 |= PHY_M_1000C_AFD;
369 if (sky2->advertising & ADVERTISED_1000baseT_Half)
370 ct1000 |= PHY_M_1000C_AHD;
371 if (sky2->advertising & ADVERTISED_100baseT_Full)
372 adv |= PHY_M_AN_100_FD;
373 if (sky2->advertising & ADVERTISED_100baseT_Half)
374 adv |= PHY_M_AN_100_HD;
375 if (sky2->advertising & ADVERTISED_10baseT_Full)
376 adv |= PHY_M_AN_10_FD;
377 if (sky2->advertising & ADVERTISED_10baseT_Half)
378 adv |= PHY_M_AN_10_HD;
379 } else /* special defines for FIBER (88E1011S only) */
380 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
382 /* Set Flow-control capabilities */
383 if (sky2->tx_pause && sky2->rx_pause)
384 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
385 else if (sky2->rx_pause && !sky2->tx_pause)
386 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
387 else if (!sky2->rx_pause && sky2->tx_pause)
388 adv |= PHY_AN_PAUSE_ASYM; /* local */
390 /* Restart Auto-negotiation */
391 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
393 /* forced speed/duplex settings */
394 ct1000 = PHY_M_1000C_MSE;
396 if (sky2->duplex == DUPLEX_FULL)
397 ctrl |= PHY_CT_DUP_MD;
399 switch (sky2->speed) {
401 ctrl |= PHY_CT_SP1000;
404 ctrl |= PHY_CT_SP100;
408 ctrl |= PHY_CT_RESET;
411 if (hw->chip_id != CHIP_ID_YUKON_FE)
412 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
414 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
415 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
417 /* Setup Phy LED's */
418 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
421 switch (hw->chip_id) {
422 case CHIP_ID_YUKON_FE:
423 /* on 88E3082 these bits are at 11..9 (shifted left) */
424 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
426 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
428 /* delete ACT LED control bits */
429 ctrl &= ~PHY_M_FELP_LED1_MSK;
430 /* change ACT LED control to blink mode */
431 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
432 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
435 case CHIP_ID_YUKON_XL:
436 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
438 /* select page 3 to access LED control register */
439 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
441 /* set LED Function Control register */
442 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
443 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
444 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
445 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
447 /* set Polarity Control register */
448 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
449 (PHY_M_POLC_LS1_P_MIX(4) |
450 PHY_M_POLC_IS0_P_MIX(4) |
451 PHY_M_POLC_LOS_CTRL(2) |
452 PHY_M_POLC_INIT_CTRL(2) |
453 PHY_M_POLC_STA1_CTRL(2) |
454 PHY_M_POLC_STA0_CTRL(2)));
456 /* restore page register */
457 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
461 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
462 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
463 /* turn off the Rx LED (LED_RX) */
464 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
467 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
469 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
470 /* turn on 100 Mbps LED (LED_LINK100) */
471 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
475 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
477 /* Enable phy interrupt on auto-negotiation complete (or link up) */
478 if (sky2->autoneg == AUTONEG_ENABLE)
479 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
481 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
484 /* Force a renegotiation */
485 static void sky2_phy_reinit(struct sky2_port *sky2)
487 down(&sky2->phy_sema);
488 sky2_phy_init(sky2->hw, sky2->port);
492 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
494 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
497 const u8 *addr = hw->dev[port]->dev_addr;
499 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
500 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
502 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
504 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
505 /* WA DEV_472 -- looks like crossed wires on port 2 */
506 /* clear GMAC 1 Control reset */
507 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
509 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
510 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
511 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
512 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
513 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
516 if (sky2->autoneg == AUTONEG_DISABLE) {
517 reg = gma_read16(hw, port, GM_GP_CTRL);
518 reg |= GM_GPCR_AU_ALL_DIS;
519 gma_write16(hw, port, GM_GP_CTRL, reg);
520 gma_read16(hw, port, GM_GP_CTRL);
522 switch (sky2->speed) {
524 reg |= GM_GPCR_SPEED_1000;
527 reg |= GM_GPCR_SPEED_100;
530 if (sky2->duplex == DUPLEX_FULL)
531 reg |= GM_GPCR_DUP_FULL;
533 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
535 if (!sky2->tx_pause && !sky2->rx_pause) {
536 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
538 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
539 } else if (sky2->tx_pause && !sky2->rx_pause) {
540 /* disable Rx flow-control */
541 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
544 gma_write16(hw, port, GM_GP_CTRL, reg);
546 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
548 down(&sky2->phy_sema);
549 sky2_phy_init(hw, port);
553 reg = gma_read16(hw, port, GM_PHY_ADDR);
554 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
556 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
557 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
558 gma_write16(hw, port, GM_PHY_ADDR, reg);
560 /* transmit control */
561 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
563 /* receive control reg: unicast + multicast + no FCS */
564 gma_write16(hw, port, GM_RX_CTRL,
565 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
567 /* transmit flow control */
568 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
570 /* transmit parameter */
571 gma_write16(hw, port, GM_TX_PARAM,
572 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
573 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
574 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
575 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
577 /* serial mode register */
578 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
579 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
581 if (hw->dev[port]->mtu > ETH_DATA_LEN)
582 reg |= GM_SMOD_JUMBO_ENA;
584 gma_write16(hw, port, GM_SERIAL_MODE, reg);
586 /* virtual address for data */
587 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
589 /* physical address: used for pause frames */
590 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
592 /* ignore counter overflows */
593 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
594 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
595 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
597 /* Configure Rx MAC FIFO */
598 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
599 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
602 /* Flush Rx MAC FIFO on any flow control or error */
603 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
605 /* Set threshold to 0xa (64 bytes)
606 * ASF disabled so no need to do WA dev #4.30
608 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
610 /* Configure Tx MAC FIFO */
611 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
612 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
614 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
615 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
616 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
617 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
618 /* set Tx GMAC FIFO Almost Empty Threshold */
619 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
620 /* Disable Store & Forward mode for TX */
621 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
627 /* Assign Ram Buffer allocation.
628 * start and end are in units of 4k bytes
629 * ram registers are in units of 64bit words
631 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
635 start = startk * 4096/8;
636 end = (endk * 4096/8) - 1;
638 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
639 sky2_write32(hw, RB_ADDR(q, RB_START), start);
640 sky2_write32(hw, RB_ADDR(q, RB_END), end);
641 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
642 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
644 if (q == Q_R1 || q == Q_R2) {
645 u32 space = (endk - startk) * 4096/8;
646 u32 tp = space - space/4;
648 /* On receive queue's set the thresholds
649 * give receiver priority when > 3/4 full
650 * send pause when down to 2K
652 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
653 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
656 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
657 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
659 /* Enable store & forward on Tx queue's because
660 * Tx FIFO is only 1K on Yukon
662 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
665 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
666 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
669 /* Setup Bus Memory Interface */
670 static void sky2_qset(struct sky2_hw *hw, u16 q)
672 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
673 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
674 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
675 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
678 /* Setup prefetch unit registers. This is the interface between
679 * hardware and driver list elements
681 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
684 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
685 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
686 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
687 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
688 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
689 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
691 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
694 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
696 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
698 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
703 * This is a workaround code taken from SysKonnect sk98lin driver
704 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
706 static void sky2_put_idx(struct sky2_hw *hw, unsigned q,
707 u16 idx, u16 *last, u16 size)
710 if (is_ec_a1(hw) && idx < *last) {
711 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
714 /* Start prefetching again */
715 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
719 if (hwget == size - 1) {
720 /* set watermark to one list element */
721 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
723 /* set put index to first list element */
724 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
725 } else /* have hardware go to end of list */
726 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
730 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
737 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
739 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
740 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
744 /* Return high part of DMA address (could be 32 or 64 bit) */
745 static inline u32 high32(dma_addr_t a)
747 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
750 /* Build description to hardware about buffer */
751 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
753 struct sky2_rx_le *le;
754 u32 hi = high32(map);
755 u16 len = sky2->rx_bufsize;
757 if (sky2->rx_addr64 != hi) {
758 le = sky2_next_rx(sky2);
759 le->addr = cpu_to_le32(hi);
761 le->opcode = OP_ADDR64 | HW_OWNER;
762 sky2->rx_addr64 = high32(map + len);
765 le = sky2_next_rx(sky2);
766 le->addr = cpu_to_le32((u32) map);
767 le->length = cpu_to_le16(len);
769 le->opcode = OP_PACKET | HW_OWNER;
773 /* Tell chip where to start receive checksum.
774 * Actually has two checksums, but set both same to avoid possible byte
777 static void rx_set_checksum(struct sky2_port *sky2)
779 struct sky2_rx_le *le;
781 le = sky2_next_rx(sky2);
782 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
784 le->opcode = OP_TCPSTART | HW_OWNER;
786 sky2_write32(sky2->hw,
787 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
788 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
793 * The RX Stop command will not work for Yukon-2 if the BMU does not
794 * reach the end of packet and since we can't make sure that we have
795 * incoming data, we must reset the BMU while it is not doing a DMA
796 * transfer. Since it is possible that the RX path is still active,
797 * the RX RAM buffer will be stopped first, so any possible incoming
798 * data will not trigger a DMA. After the RAM buffer is stopped, the
799 * BMU is polled until any DMA in progress is ended and only then it
802 static void sky2_rx_stop(struct sky2_port *sky2)
804 struct sky2_hw *hw = sky2->hw;
805 unsigned rxq = rxqaddr[sky2->port];
808 /* disable the RAM Buffer receive queue */
809 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
811 for (i = 0; i < 0xffff; i++)
812 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
813 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
816 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
819 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
821 /* reset the Rx prefetch unit */
822 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
825 /* Clean out receive buffer area, assumes receiver hardware stopped */
826 static void sky2_rx_clean(struct sky2_port *sky2)
830 memset(sky2->rx_le, 0, RX_LE_BYTES);
831 for (i = 0; i < sky2->rx_pending; i++) {
832 struct ring_info *re = sky2->rx_ring + i;
835 pci_unmap_single(sky2->hw->pdev,
836 re->mapaddr, sky2->rx_bufsize,
844 /* Basic MII support */
845 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
847 struct mii_ioctl_data *data = if_mii(ifr);
848 struct sky2_port *sky2 = netdev_priv(dev);
849 struct sky2_hw *hw = sky2->hw;
850 int err = -EOPNOTSUPP;
852 if (!netif_running(dev))
853 return -ENODEV; /* Phy still in reset */
857 data->phy_id = PHY_ADDR_MARV;
863 down(&sky2->phy_sema);
864 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
872 if (!capable(CAP_NET_ADMIN))
875 down(&sky2->phy_sema);
876 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
884 #ifdef SKY2_VLAN_TAG_USED
885 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
887 struct sky2_port *sky2 = netdev_priv(dev);
888 struct sky2_hw *hw = sky2->hw;
889 u16 port = sky2->port;
891 spin_lock_bh(&sky2->tx_lock);
893 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
894 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
897 spin_unlock_bh(&sky2->tx_lock);
900 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
902 struct sky2_port *sky2 = netdev_priv(dev);
903 struct sky2_hw *hw = sky2->hw;
904 u16 port = sky2->port;
906 spin_lock_bh(&sky2->tx_lock);
908 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
909 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
911 sky2->vlgrp->vlan_devices[vid] = NULL;
913 spin_unlock_bh(&sky2->tx_lock);
918 * It appears the hardware has a bug in the FIFO logic that
919 * cause it to hang if the FIFO gets overrun and the receive buffer
920 * is not aligned. ALso alloc_skb() won't align properly if slab
921 * debugging is enabled.
923 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
927 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
929 unsigned long p = (unsigned long) skb->data;
931 ((p + RX_SKB_ALIGN - 1) & ~(RX_SKB_ALIGN - 1)) - p);
938 * Allocate and setup receiver buffer pool.
939 * In case of 64 bit dma, there are 2X as many list elements
940 * available as ring entries
941 * and need to reserve one list element so we don't wrap around.
943 static int sky2_rx_start(struct sky2_port *sky2)
945 struct sky2_hw *hw = sky2->hw;
946 unsigned rxq = rxqaddr[sky2->port];
949 sky2->rx_put = sky2->rx_next = 0;
951 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
953 rx_set_checksum(sky2);
954 for (i = 0; i < sky2->rx_pending; i++) {
955 struct ring_info *re = sky2->rx_ring + i;
957 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
961 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
962 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
963 sky2_rx_add(sky2, re->mapaddr);
966 /* Tell chip about available buffers */
967 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
968 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
975 /* Bring up network interface. */
976 static int sky2_up(struct net_device *dev)
978 struct sky2_port *sky2 = netdev_priv(dev);
979 struct sky2_hw *hw = sky2->hw;
980 unsigned port = sky2->port;
981 u32 ramsize, rxspace;
984 if (netif_msg_ifup(sky2))
985 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
987 /* must be power of 2 */
988 sky2->tx_le = pci_alloc_consistent(hw->pdev,
990 sizeof(struct sky2_tx_le),
995 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
999 sky2->tx_prod = sky2->tx_cons = 0;
1001 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1005 memset(sky2->rx_le, 0, RX_LE_BYTES);
1007 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1012 sky2_mac_init(hw, port);
1014 /* Determine available ram buffer space (in 4K blocks).
1015 * Note: not sure about the FE setting below yet
1017 if (hw->chip_id == CHIP_ID_YUKON_FE)
1020 ramsize = sky2_read8(hw, B2_E_0);
1022 /* Give transmitter one third (rounded up) */
1023 rxspace = ramsize - (ramsize + 2) / 3;
1025 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1026 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1028 /* Make sure SyncQ is disabled */
1029 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1032 sky2_qset(hw, txqaddr[port]);
1033 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1034 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1037 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1040 err = sky2_rx_start(sky2);
1044 /* Enable interrupts from phy/mac for port */
1045 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1046 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1051 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1052 sky2->rx_le, sky2->rx_le_map);
1056 pci_free_consistent(hw->pdev,
1057 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1058 sky2->tx_le, sky2->tx_le_map);
1061 kfree(sky2->tx_ring);
1062 kfree(sky2->rx_ring);
1064 sky2->tx_ring = NULL;
1065 sky2->rx_ring = NULL;
1069 /* Modular subtraction in ring */
1070 static inline int tx_dist(unsigned tail, unsigned head)
1072 return (head - tail) % TX_RING_SIZE;
1075 /* Number of list elements available for next tx */
1076 static inline int tx_avail(const struct sky2_port *sky2)
1078 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1081 /* Estimate of number of transmit list elements required */
1082 static unsigned tx_le_req(const struct sk_buff *skb)
1086 count = sizeof(dma_addr_t) / sizeof(u32);
1087 count += skb_shinfo(skb)->nr_frags * count;
1089 if (skb_shinfo(skb)->tso_size)
1092 if (skb->ip_summed == CHECKSUM_HW)
1099 * Put one packet in ring for transmit.
1100 * A single packet can generate multiple list elements, and
1101 * the number of ring elements will probably be less than the number
1102 * of list elements used.
1104 * No BH disabling for tx_lock here (like tg3)
1106 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1108 struct sky2_port *sky2 = netdev_priv(dev);
1109 struct sky2_hw *hw = sky2->hw;
1110 struct sky2_tx_le *le = NULL;
1111 struct tx_ring_info *re;
1118 /* No BH disabling for tx_lock here. We are running in BH disabled
1119 * context and TX reclaim runs via poll inside of a software
1120 * interrupt, and no related locks in IRQ processing.
1122 if (!spin_trylock(&sky2->tx_lock))
1123 return NETDEV_TX_LOCKED;
1125 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1126 /* There is a known but harmless race with lockless tx
1127 * and netif_stop_queue.
1129 if (!netif_queue_stopped(dev)) {
1130 netif_stop_queue(dev);
1131 if (net_ratelimit())
1132 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1135 spin_unlock(&sky2->tx_lock);
1137 return NETDEV_TX_BUSY;
1140 if (unlikely(netif_msg_tx_queued(sky2)))
1141 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1142 dev->name, sky2->tx_prod, skb->len);
1144 len = skb_headlen(skb);
1145 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1146 addr64 = high32(mapping);
1148 re = sky2->tx_ring + sky2->tx_prod;
1150 /* Send high bits if changed or crosses boundary */
1151 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1152 le = get_tx_le(sky2);
1153 le->tx.addr = cpu_to_le32(addr64);
1155 le->opcode = OP_ADDR64 | HW_OWNER;
1156 sky2->tx_addr64 = high32(mapping + len);
1159 /* Check for TCP Segmentation Offload */
1160 mss = skb_shinfo(skb)->tso_size;
1162 /* just drop the packet if non-linear expansion fails */
1163 if (skb_header_cloned(skb) &&
1164 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1165 dev_kfree_skb_any(skb);
1169 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1170 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1174 if (mss != sky2->tx_last_mss) {
1175 le = get_tx_le(sky2);
1176 le->tx.tso.size = cpu_to_le16(mss);
1177 le->tx.tso.rsvd = 0;
1178 le->opcode = OP_LRGLEN | HW_OWNER;
1180 sky2->tx_last_mss = mss;
1184 #ifdef SKY2_VLAN_TAG_USED
1185 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1186 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1188 le = get_tx_le(sky2);
1190 le->opcode = OP_VLAN|HW_OWNER;
1193 le->opcode |= OP_VLAN;
1194 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1199 /* Handle TCP checksum offload */
1200 if (skb->ip_summed == CHECKSUM_HW) {
1201 u16 hdr = skb->h.raw - skb->data;
1202 u16 offset = hdr + skb->csum;
1204 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1205 if (skb->nh.iph->protocol == IPPROTO_UDP)
1208 le = get_tx_le(sky2);
1209 le->tx.csum.start = cpu_to_le16(hdr);
1210 le->tx.csum.offset = cpu_to_le16(offset);
1211 le->length = 0; /* initial checksum value */
1212 le->ctrl = 1; /* one packet */
1213 le->opcode = OP_TCPLISW | HW_OWNER;
1216 le = get_tx_le(sky2);
1217 le->tx.addr = cpu_to_le32((u32) mapping);
1218 le->length = cpu_to_le16(len);
1220 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1222 /* Record the transmit mapping info */
1224 pci_unmap_addr_set(re, mapaddr, mapping);
1226 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1227 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1228 struct tx_ring_info *fre;
1230 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1231 frag->size, PCI_DMA_TODEVICE);
1232 addr64 = high32(mapping);
1233 if (addr64 != sky2->tx_addr64) {
1234 le = get_tx_le(sky2);
1235 le->tx.addr = cpu_to_le32(addr64);
1237 le->opcode = OP_ADDR64 | HW_OWNER;
1238 sky2->tx_addr64 = addr64;
1241 le = get_tx_le(sky2);
1242 le->tx.addr = cpu_to_le32((u32) mapping);
1243 le->length = cpu_to_le16(frag->size);
1245 le->opcode = OP_BUFFER | HW_OWNER;
1248 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1249 pci_unmap_addr_set(fre, mapaddr, mapping);
1252 re->idx = sky2->tx_prod;
1255 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1256 &sky2->tx_last_put, TX_RING_SIZE);
1258 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1259 netif_stop_queue(dev);
1262 spin_unlock(&sky2->tx_lock);
1264 dev->trans_start = jiffies;
1265 return NETDEV_TX_OK;
1269 * Free ring elements from starting at tx_cons until "done"
1271 * NB: the hardware will tell us about partial completion of multi-part
1272 * buffers; these are deferred until completion.
1274 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1276 struct net_device *dev = sky2->netdev;
1277 struct pci_dev *pdev = sky2->hw->pdev;
1281 BUG_ON(done >= TX_RING_SIZE);
1283 if (unlikely(netif_msg_tx_done(sky2)))
1284 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1287 for (put = sky2->tx_cons; put != done; put = nxt) {
1288 struct tx_ring_info *re = sky2->tx_ring + put;
1289 struct sk_buff *skb = re->skb;
1292 BUG_ON(nxt >= TX_RING_SIZE);
1293 prefetch(sky2->tx_ring + nxt);
1295 /* Check for partial status */
1296 if (tx_dist(put, done) < tx_dist(put, nxt))
1300 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1301 skb_headlen(skb), PCI_DMA_TODEVICE);
1303 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1304 struct tx_ring_info *fre;
1305 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1306 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1307 skb_shinfo(skb)->frags[i].size,
1311 dev_kfree_skb_any(skb);
1314 sky2->tx_cons = put;
1315 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1316 netif_wake_queue(dev);
1319 /* Cleanup all untransmitted buffers, assume transmitter not running */
1320 static void sky2_tx_clean(struct sky2_port *sky2)
1322 spin_lock_bh(&sky2->tx_lock);
1323 sky2_tx_complete(sky2, sky2->tx_prod);
1324 spin_unlock_bh(&sky2->tx_lock);
1327 /* Network shutdown */
1328 static int sky2_down(struct net_device *dev)
1330 struct sky2_port *sky2 = netdev_priv(dev);
1331 struct sky2_hw *hw = sky2->hw;
1332 unsigned port = sky2->port;
1335 /* Never really got started! */
1339 if (netif_msg_ifdown(sky2))
1340 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1342 /* Stop more packets from being queued */
1343 netif_stop_queue(dev);
1345 /* Disable port IRQ */
1346 local_irq_disable();
1347 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1348 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1351 flush_scheduled_work();
1353 sky2_phy_reset(hw, port);
1355 /* Stop transmitter */
1356 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1357 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1359 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1360 RB_RST_SET | RB_DIS_OP_MD);
1362 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1363 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1364 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1366 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1368 /* Workaround shared GMAC reset */
1369 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1370 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1371 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1373 /* Disable Force Sync bit and Enable Alloc bit */
1374 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1375 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1377 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1378 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1379 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1381 /* Reset the PCI FIFO of the async Tx queue */
1382 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1383 BMU_RST_SET | BMU_FIFO_RST);
1385 /* Reset the Tx prefetch units */
1386 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1389 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1393 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1394 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1396 /* turn off LED's */
1397 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1399 synchronize_irq(hw->pdev->irq);
1401 sky2_tx_clean(sky2);
1402 sky2_rx_clean(sky2);
1404 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1405 sky2->rx_le, sky2->rx_le_map);
1406 kfree(sky2->rx_ring);
1408 pci_free_consistent(hw->pdev,
1409 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1410 sky2->tx_le, sky2->tx_le_map);
1411 kfree(sky2->tx_ring);
1416 sky2->rx_ring = NULL;
1417 sky2->tx_ring = NULL;
1422 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1427 if (hw->chip_id == CHIP_ID_YUKON_FE)
1428 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1430 switch (aux & PHY_M_PS_SPEED_MSK) {
1431 case PHY_M_PS_SPEED_1000:
1433 case PHY_M_PS_SPEED_100:
1440 static void sky2_link_up(struct sky2_port *sky2)
1442 struct sky2_hw *hw = sky2->hw;
1443 unsigned port = sky2->port;
1446 /* Enable Transmit FIFO Underrun */
1447 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1449 reg = gma_read16(hw, port, GM_GP_CTRL);
1450 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1451 reg |= GM_GPCR_DUP_FULL;
1454 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1455 gma_write16(hw, port, GM_GP_CTRL, reg);
1456 gma_read16(hw, port, GM_GP_CTRL);
1458 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1460 netif_carrier_on(sky2->netdev);
1461 netif_wake_queue(sky2->netdev);
1463 /* Turn on link LED */
1464 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1465 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1467 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1468 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1470 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1471 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1472 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1474 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1475 SPEED_100 ? 7 : 0) |
1476 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1477 SPEED_1000 ? 7 : 0));
1478 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1481 if (netif_msg_link(sky2))
1482 printk(KERN_INFO PFX
1483 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1484 sky2->netdev->name, sky2->speed,
1485 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1486 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1487 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1490 static void sky2_link_down(struct sky2_port *sky2)
1492 struct sky2_hw *hw = sky2->hw;
1493 unsigned port = sky2->port;
1496 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1498 reg = gma_read16(hw, port, GM_GP_CTRL);
1499 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1500 gma_write16(hw, port, GM_GP_CTRL, reg);
1501 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1503 if (sky2->rx_pause && !sky2->tx_pause) {
1504 /* restore Asymmetric Pause bit */
1505 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1506 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1510 netif_carrier_off(sky2->netdev);
1511 netif_stop_queue(sky2->netdev);
1513 /* Turn on link LED */
1514 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1516 if (netif_msg_link(sky2))
1517 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1518 sky2_phy_init(hw, port);
1521 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1523 struct sky2_hw *hw = sky2->hw;
1524 unsigned port = sky2->port;
1527 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1529 if (lpa & PHY_M_AN_RF) {
1530 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1534 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1535 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1536 printk(KERN_ERR PFX "%s: master/slave fault",
1537 sky2->netdev->name);
1541 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1542 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1543 sky2->netdev->name);
1547 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1549 sky2->speed = sky2_phy_speed(hw, aux);
1551 /* Pause bits are offset (9..8) */
1552 if (hw->chip_id == CHIP_ID_YUKON_XL)
1555 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1556 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1558 if ((sky2->tx_pause || sky2->rx_pause)
1559 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1560 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1562 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1568 * Interrupt from PHY are handled outside of interrupt context
1569 * because accessing phy registers requires spin wait which might
1570 * cause excess interrupt latency.
1572 static void sky2_phy_task(void *arg)
1574 struct sky2_port *sky2 = arg;
1575 struct sky2_hw *hw = sky2->hw;
1576 u16 istatus, phystat;
1578 down(&sky2->phy_sema);
1579 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1580 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1582 if (netif_msg_intr(sky2))
1583 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1584 sky2->netdev->name, istatus, phystat);
1586 if (istatus & PHY_M_IS_AN_COMPL) {
1587 if (sky2_autoneg_done(sky2, phystat) == 0)
1592 if (istatus & PHY_M_IS_LSP_CHANGE)
1593 sky2->speed = sky2_phy_speed(hw, phystat);
1595 if (istatus & PHY_M_IS_DUP_CHANGE)
1597 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1599 if (istatus & PHY_M_IS_LST_CHANGE) {
1600 if (phystat & PHY_M_PS_LINK_UP)
1603 sky2_link_down(sky2);
1606 up(&sky2->phy_sema);
1608 local_irq_disable();
1609 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1610 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1615 /* Transmit timeout is only called if we are running, carries is up
1616 * and tx queue is full (stopped).
1618 static void sky2_tx_timeout(struct net_device *dev)
1620 struct sky2_port *sky2 = netdev_priv(dev);
1621 struct sky2_hw *hw = sky2->hw;
1622 unsigned txq = txqaddr[sky2->port];
1625 /* Maybe we just missed an status interrupt */
1626 spin_lock(&sky2->tx_lock);
1627 ridx = sky2_read16(hw,
1628 sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1629 sky2_tx_complete(sky2, ridx);
1630 spin_unlock(&sky2->tx_lock);
1632 if (!netif_queue_stopped(dev)) {
1633 if (net_ratelimit())
1634 pr_info(PFX "transmit interrupt missed? recovered\n");
1638 if (netif_msg_timer(sky2))
1639 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1641 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1642 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1644 sky2_tx_clean(sky2);
1647 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1651 #define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
1652 /* Want receive buffer size to be multiple of 64 bits, and incl room for vlan */
1653 static inline unsigned sky2_buf_size(int mtu)
1655 return roundup(mtu + ETH_HLEN + 4, 8);
1658 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1660 struct sky2_port *sky2 = netdev_priv(dev);
1661 struct sky2_hw *hw = sky2->hw;
1665 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1668 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1671 if (!netif_running(dev)) {
1676 sky2_write32(hw, B0_IMSK, 0);
1678 dev->trans_start = jiffies; /* prevent tx timeout */
1679 netif_stop_queue(dev);
1680 netif_poll_disable(hw->dev[0]);
1682 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1683 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1685 sky2_rx_clean(sky2);
1688 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1689 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1690 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1692 if (dev->mtu > ETH_DATA_LEN)
1693 mode |= GM_SMOD_JUMBO_ENA;
1695 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1697 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1699 err = sky2_rx_start(sky2);
1700 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1705 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1707 netif_poll_enable(hw->dev[0]);
1708 netif_wake_queue(dev);
1715 * Receive one packet.
1716 * For small packets or errors, just reuse existing skb.
1717 * For larger packets, get new buffer.
1719 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1720 u16 length, u32 status)
1722 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1723 struct sk_buff *skb = NULL;
1725 if (unlikely(netif_msg_rx_status(sky2)))
1726 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1727 sky2->netdev->name, sky2->rx_next, status, length);
1729 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1730 prefetch(sky2->rx_ring + sky2->rx_next);
1732 if (status & GMR_FS_ANY_ERR)
1735 if (!(status & GMR_FS_RX_OK))
1738 if ((status >> 16) != length || length > sky2->rx_bufsize)
1741 if (length < copybreak) {
1742 skb = alloc_skb(length + 2, GFP_ATOMIC);
1746 skb_reserve(skb, 2);
1747 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1748 length, PCI_DMA_FROMDEVICE);
1749 memcpy(skb->data, re->skb->data, length);
1750 skb->ip_summed = re->skb->ip_summed;
1751 skb->csum = re->skb->csum;
1752 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1753 length, PCI_DMA_FROMDEVICE);
1755 struct sk_buff *nskb;
1757 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1763 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1764 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1765 prefetch(skb->data);
1767 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1768 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1771 skb_put(skb, length);
1773 re->skb->ip_summed = CHECKSUM_NONE;
1774 sky2_rx_add(sky2, re->mapaddr);
1776 /* Tell receiver about new buffers. */
1777 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1778 &sky2->rx_last_put, RX_LE_SIZE);
1783 ++sky2->net_stats.rx_over_errors;
1787 ++sky2->net_stats.rx_errors;
1789 if (netif_msg_rx_err(sky2) && net_ratelimit())
1790 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1791 sky2->netdev->name, status, length);
1793 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1794 sky2->net_stats.rx_length_errors++;
1795 if (status & GMR_FS_FRAGMENT)
1796 sky2->net_stats.rx_frame_errors++;
1797 if (status & GMR_FS_CRC_ERR)
1798 sky2->net_stats.rx_crc_errors++;
1799 if (status & GMR_FS_RX_FF_OV)
1800 sky2->net_stats.rx_fifo_errors++;
1806 * Check for transmit complete
1808 #define TX_NO_STATUS 0xffff
1810 static void sky2_tx_check(struct sky2_hw *hw, int port, u16 last)
1812 if (last != TX_NO_STATUS) {
1813 struct net_device *dev = hw->dev[port];
1814 if (dev && netif_running(dev)) {
1815 struct sky2_port *sky2 = netdev_priv(dev);
1817 spin_lock(&sky2->tx_lock);
1818 sky2_tx_complete(sky2, last);
1819 spin_unlock(&sky2->tx_lock);
1825 * Both ports share the same status interrupt, therefore there is only
1828 static int sky2_poll(struct net_device *dev0, int *budget)
1830 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1831 unsigned int to_do = min(dev0->quota, *budget);
1832 unsigned int work_done = 0;
1834 u16 tx_done[2] = { TX_NO_STATUS, TX_NO_STATUS };
1836 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1838 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1839 BUG_ON(hwidx >= STATUS_RING_SIZE);
1842 while (hwidx != hw->st_idx) {
1843 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1844 struct net_device *dev;
1845 struct sky2_port *sky2;
1846 struct sk_buff *skb;
1850 le = hw->st_le + hw->st_idx;
1851 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1852 prefetch(hw->st_le + hw->st_idx);
1854 BUG_ON(le->link >= 2);
1855 dev = hw->dev[le->link];
1856 if (dev == NULL || !netif_running(dev))
1859 sky2 = netdev_priv(dev);
1860 status = le32_to_cpu(le->status);
1861 length = le16_to_cpu(le->length);
1863 switch (le->opcode & ~HW_OWNER) {
1865 skb = sky2_receive(sky2, length, status);
1870 skb->protocol = eth_type_trans(skb, dev);
1871 dev->last_rx = jiffies;
1873 #ifdef SKY2_VLAN_TAG_USED
1874 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1875 vlan_hwaccel_receive_skb(skb,
1877 be16_to_cpu(sky2->rx_tag));
1880 netif_receive_skb(skb);
1882 if (++work_done >= to_do)
1886 #ifdef SKY2_VLAN_TAG_USED
1888 sky2->rx_tag = length;
1892 sky2->rx_tag = length;
1896 skb = sky2->rx_ring[sky2->rx_next].skb;
1897 skb->ip_summed = CHECKSUM_HW;
1898 skb->csum = le16_to_cpu(status);
1902 /* TX index reports status for both ports */
1903 tx_done[0] = status & 0xffff;
1904 tx_done[1] = ((status >> 24) & 0xff)
1905 | (u16)(length & 0xf) << 8;
1909 if (net_ratelimit())
1910 printk(KERN_WARNING PFX
1911 "unknown status opcode 0x%x\n", le->opcode);
1917 sky2_tx_check(hw, 0, tx_done[0]);
1918 sky2_tx_check(hw, 1, tx_done[1]);
1920 if (likely(work_done < to_do)) {
1921 /* need to restart TX timer */
1923 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1924 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1927 netif_rx_complete(dev0);
1928 hw->intr_mask |= Y2_IS_STAT_BMU;
1929 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1932 *budget -= work_done;
1933 dev0->quota -= work_done;
1938 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1940 struct net_device *dev = hw->dev[port];
1942 if (net_ratelimit())
1943 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1946 if (status & Y2_IS_PAR_RD1) {
1947 if (net_ratelimit())
1948 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1951 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1954 if (status & Y2_IS_PAR_WR1) {
1955 if (net_ratelimit())
1956 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1959 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1962 if (status & Y2_IS_PAR_MAC1) {
1963 if (net_ratelimit())
1964 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1965 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1968 if (status & Y2_IS_PAR_RX1) {
1969 if (net_ratelimit())
1970 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1971 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1974 if (status & Y2_IS_TCP_TXA1) {
1975 if (net_ratelimit())
1976 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1978 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1982 static void sky2_hw_intr(struct sky2_hw *hw)
1984 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1986 if (status & Y2_IS_TIST_OV)
1987 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1989 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1992 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1993 if (net_ratelimit())
1994 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1995 pci_name(hw->pdev), pci_err);
1997 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1998 pci_write_config_word(hw->pdev, PCI_STATUS,
1999 pci_err | PCI_STATUS_ERROR_BITS);
2000 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2003 if (status & Y2_IS_PCI_EXP) {
2004 /* PCI-Express uncorrectable Error occurred */
2007 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
2009 if (net_ratelimit())
2010 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2011 pci_name(hw->pdev), pex_err);
2013 /* clear the interrupt */
2014 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2015 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2017 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2019 if (pex_err & PEX_FATAL_ERRORS) {
2020 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2021 hwmsk &= ~Y2_IS_PCI_EXP;
2022 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2026 if (status & Y2_HWE_L1_MASK)
2027 sky2_hw_error(hw, 0, status);
2029 if (status & Y2_HWE_L1_MASK)
2030 sky2_hw_error(hw, 1, status);
2033 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2035 struct net_device *dev = hw->dev[port];
2036 struct sky2_port *sky2 = netdev_priv(dev);
2037 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2039 if (netif_msg_intr(sky2))
2040 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2043 if (status & GM_IS_RX_FF_OR) {
2044 ++sky2->net_stats.rx_fifo_errors;
2045 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2048 if (status & GM_IS_TX_FF_UR) {
2049 ++sky2->net_stats.tx_fifo_errors;
2050 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2054 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2056 struct net_device *dev = hw->dev[port];
2057 struct sky2_port *sky2 = netdev_priv(dev);
2059 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
2060 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2061 schedule_work(&sky2->phy_task);
2064 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2066 struct sky2_hw *hw = dev_id;
2067 struct net_device *dev0 = hw->dev[0];
2070 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2071 if (status == 0 || status == ~0)
2074 if (status & Y2_IS_HW_ERR)
2077 /* Do NAPI for Rx and Tx status */
2078 if (status & Y2_IS_STAT_BMU) {
2079 hw->intr_mask &= ~Y2_IS_STAT_BMU;
2080 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2082 if (likely(__netif_rx_schedule_prep(dev0))) {
2083 prefetch(&hw->st_le[hw->st_idx]);
2084 __netif_rx_schedule(dev0);
2088 if (status & Y2_IS_IRQ_PHY1)
2089 sky2_phy_intr(hw, 0);
2091 if (status & Y2_IS_IRQ_PHY2)
2092 sky2_phy_intr(hw, 1);
2094 if (status & Y2_IS_IRQ_MAC1)
2095 sky2_mac_intr(hw, 0);
2097 if (status & Y2_IS_IRQ_MAC2)
2098 sky2_mac_intr(hw, 1);
2100 sky2_write32(hw, B0_Y2_SP_ICR, 2);
2102 sky2_read32(hw, B0_IMSK);
2107 #ifdef CONFIG_NET_POLL_CONTROLLER
2108 static void sky2_netpoll(struct net_device *dev)
2110 struct sky2_port *sky2 = netdev_priv(dev);
2112 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2116 /* Chip internal frequency for clock calculations */
2117 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2119 switch (hw->chip_id) {
2120 case CHIP_ID_YUKON_EC:
2121 case CHIP_ID_YUKON_EC_U:
2122 return 125; /* 125 Mhz */
2123 case CHIP_ID_YUKON_FE:
2124 return 100; /* 100 Mhz */
2125 default: /* YUKON_XL */
2126 return 156; /* 156 Mhz */
2130 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2132 return sky2_mhz(hw) * us;
2135 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2137 return clk / sky2_mhz(hw);
2141 static int sky2_reset(struct sky2_hw *hw)
2147 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2149 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2150 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2151 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2152 pci_name(hw->pdev), hw->chip_id);
2157 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2158 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2159 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2163 sky2_write8(hw, B0_CTST, CS_RST_SET);
2164 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2166 /* clear PCI errors, if any */
2167 err = pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2171 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2172 err = pci_write_config_word(hw->pdev, PCI_STATUS,
2173 status | PCI_STATUS_ERROR_BITS);
2177 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2179 /* clear any PEX errors */
2180 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) {
2181 err = pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2187 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2188 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2191 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2192 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2193 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2196 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2198 sky2_set_power_state(hw, PCI_D0);
2200 for (i = 0; i < hw->ports; i++) {
2201 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2202 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2205 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2207 /* Clear I2C IRQ noise */
2208 sky2_write32(hw, B2_I2C_IRQ, 1);
2210 /* turn off hardware timer (unused) */
2211 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2212 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2214 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2216 /* Turn off descriptor polling */
2217 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2219 /* Turn off receive timestamp */
2220 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2221 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2223 /* enable the Tx Arbiters */
2224 for (i = 0; i < hw->ports; i++)
2225 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2227 /* Initialize ram interface */
2228 for (i = 0; i < hw->ports; i++) {
2229 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2231 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2232 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2233 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2234 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2235 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2236 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2237 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2238 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2239 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2240 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2241 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2242 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2245 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2247 for (i = 0; i < hw->ports; i++)
2248 sky2_phy_reset(hw, i);
2250 memset(hw->st_le, 0, STATUS_LE_BYTES);
2253 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2254 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2256 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2257 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2259 /* Set the list last index */
2260 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2262 /* These status setup values are copied from SysKonnect's driver */
2264 /* WA for dev. #4.3 */
2265 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2267 /* set Status-FIFO watermark */
2268 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2270 /* set Status-FIFO ISR watermark */
2271 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2272 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 10000));
2274 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2275 sky2_write8(hw, STAT_FIFO_WM, 16);
2277 /* set Status-FIFO ISR watermark */
2278 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2279 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2281 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2283 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2284 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2285 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2288 /* enable status unit */
2289 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2291 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2292 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2293 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2298 /* This is to catch a BIOS bug workaround where
2299 * mmconfig table doesn't have other buses.
2301 printk(KERN_ERR PFX "%s: can't access PCI config space\n",
2302 pci_name(hw->pdev));
2306 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2310 modes = SUPPORTED_10baseT_Half
2311 | SUPPORTED_10baseT_Full
2312 | SUPPORTED_100baseT_Half
2313 | SUPPORTED_100baseT_Full
2314 | SUPPORTED_Autoneg | SUPPORTED_TP;
2316 if (hw->chip_id != CHIP_ID_YUKON_FE)
2317 modes |= SUPPORTED_1000baseT_Half
2318 | SUPPORTED_1000baseT_Full;
2320 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2321 | SUPPORTED_Autoneg;
2325 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2327 struct sky2_port *sky2 = netdev_priv(dev);
2328 struct sky2_hw *hw = sky2->hw;
2330 ecmd->transceiver = XCVR_INTERNAL;
2331 ecmd->supported = sky2_supported_modes(hw);
2332 ecmd->phy_address = PHY_ADDR_MARV;
2334 ecmd->supported = SUPPORTED_10baseT_Half
2335 | SUPPORTED_10baseT_Full
2336 | SUPPORTED_100baseT_Half
2337 | SUPPORTED_100baseT_Full
2338 | SUPPORTED_1000baseT_Half
2339 | SUPPORTED_1000baseT_Full
2340 | SUPPORTED_Autoneg | SUPPORTED_TP;
2341 ecmd->port = PORT_TP;
2343 ecmd->port = PORT_FIBRE;
2345 ecmd->advertising = sky2->advertising;
2346 ecmd->autoneg = sky2->autoneg;
2347 ecmd->speed = sky2->speed;
2348 ecmd->duplex = sky2->duplex;
2352 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2354 struct sky2_port *sky2 = netdev_priv(dev);
2355 const struct sky2_hw *hw = sky2->hw;
2356 u32 supported = sky2_supported_modes(hw);
2358 if (ecmd->autoneg == AUTONEG_ENABLE) {
2359 ecmd->advertising = supported;
2365 switch (ecmd->speed) {
2367 if (ecmd->duplex == DUPLEX_FULL)
2368 setting = SUPPORTED_1000baseT_Full;
2369 else if (ecmd->duplex == DUPLEX_HALF)
2370 setting = SUPPORTED_1000baseT_Half;
2375 if (ecmd->duplex == DUPLEX_FULL)
2376 setting = SUPPORTED_100baseT_Full;
2377 else if (ecmd->duplex == DUPLEX_HALF)
2378 setting = SUPPORTED_100baseT_Half;
2384 if (ecmd->duplex == DUPLEX_FULL)
2385 setting = SUPPORTED_10baseT_Full;
2386 else if (ecmd->duplex == DUPLEX_HALF)
2387 setting = SUPPORTED_10baseT_Half;
2395 if ((setting & supported) == 0)
2398 sky2->speed = ecmd->speed;
2399 sky2->duplex = ecmd->duplex;
2402 sky2->autoneg = ecmd->autoneg;
2403 sky2->advertising = ecmd->advertising;
2405 if (netif_running(dev))
2406 sky2_phy_reinit(sky2);
2411 static void sky2_get_drvinfo(struct net_device *dev,
2412 struct ethtool_drvinfo *info)
2414 struct sky2_port *sky2 = netdev_priv(dev);
2416 strcpy(info->driver, DRV_NAME);
2417 strcpy(info->version, DRV_VERSION);
2418 strcpy(info->fw_version, "N/A");
2419 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2422 static const struct sky2_stat {
2423 char name[ETH_GSTRING_LEN];
2426 { "tx_bytes", GM_TXO_OK_HI },
2427 { "rx_bytes", GM_RXO_OK_HI },
2428 { "tx_broadcast", GM_TXF_BC_OK },
2429 { "rx_broadcast", GM_RXF_BC_OK },
2430 { "tx_multicast", GM_TXF_MC_OK },
2431 { "rx_multicast", GM_RXF_MC_OK },
2432 { "tx_unicast", GM_TXF_UC_OK },
2433 { "rx_unicast", GM_RXF_UC_OK },
2434 { "tx_mac_pause", GM_TXF_MPAUSE },
2435 { "rx_mac_pause", GM_RXF_MPAUSE },
2436 { "collisions", GM_TXF_SNG_COL },
2437 { "late_collision",GM_TXF_LAT_COL },
2438 { "aborted", GM_TXF_ABO_COL },
2439 { "multi_collisions", GM_TXF_MUL_COL },
2440 { "fifo_underrun", GM_TXE_FIFO_UR },
2441 { "fifo_overflow", GM_RXE_FIFO_OV },
2442 { "rx_toolong", GM_RXF_LNG_ERR },
2443 { "rx_jabber", GM_RXF_JAB_PKT },
2444 { "rx_runt", GM_RXE_FRAG },
2445 { "rx_too_long", GM_RXF_LNG_ERR },
2446 { "rx_fcs_error", GM_RXF_FCS_ERR },
2449 static u32 sky2_get_rx_csum(struct net_device *dev)
2451 struct sky2_port *sky2 = netdev_priv(dev);
2453 return sky2->rx_csum;
2456 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2458 struct sky2_port *sky2 = netdev_priv(dev);
2460 sky2->rx_csum = data;
2462 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2463 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2468 static u32 sky2_get_msglevel(struct net_device *netdev)
2470 struct sky2_port *sky2 = netdev_priv(netdev);
2471 return sky2->msg_enable;
2474 static int sky2_nway_reset(struct net_device *dev)
2476 struct sky2_port *sky2 = netdev_priv(dev);
2478 if (sky2->autoneg != AUTONEG_ENABLE)
2481 sky2_phy_reinit(sky2);
2486 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2488 struct sky2_hw *hw = sky2->hw;
2489 unsigned port = sky2->port;
2492 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2493 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2494 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2495 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2497 for (i = 2; i < count; i++)
2498 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2501 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2503 struct sky2_port *sky2 = netdev_priv(netdev);
2504 sky2->msg_enable = value;
2507 static int sky2_get_stats_count(struct net_device *dev)
2509 return ARRAY_SIZE(sky2_stats);
2512 static void sky2_get_ethtool_stats(struct net_device *dev,
2513 struct ethtool_stats *stats, u64 * data)
2515 struct sky2_port *sky2 = netdev_priv(dev);
2517 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2520 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2524 switch (stringset) {
2526 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2527 memcpy(data + i * ETH_GSTRING_LEN,
2528 sky2_stats[i].name, ETH_GSTRING_LEN);
2533 /* Use hardware MIB variables for critical path statistics and
2534 * transmit feedback not reported at interrupt.
2535 * Other errors are accounted for in interrupt handler.
2537 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2539 struct sky2_port *sky2 = netdev_priv(dev);
2542 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2544 sky2->net_stats.tx_bytes = data[0];
2545 sky2->net_stats.rx_bytes = data[1];
2546 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2547 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2548 sky2->net_stats.multicast = data[5] + data[7];
2549 sky2->net_stats.collisions = data[10];
2550 sky2->net_stats.tx_aborted_errors = data[12];
2552 return &sky2->net_stats;
2555 static int sky2_set_mac_address(struct net_device *dev, void *p)
2557 struct sky2_port *sky2 = netdev_priv(dev);
2558 struct sky2_hw *hw = sky2->hw;
2559 unsigned port = sky2->port;
2560 const struct sockaddr *addr = p;
2562 if (!is_valid_ether_addr(addr->sa_data))
2563 return -EADDRNOTAVAIL;
2565 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2566 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2567 dev->dev_addr, ETH_ALEN);
2568 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2569 dev->dev_addr, ETH_ALEN);
2571 /* virtual address for data */
2572 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2574 /* physical address: used for pause frames */
2575 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2580 static void sky2_set_multicast(struct net_device *dev)
2582 struct sky2_port *sky2 = netdev_priv(dev);
2583 struct sky2_hw *hw = sky2->hw;
2584 unsigned port = sky2->port;
2585 struct dev_mc_list *list = dev->mc_list;
2589 memset(filter, 0, sizeof(filter));
2591 reg = gma_read16(hw, port, GM_RX_CTRL);
2592 reg |= GM_RXCR_UCF_ENA;
2594 if (dev->flags & IFF_PROMISC) /* promiscuous */
2595 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2596 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2597 memset(filter, 0xff, sizeof(filter));
2598 else if (dev->mc_count == 0) /* no multicast */
2599 reg &= ~GM_RXCR_MCF_ENA;
2602 reg |= GM_RXCR_MCF_ENA;
2604 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2605 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2606 filter[bit / 8] |= 1 << (bit % 8);
2610 gma_write16(hw, port, GM_MC_ADDR_H1,
2611 (u16) filter[0] | ((u16) filter[1] << 8));
2612 gma_write16(hw, port, GM_MC_ADDR_H2,
2613 (u16) filter[2] | ((u16) filter[3] << 8));
2614 gma_write16(hw, port, GM_MC_ADDR_H3,
2615 (u16) filter[4] | ((u16) filter[5] << 8));
2616 gma_write16(hw, port, GM_MC_ADDR_H4,
2617 (u16) filter[6] | ((u16) filter[7] << 8));
2619 gma_write16(hw, port, GM_RX_CTRL, reg);
2622 /* Can have one global because blinking is controlled by
2623 * ethtool and that is always under RTNL mutex
2625 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2629 switch (hw->chip_id) {
2630 case CHIP_ID_YUKON_XL:
2631 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2632 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2633 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2634 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2635 PHY_M_LEDC_INIT_CTRL(7) |
2636 PHY_M_LEDC_STA1_CTRL(7) |
2637 PHY_M_LEDC_STA0_CTRL(7))
2640 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2644 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2645 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2646 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2647 PHY_M_LED_MO_10(MO_LED_ON) |
2648 PHY_M_LED_MO_100(MO_LED_ON) |
2649 PHY_M_LED_MO_1000(MO_LED_ON) |
2650 PHY_M_LED_MO_RX(MO_LED_ON)
2651 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2652 PHY_M_LED_MO_10(MO_LED_OFF) |
2653 PHY_M_LED_MO_100(MO_LED_OFF) |
2654 PHY_M_LED_MO_1000(MO_LED_OFF) |
2655 PHY_M_LED_MO_RX(MO_LED_OFF));
2660 /* blink LED's for finding board */
2661 static int sky2_phys_id(struct net_device *dev, u32 data)
2663 struct sky2_port *sky2 = netdev_priv(dev);
2664 struct sky2_hw *hw = sky2->hw;
2665 unsigned port = sky2->port;
2666 u16 ledctrl, ledover = 0;
2671 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2672 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2676 /* save initial values */
2677 down(&sky2->phy_sema);
2678 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2679 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2680 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2681 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2682 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2684 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2685 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2689 while (!interrupted && ms > 0) {
2690 sky2_led(hw, port, onoff);
2693 up(&sky2->phy_sema);
2694 interrupted = msleep_interruptible(250);
2695 down(&sky2->phy_sema);
2700 /* resume regularly scheduled programming */
2701 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2702 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2703 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2704 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2707 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2708 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2710 up(&sky2->phy_sema);
2715 static void sky2_get_pauseparam(struct net_device *dev,
2716 struct ethtool_pauseparam *ecmd)
2718 struct sky2_port *sky2 = netdev_priv(dev);
2720 ecmd->tx_pause = sky2->tx_pause;
2721 ecmd->rx_pause = sky2->rx_pause;
2722 ecmd->autoneg = sky2->autoneg;
2725 static int sky2_set_pauseparam(struct net_device *dev,
2726 struct ethtool_pauseparam *ecmd)
2728 struct sky2_port *sky2 = netdev_priv(dev);
2731 sky2->autoneg = ecmd->autoneg;
2732 sky2->tx_pause = ecmd->tx_pause != 0;
2733 sky2->rx_pause = ecmd->rx_pause != 0;
2735 sky2_phy_reinit(sky2);
2741 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2743 struct sky2_port *sky2 = netdev_priv(dev);
2745 wol->supported = WAKE_MAGIC;
2746 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2749 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2751 struct sky2_port *sky2 = netdev_priv(dev);
2752 struct sky2_hw *hw = sky2->hw;
2754 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2757 sky2->wol = wol->wolopts == WAKE_MAGIC;
2760 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2762 sky2_write16(hw, WOL_CTRL_STAT,
2763 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2764 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2766 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2772 static int sky2_get_coalesce(struct net_device *dev,
2773 struct ethtool_coalesce *ecmd)
2775 struct sky2_port *sky2 = netdev_priv(dev);
2776 struct sky2_hw *hw = sky2->hw;
2778 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2779 ecmd->tx_coalesce_usecs = 0;
2781 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2782 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2784 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2786 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2787 ecmd->rx_coalesce_usecs = 0;
2789 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2790 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2792 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2794 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2795 ecmd->rx_coalesce_usecs_irq = 0;
2797 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2798 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2801 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2806 /* Note: this affect both ports */
2807 static int sky2_set_coalesce(struct net_device *dev,
2808 struct ethtool_coalesce *ecmd)
2810 struct sky2_port *sky2 = netdev_priv(dev);
2811 struct sky2_hw *hw = sky2->hw;
2812 const u32 tmin = sky2_clk2us(hw, 1);
2813 const u32 tmax = 5000;
2815 if (ecmd->tx_coalesce_usecs != 0 &&
2816 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2819 if (ecmd->rx_coalesce_usecs != 0 &&
2820 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2823 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2824 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2827 if (ecmd->tx_max_coalesced_frames > 0xffff)
2829 if (ecmd->rx_max_coalesced_frames > 0xff)
2831 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2834 if (ecmd->tx_coalesce_usecs == 0)
2835 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2837 sky2_write32(hw, STAT_TX_TIMER_INI,
2838 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2839 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2841 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2843 if (ecmd->rx_coalesce_usecs == 0)
2844 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2846 sky2_write32(hw, STAT_LEV_TIMER_INI,
2847 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2848 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2850 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2852 if (ecmd->rx_coalesce_usecs_irq == 0)
2853 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2855 sky2_write32(hw, STAT_ISR_TIMER_INI,
2856 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2857 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2859 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2863 static void sky2_get_ringparam(struct net_device *dev,
2864 struct ethtool_ringparam *ering)
2866 struct sky2_port *sky2 = netdev_priv(dev);
2868 ering->rx_max_pending = RX_MAX_PENDING;
2869 ering->rx_mini_max_pending = 0;
2870 ering->rx_jumbo_max_pending = 0;
2871 ering->tx_max_pending = TX_RING_SIZE - 1;
2873 ering->rx_pending = sky2->rx_pending;
2874 ering->rx_mini_pending = 0;
2875 ering->rx_jumbo_pending = 0;
2876 ering->tx_pending = sky2->tx_pending;
2879 static int sky2_set_ringparam(struct net_device *dev,
2880 struct ethtool_ringparam *ering)
2882 struct sky2_port *sky2 = netdev_priv(dev);
2885 if (ering->rx_pending > RX_MAX_PENDING ||
2886 ering->rx_pending < 8 ||
2887 ering->tx_pending < MAX_SKB_TX_LE ||
2888 ering->tx_pending > TX_RING_SIZE - 1)
2891 if (netif_running(dev))
2894 sky2->rx_pending = ering->rx_pending;
2895 sky2->tx_pending = ering->tx_pending;
2897 if (netif_running(dev)) {
2902 sky2_set_multicast(dev);
2908 static int sky2_get_regs_len(struct net_device *dev)
2914 * Returns copy of control register region
2915 * Note: access to the RAM address register set will cause timeouts.
2917 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2920 const struct sky2_port *sky2 = netdev_priv(dev);
2921 const void __iomem *io = sky2->hw->regs;
2923 BUG_ON(regs->len < B3_RI_WTO_R1);
2925 memset(p, 0, regs->len);
2927 memcpy_fromio(p, io, B3_RAM_ADDR);
2929 memcpy_fromio(p + B3_RI_WTO_R1,
2931 regs->len - B3_RI_WTO_R1);
2934 static struct ethtool_ops sky2_ethtool_ops = {
2935 .get_settings = sky2_get_settings,
2936 .set_settings = sky2_set_settings,
2937 .get_drvinfo = sky2_get_drvinfo,
2938 .get_msglevel = sky2_get_msglevel,
2939 .set_msglevel = sky2_set_msglevel,
2940 .nway_reset = sky2_nway_reset,
2941 .get_regs_len = sky2_get_regs_len,
2942 .get_regs = sky2_get_regs,
2943 .get_link = ethtool_op_get_link,
2944 .get_sg = ethtool_op_get_sg,
2945 .set_sg = ethtool_op_set_sg,
2946 .get_tx_csum = ethtool_op_get_tx_csum,
2947 .set_tx_csum = ethtool_op_set_tx_csum,
2948 .get_tso = ethtool_op_get_tso,
2949 .set_tso = ethtool_op_set_tso,
2950 .get_rx_csum = sky2_get_rx_csum,
2951 .set_rx_csum = sky2_set_rx_csum,
2952 .get_strings = sky2_get_strings,
2953 .get_coalesce = sky2_get_coalesce,
2954 .set_coalesce = sky2_set_coalesce,
2955 .get_ringparam = sky2_get_ringparam,
2956 .set_ringparam = sky2_set_ringparam,
2957 .get_pauseparam = sky2_get_pauseparam,
2958 .set_pauseparam = sky2_set_pauseparam,
2960 .get_wol = sky2_get_wol,
2961 .set_wol = sky2_set_wol,
2963 .phys_id = sky2_phys_id,
2964 .get_stats_count = sky2_get_stats_count,
2965 .get_ethtool_stats = sky2_get_ethtool_stats,
2966 .get_perm_addr = ethtool_op_get_perm_addr,
2969 /* Initialize network device */
2970 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2971 unsigned port, int highmem)
2973 struct sky2_port *sky2;
2974 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2977 printk(KERN_ERR "sky2 etherdev alloc failed");
2981 SET_MODULE_OWNER(dev);
2982 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2983 dev->irq = hw->pdev->irq;
2984 dev->open = sky2_up;
2985 dev->stop = sky2_down;
2986 dev->do_ioctl = sky2_ioctl;
2987 dev->hard_start_xmit = sky2_xmit_frame;
2988 dev->get_stats = sky2_get_stats;
2989 dev->set_multicast_list = sky2_set_multicast;
2990 dev->set_mac_address = sky2_set_mac_address;
2991 dev->change_mtu = sky2_change_mtu;
2992 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2993 dev->tx_timeout = sky2_tx_timeout;
2994 dev->watchdog_timeo = TX_WATCHDOG;
2996 dev->poll = sky2_poll;
2997 dev->weight = NAPI_WEIGHT;
2998 #ifdef CONFIG_NET_POLL_CONTROLLER
2999 dev->poll_controller = sky2_netpoll;
3002 sky2 = netdev_priv(dev);
3005 sky2->msg_enable = netif_msg_init(debug, default_msg);
3007 spin_lock_init(&sky2->tx_lock);
3008 /* Auto speed and flow control */
3009 sky2->autoneg = AUTONEG_ENABLE;
3014 sky2->advertising = sky2_supported_modes(hw);
3016 /* Receive checksum disabled for Yukon XL
3017 * because of observed problems with incorrect
3018 * values when multiple packets are received in one interrupt
3020 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3022 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
3023 init_MUTEX(&sky2->phy_sema);
3024 sky2->tx_pending = TX_DEF_PENDING;
3025 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
3026 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3028 hw->dev[port] = dev;
3032 dev->features |= NETIF_F_LLTX;
3033 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3034 dev->features |= NETIF_F_TSO;
3036 dev->features |= NETIF_F_HIGHDMA;
3037 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3039 #ifdef SKY2_VLAN_TAG_USED
3040 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3041 dev->vlan_rx_register = sky2_vlan_rx_register;
3042 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3045 /* read the mac address */
3046 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3047 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3049 /* device is off until link detection */
3050 netif_carrier_off(dev);
3051 netif_stop_queue(dev);
3056 static void __devinit sky2_show_addr(struct net_device *dev)
3058 const struct sky2_port *sky2 = netdev_priv(dev);
3060 if (netif_msg_probe(sky2))
3061 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3063 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3064 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3067 static int __devinit sky2_probe(struct pci_dev *pdev,
3068 const struct pci_device_id *ent)
3070 struct net_device *dev, *dev1 = NULL;
3072 int err, pm_cap, using_dac = 0;
3074 err = pci_enable_device(pdev);
3076 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3081 err = pci_request_regions(pdev, DRV_NAME);
3083 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3088 pci_set_master(pdev);
3090 /* Find power-management capability. */
3091 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3093 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3096 goto err_out_free_regions;
3099 if (sizeof(dma_addr_t) > sizeof(u32) &&
3100 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3102 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3104 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3105 "for consistent allocations\n", pci_name(pdev));
3106 goto err_out_free_regions;
3110 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3112 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3114 goto err_out_free_regions;
3119 /* byte swap descriptors in hardware */
3123 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3124 reg |= PCI_REV_DESC;
3125 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3130 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3132 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3134 goto err_out_free_regions;
3139 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3141 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3143 goto err_out_free_hw;
3145 hw->pm_cap = pm_cap;
3147 /* ring for status responses */
3148 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3151 goto err_out_iounmap;
3153 err = sky2_reset(hw);
3155 goto err_out_iounmap;
3157 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3158 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3159 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3160 hw->chip_id, hw->chip_rev);
3162 dev = sky2_init_netdev(hw, 0, using_dac);
3164 goto err_out_free_pci;
3166 err = register_netdev(dev);
3168 printk(KERN_ERR PFX "%s: cannot register net device\n",
3170 goto err_out_free_netdev;
3173 sky2_show_addr(dev);
3175 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3176 if (register_netdev(dev1) == 0)
3177 sky2_show_addr(dev1);
3179 /* Failure to register second port need not be fatal */
3180 printk(KERN_WARNING PFX
3181 "register of second port failed\n");
3187 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3189 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3190 pci_name(pdev), pdev->irq);
3191 goto err_out_unregister;
3194 hw->intr_mask = Y2_IS_BASE;
3195 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3197 pci_set_drvdata(pdev, hw);
3203 unregister_netdev(dev1);
3206 unregister_netdev(dev);
3207 err_out_free_netdev:
3210 sky2_write8(hw, B0_CTST, CS_RST_SET);
3211 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3216 err_out_free_regions:
3217 pci_release_regions(pdev);
3218 pci_disable_device(pdev);
3223 static void __devexit sky2_remove(struct pci_dev *pdev)
3225 struct sky2_hw *hw = pci_get_drvdata(pdev);
3226 struct net_device *dev0, *dev1;
3234 unregister_netdev(dev1);
3235 unregister_netdev(dev0);
3237 sky2_write32(hw, B0_IMSK, 0);
3238 sky2_set_power_state(hw, PCI_D3hot);
3239 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3240 sky2_write8(hw, B0_CTST, CS_RST_SET);
3241 sky2_read8(hw, B0_CTST);
3243 free_irq(pdev->irq, hw);
3244 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3245 pci_release_regions(pdev);
3246 pci_disable_device(pdev);
3254 pci_set_drvdata(pdev, NULL);
3258 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3260 struct sky2_hw *hw = pci_get_drvdata(pdev);
3263 for (i = 0; i < 2; i++) {
3264 struct net_device *dev = hw->dev[i];
3267 if (!netif_running(dev))
3271 netif_device_detach(dev);
3275 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3278 static int sky2_resume(struct pci_dev *pdev)
3280 struct sky2_hw *hw = pci_get_drvdata(pdev);
3283 pci_restore_state(pdev);
3284 pci_enable_wake(pdev, PCI_D0, 0);
3285 err = sky2_set_power_state(hw, PCI_D0);
3289 err = sky2_reset(hw);
3293 for (i = 0; i < 2; i++) {
3294 struct net_device *dev = hw->dev[i];
3295 if (dev && netif_running(dev)) {
3296 netif_device_attach(dev);
3299 printk(KERN_ERR PFX "%s: could not up: %d\n",
3311 static struct pci_driver sky2_driver = {
3313 .id_table = sky2_id_table,
3314 .probe = sky2_probe,
3315 .remove = __devexit_p(sky2_remove),
3317 .suspend = sky2_suspend,
3318 .resume = sky2_resume,
3322 static int __init sky2_init_module(void)
3324 return pci_register_driver(&sky2_driver);
3327 static void __exit sky2_cleanup_module(void)
3329 pci_unregister_driver(&sky2_driver);
3332 module_init(sky2_init_module);
3333 module_exit(sky2_cleanup_module);
3335 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3336 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3337 MODULE_LICENSE("GPL");
3338 MODULE_VERSION(DRV_VERSION);