2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.2"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 static const u32 default_msg =
83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87 static int debug = -1; /* defaults above */
88 module_param(debug, int, 0);
89 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly = 256;
92 module_param(copybreak, int, 0);
93 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95 static int disable_msi = 0;
96 module_param(disable_msi, int, 0);
97 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99 static const struct pci_device_id sky2_id_table[] = {
100 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
101 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
102 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
103 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
104 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
105 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
106 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
107 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
120 MODULE_DEVICE_TABLE(pci, sky2_id_table);
122 /* Avoid conditionals by using array */
123 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
124 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
125 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
127 /* This driver supports yukon2 chipset only */
128 static const char *yukon2_name[] = {
130 "EC Ultra", /* 0xb4 */
131 "UNKNOWN", /* 0xb5 */
136 /* Access to external PHY */
137 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
141 gma_write16(hw, port, GM_SMI_DATA, val);
142 gma_write16(hw, port, GM_SMI_CTRL,
143 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
145 for (i = 0; i < PHY_RETRIES; i++) {
146 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
151 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
155 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
159 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
160 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
162 for (i = 0; i < PHY_RETRIES; i++) {
163 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
164 *val = gma_read16(hw, port, GM_SMI_DATA);
174 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
178 if (__gm_phy_read(hw, port, reg, &v) != 0)
179 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
183 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
190 pr_debug("sky2_set_power_state %d\n", state);
191 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
193 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
194 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
195 (power_control & PCI_PM_CAP_PME_D3cold);
197 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
199 power_control |= PCI_PM_CTRL_PME_STATUS;
200 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
204 /* switch power to VCC (WA for VAUX problem) */
205 sky2_write8(hw, B0_POWER_CTRL,
206 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
208 /* disable Core Clock Division, */
209 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
211 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
212 /* enable bits are inverted */
213 sky2_write8(hw, B2_Y2_CLK_GATE,
214 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
215 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
216 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
220 /* Turn off phy power saving */
221 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
222 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
224 /* looks like this XL is back asswards .. */
225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
226 reg1 |= PCI_Y2_PHY1_COMA;
228 reg1 |= PCI_Y2_PHY2_COMA;
231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
232 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
233 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
234 reg1 &= P_ASPM_CONTROL_MSK;
235 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
236 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
239 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
245 /* Turn on phy power saving */
246 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
247 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
248 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
250 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
251 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
253 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
254 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
256 /* enable bits are inverted */
257 sky2_write8(hw, B2_Y2_CLK_GATE,
258 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
259 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
260 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
262 /* switch power to VAUX */
263 if (vaux && state != PCI_D3cold)
264 sky2_write8(hw, B0_POWER_CTRL,
265 (PC_VAUX_ENA | PC_VCC_ENA |
266 PC_VAUX_ON | PC_VCC_OFF));
269 printk(KERN_ERR PFX "Unknown power state %d\n", state);
273 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
274 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
278 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
282 /* disable all GMAC IRQ's */
283 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
284 /* disable PHY IRQs */
285 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
287 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
288 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
289 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
290 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
292 reg = gma_read16(hw, port, GM_RX_CTRL);
293 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
294 gma_write16(hw, port, GM_RX_CTRL, reg);
297 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
299 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
300 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
302 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
303 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
305 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
307 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
309 if (hw->chip_id == CHIP_ID_YUKON_EC)
310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
312 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
314 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
317 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
319 if (hw->chip_id == CHIP_ID_YUKON_FE) {
320 /* enable automatic crossover */
321 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 /* disable energy detect */
324 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326 /* enable automatic crossover */
327 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329 if (sky2->autoneg == AUTONEG_ENABLE &&
330 hw->chip_id == CHIP_ID_YUKON_XL) {
331 ctrl &= ~PHY_M_PC_DSC_MSK;
332 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
335 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
337 /* workaround for deviation #4.88 (CRC errors) */
338 /* disable Automatic Crossover */
340 ctrl &= ~PHY_M_PC_MDIX_MSK;
341 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
343 if (hw->chip_id == CHIP_ID_YUKON_XL) {
344 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
345 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
346 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
347 ctrl &= ~PHY_M_MAC_MD_MSK;
348 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
349 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
351 /* select page 1 to access Fiber registers */
352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
356 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
357 if (sky2->autoneg == AUTONEG_DISABLE)
362 ctrl |= PHY_CT_RESET;
363 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
369 if (sky2->autoneg == AUTONEG_ENABLE) {
371 if (sky2->advertising & ADVERTISED_1000baseT_Full)
372 ct1000 |= PHY_M_1000C_AFD;
373 if (sky2->advertising & ADVERTISED_1000baseT_Half)
374 ct1000 |= PHY_M_1000C_AHD;
375 if (sky2->advertising & ADVERTISED_100baseT_Full)
376 adv |= PHY_M_AN_100_FD;
377 if (sky2->advertising & ADVERTISED_100baseT_Half)
378 adv |= PHY_M_AN_100_HD;
379 if (sky2->advertising & ADVERTISED_10baseT_Full)
380 adv |= PHY_M_AN_10_FD;
381 if (sky2->advertising & ADVERTISED_10baseT_Half)
382 adv |= PHY_M_AN_10_HD;
383 } else /* special defines for FIBER (88E1011S only) */
384 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
386 /* Set Flow-control capabilities */
387 if (sky2->tx_pause && sky2->rx_pause)
388 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
389 else if (sky2->rx_pause && !sky2->tx_pause)
390 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
391 else if (!sky2->rx_pause && sky2->tx_pause)
392 adv |= PHY_AN_PAUSE_ASYM; /* local */
394 /* Restart Auto-negotiation */
395 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
397 /* forced speed/duplex settings */
398 ct1000 = PHY_M_1000C_MSE;
400 if (sky2->duplex == DUPLEX_FULL)
401 ctrl |= PHY_CT_DUP_MD;
403 switch (sky2->speed) {
405 ctrl |= PHY_CT_SP1000;
408 ctrl |= PHY_CT_SP100;
412 ctrl |= PHY_CT_RESET;
415 if (hw->chip_id != CHIP_ID_YUKON_FE)
416 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
418 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
419 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
421 /* Setup Phy LED's */
422 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
425 switch (hw->chip_id) {
426 case CHIP_ID_YUKON_FE:
427 /* on 88E3082 these bits are at 11..9 (shifted left) */
428 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
430 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
432 /* delete ACT LED control bits */
433 ctrl &= ~PHY_M_FELP_LED1_MSK;
434 /* change ACT LED control to blink mode */
435 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
436 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
439 case CHIP_ID_YUKON_XL:
440 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
442 /* select page 3 to access LED control register */
443 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
445 /* set LED Function Control register */
446 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
447 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
448 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
449 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
451 /* set Polarity Control register */
452 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
453 (PHY_M_POLC_LS1_P_MIX(4) |
454 PHY_M_POLC_IS0_P_MIX(4) |
455 PHY_M_POLC_LOS_CTRL(2) |
456 PHY_M_POLC_INIT_CTRL(2) |
457 PHY_M_POLC_STA1_CTRL(2) |
458 PHY_M_POLC_STA0_CTRL(2)));
460 /* restore page register */
461 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
465 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
466 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
467 /* turn off the Rx LED (LED_RX) */
468 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
471 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
472 /* apply fixes in PHY AFE */
473 gm_phy_write(hw, port, 22, 255);
474 /* increase differential signal amplitude in 10BASE-T */
475 gm_phy_write(hw, port, 24, 0xaa99);
476 gm_phy_write(hw, port, 23, 0x2011);
478 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
479 gm_phy_write(hw, port, 24, 0xa204);
480 gm_phy_write(hw, port, 23, 0x2002);
482 /* set page register to 0 */
483 gm_phy_write(hw, port, 22, 0);
485 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
487 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
488 /* turn on 100 Mbps LED (LED_LINK100) */
489 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
493 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
496 /* Enable phy interrupt on auto-negotiation complete (or link up) */
497 if (sky2->autoneg == AUTONEG_ENABLE)
498 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
500 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
503 /* Force a renegotiation */
504 static void sky2_phy_reinit(struct sky2_port *sky2)
506 spin_lock_bh(&sky2->phy_lock);
507 sky2_phy_init(sky2->hw, sky2->port);
508 spin_unlock_bh(&sky2->phy_lock);
511 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
513 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
516 const u8 *addr = hw->dev[port]->dev_addr;
518 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
519 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
521 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
523 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
524 /* WA DEV_472 -- looks like crossed wires on port 2 */
525 /* clear GMAC 1 Control reset */
526 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
528 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
529 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
530 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
531 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
532 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
535 if (sky2->autoneg == AUTONEG_DISABLE) {
536 reg = gma_read16(hw, port, GM_GP_CTRL);
537 reg |= GM_GPCR_AU_ALL_DIS;
538 gma_write16(hw, port, GM_GP_CTRL, reg);
539 gma_read16(hw, port, GM_GP_CTRL);
541 switch (sky2->speed) {
543 reg &= ~GM_GPCR_SPEED_100;
544 reg |= GM_GPCR_SPEED_1000;
547 reg &= ~GM_GPCR_SPEED_1000;
548 reg |= GM_GPCR_SPEED_100;
551 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
555 if (sky2->duplex == DUPLEX_FULL)
556 reg |= GM_GPCR_DUP_FULL;
558 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
560 if (!sky2->tx_pause && !sky2->rx_pause) {
561 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
563 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
564 } else if (sky2->tx_pause && !sky2->rx_pause) {
565 /* disable Rx flow-control */
566 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
569 gma_write16(hw, port, GM_GP_CTRL, reg);
571 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
573 spin_lock_bh(&sky2->phy_lock);
574 sky2_phy_init(hw, port);
575 spin_unlock_bh(&sky2->phy_lock);
578 reg = gma_read16(hw, port, GM_PHY_ADDR);
579 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
581 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
582 gma_read16(hw, port, i);
583 gma_write16(hw, port, GM_PHY_ADDR, reg);
585 /* transmit control */
586 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
588 /* receive control reg: unicast + multicast + no FCS */
589 gma_write16(hw, port, GM_RX_CTRL,
590 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
592 /* transmit flow control */
593 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
595 /* transmit parameter */
596 gma_write16(hw, port, GM_TX_PARAM,
597 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
598 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
599 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
600 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
602 /* serial mode register */
603 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
604 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
606 if (hw->dev[port]->mtu > ETH_DATA_LEN)
607 reg |= GM_SMOD_JUMBO_ENA;
609 gma_write16(hw, port, GM_SERIAL_MODE, reg);
611 /* virtual address for data */
612 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
614 /* physical address: used for pause frames */
615 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
617 /* ignore counter overflows */
618 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
619 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
620 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
622 /* Configure Rx MAC FIFO */
623 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
624 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
625 GMF_OPER_ON | GMF_RX_F_FL_ON);
627 /* Flush Rx MAC FIFO on any flow control or error */
628 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
630 /* Set threshold to 0xa (64 bytes)
631 * ASF disabled so no need to do WA dev #4.30
633 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
635 /* Configure Tx MAC FIFO */
636 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
637 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
639 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
640 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
641 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
642 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
643 /* set Tx GMAC FIFO Almost Empty Threshold */
644 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
645 /* Disable Store & Forward mode for TX */
646 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
652 /* Assign Ram Buffer allocation.
653 * start and end are in units of 4k bytes
654 * ram registers are in units of 64bit words
656 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
660 start = startk * 4096/8;
661 end = (endk * 4096/8) - 1;
663 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
664 sky2_write32(hw, RB_ADDR(q, RB_START), start);
665 sky2_write32(hw, RB_ADDR(q, RB_END), end);
666 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
667 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
669 if (q == Q_R1 || q == Q_R2) {
670 u32 space = (endk - startk) * 4096/8;
671 u32 tp = space - space/4;
673 /* On receive queue's set the thresholds
674 * give receiver priority when > 3/4 full
675 * send pause when down to 2K
677 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
678 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
681 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
682 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
684 /* Enable store & forward on Tx queue's because
685 * Tx FIFO is only 1K on Yukon
687 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
690 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
691 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
694 /* Setup Bus Memory Interface */
695 static void sky2_qset(struct sky2_hw *hw, u16 q)
697 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
698 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
699 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
700 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
703 /* Setup prefetch unit registers. This is the interface between
704 * hardware and driver list elements
706 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
709 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
710 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
711 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
712 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
713 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
714 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
716 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
719 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
721 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
723 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
727 /* Update chip's next pointer */
728 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
731 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
736 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
738 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
739 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
743 /* Return high part of DMA address (could be 32 or 64 bit) */
744 static inline u32 high32(dma_addr_t a)
746 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
749 /* Build description to hardware about buffer */
750 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
752 struct sky2_rx_le *le;
753 u32 hi = high32(map);
754 u16 len = sky2->rx_bufsize;
756 if (sky2->rx_addr64 != hi) {
757 le = sky2_next_rx(sky2);
758 le->addr = cpu_to_le32(hi);
760 le->opcode = OP_ADDR64 | HW_OWNER;
761 sky2->rx_addr64 = high32(map + len);
764 le = sky2_next_rx(sky2);
765 le->addr = cpu_to_le32((u32) map);
766 le->length = cpu_to_le16(len);
768 le->opcode = OP_PACKET | HW_OWNER;
772 /* Tell chip where to start receive checksum.
773 * Actually has two checksums, but set both same to avoid possible byte
776 static void rx_set_checksum(struct sky2_port *sky2)
778 struct sky2_rx_le *le;
780 le = sky2_next_rx(sky2);
781 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
783 le->opcode = OP_TCPSTART | HW_OWNER;
785 sky2_write32(sky2->hw,
786 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
787 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
792 * The RX Stop command will not work for Yukon-2 if the BMU does not
793 * reach the end of packet and since we can't make sure that we have
794 * incoming data, we must reset the BMU while it is not doing a DMA
795 * transfer. Since it is possible that the RX path is still active,
796 * the RX RAM buffer will be stopped first, so any possible incoming
797 * data will not trigger a DMA. After the RAM buffer is stopped, the
798 * BMU is polled until any DMA in progress is ended and only then it
801 static void sky2_rx_stop(struct sky2_port *sky2)
803 struct sky2_hw *hw = sky2->hw;
804 unsigned rxq = rxqaddr[sky2->port];
807 /* disable the RAM Buffer receive queue */
808 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
810 for (i = 0; i < 0xffff; i++)
811 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
812 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
815 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
818 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
820 /* reset the Rx prefetch unit */
821 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
824 /* Clean out receive buffer area, assumes receiver hardware stopped */
825 static void sky2_rx_clean(struct sky2_port *sky2)
829 memset(sky2->rx_le, 0, RX_LE_BYTES);
830 for (i = 0; i < sky2->rx_pending; i++) {
831 struct ring_info *re = sky2->rx_ring + i;
834 pci_unmap_single(sky2->hw->pdev,
835 re->mapaddr, sky2->rx_bufsize,
843 /* Basic MII support */
844 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
846 struct mii_ioctl_data *data = if_mii(ifr);
847 struct sky2_port *sky2 = netdev_priv(dev);
848 struct sky2_hw *hw = sky2->hw;
849 int err = -EOPNOTSUPP;
851 if (!netif_running(dev))
852 return -ENODEV; /* Phy still in reset */
856 data->phy_id = PHY_ADDR_MARV;
862 spin_lock_bh(&sky2->phy_lock);
863 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
864 spin_unlock_bh(&sky2->phy_lock);
871 if (!capable(CAP_NET_ADMIN))
874 spin_lock_bh(&sky2->phy_lock);
875 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
877 spin_unlock_bh(&sky2->phy_lock);
883 #ifdef SKY2_VLAN_TAG_USED
884 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
886 struct sky2_port *sky2 = netdev_priv(dev);
887 struct sky2_hw *hw = sky2->hw;
888 u16 port = sky2->port;
890 spin_lock_bh(&sky2->tx_lock);
892 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
893 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
896 spin_unlock_bh(&sky2->tx_lock);
899 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
901 struct sky2_port *sky2 = netdev_priv(dev);
902 struct sky2_hw *hw = sky2->hw;
903 u16 port = sky2->port;
905 spin_lock_bh(&sky2->tx_lock);
907 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
908 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
910 sky2->vlgrp->vlan_devices[vid] = NULL;
912 spin_unlock_bh(&sky2->tx_lock);
917 * It appears the hardware has a bug in the FIFO logic that
918 * cause it to hang if the FIFO gets overrun and the receive buffer
919 * is not aligned. ALso alloc_skb() won't align properly if slab
920 * debugging is enabled.
922 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
926 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
928 unsigned long p = (unsigned long) skb->data;
929 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
936 * Allocate and setup receiver buffer pool.
937 * In case of 64 bit dma, there are 2X as many list elements
938 * available as ring entries
939 * and need to reserve one list element so we don't wrap around.
941 static int sky2_rx_start(struct sky2_port *sky2)
943 struct sky2_hw *hw = sky2->hw;
944 unsigned rxq = rxqaddr[sky2->port];
947 sky2->rx_put = sky2->rx_next = 0;
950 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
951 /* MAC Rx RAM Read is controlled by hardware */
952 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
955 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
957 rx_set_checksum(sky2);
958 for (i = 0; i < sky2->rx_pending; i++) {
959 struct ring_info *re = sky2->rx_ring + i;
961 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
965 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
966 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
967 sky2_rx_add(sky2, re->mapaddr);
970 /* Truncate oversize frames */
971 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
972 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
974 /* Tell chip about available buffers */
975 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
982 /* Bring up network interface. */
983 static int sky2_up(struct net_device *dev)
985 struct sky2_port *sky2 = netdev_priv(dev);
986 struct sky2_hw *hw = sky2->hw;
987 unsigned port = sky2->port;
988 u32 ramsize, rxspace, imask;
991 if (netif_msg_ifup(sky2))
992 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
994 /* must be power of 2 */
995 sky2->tx_le = pci_alloc_consistent(hw->pdev,
997 sizeof(struct sky2_tx_le),
1002 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1006 sky2->tx_prod = sky2->tx_cons = 0;
1008 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1012 memset(sky2->rx_le, 0, RX_LE_BYTES);
1014 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1019 sky2_mac_init(hw, port);
1021 /* Determine available ram buffer space (in 4K blocks).
1022 * Note: not sure about the FE setting below yet
1024 if (hw->chip_id == CHIP_ID_YUKON_FE)
1027 ramsize = sky2_read8(hw, B2_E_0);
1029 /* Give transmitter one third (rounded up) */
1030 rxspace = ramsize - (ramsize + 2) / 3;
1032 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1033 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1035 /* Make sure SyncQ is disabled */
1036 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1039 sky2_qset(hw, txqaddr[port]);
1041 /* Set almost empty threshold */
1042 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1043 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1045 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1048 err = sky2_rx_start(sky2);
1052 /* Enable interrupts from phy/mac for port */
1053 imask = sky2_read32(hw, B0_IMSK);
1054 imask |= portirq_msk[port];
1055 sky2_write32(hw, B0_IMSK, imask);
1061 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1062 sky2->rx_le, sky2->rx_le_map);
1066 pci_free_consistent(hw->pdev,
1067 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1068 sky2->tx_le, sky2->tx_le_map);
1071 kfree(sky2->tx_ring);
1072 kfree(sky2->rx_ring);
1074 sky2->tx_ring = NULL;
1075 sky2->rx_ring = NULL;
1079 /* Modular subtraction in ring */
1080 static inline int tx_dist(unsigned tail, unsigned head)
1082 return (head - tail) % TX_RING_SIZE;
1085 /* Number of list elements available for next tx */
1086 static inline int tx_avail(const struct sky2_port *sky2)
1088 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1091 /* Estimate of number of transmit list elements required */
1092 static unsigned tx_le_req(const struct sk_buff *skb)
1096 count = sizeof(dma_addr_t) / sizeof(u32);
1097 count += skb_shinfo(skb)->nr_frags * count;
1099 if (skb_shinfo(skb)->tso_size)
1102 if (skb->ip_summed == CHECKSUM_HW)
1109 * Put one packet in ring for transmit.
1110 * A single packet can generate multiple list elements, and
1111 * the number of ring elements will probably be less than the number
1112 * of list elements used.
1114 * No BH disabling for tx_lock here (like tg3)
1116 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1118 struct sky2_port *sky2 = netdev_priv(dev);
1119 struct sky2_hw *hw = sky2->hw;
1120 struct sky2_tx_le *le = NULL;
1121 struct tx_ring_info *re;
1129 /* No BH disabling for tx_lock here. We are running in BH disabled
1130 * context and TX reclaim runs via poll inside of a software
1131 * interrupt, and no related locks in IRQ processing.
1133 if (!spin_trylock(&sky2->tx_lock))
1134 return NETDEV_TX_LOCKED;
1136 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1137 /* There is a known but harmless race with lockless tx
1138 * and netif_stop_queue.
1140 if (!netif_queue_stopped(dev)) {
1141 netif_stop_queue(dev);
1142 if (net_ratelimit())
1143 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1146 spin_unlock(&sky2->tx_lock);
1148 return NETDEV_TX_BUSY;
1151 if (unlikely(netif_msg_tx_queued(sky2)))
1152 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1153 dev->name, sky2->tx_prod, skb->len);
1155 len = skb_headlen(skb);
1156 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1157 addr64 = high32(mapping);
1159 re = sky2->tx_ring + sky2->tx_prod;
1161 /* Send high bits if changed or crosses boundary */
1162 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1163 le = get_tx_le(sky2);
1164 le->tx.addr = cpu_to_le32(addr64);
1166 le->opcode = OP_ADDR64 | HW_OWNER;
1167 sky2->tx_addr64 = high32(mapping + len);
1170 /* Check for TCP Segmentation Offload */
1171 mss = skb_shinfo(skb)->tso_size;
1173 /* just drop the packet if non-linear expansion fails */
1174 if (skb_header_cloned(skb) &&
1175 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1180 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1181 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1185 if (mss != sky2->tx_last_mss) {
1186 le = get_tx_le(sky2);
1187 le->tx.tso.size = cpu_to_le16(mss);
1188 le->tx.tso.rsvd = 0;
1189 le->opcode = OP_LRGLEN | HW_OWNER;
1191 sky2->tx_last_mss = mss;
1195 #ifdef SKY2_VLAN_TAG_USED
1196 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1197 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1199 le = get_tx_le(sky2);
1201 le->opcode = OP_VLAN|HW_OWNER;
1204 le->opcode |= OP_VLAN;
1205 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1210 /* Handle TCP checksum offload */
1211 if (skb->ip_summed == CHECKSUM_HW) {
1212 u16 hdr = skb->h.raw - skb->data;
1213 u16 offset = hdr + skb->csum;
1215 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1216 if (skb->nh.iph->protocol == IPPROTO_UDP)
1219 le = get_tx_le(sky2);
1220 le->tx.csum.start = cpu_to_le16(hdr);
1221 le->tx.csum.offset = cpu_to_le16(offset);
1222 le->length = 0; /* initial checksum value */
1223 le->ctrl = 1; /* one packet */
1224 le->opcode = OP_TCPLISW | HW_OWNER;
1227 le = get_tx_le(sky2);
1228 le->tx.addr = cpu_to_le32((u32) mapping);
1229 le->length = cpu_to_le16(len);
1231 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1233 /* Record the transmit mapping info */
1235 pci_unmap_addr_set(re, mapaddr, mapping);
1237 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1238 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1239 struct tx_ring_info *fre;
1241 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1242 frag->size, PCI_DMA_TODEVICE);
1243 addr64 = high32(mapping);
1244 if (addr64 != sky2->tx_addr64) {
1245 le = get_tx_le(sky2);
1246 le->tx.addr = cpu_to_le32(addr64);
1248 le->opcode = OP_ADDR64 | HW_OWNER;
1249 sky2->tx_addr64 = addr64;
1252 le = get_tx_le(sky2);
1253 le->tx.addr = cpu_to_le32((u32) mapping);
1254 le->length = cpu_to_le16(frag->size);
1256 le->opcode = OP_BUFFER | HW_OWNER;
1259 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1260 pci_unmap_addr_set(fre, mapaddr, mapping);
1263 re->idx = sky2->tx_prod;
1266 avail = tx_avail(sky2);
1267 if (mss != 0 || avail < TX_MIN_PENDING) {
1268 le->ctrl |= FRC_STAT;
1269 if (avail <= MAX_SKB_TX_LE)
1270 netif_stop_queue(dev);
1273 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1276 spin_unlock(&sky2->tx_lock);
1278 dev->trans_start = jiffies;
1279 return NETDEV_TX_OK;
1283 * Free ring elements from starting at tx_cons until "done"
1285 * NB: the hardware will tell us about partial completion of multi-part
1286 * buffers; these are deferred until completion.
1288 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1290 struct net_device *dev = sky2->netdev;
1291 struct pci_dev *pdev = sky2->hw->pdev;
1295 BUG_ON(done >= TX_RING_SIZE);
1297 if (unlikely(netif_msg_tx_done(sky2)))
1298 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1301 for (put = sky2->tx_cons; put != done; put = nxt) {
1302 struct tx_ring_info *re = sky2->tx_ring + put;
1303 struct sk_buff *skb = re->skb;
1306 BUG_ON(nxt >= TX_RING_SIZE);
1307 prefetch(sky2->tx_ring + nxt);
1309 /* Check for partial status */
1310 if (tx_dist(put, done) < tx_dist(put, nxt))
1314 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1315 skb_headlen(skb), PCI_DMA_TODEVICE);
1317 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1318 struct tx_ring_info *fre;
1319 fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
1320 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1321 skb_shinfo(skb)->frags[i].size,
1328 sky2->tx_cons = put;
1329 if (tx_avail(sky2) > MAX_SKB_TX_LE)
1330 netif_wake_queue(dev);
1333 /* Cleanup all untransmitted buffers, assume transmitter not running */
1334 static void sky2_tx_clean(struct sky2_port *sky2)
1336 spin_lock_bh(&sky2->tx_lock);
1337 sky2_tx_complete(sky2, sky2->tx_prod);
1338 spin_unlock_bh(&sky2->tx_lock);
1341 /* Network shutdown */
1342 static int sky2_down(struct net_device *dev)
1344 struct sky2_port *sky2 = netdev_priv(dev);
1345 struct sky2_hw *hw = sky2->hw;
1346 unsigned port = sky2->port;
1350 /* Never really got started! */
1354 if (netif_msg_ifdown(sky2))
1355 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1357 /* Stop more packets from being queued */
1358 netif_stop_queue(dev);
1360 sky2_phy_reset(hw, port);
1362 /* Stop transmitter */
1363 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1364 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1366 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1367 RB_RST_SET | RB_DIS_OP_MD);
1369 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1370 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1371 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1373 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1375 /* Workaround shared GMAC reset */
1376 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1377 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1378 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1380 /* Disable Force Sync bit and Enable Alloc bit */
1381 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1382 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1384 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1385 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1386 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1388 /* Reset the PCI FIFO of the async Tx queue */
1389 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1390 BMU_RST_SET | BMU_FIFO_RST);
1392 /* Reset the Tx prefetch units */
1393 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1396 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1400 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1401 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1403 /* Disable port IRQ */
1404 imask = sky2_read32(hw, B0_IMSK);
1405 imask &= ~portirq_msk[port];
1406 sky2_write32(hw, B0_IMSK, imask);
1408 /* turn off LED's */
1409 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1411 synchronize_irq(hw->pdev->irq);
1413 sky2_tx_clean(sky2);
1414 sky2_rx_clean(sky2);
1416 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1417 sky2->rx_le, sky2->rx_le_map);
1418 kfree(sky2->rx_ring);
1420 pci_free_consistent(hw->pdev,
1421 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1422 sky2->tx_le, sky2->tx_le_map);
1423 kfree(sky2->tx_ring);
1428 sky2->rx_ring = NULL;
1429 sky2->tx_ring = NULL;
1434 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1439 if (hw->chip_id == CHIP_ID_YUKON_FE)
1440 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1442 switch (aux & PHY_M_PS_SPEED_MSK) {
1443 case PHY_M_PS_SPEED_1000:
1445 case PHY_M_PS_SPEED_100:
1452 static void sky2_link_up(struct sky2_port *sky2)
1454 struct sky2_hw *hw = sky2->hw;
1455 unsigned port = sky2->port;
1458 /* Enable Transmit FIFO Underrun */
1459 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1461 reg = gma_read16(hw, port, GM_GP_CTRL);
1462 if (sky2->autoneg == AUTONEG_DISABLE) {
1463 reg |= GM_GPCR_AU_ALL_DIS;
1465 /* Is write/read necessary? Copied from sky2_mac_init */
1466 gma_write16(hw, port, GM_GP_CTRL, reg);
1467 gma_read16(hw, port, GM_GP_CTRL);
1469 switch (sky2->speed) {
1471 reg &= ~GM_GPCR_SPEED_100;
1472 reg |= GM_GPCR_SPEED_1000;
1475 reg &= ~GM_GPCR_SPEED_1000;
1476 reg |= GM_GPCR_SPEED_100;
1479 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1483 reg &= ~GM_GPCR_AU_ALL_DIS;
1485 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1486 reg |= GM_GPCR_DUP_FULL;
1489 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1490 gma_write16(hw, port, GM_GP_CTRL, reg);
1491 gma_read16(hw, port, GM_GP_CTRL);
1493 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1495 netif_carrier_on(sky2->netdev);
1496 netif_wake_queue(sky2->netdev);
1498 /* Turn on link LED */
1499 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1500 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1502 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1503 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1506 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1507 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1509 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1510 SPEED_100 ? 7 : 0) |
1511 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1512 SPEED_1000 ? 7 : 0));
1513 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1516 if (netif_msg_link(sky2))
1517 printk(KERN_INFO PFX
1518 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1519 sky2->netdev->name, sky2->speed,
1520 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1521 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1522 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1525 static void sky2_link_down(struct sky2_port *sky2)
1527 struct sky2_hw *hw = sky2->hw;
1528 unsigned port = sky2->port;
1531 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1533 reg = gma_read16(hw, port, GM_GP_CTRL);
1534 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1535 gma_write16(hw, port, GM_GP_CTRL, reg);
1536 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1538 if (sky2->rx_pause && !sky2->tx_pause) {
1539 /* restore Asymmetric Pause bit */
1540 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1541 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1545 netif_carrier_off(sky2->netdev);
1546 netif_stop_queue(sky2->netdev);
1548 /* Turn on link LED */
1549 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1551 if (netif_msg_link(sky2))
1552 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1553 sky2_phy_init(hw, port);
1556 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1558 struct sky2_hw *hw = sky2->hw;
1559 unsigned port = sky2->port;
1562 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1564 if (lpa & PHY_M_AN_RF) {
1565 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1569 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1570 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1571 printk(KERN_ERR PFX "%s: master/slave fault",
1572 sky2->netdev->name);
1576 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1577 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1578 sky2->netdev->name);
1582 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1584 sky2->speed = sky2_phy_speed(hw, aux);
1586 /* Pause bits are offset (9..8) */
1587 if (hw->chip_id == CHIP_ID_YUKON_XL)
1590 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1591 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1593 if ((sky2->tx_pause || sky2->rx_pause)
1594 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1595 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1602 /* Interrupt from PHY */
1603 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1605 struct net_device *dev = hw->dev[port];
1606 struct sky2_port *sky2 = netdev_priv(dev);
1607 u16 istatus, phystat;
1609 spin_lock(&sky2->phy_lock);
1610 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1611 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1613 if (!netif_running(dev))
1616 if (netif_msg_intr(sky2))
1617 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1618 sky2->netdev->name, istatus, phystat);
1620 if (istatus & PHY_M_IS_AN_COMPL) {
1621 if (sky2_autoneg_done(sky2, phystat) == 0)
1626 if (istatus & PHY_M_IS_LSP_CHANGE)
1627 sky2->speed = sky2_phy_speed(hw, phystat);
1629 if (istatus & PHY_M_IS_DUP_CHANGE)
1631 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1633 if (istatus & PHY_M_IS_LST_CHANGE) {
1634 if (phystat & PHY_M_PS_LINK_UP)
1637 sky2_link_down(sky2);
1640 spin_unlock(&sky2->phy_lock);
1644 /* Transmit timeout is only called if we are running, carries is up
1645 * and tx queue is full (stopped).
1647 static void sky2_tx_timeout(struct net_device *dev)
1649 struct sky2_port *sky2 = netdev_priv(dev);
1650 struct sky2_hw *hw = sky2->hw;
1651 unsigned txq = txqaddr[sky2->port];
1654 if (netif_msg_timer(sky2))
1655 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1657 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1658 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1660 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1662 sky2->tx_cons, sky2->tx_prod, report, done);
1664 if (report != done) {
1665 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1667 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1668 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1669 } else if (report != sky2->tx_cons) {
1670 printk(KERN_INFO PFX "status report lost?\n");
1672 spin_lock_bh(&sky2->tx_lock);
1673 sky2_tx_complete(sky2, report);
1674 spin_unlock_bh(&sky2->tx_lock);
1676 printk(KERN_INFO PFX "hardware hung? flushing\n");
1678 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1679 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1681 sky2_tx_clean(sky2);
1684 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1689 /* Want receive buffer size to be multiple of 64 bits
1690 * and incl room for vlan and truncation
1692 static inline unsigned sky2_buf_size(int mtu)
1694 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1697 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1699 struct sky2_port *sky2 = netdev_priv(dev);
1700 struct sky2_hw *hw = sky2->hw;
1705 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1708 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1711 if (!netif_running(dev)) {
1716 imask = sky2_read32(hw, B0_IMSK);
1717 sky2_write32(hw, B0_IMSK, 0);
1719 dev->trans_start = jiffies; /* prevent tx timeout */
1720 netif_stop_queue(dev);
1721 netif_poll_disable(hw->dev[0]);
1723 synchronize_irq(hw->pdev->irq);
1725 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1726 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1728 sky2_rx_clean(sky2);
1731 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1732 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1733 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1735 if (dev->mtu > ETH_DATA_LEN)
1736 mode |= GM_SMOD_JUMBO_ENA;
1738 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1740 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1742 err = sky2_rx_start(sky2);
1743 sky2_write32(hw, B0_IMSK, imask);
1748 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1750 netif_poll_enable(hw->dev[0]);
1751 netif_wake_queue(dev);
1758 * Receive one packet.
1759 * For small packets or errors, just reuse existing skb.
1760 * For larger packets, get new buffer.
1762 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1763 u16 length, u32 status)
1765 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1766 struct sk_buff *skb = NULL;
1768 if (unlikely(netif_msg_rx_status(sky2)))
1769 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1770 sky2->netdev->name, sky2->rx_next, status, length);
1772 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1773 prefetch(sky2->rx_ring + sky2->rx_next);
1775 if (status & GMR_FS_ANY_ERR)
1778 if (!(status & GMR_FS_RX_OK))
1781 if (length > sky2->netdev->mtu + ETH_HLEN)
1784 if (length < copybreak) {
1785 skb = alloc_skb(length + 2, GFP_ATOMIC);
1789 skb_reserve(skb, 2);
1790 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1791 length, PCI_DMA_FROMDEVICE);
1792 memcpy(skb->data, re->skb->data, length);
1793 skb->ip_summed = re->skb->ip_summed;
1794 skb->csum = re->skb->csum;
1795 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1796 length, PCI_DMA_FROMDEVICE);
1798 struct sk_buff *nskb;
1800 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1806 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1807 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1808 prefetch(skb->data);
1810 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1811 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1814 skb_put(skb, length);
1816 re->skb->ip_summed = CHECKSUM_NONE;
1817 sky2_rx_add(sky2, re->mapaddr);
1819 /* Tell receiver about new buffers. */
1820 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
1825 ++sky2->net_stats.rx_over_errors;
1829 ++sky2->net_stats.rx_errors;
1831 if (netif_msg_rx_err(sky2) && net_ratelimit())
1832 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1833 sky2->netdev->name, status, length);
1835 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1836 sky2->net_stats.rx_length_errors++;
1837 if (status & GMR_FS_FRAGMENT)
1838 sky2->net_stats.rx_frame_errors++;
1839 if (status & GMR_FS_CRC_ERR)
1840 sky2->net_stats.rx_crc_errors++;
1841 if (status & GMR_FS_RX_FF_OV)
1842 sky2->net_stats.rx_fifo_errors++;
1847 /* Transmit complete */
1848 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1850 struct sky2_port *sky2 = netdev_priv(dev);
1852 if (netif_running(dev)) {
1853 spin_lock(&sky2->tx_lock);
1854 sky2_tx_complete(sky2, last);
1855 spin_unlock(&sky2->tx_lock);
1859 /* Process status response ring */
1860 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1867 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1868 struct net_device *dev;
1869 struct sky2_port *sky2;
1870 struct sk_buff *skb;
1875 opcode = le->opcode;
1878 opcode &= ~HW_OWNER;
1880 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1885 dev = hw->dev[link];
1887 sky2 = netdev_priv(dev);
1888 length = le->length;
1889 status = le->status;
1893 skb = sky2_receive(sky2, length, status);
1898 skb->protocol = eth_type_trans(skb, dev);
1899 dev->last_rx = jiffies;
1901 #ifdef SKY2_VLAN_TAG_USED
1902 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1903 vlan_hwaccel_receive_skb(skb,
1905 be16_to_cpu(sky2->rx_tag));
1908 netif_receive_skb(skb);
1910 if (++work_done >= to_do)
1914 #ifdef SKY2_VLAN_TAG_USED
1916 sky2->rx_tag = length;
1920 sky2->rx_tag = length;
1924 skb = sky2->rx_ring[sky2->rx_next].skb;
1925 skb->ip_summed = CHECKSUM_HW;
1926 skb->csum = le16_to_cpu(status);
1930 /* TX index reports status for both ports */
1931 sky2_tx_done(hw->dev[0], status & 0xffff);
1933 sky2_tx_done(hw->dev[1],
1934 ((status >> 24) & 0xff)
1935 | (u16)(length & 0xf) << 8);
1939 if (net_ratelimit())
1940 printk(KERN_WARNING PFX
1941 "unknown status opcode 0x%x\n", opcode);
1950 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1952 struct net_device *dev = hw->dev[port];
1954 if (net_ratelimit())
1955 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1958 if (status & Y2_IS_PAR_RD1) {
1959 if (net_ratelimit())
1960 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1963 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1966 if (status & Y2_IS_PAR_WR1) {
1967 if (net_ratelimit())
1968 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1971 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1974 if (status & Y2_IS_PAR_MAC1) {
1975 if (net_ratelimit())
1976 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1977 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1980 if (status & Y2_IS_PAR_RX1) {
1981 if (net_ratelimit())
1982 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1983 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1986 if (status & Y2_IS_TCP_TXA1) {
1987 if (net_ratelimit())
1988 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
1990 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1994 static void sky2_hw_intr(struct sky2_hw *hw)
1996 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1998 if (status & Y2_IS_TIST_OV)
1999 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2001 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2004 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2005 if (net_ratelimit())
2006 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2007 pci_name(hw->pdev), pci_err);
2009 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2010 sky2_pci_write16(hw, PCI_STATUS,
2011 pci_err | PCI_STATUS_ERROR_BITS);
2012 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2015 if (status & Y2_IS_PCI_EXP) {
2016 /* PCI-Express uncorrectable Error occurred */
2019 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2021 if (net_ratelimit())
2022 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2023 pci_name(hw->pdev), pex_err);
2025 /* clear the interrupt */
2026 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2027 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2029 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2031 if (pex_err & PEX_FATAL_ERRORS) {
2032 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2033 hwmsk &= ~Y2_IS_PCI_EXP;
2034 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2038 if (status & Y2_HWE_L1_MASK)
2039 sky2_hw_error(hw, 0, status);
2041 if (status & Y2_HWE_L1_MASK)
2042 sky2_hw_error(hw, 1, status);
2045 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2047 struct net_device *dev = hw->dev[port];
2048 struct sky2_port *sky2 = netdev_priv(dev);
2049 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2051 if (netif_msg_intr(sky2))
2052 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2055 if (status & GM_IS_RX_FF_OR) {
2056 ++sky2->net_stats.rx_fifo_errors;
2057 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2060 if (status & GM_IS_TX_FF_UR) {
2061 ++sky2->net_stats.tx_fifo_errors;
2062 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2066 /* This should never happen it is a fatal situation */
2067 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2068 const char *rxtx, u32 mask)
2070 struct net_device *dev = hw->dev[port];
2071 struct sky2_port *sky2 = netdev_priv(dev);
2074 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2075 dev ? dev->name : "<not registered>", rxtx);
2077 imask = sky2_read32(hw, B0_IMSK);
2079 sky2_write32(hw, B0_IMSK, imask);
2082 spin_lock(&sky2->phy_lock);
2083 sky2_link_down(sky2);
2084 spin_unlock(&sky2->phy_lock);
2088 /* If idle then force a fake soft NAPI poll once a second
2089 * to work around cases where sharing an edge triggered interrupt.
2091 static void sky2_idle(unsigned long arg)
2093 struct net_device *dev = (struct net_device *) arg;
2095 local_irq_disable();
2096 if (__netif_rx_schedule_prep(dev))
2097 __netif_rx_schedule(dev);
2102 static int sky2_poll(struct net_device *dev0, int *budget)
2104 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2105 int work_limit = min(dev0->quota, *budget);
2107 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2110 if (unlikely(status & ~Y2_IS_STAT_BMU)) {
2111 if (status & Y2_IS_HW_ERR)
2114 if (status & Y2_IS_IRQ_PHY1)
2115 sky2_phy_intr(hw, 0);
2117 if (status & Y2_IS_IRQ_PHY2)
2118 sky2_phy_intr(hw, 1);
2120 if (status & Y2_IS_IRQ_MAC1)
2121 sky2_mac_intr(hw, 0);
2123 if (status & Y2_IS_IRQ_MAC2)
2124 sky2_mac_intr(hw, 1);
2126 if (status & Y2_IS_CHK_RX1)
2127 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2129 if (status & Y2_IS_CHK_RX2)
2130 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2132 if (status & Y2_IS_CHK_TXA1)
2133 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2135 if (status & Y2_IS_CHK_TXA2)
2136 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2139 if (status & Y2_IS_STAT_BMU) {
2140 work_done += sky2_status_intr(hw, work_limit - work_done);
2141 *budget -= work_done;
2142 dev0->quota -= work_done;
2144 if (work_done >= work_limit)
2147 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2150 mod_timer(&hw->idle_timer, jiffies + HZ);
2152 local_irq_disable();
2153 __netif_rx_complete(dev0);
2155 status = sky2_read32(hw, B0_Y2_SP_LISR);
2157 if (unlikely(status)) {
2158 /* More work pending, try and keep going */
2159 if (__netif_rx_schedule_prep(dev0)) {
2160 __netif_rx_reschedule(dev0, work_done);
2161 status = sky2_read32(hw, B0_Y2_SP_EISR);
2171 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2173 struct sky2_hw *hw = dev_id;
2174 struct net_device *dev0 = hw->dev[0];
2177 /* Reading this mask interrupts as side effect */
2178 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2179 if (status == 0 || status == ~0)
2182 prefetch(&hw->st_le[hw->st_idx]);
2183 if (likely(__netif_rx_schedule_prep(dev0)))
2184 __netif_rx_schedule(dev0);
2189 #ifdef CONFIG_NET_POLL_CONTROLLER
2190 static void sky2_netpoll(struct net_device *dev)
2192 struct sky2_port *sky2 = netdev_priv(dev);
2194 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2198 /* Chip internal frequency for clock calculations */
2199 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2201 switch (hw->chip_id) {
2202 case CHIP_ID_YUKON_EC:
2203 case CHIP_ID_YUKON_EC_U:
2204 return 125; /* 125 Mhz */
2205 case CHIP_ID_YUKON_FE:
2206 return 100; /* 100 Mhz */
2207 default: /* YUKON_XL */
2208 return 156; /* 156 Mhz */
2212 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2214 return sky2_mhz(hw) * us;
2217 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2219 return clk / sky2_mhz(hw);
2223 static int __devinit sky2_reset(struct sky2_hw *hw)
2229 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2231 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2232 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2233 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2234 pci_name(hw->pdev), hw->chip_id);
2238 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2240 /* This rev is really old, and requires untested workarounds */
2241 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2242 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2243 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2244 hw->chip_id, hw->chip_rev);
2248 /* This chip is new and not tested yet */
2249 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
2250 pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
2251 pci_name(hw->pdev));
2252 pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
2256 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2257 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2258 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2262 sky2_write8(hw, B0_CTST, CS_RST_SET);
2263 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2265 /* clear PCI errors, if any */
2266 status = sky2_pci_read16(hw, PCI_STATUS);
2268 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2269 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2272 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2274 /* clear any PEX errors */
2275 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2276 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2279 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2280 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2283 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2284 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2285 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2289 sky2_set_power_state(hw, PCI_D0);
2291 for (i = 0; i < hw->ports; i++) {
2292 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2293 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2296 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2298 /* Clear I2C IRQ noise */
2299 sky2_write32(hw, B2_I2C_IRQ, 1);
2301 /* turn off hardware timer (unused) */
2302 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2303 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2305 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2307 /* Turn off descriptor polling */
2308 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2310 /* Turn off receive timestamp */
2311 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2312 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2314 /* enable the Tx Arbiters */
2315 for (i = 0; i < hw->ports; i++)
2316 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2318 /* Initialize ram interface */
2319 for (i = 0; i < hw->ports; i++) {
2320 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2322 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2323 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2324 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2325 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2326 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2327 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2328 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2329 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2330 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2331 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2332 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2333 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2336 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2338 for (i = 0; i < hw->ports; i++)
2339 sky2_phy_reset(hw, i);
2341 memset(hw->st_le, 0, STATUS_LE_BYTES);
2344 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2345 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2347 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2348 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2350 /* Set the list last index */
2351 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2353 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2354 sky2_write8(hw, STAT_FIFO_WM, 16);
2356 /* set Status-FIFO ISR watermark */
2357 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2358 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2360 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2362 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2363 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2364 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2366 /* enable status unit */
2367 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2369 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2370 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2371 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2376 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2380 modes = SUPPORTED_10baseT_Half
2381 | SUPPORTED_10baseT_Full
2382 | SUPPORTED_100baseT_Half
2383 | SUPPORTED_100baseT_Full
2384 | SUPPORTED_Autoneg | SUPPORTED_TP;
2386 if (hw->chip_id != CHIP_ID_YUKON_FE)
2387 modes |= SUPPORTED_1000baseT_Half
2388 | SUPPORTED_1000baseT_Full;
2390 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2391 | SUPPORTED_Autoneg;
2395 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2397 struct sky2_port *sky2 = netdev_priv(dev);
2398 struct sky2_hw *hw = sky2->hw;
2400 ecmd->transceiver = XCVR_INTERNAL;
2401 ecmd->supported = sky2_supported_modes(hw);
2402 ecmd->phy_address = PHY_ADDR_MARV;
2404 ecmd->supported = SUPPORTED_10baseT_Half
2405 | SUPPORTED_10baseT_Full
2406 | SUPPORTED_100baseT_Half
2407 | SUPPORTED_100baseT_Full
2408 | SUPPORTED_1000baseT_Half
2409 | SUPPORTED_1000baseT_Full
2410 | SUPPORTED_Autoneg | SUPPORTED_TP;
2411 ecmd->port = PORT_TP;
2413 ecmd->port = PORT_FIBRE;
2415 ecmd->advertising = sky2->advertising;
2416 ecmd->autoneg = sky2->autoneg;
2417 ecmd->speed = sky2->speed;
2418 ecmd->duplex = sky2->duplex;
2422 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2424 struct sky2_port *sky2 = netdev_priv(dev);
2425 const struct sky2_hw *hw = sky2->hw;
2426 u32 supported = sky2_supported_modes(hw);
2428 if (ecmd->autoneg == AUTONEG_ENABLE) {
2429 ecmd->advertising = supported;
2435 switch (ecmd->speed) {
2437 if (ecmd->duplex == DUPLEX_FULL)
2438 setting = SUPPORTED_1000baseT_Full;
2439 else if (ecmd->duplex == DUPLEX_HALF)
2440 setting = SUPPORTED_1000baseT_Half;
2445 if (ecmd->duplex == DUPLEX_FULL)
2446 setting = SUPPORTED_100baseT_Full;
2447 else if (ecmd->duplex == DUPLEX_HALF)
2448 setting = SUPPORTED_100baseT_Half;
2454 if (ecmd->duplex == DUPLEX_FULL)
2455 setting = SUPPORTED_10baseT_Full;
2456 else if (ecmd->duplex == DUPLEX_HALF)
2457 setting = SUPPORTED_10baseT_Half;
2465 if ((setting & supported) == 0)
2468 sky2->speed = ecmd->speed;
2469 sky2->duplex = ecmd->duplex;
2472 sky2->autoneg = ecmd->autoneg;
2473 sky2->advertising = ecmd->advertising;
2475 if (netif_running(dev))
2476 sky2_phy_reinit(sky2);
2481 static void sky2_get_drvinfo(struct net_device *dev,
2482 struct ethtool_drvinfo *info)
2484 struct sky2_port *sky2 = netdev_priv(dev);
2486 strcpy(info->driver, DRV_NAME);
2487 strcpy(info->version, DRV_VERSION);
2488 strcpy(info->fw_version, "N/A");
2489 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2492 static const struct sky2_stat {
2493 char name[ETH_GSTRING_LEN];
2496 { "tx_bytes", GM_TXO_OK_HI },
2497 { "rx_bytes", GM_RXO_OK_HI },
2498 { "tx_broadcast", GM_TXF_BC_OK },
2499 { "rx_broadcast", GM_RXF_BC_OK },
2500 { "tx_multicast", GM_TXF_MC_OK },
2501 { "rx_multicast", GM_RXF_MC_OK },
2502 { "tx_unicast", GM_TXF_UC_OK },
2503 { "rx_unicast", GM_RXF_UC_OK },
2504 { "tx_mac_pause", GM_TXF_MPAUSE },
2505 { "rx_mac_pause", GM_RXF_MPAUSE },
2506 { "collisions", GM_TXF_COL },
2507 { "late_collision",GM_TXF_LAT_COL },
2508 { "aborted", GM_TXF_ABO_COL },
2509 { "single_collisions", GM_TXF_SNG_COL },
2510 { "multi_collisions", GM_TXF_MUL_COL },
2512 { "rx_short", GM_RXF_SHT },
2513 { "rx_runt", GM_RXE_FRAG },
2514 { "rx_64_byte_packets", GM_RXF_64B },
2515 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2516 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2517 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2518 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2519 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2520 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2521 { "rx_too_long", GM_RXF_LNG_ERR },
2522 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2523 { "rx_jabber", GM_RXF_JAB_PKT },
2524 { "rx_fcs_error", GM_RXF_FCS_ERR },
2526 { "tx_64_byte_packets", GM_TXF_64B },
2527 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2528 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2529 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2530 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2531 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2532 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2533 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2536 static u32 sky2_get_rx_csum(struct net_device *dev)
2538 struct sky2_port *sky2 = netdev_priv(dev);
2540 return sky2->rx_csum;
2543 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2545 struct sky2_port *sky2 = netdev_priv(dev);
2547 sky2->rx_csum = data;
2549 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2550 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2555 static u32 sky2_get_msglevel(struct net_device *netdev)
2557 struct sky2_port *sky2 = netdev_priv(netdev);
2558 return sky2->msg_enable;
2561 static int sky2_nway_reset(struct net_device *dev)
2563 struct sky2_port *sky2 = netdev_priv(dev);
2565 if (sky2->autoneg != AUTONEG_ENABLE)
2568 sky2_phy_reinit(sky2);
2573 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2575 struct sky2_hw *hw = sky2->hw;
2576 unsigned port = sky2->port;
2579 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2580 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2581 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2582 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2584 for (i = 2; i < count; i++)
2585 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2588 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2590 struct sky2_port *sky2 = netdev_priv(netdev);
2591 sky2->msg_enable = value;
2594 static int sky2_get_stats_count(struct net_device *dev)
2596 return ARRAY_SIZE(sky2_stats);
2599 static void sky2_get_ethtool_stats(struct net_device *dev,
2600 struct ethtool_stats *stats, u64 * data)
2602 struct sky2_port *sky2 = netdev_priv(dev);
2604 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2607 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2611 switch (stringset) {
2613 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2614 memcpy(data + i * ETH_GSTRING_LEN,
2615 sky2_stats[i].name, ETH_GSTRING_LEN);
2620 /* Use hardware MIB variables for critical path statistics and
2621 * transmit feedback not reported at interrupt.
2622 * Other errors are accounted for in interrupt handler.
2624 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2626 struct sky2_port *sky2 = netdev_priv(dev);
2629 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2631 sky2->net_stats.tx_bytes = data[0];
2632 sky2->net_stats.rx_bytes = data[1];
2633 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2634 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2635 sky2->net_stats.multicast = data[3] + data[5];
2636 sky2->net_stats.collisions = data[10];
2637 sky2->net_stats.tx_aborted_errors = data[12];
2639 return &sky2->net_stats;
2642 static int sky2_set_mac_address(struct net_device *dev, void *p)
2644 struct sky2_port *sky2 = netdev_priv(dev);
2645 struct sky2_hw *hw = sky2->hw;
2646 unsigned port = sky2->port;
2647 const struct sockaddr *addr = p;
2649 if (!is_valid_ether_addr(addr->sa_data))
2650 return -EADDRNOTAVAIL;
2652 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2653 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2654 dev->dev_addr, ETH_ALEN);
2655 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2656 dev->dev_addr, ETH_ALEN);
2658 /* virtual address for data */
2659 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2661 /* physical address: used for pause frames */
2662 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2667 static void sky2_set_multicast(struct net_device *dev)
2669 struct sky2_port *sky2 = netdev_priv(dev);
2670 struct sky2_hw *hw = sky2->hw;
2671 unsigned port = sky2->port;
2672 struct dev_mc_list *list = dev->mc_list;
2676 memset(filter, 0, sizeof(filter));
2678 reg = gma_read16(hw, port, GM_RX_CTRL);
2679 reg |= GM_RXCR_UCF_ENA;
2681 if (dev->flags & IFF_PROMISC) /* promiscuous */
2682 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2683 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2684 memset(filter, 0xff, sizeof(filter));
2685 else if (dev->mc_count == 0) /* no multicast */
2686 reg &= ~GM_RXCR_MCF_ENA;
2689 reg |= GM_RXCR_MCF_ENA;
2691 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2692 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2693 filter[bit / 8] |= 1 << (bit % 8);
2697 gma_write16(hw, port, GM_MC_ADDR_H1,
2698 (u16) filter[0] | ((u16) filter[1] << 8));
2699 gma_write16(hw, port, GM_MC_ADDR_H2,
2700 (u16) filter[2] | ((u16) filter[3] << 8));
2701 gma_write16(hw, port, GM_MC_ADDR_H3,
2702 (u16) filter[4] | ((u16) filter[5] << 8));
2703 gma_write16(hw, port, GM_MC_ADDR_H4,
2704 (u16) filter[6] | ((u16) filter[7] << 8));
2706 gma_write16(hw, port, GM_RX_CTRL, reg);
2709 /* Can have one global because blinking is controlled by
2710 * ethtool and that is always under RTNL mutex
2712 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2716 switch (hw->chip_id) {
2717 case CHIP_ID_YUKON_XL:
2718 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2719 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2720 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2721 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2722 PHY_M_LEDC_INIT_CTRL(7) |
2723 PHY_M_LEDC_STA1_CTRL(7) |
2724 PHY_M_LEDC_STA0_CTRL(7))
2727 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2731 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2732 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2733 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2734 PHY_M_LED_MO_10(MO_LED_ON) |
2735 PHY_M_LED_MO_100(MO_LED_ON) |
2736 PHY_M_LED_MO_1000(MO_LED_ON) |
2737 PHY_M_LED_MO_RX(MO_LED_ON)
2738 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2739 PHY_M_LED_MO_10(MO_LED_OFF) |
2740 PHY_M_LED_MO_100(MO_LED_OFF) |
2741 PHY_M_LED_MO_1000(MO_LED_OFF) |
2742 PHY_M_LED_MO_RX(MO_LED_OFF));
2747 /* blink LED's for finding board */
2748 static int sky2_phys_id(struct net_device *dev, u32 data)
2750 struct sky2_port *sky2 = netdev_priv(dev);
2751 struct sky2_hw *hw = sky2->hw;
2752 unsigned port = sky2->port;
2753 u16 ledctrl, ledover = 0;
2758 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2759 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2763 /* save initial values */
2764 spin_lock_bh(&sky2->phy_lock);
2765 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2766 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2767 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2768 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2769 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2771 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2772 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2776 while (!interrupted && ms > 0) {
2777 sky2_led(hw, port, onoff);
2780 spin_unlock_bh(&sky2->phy_lock);
2781 interrupted = msleep_interruptible(250);
2782 spin_lock_bh(&sky2->phy_lock);
2787 /* resume regularly scheduled programming */
2788 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2789 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2790 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2791 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2792 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2794 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2795 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2797 spin_unlock_bh(&sky2->phy_lock);
2802 static void sky2_get_pauseparam(struct net_device *dev,
2803 struct ethtool_pauseparam *ecmd)
2805 struct sky2_port *sky2 = netdev_priv(dev);
2807 ecmd->tx_pause = sky2->tx_pause;
2808 ecmd->rx_pause = sky2->rx_pause;
2809 ecmd->autoneg = sky2->autoneg;
2812 static int sky2_set_pauseparam(struct net_device *dev,
2813 struct ethtool_pauseparam *ecmd)
2815 struct sky2_port *sky2 = netdev_priv(dev);
2818 sky2->autoneg = ecmd->autoneg;
2819 sky2->tx_pause = ecmd->tx_pause != 0;
2820 sky2->rx_pause = ecmd->rx_pause != 0;
2822 sky2_phy_reinit(sky2);
2827 static int sky2_get_coalesce(struct net_device *dev,
2828 struct ethtool_coalesce *ecmd)
2830 struct sky2_port *sky2 = netdev_priv(dev);
2831 struct sky2_hw *hw = sky2->hw;
2833 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2834 ecmd->tx_coalesce_usecs = 0;
2836 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2837 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2839 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2841 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2842 ecmd->rx_coalesce_usecs = 0;
2844 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2845 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2847 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2849 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2850 ecmd->rx_coalesce_usecs_irq = 0;
2852 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2853 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2856 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2861 /* Note: this affect both ports */
2862 static int sky2_set_coalesce(struct net_device *dev,
2863 struct ethtool_coalesce *ecmd)
2865 struct sky2_port *sky2 = netdev_priv(dev);
2866 struct sky2_hw *hw = sky2->hw;
2867 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2869 if (ecmd->tx_coalesce_usecs > tmax ||
2870 ecmd->rx_coalesce_usecs > tmax ||
2871 ecmd->rx_coalesce_usecs_irq > tmax)
2874 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2876 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2878 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2881 if (ecmd->tx_coalesce_usecs == 0)
2882 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2884 sky2_write32(hw, STAT_TX_TIMER_INI,
2885 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2886 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2888 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2890 if (ecmd->rx_coalesce_usecs == 0)
2891 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2893 sky2_write32(hw, STAT_LEV_TIMER_INI,
2894 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2895 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2897 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2899 if (ecmd->rx_coalesce_usecs_irq == 0)
2900 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2902 sky2_write32(hw, STAT_ISR_TIMER_INI,
2903 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2904 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2906 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2910 static void sky2_get_ringparam(struct net_device *dev,
2911 struct ethtool_ringparam *ering)
2913 struct sky2_port *sky2 = netdev_priv(dev);
2915 ering->rx_max_pending = RX_MAX_PENDING;
2916 ering->rx_mini_max_pending = 0;
2917 ering->rx_jumbo_max_pending = 0;
2918 ering->tx_max_pending = TX_RING_SIZE - 1;
2920 ering->rx_pending = sky2->rx_pending;
2921 ering->rx_mini_pending = 0;
2922 ering->rx_jumbo_pending = 0;
2923 ering->tx_pending = sky2->tx_pending;
2926 static int sky2_set_ringparam(struct net_device *dev,
2927 struct ethtool_ringparam *ering)
2929 struct sky2_port *sky2 = netdev_priv(dev);
2932 if (ering->rx_pending > RX_MAX_PENDING ||
2933 ering->rx_pending < 8 ||
2934 ering->tx_pending < MAX_SKB_TX_LE ||
2935 ering->tx_pending > TX_RING_SIZE - 1)
2938 if (netif_running(dev))
2941 sky2->rx_pending = ering->rx_pending;
2942 sky2->tx_pending = ering->tx_pending;
2944 if (netif_running(dev)) {
2949 sky2_set_multicast(dev);
2955 static int sky2_get_regs_len(struct net_device *dev)
2961 * Returns copy of control register region
2962 * Note: access to the RAM address register set will cause timeouts.
2964 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2967 const struct sky2_port *sky2 = netdev_priv(dev);
2968 const void __iomem *io = sky2->hw->regs;
2970 BUG_ON(regs->len < B3_RI_WTO_R1);
2972 memset(p, 0, regs->len);
2974 memcpy_fromio(p, io, B3_RAM_ADDR);
2976 memcpy_fromio(p + B3_RI_WTO_R1,
2978 regs->len - B3_RI_WTO_R1);
2981 static struct ethtool_ops sky2_ethtool_ops = {
2982 .get_settings = sky2_get_settings,
2983 .set_settings = sky2_set_settings,
2984 .get_drvinfo = sky2_get_drvinfo,
2985 .get_msglevel = sky2_get_msglevel,
2986 .set_msglevel = sky2_set_msglevel,
2987 .nway_reset = sky2_nway_reset,
2988 .get_regs_len = sky2_get_regs_len,
2989 .get_regs = sky2_get_regs,
2990 .get_link = ethtool_op_get_link,
2991 .get_sg = ethtool_op_get_sg,
2992 .set_sg = ethtool_op_set_sg,
2993 .get_tx_csum = ethtool_op_get_tx_csum,
2994 .set_tx_csum = ethtool_op_set_tx_csum,
2995 .get_tso = ethtool_op_get_tso,
2996 .set_tso = ethtool_op_set_tso,
2997 .get_rx_csum = sky2_get_rx_csum,
2998 .set_rx_csum = sky2_set_rx_csum,
2999 .get_strings = sky2_get_strings,
3000 .get_coalesce = sky2_get_coalesce,
3001 .set_coalesce = sky2_set_coalesce,
3002 .get_ringparam = sky2_get_ringparam,
3003 .set_ringparam = sky2_set_ringparam,
3004 .get_pauseparam = sky2_get_pauseparam,
3005 .set_pauseparam = sky2_set_pauseparam,
3006 .phys_id = sky2_phys_id,
3007 .get_stats_count = sky2_get_stats_count,
3008 .get_ethtool_stats = sky2_get_ethtool_stats,
3009 .get_perm_addr = ethtool_op_get_perm_addr,
3012 /* Initialize network device */
3013 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3014 unsigned port, int highmem)
3016 struct sky2_port *sky2;
3017 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3020 printk(KERN_ERR "sky2 etherdev alloc failed");
3024 SET_MODULE_OWNER(dev);
3025 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3026 dev->irq = hw->pdev->irq;
3027 dev->open = sky2_up;
3028 dev->stop = sky2_down;
3029 dev->do_ioctl = sky2_ioctl;
3030 dev->hard_start_xmit = sky2_xmit_frame;
3031 dev->get_stats = sky2_get_stats;
3032 dev->set_multicast_list = sky2_set_multicast;
3033 dev->set_mac_address = sky2_set_mac_address;
3034 dev->change_mtu = sky2_change_mtu;
3035 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3036 dev->tx_timeout = sky2_tx_timeout;
3037 dev->watchdog_timeo = TX_WATCHDOG;
3039 dev->poll = sky2_poll;
3040 dev->weight = NAPI_WEIGHT;
3041 #ifdef CONFIG_NET_POLL_CONTROLLER
3042 dev->poll_controller = sky2_netpoll;
3045 sky2 = netdev_priv(dev);
3048 sky2->msg_enable = netif_msg_init(debug, default_msg);
3050 spin_lock_init(&sky2->tx_lock);
3051 /* Auto speed and flow control */
3052 sky2->autoneg = AUTONEG_ENABLE;
3057 sky2->advertising = sky2_supported_modes(hw);
3059 /* Receive checksum disabled for Yukon XL
3060 * because of observed problems with incorrect
3061 * values when multiple packets are received in one interrupt
3063 sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);
3065 spin_lock_init(&sky2->phy_lock);
3066 sky2->tx_pending = TX_DEF_PENDING;
3067 sky2->rx_pending = RX_DEF_PENDING;
3068 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3070 hw->dev[port] = dev;
3074 dev->features |= NETIF_F_LLTX;
3075 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3076 dev->features |= NETIF_F_TSO;
3078 dev->features |= NETIF_F_HIGHDMA;
3079 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3081 #ifdef SKY2_VLAN_TAG_USED
3082 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3083 dev->vlan_rx_register = sky2_vlan_rx_register;
3084 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3087 /* read the mac address */
3088 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3089 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3091 /* device is off until link detection */
3092 netif_carrier_off(dev);
3093 netif_stop_queue(dev);
3098 static void __devinit sky2_show_addr(struct net_device *dev)
3100 const struct sky2_port *sky2 = netdev_priv(dev);
3102 if (netif_msg_probe(sky2))
3103 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3105 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3106 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3109 /* Handle software interrupt used during MSI test */
3110 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3111 struct pt_regs *regs)
3113 struct sky2_hw *hw = dev_id;
3114 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3119 if (status & Y2_IS_IRQ_SW) {
3120 hw->msi_detected = 1;
3121 wake_up(&hw->msi_wait);
3122 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3124 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3129 /* Test interrupt path by forcing a a software IRQ */
3130 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3132 struct pci_dev *pdev = hw->pdev;
3135 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3137 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3139 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3140 pci_name(pdev), pdev->irq);
3144 init_waitqueue_head (&hw->msi_wait);
3146 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3149 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3151 if (!hw->msi_detected) {
3152 /* MSI test failed, go back to INTx mode */
3153 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3154 "switching to INTx mode. Please report this failure to "
3155 "the PCI maintainer and include system chipset information.\n",
3159 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3162 sky2_write32(hw, B0_IMSK, 0);
3164 free_irq(pdev->irq, hw);
3169 static int __devinit sky2_probe(struct pci_dev *pdev,
3170 const struct pci_device_id *ent)
3172 struct net_device *dev, *dev1 = NULL;
3174 int err, pm_cap, using_dac = 0;
3176 err = pci_enable_device(pdev);
3178 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3183 err = pci_request_regions(pdev, DRV_NAME);
3185 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3190 pci_set_master(pdev);
3192 /* Find power-management capability. */
3193 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3195 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3198 goto err_out_free_regions;
3201 if (sizeof(dma_addr_t) > sizeof(u32) &&
3202 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3204 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3206 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3207 "for consistent allocations\n", pci_name(pdev));
3208 goto err_out_free_regions;
3212 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3214 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3216 goto err_out_free_regions;
3221 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3223 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3225 goto err_out_free_regions;
3230 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3232 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3234 goto err_out_free_hw;
3236 hw->pm_cap = pm_cap;
3239 /* byte swap descriptors in hardware */
3243 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3244 reg |= PCI_REV_DESC;
3245 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3249 /* ring for status responses */
3250 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3253 goto err_out_iounmap;
3255 err = sky2_reset(hw);
3257 goto err_out_iounmap;
3259 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3260 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3261 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3262 hw->chip_id, hw->chip_rev);
3264 dev = sky2_init_netdev(hw, 0, using_dac);
3266 goto err_out_free_pci;
3268 err = register_netdev(dev);
3270 printk(KERN_ERR PFX "%s: cannot register net device\n",
3272 goto err_out_free_netdev;
3275 sky2_show_addr(dev);
3277 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3278 if (register_netdev(dev1) == 0)
3279 sky2_show_addr(dev1);
3281 /* Failure to register second port need not be fatal */
3282 printk(KERN_WARNING PFX
3283 "register of second port failed\n");
3289 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3290 err = sky2_test_msi(hw);
3291 if (err == -EOPNOTSUPP)
3292 pci_disable_msi(pdev);
3294 goto err_out_unregister;
3297 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3299 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3300 pci_name(pdev), pdev->irq);
3301 goto err_out_unregister;
3304 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3306 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) dev);
3308 pci_set_drvdata(pdev, hw);
3313 pci_disable_msi(pdev);
3315 unregister_netdev(dev1);
3318 unregister_netdev(dev);
3319 err_out_free_netdev:
3322 sky2_write8(hw, B0_CTST, CS_RST_SET);
3323 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3328 err_out_free_regions:
3329 pci_release_regions(pdev);
3330 pci_disable_device(pdev);
3335 static void __devexit sky2_remove(struct pci_dev *pdev)
3337 struct sky2_hw *hw = pci_get_drvdata(pdev);
3338 struct net_device *dev0, *dev1;
3343 del_timer_sync(&hw->idle_timer);
3345 sky2_write32(hw, B0_IMSK, 0);
3349 unregister_netdev(dev1);
3350 unregister_netdev(dev0);
3352 sky2_set_power_state(hw, PCI_D3hot);
3353 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3354 sky2_write8(hw, B0_CTST, CS_RST_SET);
3355 sky2_read8(hw, B0_CTST);
3357 free_irq(pdev->irq, hw);
3358 pci_disable_msi(pdev);
3359 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3360 pci_release_regions(pdev);
3361 pci_disable_device(pdev);
3369 pci_set_drvdata(pdev, NULL);
3373 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3375 struct sky2_hw *hw = pci_get_drvdata(pdev);
3378 for (i = 0; i < 2; i++) {
3379 struct net_device *dev = hw->dev[i];
3382 if (!netif_running(dev))
3386 netif_device_detach(dev);
3390 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3393 static int sky2_resume(struct pci_dev *pdev)
3395 struct sky2_hw *hw = pci_get_drvdata(pdev);
3398 pci_restore_state(pdev);
3399 pci_enable_wake(pdev, PCI_D0, 0);
3400 err = sky2_set_power_state(hw, PCI_D0);
3404 err = sky2_reset(hw);
3408 for (i = 0; i < 2; i++) {
3409 struct net_device *dev = hw->dev[i];
3410 if (dev && netif_running(dev)) {
3411 netif_device_attach(dev);
3414 printk(KERN_ERR PFX "%s: could not up: %d\n",
3426 static struct pci_driver sky2_driver = {
3428 .id_table = sky2_id_table,
3429 .probe = sky2_probe,
3430 .remove = __devexit_p(sky2_remove),
3432 .suspend = sky2_suspend,
3433 .resume = sky2_resume,
3437 static int __init sky2_init_module(void)
3439 return pci_register_driver(&sky2_driver);
3442 static void __exit sky2_cleanup_module(void)
3444 pci_unregister_driver(&sky2_driver);
3447 module_init(sky2_init_module);
3448 module_exit(sky2_cleanup_module);
3450 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3451 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3452 MODULE_LICENSE("GPL");
3453 MODULE_VERSION(DRV_VERSION);