2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/config.h>
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/version.h>
30 #include <linux/module.h>
31 #include <linux/netdevice.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
37 #include <linux/tcp.h>
39 #include <linux/delay.h>
40 #include <linux/workqueue.h>
41 #include <linux/if_vlan.h>
42 #include <linux/prefetch.h>
43 #include <linux/mii.h>
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.3"
55 #define PFX DRV_NAME " "
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3. A transmit can require several elements;
61 * a receive requires one (or two if using 64 bit dma).
64 #define RX_LE_SIZE 512
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
68 #define RX_SKB_ALIGN 8
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly = 256;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101 static int idle_timeout = 100;
102 module_param(idle_timeout, int, 0);
103 MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 MODULE_DEVICE_TABLE(pci, sky2_id_table);
128 /* Avoid conditionals by using array */
129 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
133 /* This driver supports yukon2 chipset only */
134 static const char *yukon2_name[] = {
136 "EC Ultra", /* 0xb4 */
137 "UNKNOWN", /* 0xb5 */
142 /* Access to external PHY */
143 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
151 for (i = 0; i < PHY_RETRIES; i++) {
152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
157 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
161 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
165 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
166 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
168 for (i = 0; i < PHY_RETRIES; i++) {
169 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
170 *val = gma_read16(hw, port, GM_SMI_DATA);
180 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
184 if (__gm_phy_read(hw, port, reg, &v) != 0)
185 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
189 static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
196 pr_debug("sky2_set_power_state %d\n", state);
197 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
199 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
200 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
201 (power_control & PCI_PM_CAP_PME_D3cold);
203 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
205 power_control |= PCI_PM_CTRL_PME_STATUS;
206 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
210 /* switch power to VCC (WA for VAUX problem) */
211 sky2_write8(hw, B0_POWER_CTRL,
212 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
214 /* disable Core Clock Division, */
215 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
217 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
218 /* enable bits are inverted */
219 sky2_write8(hw, B2_Y2_CLK_GATE,
220 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
221 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
222 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
224 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
226 /* Turn off phy power saving */
227 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
228 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
230 /* looks like this XL is back asswards .. */
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
232 reg1 |= PCI_Y2_PHY1_COMA;
234 reg1 |= PCI_Y2_PHY2_COMA;
237 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
238 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
239 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
240 reg1 &= P_ASPM_CONTROL_MSK;
241 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
242 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
245 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
251 /* Turn on phy power saving */
252 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
253 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
254 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
256 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
257 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
259 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
260 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
262 /* enable bits are inverted */
263 sky2_write8(hw, B2_Y2_CLK_GATE,
264 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
265 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
266 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
268 /* switch power to VAUX */
269 if (vaux && state != PCI_D3cold)
270 sky2_write8(hw, B0_POWER_CTRL,
271 (PC_VAUX_ENA | PC_VCC_ENA |
272 PC_VAUX_ON | PC_VCC_OFF));
275 printk(KERN_ERR PFX "Unknown power state %d\n", state);
279 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
280 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
284 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
288 /* disable all GMAC IRQ's */
289 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
290 /* disable PHY IRQs */
291 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
293 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
294 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
295 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
296 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
298 reg = gma_read16(hw, port, GM_RX_CTRL);
299 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
300 gma_write16(hw, port, GM_RX_CTRL, reg);
303 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
305 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
306 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
308 if (sky2->autoneg == AUTONEG_ENABLE &&
309 (hw->chip_id != CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
310 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
312 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
314 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
316 if (hw->chip_id == CHIP_ID_YUKON_EC)
317 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
319 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
321 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
324 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
326 if (hw->chip_id == CHIP_ID_YUKON_FE) {
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
330 /* disable energy detect */
331 ctrl &= ~PHY_M_PC_EN_DET_MSK;
333 /* enable automatic crossover */
334 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
336 if (sky2->autoneg == AUTONEG_ENABLE &&
337 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
338 ctrl &= ~PHY_M_PC_DSC_MSK;
339 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
342 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
344 /* workaround for deviation #4.88 (CRC errors) */
345 /* disable Automatic Crossover */
347 ctrl &= ~PHY_M_PC_MDIX_MSK;
348 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
350 if (hw->chip_id == CHIP_ID_YUKON_XL) {
351 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl &= ~PHY_M_MAC_MD_MSK;
355 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
356 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
363 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
364 if (sky2->autoneg == AUTONEG_DISABLE)
369 ctrl |= PHY_CT_RESET;
370 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
376 if (sky2->autoneg == AUTONEG_ENABLE) {
378 if (sky2->advertising & ADVERTISED_1000baseT_Full)
379 ct1000 |= PHY_M_1000C_AFD;
380 if (sky2->advertising & ADVERTISED_1000baseT_Half)
381 ct1000 |= PHY_M_1000C_AHD;
382 if (sky2->advertising & ADVERTISED_100baseT_Full)
383 adv |= PHY_M_AN_100_FD;
384 if (sky2->advertising & ADVERTISED_100baseT_Half)
385 adv |= PHY_M_AN_100_HD;
386 if (sky2->advertising & ADVERTISED_10baseT_Full)
387 adv |= PHY_M_AN_10_FD;
388 if (sky2->advertising & ADVERTISED_10baseT_Half)
389 adv |= PHY_M_AN_10_HD;
390 } else /* special defines for FIBER (88E1011S only) */
391 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
393 /* Set Flow-control capabilities */
394 if (sky2->tx_pause && sky2->rx_pause)
395 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
396 else if (sky2->rx_pause && !sky2->tx_pause)
397 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
398 else if (!sky2->rx_pause && sky2->tx_pause)
399 adv |= PHY_AN_PAUSE_ASYM; /* local */
401 /* Restart Auto-negotiation */
402 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
404 /* forced speed/duplex settings */
405 ct1000 = PHY_M_1000C_MSE;
407 if (sky2->duplex == DUPLEX_FULL)
408 ctrl |= PHY_CT_DUP_MD;
410 switch (sky2->speed) {
412 ctrl |= PHY_CT_SP1000;
415 ctrl |= PHY_CT_SP100;
419 ctrl |= PHY_CT_RESET;
422 if (hw->chip_id != CHIP_ID_YUKON_FE)
423 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
425 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
426 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
428 /* Setup Phy LED's */
429 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
432 switch (hw->chip_id) {
433 case CHIP_ID_YUKON_FE:
434 /* on 88E3082 these bits are at 11..9 (shifted left) */
435 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
437 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
439 /* delete ACT LED control bits */
440 ctrl &= ~PHY_M_FELP_LED1_MSK;
441 /* change ACT LED control to blink mode */
442 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
443 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
446 case CHIP_ID_YUKON_XL:
447 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
449 /* select page 3 to access LED control register */
450 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
452 /* set LED Function Control register */
453 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
454 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
455 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
456 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
457 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
459 /* set Polarity Control register */
460 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
461 (PHY_M_POLC_LS1_P_MIX(4) |
462 PHY_M_POLC_IS0_P_MIX(4) |
463 PHY_M_POLC_LOS_CTRL(2) |
464 PHY_M_POLC_INIT_CTRL(2) |
465 PHY_M_POLC_STA1_CTRL(2) |
466 PHY_M_POLC_STA0_CTRL(2)));
468 /* restore page register */
469 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
471 case CHIP_ID_YUKON_EC_U:
472 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
474 /* select page 3 to access LED control register */
475 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
477 /* set LED Function Control register */
478 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
479 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
480 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
481 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
482 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
484 /* set Blink Rate in LED Timer Control Register */
485 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
486 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
487 /* restore page register */
488 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
492 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
493 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
494 /* turn off the Rx LED (LED_RX) */
495 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
498 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
499 /* apply fixes in PHY AFE */
500 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
501 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
503 /* increase differential signal amplitude in 10BASE-T */
504 gm_phy_write(hw, port, 0x18, 0xaa99);
505 gm_phy_write(hw, port, 0x17, 0x2011);
507 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
508 gm_phy_write(hw, port, 0x18, 0xa204);
509 gm_phy_write(hw, port, 0x17, 0x2002);
511 /* set page register to 0 */
512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
514 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
516 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
517 /* turn on 100 Mbps LED (LED_LINK100) */
518 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
522 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
525 /* Enable phy interrupt on auto-negotiation complete (or link up) */
526 if (sky2->autoneg == AUTONEG_ENABLE)
527 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
529 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
532 /* Force a renegotiation */
533 static void sky2_phy_reinit(struct sky2_port *sky2)
535 spin_lock_bh(&sky2->phy_lock);
536 sky2_phy_init(sky2->hw, sky2->port);
537 spin_unlock_bh(&sky2->phy_lock);
540 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
542 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
545 const u8 *addr = hw->dev[port]->dev_addr;
547 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
548 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
550 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
552 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
553 /* WA DEV_472 -- looks like crossed wires on port 2 */
554 /* clear GMAC 1 Control reset */
555 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
557 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
558 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
559 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
560 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
561 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
564 if (sky2->autoneg == AUTONEG_DISABLE) {
565 reg = gma_read16(hw, port, GM_GP_CTRL);
566 reg |= GM_GPCR_AU_ALL_DIS;
567 gma_write16(hw, port, GM_GP_CTRL, reg);
568 gma_read16(hw, port, GM_GP_CTRL);
570 switch (sky2->speed) {
572 reg &= ~GM_GPCR_SPEED_100;
573 reg |= GM_GPCR_SPEED_1000;
576 reg &= ~GM_GPCR_SPEED_1000;
577 reg |= GM_GPCR_SPEED_100;
580 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
584 if (sky2->duplex == DUPLEX_FULL)
585 reg |= GM_GPCR_DUP_FULL;
587 /* turn off pause in 10/100mbps half duplex */
588 else if (sky2->speed != SPEED_1000 &&
589 hw->chip_id != CHIP_ID_YUKON_EC_U)
590 sky2->tx_pause = sky2->rx_pause = 0;
592 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
594 if (!sky2->tx_pause && !sky2->rx_pause) {
595 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
597 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
598 } else if (sky2->tx_pause && !sky2->rx_pause) {
599 /* disable Rx flow-control */
600 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
603 gma_write16(hw, port, GM_GP_CTRL, reg);
605 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
607 spin_lock_bh(&sky2->phy_lock);
608 sky2_phy_init(hw, port);
609 spin_unlock_bh(&sky2->phy_lock);
612 reg = gma_read16(hw, port, GM_PHY_ADDR);
613 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
615 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
616 gma_read16(hw, port, i);
617 gma_write16(hw, port, GM_PHY_ADDR, reg);
619 /* transmit control */
620 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
622 /* receive control reg: unicast + multicast + no FCS */
623 gma_write16(hw, port, GM_RX_CTRL,
624 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
626 /* transmit flow control */
627 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
629 /* transmit parameter */
630 gma_write16(hw, port, GM_TX_PARAM,
631 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
632 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
633 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
634 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
636 /* serial mode register */
637 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
638 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
640 if (hw->dev[port]->mtu > ETH_DATA_LEN)
641 reg |= GM_SMOD_JUMBO_ENA;
643 gma_write16(hw, port, GM_SERIAL_MODE, reg);
645 /* virtual address for data */
646 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
648 /* physical address: used for pause frames */
649 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
651 /* ignore counter overflows */
652 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
653 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
654 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
656 /* Configure Rx MAC FIFO */
657 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
658 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
659 GMF_OPER_ON | GMF_RX_F_FL_ON);
661 /* Flush Rx MAC FIFO on any flow control or error */
662 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
664 /* Set threshold to 0xa (64 bytes)
665 * ASF disabled so no need to do WA dev #4.30
667 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
669 /* Configure Tx MAC FIFO */
670 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
671 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
673 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
674 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
675 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
676 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
677 /* set Tx GMAC FIFO Almost Empty Threshold */
678 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
679 /* Disable Store & Forward mode for TX */
680 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
686 /* Assign Ram Buffer allocation.
687 * start and end are in units of 4k bytes
688 * ram registers are in units of 64bit words
690 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
694 start = startk * 4096/8;
695 end = (endk * 4096/8) - 1;
697 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
698 sky2_write32(hw, RB_ADDR(q, RB_START), start);
699 sky2_write32(hw, RB_ADDR(q, RB_END), end);
700 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
701 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
703 if (q == Q_R1 || q == Q_R2) {
704 u32 space = (endk - startk) * 4096/8;
705 u32 tp = space - space/4;
707 /* On receive queue's set the thresholds
708 * give receiver priority when > 3/4 full
709 * send pause when down to 2K
711 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
712 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
715 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
716 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
718 /* Enable store & forward on Tx queue's because
719 * Tx FIFO is only 1K on Yukon
721 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
724 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
725 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
728 /* Setup Bus Memory Interface */
729 static void sky2_qset(struct sky2_hw *hw, u16 q)
731 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
732 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
733 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
734 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
737 /* Setup prefetch unit registers. This is the interface between
738 * hardware and driver list elements
740 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
743 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
744 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
745 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
746 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
747 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
748 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
750 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
753 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
755 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
757 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
761 /* Update chip's next pointer */
762 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
765 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
770 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
772 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
773 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
777 /* Return high part of DMA address (could be 32 or 64 bit) */
778 static inline u32 high32(dma_addr_t a)
780 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
783 /* Build description to hardware about buffer */
784 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
786 struct sky2_rx_le *le;
787 u32 hi = high32(map);
788 u16 len = sky2->rx_bufsize;
790 if (sky2->rx_addr64 != hi) {
791 le = sky2_next_rx(sky2);
792 le->addr = cpu_to_le32(hi);
794 le->opcode = OP_ADDR64 | HW_OWNER;
795 sky2->rx_addr64 = high32(map + len);
798 le = sky2_next_rx(sky2);
799 le->addr = cpu_to_le32((u32) map);
800 le->length = cpu_to_le16(len);
802 le->opcode = OP_PACKET | HW_OWNER;
806 /* Tell chip where to start receive checksum.
807 * Actually has two checksums, but set both same to avoid possible byte
810 static void rx_set_checksum(struct sky2_port *sky2)
812 struct sky2_rx_le *le;
814 le = sky2_next_rx(sky2);
815 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
817 le->opcode = OP_TCPSTART | HW_OWNER;
819 sky2_write32(sky2->hw,
820 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
821 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
826 * The RX Stop command will not work for Yukon-2 if the BMU does not
827 * reach the end of packet and since we can't make sure that we have
828 * incoming data, we must reset the BMU while it is not doing a DMA
829 * transfer. Since it is possible that the RX path is still active,
830 * the RX RAM buffer will be stopped first, so any possible incoming
831 * data will not trigger a DMA. After the RAM buffer is stopped, the
832 * BMU is polled until any DMA in progress is ended and only then it
835 static void sky2_rx_stop(struct sky2_port *sky2)
837 struct sky2_hw *hw = sky2->hw;
838 unsigned rxq = rxqaddr[sky2->port];
841 /* disable the RAM Buffer receive queue */
842 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
844 for (i = 0; i < 0xffff; i++)
845 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
846 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
849 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
852 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
854 /* reset the Rx prefetch unit */
855 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
858 /* Clean out receive buffer area, assumes receiver hardware stopped */
859 static void sky2_rx_clean(struct sky2_port *sky2)
863 memset(sky2->rx_le, 0, RX_LE_BYTES);
864 for (i = 0; i < sky2->rx_pending; i++) {
865 struct ring_info *re = sky2->rx_ring + i;
868 pci_unmap_single(sky2->hw->pdev,
869 re->mapaddr, sky2->rx_bufsize,
877 /* Basic MII support */
878 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
880 struct mii_ioctl_data *data = if_mii(ifr);
881 struct sky2_port *sky2 = netdev_priv(dev);
882 struct sky2_hw *hw = sky2->hw;
883 int err = -EOPNOTSUPP;
885 if (!netif_running(dev))
886 return -ENODEV; /* Phy still in reset */
890 data->phy_id = PHY_ADDR_MARV;
896 spin_lock_bh(&sky2->phy_lock);
897 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
898 spin_unlock_bh(&sky2->phy_lock);
905 if (!capable(CAP_NET_ADMIN))
908 spin_lock_bh(&sky2->phy_lock);
909 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
911 spin_unlock_bh(&sky2->phy_lock);
917 #ifdef SKY2_VLAN_TAG_USED
918 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
920 struct sky2_port *sky2 = netdev_priv(dev);
921 struct sky2_hw *hw = sky2->hw;
922 u16 port = sky2->port;
924 spin_lock_bh(&sky2->tx_lock);
926 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
927 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
930 spin_unlock_bh(&sky2->tx_lock);
933 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
935 struct sky2_port *sky2 = netdev_priv(dev);
936 struct sky2_hw *hw = sky2->hw;
937 u16 port = sky2->port;
939 spin_lock_bh(&sky2->tx_lock);
941 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
942 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
944 sky2->vlgrp->vlan_devices[vid] = NULL;
946 spin_unlock_bh(&sky2->tx_lock);
951 * It appears the hardware has a bug in the FIFO logic that
952 * cause it to hang if the FIFO gets overrun and the receive buffer
953 * is not aligned. ALso alloc_skb() won't align properly if slab
954 * debugging is enabled.
956 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
960 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
962 unsigned long p = (unsigned long) skb->data;
963 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
970 * Allocate and setup receiver buffer pool.
971 * In case of 64 bit dma, there are 2X as many list elements
972 * available as ring entries
973 * and need to reserve one list element so we don't wrap around.
975 static int sky2_rx_start(struct sky2_port *sky2)
977 struct sky2_hw *hw = sky2->hw;
978 unsigned rxq = rxqaddr[sky2->port];
981 sky2->rx_put = sky2->rx_next = 0;
984 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
985 /* MAC Rx RAM Read is controlled by hardware */
986 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
989 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
991 rx_set_checksum(sky2);
992 for (i = 0; i < sky2->rx_pending; i++) {
993 struct ring_info *re = sky2->rx_ring + i;
995 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
999 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
1000 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1001 sky2_rx_add(sky2, re->mapaddr);
1004 /* Truncate oversize frames */
1005 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
1006 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1008 /* Tell chip about available buffers */
1009 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1012 sky2_rx_clean(sky2);
1016 /* Bring up network interface. */
1017 static int sky2_up(struct net_device *dev)
1019 struct sky2_port *sky2 = netdev_priv(dev);
1020 struct sky2_hw *hw = sky2->hw;
1021 unsigned port = sky2->port;
1022 u32 ramsize, rxspace, imask;
1023 int cap, err = -ENOMEM;
1024 struct net_device *otherdev = hw->dev[sky2->port^1];
1027 * On dual port PCI-X card, there is an problem where status
1028 * can be received out of order due to split transactions
1030 if (otherdev && netif_running(otherdev) &&
1031 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1032 struct sky2_port *osky2 = netdev_priv(otherdev);
1035 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1036 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1037 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1043 if (netif_msg_ifup(sky2))
1044 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1046 /* must be power of 2 */
1047 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1049 sizeof(struct sky2_tx_le),
1054 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1058 sky2->tx_prod = sky2->tx_cons = 0;
1060 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1064 memset(sky2->rx_le, 0, RX_LE_BYTES);
1066 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1071 sky2_mac_init(hw, port);
1073 /* Determine available ram buffer space (in 4K blocks).
1074 * Note: not sure about the FE setting below yet
1076 if (hw->chip_id == CHIP_ID_YUKON_FE)
1079 ramsize = sky2_read8(hw, B2_E_0);
1081 /* Give transmitter one third (rounded up) */
1082 rxspace = ramsize - (ramsize + 2) / 3;
1084 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1085 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1087 /* Make sure SyncQ is disabled */
1088 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1091 sky2_qset(hw, txqaddr[port]);
1093 /* Set almost empty threshold */
1094 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1095 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1097 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1100 err = sky2_rx_start(sky2);
1104 /* Enable interrupts from phy/mac for port */
1105 imask = sky2_read32(hw, B0_IMSK);
1106 imask |= portirq_msk[port];
1107 sky2_write32(hw, B0_IMSK, imask);
1113 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1114 sky2->rx_le, sky2->rx_le_map);
1118 pci_free_consistent(hw->pdev,
1119 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1120 sky2->tx_le, sky2->tx_le_map);
1123 kfree(sky2->tx_ring);
1124 kfree(sky2->rx_ring);
1126 sky2->tx_ring = NULL;
1127 sky2->rx_ring = NULL;
1131 /* Modular subtraction in ring */
1132 static inline int tx_dist(unsigned tail, unsigned head)
1134 return (head - tail) & (TX_RING_SIZE - 1);
1137 /* Number of list elements available for next tx */
1138 static inline int tx_avail(const struct sky2_port *sky2)
1140 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1143 /* Estimate of number of transmit list elements required */
1144 static unsigned tx_le_req(const struct sk_buff *skb)
1148 count = sizeof(dma_addr_t) / sizeof(u32);
1149 count += skb_shinfo(skb)->nr_frags * count;
1151 if (skb_shinfo(skb)->tso_size)
1154 if (skb->ip_summed == CHECKSUM_HW)
1161 * Put one packet in ring for transmit.
1162 * A single packet can generate multiple list elements, and
1163 * the number of ring elements will probably be less than the number
1164 * of list elements used.
1166 * No BH disabling for tx_lock here (like tg3)
1168 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1170 struct sky2_port *sky2 = netdev_priv(dev);
1171 struct sky2_hw *hw = sky2->hw;
1172 struct sky2_tx_le *le = NULL;
1173 struct tx_ring_info *re;
1181 /* No BH disabling for tx_lock here. We are running in BH disabled
1182 * context and TX reclaim runs via poll inside of a software
1183 * interrupt, and no related locks in IRQ processing.
1185 if (!spin_trylock(&sky2->tx_lock))
1186 return NETDEV_TX_LOCKED;
1188 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1189 /* There is a known but harmless race with lockless tx
1190 * and netif_stop_queue.
1192 if (!netif_queue_stopped(dev)) {
1193 netif_stop_queue(dev);
1194 if (net_ratelimit())
1195 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1198 spin_unlock(&sky2->tx_lock);
1200 return NETDEV_TX_BUSY;
1203 if (unlikely(netif_msg_tx_queued(sky2)))
1204 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1205 dev->name, sky2->tx_prod, skb->len);
1207 len = skb_headlen(skb);
1208 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1209 addr64 = high32(mapping);
1211 re = sky2->tx_ring + sky2->tx_prod;
1213 /* Send high bits if changed or crosses boundary */
1214 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1215 le = get_tx_le(sky2);
1216 le->tx.addr = cpu_to_le32(addr64);
1218 le->opcode = OP_ADDR64 | HW_OWNER;
1219 sky2->tx_addr64 = high32(mapping + len);
1222 /* Check for TCP Segmentation Offload */
1223 mss = skb_shinfo(skb)->tso_size;
1225 /* just drop the packet if non-linear expansion fails */
1226 if (skb_header_cloned(skb) &&
1227 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1232 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1233 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1237 if (mss != sky2->tx_last_mss) {
1238 le = get_tx_le(sky2);
1239 le->tx.tso.size = cpu_to_le16(mss);
1240 le->tx.tso.rsvd = 0;
1241 le->opcode = OP_LRGLEN | HW_OWNER;
1243 sky2->tx_last_mss = mss;
1247 #ifdef SKY2_VLAN_TAG_USED
1248 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1249 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1251 le = get_tx_le(sky2);
1253 le->opcode = OP_VLAN|HW_OWNER;
1256 le->opcode |= OP_VLAN;
1257 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1262 /* Handle TCP checksum offload */
1263 if (skb->ip_summed == CHECKSUM_HW) {
1264 u16 hdr = skb->h.raw - skb->data;
1265 u16 offset = hdr + skb->csum;
1267 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1268 if (skb->nh.iph->protocol == IPPROTO_UDP)
1271 le = get_tx_le(sky2);
1272 le->tx.csum.start = cpu_to_le16(hdr);
1273 le->tx.csum.offset = cpu_to_le16(offset);
1274 le->length = 0; /* initial checksum value */
1275 le->ctrl = 1; /* one packet */
1276 le->opcode = OP_TCPLISW | HW_OWNER;
1279 le = get_tx_le(sky2);
1280 le->tx.addr = cpu_to_le32((u32) mapping);
1281 le->length = cpu_to_le16(len);
1283 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1285 /* Record the transmit mapping info */
1287 pci_unmap_addr_set(re, mapaddr, mapping);
1289 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1290 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1291 struct tx_ring_info *fre;
1293 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1294 frag->size, PCI_DMA_TODEVICE);
1295 addr64 = high32(mapping);
1296 if (addr64 != sky2->tx_addr64) {
1297 le = get_tx_le(sky2);
1298 le->tx.addr = cpu_to_le32(addr64);
1300 le->opcode = OP_ADDR64 | HW_OWNER;
1301 sky2->tx_addr64 = addr64;
1304 le = get_tx_le(sky2);
1305 le->tx.addr = cpu_to_le32((u32) mapping);
1306 le->length = cpu_to_le16(frag->size);
1308 le->opcode = OP_BUFFER | HW_OWNER;
1311 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1312 pci_unmap_addr_set(fre, mapaddr, mapping);
1315 re->idx = sky2->tx_prod;
1318 avail = tx_avail(sky2);
1319 if (mss != 0 || avail < TX_MIN_PENDING) {
1320 le->ctrl |= FRC_STAT;
1321 if (avail <= MAX_SKB_TX_LE)
1322 netif_stop_queue(dev);
1325 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1328 spin_unlock(&sky2->tx_lock);
1330 dev->trans_start = jiffies;
1331 return NETDEV_TX_OK;
1335 * Free ring elements from starting at tx_cons until "done"
1337 * NB: the hardware will tell us about partial completion of multi-part
1338 * buffers; these are deferred until completion.
1340 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1342 struct net_device *dev = sky2->netdev;
1343 struct pci_dev *pdev = sky2->hw->pdev;
1347 BUG_ON(done >= TX_RING_SIZE);
1349 if (unlikely(netif_msg_tx_done(sky2)))
1350 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1353 for (put = sky2->tx_cons; put != done; put = nxt) {
1354 struct tx_ring_info *re = sky2->tx_ring + put;
1355 struct sk_buff *skb = re->skb;
1358 BUG_ON(nxt >= TX_RING_SIZE);
1359 prefetch(sky2->tx_ring + nxt);
1361 /* Check for partial status */
1362 if (tx_dist(put, done) < tx_dist(put, nxt))
1366 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1367 skb_headlen(skb), PCI_DMA_TODEVICE);
1369 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1370 struct tx_ring_info *fre;
1371 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
1372 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1373 skb_shinfo(skb)->frags[i].size,
1380 sky2->tx_cons = put;
1381 if (tx_avail(sky2) > MAX_SKB_TX_LE)
1382 netif_wake_queue(dev);
1385 /* Cleanup all untransmitted buffers, assume transmitter not running */
1386 static void sky2_tx_clean(struct sky2_port *sky2)
1388 spin_lock_bh(&sky2->tx_lock);
1389 sky2_tx_complete(sky2, sky2->tx_prod);
1390 spin_unlock_bh(&sky2->tx_lock);
1393 /* Network shutdown */
1394 static int sky2_down(struct net_device *dev)
1396 struct sky2_port *sky2 = netdev_priv(dev);
1397 struct sky2_hw *hw = sky2->hw;
1398 unsigned port = sky2->port;
1402 /* Never really got started! */
1406 if (netif_msg_ifdown(sky2))
1407 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1409 /* Stop more packets from being queued */
1410 netif_stop_queue(dev);
1412 sky2_phy_reset(hw, port);
1414 /* Stop transmitter */
1415 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1416 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1418 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1419 RB_RST_SET | RB_DIS_OP_MD);
1421 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1422 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1423 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1425 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1427 /* Workaround shared GMAC reset */
1428 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1429 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1430 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1432 /* Disable Force Sync bit and Enable Alloc bit */
1433 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1434 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1436 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1437 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1438 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1440 /* Reset the PCI FIFO of the async Tx queue */
1441 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1442 BMU_RST_SET | BMU_FIFO_RST);
1444 /* Reset the Tx prefetch units */
1445 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1448 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1452 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1453 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1455 /* Disable port IRQ */
1456 imask = sky2_read32(hw, B0_IMSK);
1457 imask &= ~portirq_msk[port];
1458 sky2_write32(hw, B0_IMSK, imask);
1460 /* turn off LED's */
1461 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1463 synchronize_irq(hw->pdev->irq);
1465 sky2_tx_clean(sky2);
1466 sky2_rx_clean(sky2);
1468 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1469 sky2->rx_le, sky2->rx_le_map);
1470 kfree(sky2->rx_ring);
1472 pci_free_consistent(hw->pdev,
1473 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1474 sky2->tx_le, sky2->tx_le_map);
1475 kfree(sky2->tx_ring);
1480 sky2->rx_ring = NULL;
1481 sky2->tx_ring = NULL;
1486 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1491 if (hw->chip_id == CHIP_ID_YUKON_FE)
1492 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1494 switch (aux & PHY_M_PS_SPEED_MSK) {
1495 case PHY_M_PS_SPEED_1000:
1497 case PHY_M_PS_SPEED_100:
1504 static void sky2_link_up(struct sky2_port *sky2)
1506 struct sky2_hw *hw = sky2->hw;
1507 unsigned port = sky2->port;
1510 /* Enable Transmit FIFO Underrun */
1511 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1513 reg = gma_read16(hw, port, GM_GP_CTRL);
1514 if (sky2->autoneg == AUTONEG_DISABLE) {
1515 reg |= GM_GPCR_AU_ALL_DIS;
1517 /* Is write/read necessary? Copied from sky2_mac_init */
1518 gma_write16(hw, port, GM_GP_CTRL, reg);
1519 gma_read16(hw, port, GM_GP_CTRL);
1521 switch (sky2->speed) {
1523 reg &= ~GM_GPCR_SPEED_100;
1524 reg |= GM_GPCR_SPEED_1000;
1527 reg &= ~GM_GPCR_SPEED_1000;
1528 reg |= GM_GPCR_SPEED_100;
1531 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1535 reg &= ~GM_GPCR_AU_ALL_DIS;
1537 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1538 reg |= GM_GPCR_DUP_FULL;
1541 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1542 gma_write16(hw, port, GM_GP_CTRL, reg);
1543 gma_read16(hw, port, GM_GP_CTRL);
1545 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1547 netif_carrier_on(sky2->netdev);
1548 netif_wake_queue(sky2->netdev);
1550 /* Turn on link LED */
1551 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1552 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1554 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1555 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1556 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1558 switch(sky2->speed) {
1560 led |= PHY_M_LEDC_INIT_CTRL(7);
1564 led |= PHY_M_LEDC_STA1_CTRL(7);
1568 led |= PHY_M_LEDC_STA0_CTRL(7);
1572 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1573 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1574 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1577 if (netif_msg_link(sky2))
1578 printk(KERN_INFO PFX
1579 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1580 sky2->netdev->name, sky2->speed,
1581 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1582 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1583 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1586 static void sky2_link_down(struct sky2_port *sky2)
1588 struct sky2_hw *hw = sky2->hw;
1589 unsigned port = sky2->port;
1592 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1594 reg = gma_read16(hw, port, GM_GP_CTRL);
1595 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1596 gma_write16(hw, port, GM_GP_CTRL, reg);
1597 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1599 if (sky2->rx_pause && !sky2->tx_pause) {
1600 /* restore Asymmetric Pause bit */
1601 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1602 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1606 netif_carrier_off(sky2->netdev);
1607 netif_stop_queue(sky2->netdev);
1609 /* Turn on link LED */
1610 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1612 if (netif_msg_link(sky2))
1613 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1614 sky2_phy_init(hw, port);
1617 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1619 struct sky2_hw *hw = sky2->hw;
1620 unsigned port = sky2->port;
1623 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1625 if (lpa & PHY_M_AN_RF) {
1626 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1630 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1631 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1632 printk(KERN_ERR PFX "%s: master/slave fault",
1633 sky2->netdev->name);
1637 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1638 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1639 sky2->netdev->name);
1643 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1645 sky2->speed = sky2_phy_speed(hw, aux);
1647 /* Pause bits are offset (9..8) */
1648 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1651 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1652 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1654 if ((sky2->tx_pause || sky2->rx_pause)
1655 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1656 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1658 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1663 /* Interrupt from PHY */
1664 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1666 struct net_device *dev = hw->dev[port];
1667 struct sky2_port *sky2 = netdev_priv(dev);
1668 u16 istatus, phystat;
1670 spin_lock(&sky2->phy_lock);
1671 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1672 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1674 if (!netif_running(dev))
1677 if (netif_msg_intr(sky2))
1678 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1679 sky2->netdev->name, istatus, phystat);
1681 if (istatus & PHY_M_IS_AN_COMPL) {
1682 if (sky2_autoneg_done(sky2, phystat) == 0)
1687 if (istatus & PHY_M_IS_LSP_CHANGE)
1688 sky2->speed = sky2_phy_speed(hw, phystat);
1690 if (istatus & PHY_M_IS_DUP_CHANGE)
1692 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1694 if (istatus & PHY_M_IS_LST_CHANGE) {
1695 if (phystat & PHY_M_PS_LINK_UP)
1698 sky2_link_down(sky2);
1701 spin_unlock(&sky2->phy_lock);
1705 /* Transmit timeout is only called if we are running, carries is up
1706 * and tx queue is full (stopped).
1708 static void sky2_tx_timeout(struct net_device *dev)
1710 struct sky2_port *sky2 = netdev_priv(dev);
1711 struct sky2_hw *hw = sky2->hw;
1712 unsigned txq = txqaddr[sky2->port];
1715 if (netif_msg_timer(sky2))
1716 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1718 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1719 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1721 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1723 sky2->tx_cons, sky2->tx_prod, report, done);
1725 if (report != done) {
1726 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1728 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1729 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1730 } else if (report != sky2->tx_cons) {
1731 printk(KERN_INFO PFX "status report lost?\n");
1733 spin_lock_bh(&sky2->tx_lock);
1734 sky2_tx_complete(sky2, report);
1735 spin_unlock_bh(&sky2->tx_lock);
1737 printk(KERN_INFO PFX "hardware hung? flushing\n");
1739 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1740 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1742 sky2_tx_clean(sky2);
1745 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1750 /* Want receive buffer size to be multiple of 64 bits
1751 * and incl room for vlan and truncation
1753 static inline unsigned sky2_buf_size(int mtu)
1755 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1758 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1760 struct sky2_port *sky2 = netdev_priv(dev);
1761 struct sky2_hw *hw = sky2->hw;
1766 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1769 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1772 if (!netif_running(dev)) {
1777 imask = sky2_read32(hw, B0_IMSK);
1778 sky2_write32(hw, B0_IMSK, 0);
1780 dev->trans_start = jiffies; /* prevent tx timeout */
1781 netif_stop_queue(dev);
1782 netif_poll_disable(hw->dev[0]);
1784 synchronize_irq(hw->pdev->irq);
1786 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1787 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1789 sky2_rx_clean(sky2);
1792 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1793 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1794 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1796 if (dev->mtu > ETH_DATA_LEN)
1797 mode |= GM_SMOD_JUMBO_ENA;
1799 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1801 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1803 err = sky2_rx_start(sky2);
1804 sky2_write32(hw, B0_IMSK, imask);
1809 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1811 netif_poll_enable(hw->dev[0]);
1812 netif_wake_queue(dev);
1819 * Receive one packet.
1820 * For small packets or errors, just reuse existing skb.
1821 * For larger packets, get new buffer.
1823 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1824 u16 length, u32 status)
1826 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1827 struct sk_buff *skb = NULL;
1829 if (unlikely(netif_msg_rx_status(sky2)))
1830 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1831 sky2->netdev->name, sky2->rx_next, status, length);
1833 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1834 prefetch(sky2->rx_ring + sky2->rx_next);
1836 if (status & GMR_FS_ANY_ERR)
1839 if (!(status & GMR_FS_RX_OK))
1842 if (length > sky2->netdev->mtu + ETH_HLEN)
1845 if (length < copybreak) {
1846 skb = alloc_skb(length + 2, GFP_ATOMIC);
1850 skb_reserve(skb, 2);
1851 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1852 length, PCI_DMA_FROMDEVICE);
1853 memcpy(skb->data, re->skb->data, length);
1854 skb->ip_summed = re->skb->ip_summed;
1855 skb->csum = re->skb->csum;
1856 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1857 length, PCI_DMA_FROMDEVICE);
1859 struct sk_buff *nskb;
1861 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1867 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1868 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1869 prefetch(skb->data);
1871 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1872 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1875 skb_put(skb, length);
1877 re->skb->ip_summed = CHECKSUM_NONE;
1878 sky2_rx_add(sky2, re->mapaddr);
1880 /* Tell receiver about new buffers. */
1881 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
1886 ++sky2->net_stats.rx_over_errors;
1890 ++sky2->net_stats.rx_errors;
1892 if (netif_msg_rx_err(sky2) && net_ratelimit())
1893 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1894 sky2->netdev->name, status, length);
1896 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1897 sky2->net_stats.rx_length_errors++;
1898 if (status & GMR_FS_FRAGMENT)
1899 sky2->net_stats.rx_frame_errors++;
1900 if (status & GMR_FS_CRC_ERR)
1901 sky2->net_stats.rx_crc_errors++;
1902 if (status & GMR_FS_RX_FF_OV)
1903 sky2->net_stats.rx_fifo_errors++;
1908 /* Transmit complete */
1909 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1911 struct sky2_port *sky2 = netdev_priv(dev);
1913 if (netif_running(dev)) {
1914 spin_lock(&sky2->tx_lock);
1915 sky2_tx_complete(sky2, last);
1916 spin_unlock(&sky2->tx_lock);
1920 /* Process status response ring */
1921 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1924 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1928 while (hw->st_idx != hwidx) {
1929 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1930 struct net_device *dev;
1931 struct sky2_port *sky2;
1932 struct sk_buff *skb;
1936 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1938 BUG_ON(le->link >= 2);
1939 dev = hw->dev[le->link];
1941 sky2 = netdev_priv(dev);
1942 length = le->length;
1943 status = le->status;
1945 switch (le->opcode & ~HW_OWNER) {
1947 skb = sky2_receive(sky2, length, status);
1952 skb->protocol = eth_type_trans(skb, dev);
1953 dev->last_rx = jiffies;
1955 #ifdef SKY2_VLAN_TAG_USED
1956 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1957 vlan_hwaccel_receive_skb(skb,
1959 be16_to_cpu(sky2->rx_tag));
1962 netif_receive_skb(skb);
1964 if (++work_done >= to_do)
1968 #ifdef SKY2_VLAN_TAG_USED
1970 sky2->rx_tag = length;
1974 sky2->rx_tag = length;
1978 skb = sky2->rx_ring[sky2->rx_next].skb;
1979 skb->ip_summed = CHECKSUM_HW;
1980 skb->csum = le16_to_cpu(status);
1984 /* TX index reports status for both ports */
1985 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
1986 sky2_tx_done(hw->dev[0], status & 0xfff);
1988 sky2_tx_done(hw->dev[1],
1989 ((status >> 24) & 0xff)
1990 | (u16)(length & 0xf) << 8);
1994 if (net_ratelimit())
1995 printk(KERN_WARNING PFX
1996 "unknown status opcode 0x%x\n", le->opcode);
2005 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2007 struct net_device *dev = hw->dev[port];
2009 if (net_ratelimit())
2010 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2013 if (status & Y2_IS_PAR_RD1) {
2014 if (net_ratelimit())
2015 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2018 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2021 if (status & Y2_IS_PAR_WR1) {
2022 if (net_ratelimit())
2023 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2026 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2029 if (status & Y2_IS_PAR_MAC1) {
2030 if (net_ratelimit())
2031 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2032 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2035 if (status & Y2_IS_PAR_RX1) {
2036 if (net_ratelimit())
2037 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2038 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2041 if (status & Y2_IS_TCP_TXA1) {
2042 if (net_ratelimit())
2043 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2045 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2049 static void sky2_hw_intr(struct sky2_hw *hw)
2051 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2053 if (status & Y2_IS_TIST_OV)
2054 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2056 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2059 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2060 if (net_ratelimit())
2061 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2062 pci_name(hw->pdev), pci_err);
2064 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2065 sky2_pci_write16(hw, PCI_STATUS,
2066 pci_err | PCI_STATUS_ERROR_BITS);
2067 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2070 if (status & Y2_IS_PCI_EXP) {
2071 /* PCI-Express uncorrectable Error occurred */
2074 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2076 if (net_ratelimit())
2077 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2078 pci_name(hw->pdev), pex_err);
2080 /* clear the interrupt */
2081 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2082 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2084 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2086 if (pex_err & PEX_FATAL_ERRORS) {
2087 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2088 hwmsk &= ~Y2_IS_PCI_EXP;
2089 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2093 if (status & Y2_HWE_L1_MASK)
2094 sky2_hw_error(hw, 0, status);
2096 if (status & Y2_HWE_L1_MASK)
2097 sky2_hw_error(hw, 1, status);
2100 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2102 struct net_device *dev = hw->dev[port];
2103 struct sky2_port *sky2 = netdev_priv(dev);
2104 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2106 if (netif_msg_intr(sky2))
2107 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2110 if (status & GM_IS_RX_FF_OR) {
2111 ++sky2->net_stats.rx_fifo_errors;
2112 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2115 if (status & GM_IS_TX_FF_UR) {
2116 ++sky2->net_stats.tx_fifo_errors;
2117 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2121 /* This should never happen it is a fatal situation */
2122 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2123 const char *rxtx, u32 mask)
2125 struct net_device *dev = hw->dev[port];
2126 struct sky2_port *sky2 = netdev_priv(dev);
2129 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2130 dev ? dev->name : "<not registered>", rxtx);
2132 imask = sky2_read32(hw, B0_IMSK);
2134 sky2_write32(hw, B0_IMSK, imask);
2137 spin_lock(&sky2->phy_lock);
2138 sky2_link_down(sky2);
2139 spin_unlock(&sky2->phy_lock);
2143 /* If idle then force a fake soft NAPI poll once a second
2144 * to work around cases where sharing an edge triggered interrupt.
2146 static void sky2_idle(unsigned long arg)
2148 struct sky2_hw *hw = (struct sky2_hw *) arg;
2149 struct net_device *dev = hw->dev[0];
2151 if (__netif_rx_schedule_prep(dev))
2152 __netif_rx_schedule(dev);
2154 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2158 static int sky2_poll(struct net_device *dev0, int *budget)
2160 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2161 int work_limit = min(dev0->quota, *budget);
2163 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2165 if (status & Y2_IS_HW_ERR)
2168 if (status & Y2_IS_IRQ_PHY1)
2169 sky2_phy_intr(hw, 0);
2171 if (status & Y2_IS_IRQ_PHY2)
2172 sky2_phy_intr(hw, 1);
2174 if (status & Y2_IS_IRQ_MAC1)
2175 sky2_mac_intr(hw, 0);
2177 if (status & Y2_IS_IRQ_MAC2)
2178 sky2_mac_intr(hw, 1);
2180 if (status & Y2_IS_CHK_RX1)
2181 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2183 if (status & Y2_IS_CHK_RX2)
2184 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2186 if (status & Y2_IS_CHK_TXA1)
2187 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2189 if (status & Y2_IS_CHK_TXA2)
2190 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2192 if (status & Y2_IS_STAT_BMU)
2193 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2195 work_done = sky2_status_intr(hw, work_limit);
2196 *budget -= work_done;
2197 dev0->quota -= work_done;
2199 if (work_done >= work_limit)
2202 netif_rx_complete(dev0);
2204 status = sky2_read32(hw, B0_Y2_SP_LISR);
2208 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2210 struct sky2_hw *hw = dev_id;
2211 struct net_device *dev0 = hw->dev[0];
2214 /* Reading this mask interrupts as side effect */
2215 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2216 if (status == 0 || status == ~0)
2219 prefetch(&hw->st_le[hw->st_idx]);
2220 if (likely(__netif_rx_schedule_prep(dev0)))
2221 __netif_rx_schedule(dev0);
2226 #ifdef CONFIG_NET_POLL_CONTROLLER
2227 static void sky2_netpoll(struct net_device *dev)
2229 struct sky2_port *sky2 = netdev_priv(dev);
2231 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2235 /* Chip internal frequency for clock calculations */
2236 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2238 switch (hw->chip_id) {
2239 case CHIP_ID_YUKON_EC:
2240 case CHIP_ID_YUKON_EC_U:
2241 return 125; /* 125 Mhz */
2242 case CHIP_ID_YUKON_FE:
2243 return 100; /* 100 Mhz */
2244 default: /* YUKON_XL */
2245 return 156; /* 156 Mhz */
2249 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2251 return sky2_mhz(hw) * us;
2254 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2256 return clk / sky2_mhz(hw);
2260 static int __devinit sky2_reset(struct sky2_hw *hw)
2266 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2268 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2269 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2270 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2271 pci_name(hw->pdev), hw->chip_id);
2275 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2277 /* This rev is really old, and requires untested workarounds */
2278 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2279 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2280 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2281 hw->chip_id, hw->chip_rev);
2286 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2287 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2288 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2292 sky2_write8(hw, B0_CTST, CS_RST_SET);
2293 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2295 /* clear PCI errors, if any */
2296 status = sky2_pci_read16(hw, PCI_STATUS);
2298 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2299 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2302 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2304 /* clear any PEX errors */
2305 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2306 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2309 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2310 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2313 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2314 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2315 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2319 sky2_set_power_state(hw, PCI_D0);
2321 for (i = 0; i < hw->ports; i++) {
2322 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2323 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2326 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2328 /* Clear I2C IRQ noise */
2329 sky2_write32(hw, B2_I2C_IRQ, 1);
2331 /* turn off hardware timer (unused) */
2332 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2333 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2335 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2337 /* Turn off descriptor polling */
2338 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2340 /* Turn off receive timestamp */
2341 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2342 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2344 /* enable the Tx Arbiters */
2345 for (i = 0; i < hw->ports; i++)
2346 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2348 /* Initialize ram interface */
2349 for (i = 0; i < hw->ports; i++) {
2350 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2352 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2353 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2354 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2355 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2356 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2357 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2358 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2359 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2360 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2361 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2362 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2363 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2366 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2368 for (i = 0; i < hw->ports; i++)
2369 sky2_phy_reset(hw, i);
2371 memset(hw->st_le, 0, STATUS_LE_BYTES);
2374 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2375 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2377 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2378 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2380 /* Set the list last index */
2381 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2383 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2384 sky2_write8(hw, STAT_FIFO_WM, 16);
2386 /* set Status-FIFO ISR watermark */
2387 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2388 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2390 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2392 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2393 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2394 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2396 /* enable status unit */
2397 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2399 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2400 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2401 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2406 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2410 modes = SUPPORTED_10baseT_Half
2411 | SUPPORTED_10baseT_Full
2412 | SUPPORTED_100baseT_Half
2413 | SUPPORTED_100baseT_Full
2414 | SUPPORTED_Autoneg | SUPPORTED_TP;
2416 if (hw->chip_id != CHIP_ID_YUKON_FE)
2417 modes |= SUPPORTED_1000baseT_Half
2418 | SUPPORTED_1000baseT_Full;
2420 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2421 | SUPPORTED_Autoneg;
2425 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2427 struct sky2_port *sky2 = netdev_priv(dev);
2428 struct sky2_hw *hw = sky2->hw;
2430 ecmd->transceiver = XCVR_INTERNAL;
2431 ecmd->supported = sky2_supported_modes(hw);
2432 ecmd->phy_address = PHY_ADDR_MARV;
2434 ecmd->supported = SUPPORTED_10baseT_Half
2435 | SUPPORTED_10baseT_Full
2436 | SUPPORTED_100baseT_Half
2437 | SUPPORTED_100baseT_Full
2438 | SUPPORTED_1000baseT_Half
2439 | SUPPORTED_1000baseT_Full
2440 | SUPPORTED_Autoneg | SUPPORTED_TP;
2441 ecmd->port = PORT_TP;
2443 ecmd->port = PORT_FIBRE;
2445 ecmd->advertising = sky2->advertising;
2446 ecmd->autoneg = sky2->autoneg;
2447 ecmd->speed = sky2->speed;
2448 ecmd->duplex = sky2->duplex;
2452 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2454 struct sky2_port *sky2 = netdev_priv(dev);
2455 const struct sky2_hw *hw = sky2->hw;
2456 u32 supported = sky2_supported_modes(hw);
2458 if (ecmd->autoneg == AUTONEG_ENABLE) {
2459 ecmd->advertising = supported;
2465 switch (ecmd->speed) {
2467 if (ecmd->duplex == DUPLEX_FULL)
2468 setting = SUPPORTED_1000baseT_Full;
2469 else if (ecmd->duplex == DUPLEX_HALF)
2470 setting = SUPPORTED_1000baseT_Half;
2475 if (ecmd->duplex == DUPLEX_FULL)
2476 setting = SUPPORTED_100baseT_Full;
2477 else if (ecmd->duplex == DUPLEX_HALF)
2478 setting = SUPPORTED_100baseT_Half;
2484 if (ecmd->duplex == DUPLEX_FULL)
2485 setting = SUPPORTED_10baseT_Full;
2486 else if (ecmd->duplex == DUPLEX_HALF)
2487 setting = SUPPORTED_10baseT_Half;
2495 if ((setting & supported) == 0)
2498 sky2->speed = ecmd->speed;
2499 sky2->duplex = ecmd->duplex;
2502 sky2->autoneg = ecmd->autoneg;
2503 sky2->advertising = ecmd->advertising;
2505 if (netif_running(dev))
2506 sky2_phy_reinit(sky2);
2511 static void sky2_get_drvinfo(struct net_device *dev,
2512 struct ethtool_drvinfo *info)
2514 struct sky2_port *sky2 = netdev_priv(dev);
2516 strcpy(info->driver, DRV_NAME);
2517 strcpy(info->version, DRV_VERSION);
2518 strcpy(info->fw_version, "N/A");
2519 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2522 static const struct sky2_stat {
2523 char name[ETH_GSTRING_LEN];
2526 { "tx_bytes", GM_TXO_OK_HI },
2527 { "rx_bytes", GM_RXO_OK_HI },
2528 { "tx_broadcast", GM_TXF_BC_OK },
2529 { "rx_broadcast", GM_RXF_BC_OK },
2530 { "tx_multicast", GM_TXF_MC_OK },
2531 { "rx_multicast", GM_RXF_MC_OK },
2532 { "tx_unicast", GM_TXF_UC_OK },
2533 { "rx_unicast", GM_RXF_UC_OK },
2534 { "tx_mac_pause", GM_TXF_MPAUSE },
2535 { "rx_mac_pause", GM_RXF_MPAUSE },
2536 { "collisions", GM_TXF_COL },
2537 { "late_collision",GM_TXF_LAT_COL },
2538 { "aborted", GM_TXF_ABO_COL },
2539 { "single_collisions", GM_TXF_SNG_COL },
2540 { "multi_collisions", GM_TXF_MUL_COL },
2542 { "rx_short", GM_RXF_SHT },
2543 { "rx_runt", GM_RXE_FRAG },
2544 { "rx_64_byte_packets", GM_RXF_64B },
2545 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2546 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2547 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2548 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2549 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2550 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2551 { "rx_too_long", GM_RXF_LNG_ERR },
2552 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2553 { "rx_jabber", GM_RXF_JAB_PKT },
2554 { "rx_fcs_error", GM_RXF_FCS_ERR },
2556 { "tx_64_byte_packets", GM_TXF_64B },
2557 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2558 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2559 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2560 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2561 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2562 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2563 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2566 static u32 sky2_get_rx_csum(struct net_device *dev)
2568 struct sky2_port *sky2 = netdev_priv(dev);
2570 return sky2->rx_csum;
2573 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2575 struct sky2_port *sky2 = netdev_priv(dev);
2577 sky2->rx_csum = data;
2579 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2580 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2585 static u32 sky2_get_msglevel(struct net_device *netdev)
2587 struct sky2_port *sky2 = netdev_priv(netdev);
2588 return sky2->msg_enable;
2591 static int sky2_nway_reset(struct net_device *dev)
2593 struct sky2_port *sky2 = netdev_priv(dev);
2595 if (sky2->autoneg != AUTONEG_ENABLE)
2598 sky2_phy_reinit(sky2);
2603 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2605 struct sky2_hw *hw = sky2->hw;
2606 unsigned port = sky2->port;
2609 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2610 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2611 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2612 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2614 for (i = 2; i < count; i++)
2615 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2618 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2620 struct sky2_port *sky2 = netdev_priv(netdev);
2621 sky2->msg_enable = value;
2624 static int sky2_get_stats_count(struct net_device *dev)
2626 return ARRAY_SIZE(sky2_stats);
2629 static void sky2_get_ethtool_stats(struct net_device *dev,
2630 struct ethtool_stats *stats, u64 * data)
2632 struct sky2_port *sky2 = netdev_priv(dev);
2634 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2637 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2641 switch (stringset) {
2643 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2644 memcpy(data + i * ETH_GSTRING_LEN,
2645 sky2_stats[i].name, ETH_GSTRING_LEN);
2650 /* Use hardware MIB variables for critical path statistics and
2651 * transmit feedback not reported at interrupt.
2652 * Other errors are accounted for in interrupt handler.
2654 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2656 struct sky2_port *sky2 = netdev_priv(dev);
2659 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2661 sky2->net_stats.tx_bytes = data[0];
2662 sky2->net_stats.rx_bytes = data[1];
2663 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2664 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2665 sky2->net_stats.multicast = data[3] + data[5];
2666 sky2->net_stats.collisions = data[10];
2667 sky2->net_stats.tx_aborted_errors = data[12];
2669 return &sky2->net_stats;
2672 static int sky2_set_mac_address(struct net_device *dev, void *p)
2674 struct sky2_port *sky2 = netdev_priv(dev);
2675 struct sky2_hw *hw = sky2->hw;
2676 unsigned port = sky2->port;
2677 const struct sockaddr *addr = p;
2679 if (!is_valid_ether_addr(addr->sa_data))
2680 return -EADDRNOTAVAIL;
2682 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2683 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2684 dev->dev_addr, ETH_ALEN);
2685 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2686 dev->dev_addr, ETH_ALEN);
2688 /* virtual address for data */
2689 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2691 /* physical address: used for pause frames */
2692 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2697 static void sky2_set_multicast(struct net_device *dev)
2699 struct sky2_port *sky2 = netdev_priv(dev);
2700 struct sky2_hw *hw = sky2->hw;
2701 unsigned port = sky2->port;
2702 struct dev_mc_list *list = dev->mc_list;
2706 memset(filter, 0, sizeof(filter));
2708 reg = gma_read16(hw, port, GM_RX_CTRL);
2709 reg |= GM_RXCR_UCF_ENA;
2711 if (dev->flags & IFF_PROMISC) /* promiscuous */
2712 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2713 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2714 memset(filter, 0xff, sizeof(filter));
2715 else if (dev->mc_count == 0) /* no multicast */
2716 reg &= ~GM_RXCR_MCF_ENA;
2719 reg |= GM_RXCR_MCF_ENA;
2721 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2722 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2723 filter[bit / 8] |= 1 << (bit % 8);
2727 gma_write16(hw, port, GM_MC_ADDR_H1,
2728 (u16) filter[0] | ((u16) filter[1] << 8));
2729 gma_write16(hw, port, GM_MC_ADDR_H2,
2730 (u16) filter[2] | ((u16) filter[3] << 8));
2731 gma_write16(hw, port, GM_MC_ADDR_H3,
2732 (u16) filter[4] | ((u16) filter[5] << 8));
2733 gma_write16(hw, port, GM_MC_ADDR_H4,
2734 (u16) filter[6] | ((u16) filter[7] << 8));
2736 gma_write16(hw, port, GM_RX_CTRL, reg);
2739 /* Can have one global because blinking is controlled by
2740 * ethtool and that is always under RTNL mutex
2742 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2746 switch (hw->chip_id) {
2747 case CHIP_ID_YUKON_XL:
2748 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2749 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2750 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2751 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2752 PHY_M_LEDC_INIT_CTRL(7) |
2753 PHY_M_LEDC_STA1_CTRL(7) |
2754 PHY_M_LEDC_STA0_CTRL(7))
2757 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2761 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2762 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2763 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2764 PHY_M_LED_MO_10(MO_LED_ON) |
2765 PHY_M_LED_MO_100(MO_LED_ON) |
2766 PHY_M_LED_MO_1000(MO_LED_ON) |
2767 PHY_M_LED_MO_RX(MO_LED_ON)
2768 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2769 PHY_M_LED_MO_10(MO_LED_OFF) |
2770 PHY_M_LED_MO_100(MO_LED_OFF) |
2771 PHY_M_LED_MO_1000(MO_LED_OFF) |
2772 PHY_M_LED_MO_RX(MO_LED_OFF));
2777 /* blink LED's for finding board */
2778 static int sky2_phys_id(struct net_device *dev, u32 data)
2780 struct sky2_port *sky2 = netdev_priv(dev);
2781 struct sky2_hw *hw = sky2->hw;
2782 unsigned port = sky2->port;
2783 u16 ledctrl, ledover = 0;
2788 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2789 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2793 /* save initial values */
2794 spin_lock_bh(&sky2->phy_lock);
2795 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2796 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2797 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2798 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2799 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2801 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2802 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2806 while (!interrupted && ms > 0) {
2807 sky2_led(hw, port, onoff);
2810 spin_unlock_bh(&sky2->phy_lock);
2811 interrupted = msleep_interruptible(250);
2812 spin_lock_bh(&sky2->phy_lock);
2817 /* resume regularly scheduled programming */
2818 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2819 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2820 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2821 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2822 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2824 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2825 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2827 spin_unlock_bh(&sky2->phy_lock);
2832 static void sky2_get_pauseparam(struct net_device *dev,
2833 struct ethtool_pauseparam *ecmd)
2835 struct sky2_port *sky2 = netdev_priv(dev);
2837 ecmd->tx_pause = sky2->tx_pause;
2838 ecmd->rx_pause = sky2->rx_pause;
2839 ecmd->autoneg = sky2->autoneg;
2842 static int sky2_set_pauseparam(struct net_device *dev,
2843 struct ethtool_pauseparam *ecmd)
2845 struct sky2_port *sky2 = netdev_priv(dev);
2848 sky2->autoneg = ecmd->autoneg;
2849 sky2->tx_pause = ecmd->tx_pause != 0;
2850 sky2->rx_pause = ecmd->rx_pause != 0;
2852 sky2_phy_reinit(sky2);
2857 static int sky2_get_coalesce(struct net_device *dev,
2858 struct ethtool_coalesce *ecmd)
2860 struct sky2_port *sky2 = netdev_priv(dev);
2861 struct sky2_hw *hw = sky2->hw;
2863 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2864 ecmd->tx_coalesce_usecs = 0;
2866 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2867 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2869 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2871 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2872 ecmd->rx_coalesce_usecs = 0;
2874 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2875 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2877 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2879 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2880 ecmd->rx_coalesce_usecs_irq = 0;
2882 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2883 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2886 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2891 /* Note: this affect both ports */
2892 static int sky2_set_coalesce(struct net_device *dev,
2893 struct ethtool_coalesce *ecmd)
2895 struct sky2_port *sky2 = netdev_priv(dev);
2896 struct sky2_hw *hw = sky2->hw;
2897 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2899 if (ecmd->tx_coalesce_usecs > tmax ||
2900 ecmd->rx_coalesce_usecs > tmax ||
2901 ecmd->rx_coalesce_usecs_irq > tmax)
2904 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2906 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2908 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2911 if (ecmd->tx_coalesce_usecs == 0)
2912 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2914 sky2_write32(hw, STAT_TX_TIMER_INI,
2915 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2916 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2918 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2920 if (ecmd->rx_coalesce_usecs == 0)
2921 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2923 sky2_write32(hw, STAT_LEV_TIMER_INI,
2924 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2925 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2927 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2929 if (ecmd->rx_coalesce_usecs_irq == 0)
2930 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2932 sky2_write32(hw, STAT_ISR_TIMER_INI,
2933 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2934 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2936 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2940 static void sky2_get_ringparam(struct net_device *dev,
2941 struct ethtool_ringparam *ering)
2943 struct sky2_port *sky2 = netdev_priv(dev);
2945 ering->rx_max_pending = RX_MAX_PENDING;
2946 ering->rx_mini_max_pending = 0;
2947 ering->rx_jumbo_max_pending = 0;
2948 ering->tx_max_pending = TX_RING_SIZE - 1;
2950 ering->rx_pending = sky2->rx_pending;
2951 ering->rx_mini_pending = 0;
2952 ering->rx_jumbo_pending = 0;
2953 ering->tx_pending = sky2->tx_pending;
2956 static int sky2_set_ringparam(struct net_device *dev,
2957 struct ethtool_ringparam *ering)
2959 struct sky2_port *sky2 = netdev_priv(dev);
2962 if (ering->rx_pending > RX_MAX_PENDING ||
2963 ering->rx_pending < 8 ||
2964 ering->tx_pending < MAX_SKB_TX_LE ||
2965 ering->tx_pending > TX_RING_SIZE - 1)
2968 if (netif_running(dev))
2971 sky2->rx_pending = ering->rx_pending;
2972 sky2->tx_pending = ering->tx_pending;
2974 if (netif_running(dev)) {
2979 sky2_set_multicast(dev);
2985 static int sky2_get_regs_len(struct net_device *dev)
2991 * Returns copy of control register region
2992 * Note: access to the RAM address register set will cause timeouts.
2994 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2997 const struct sky2_port *sky2 = netdev_priv(dev);
2998 const void __iomem *io = sky2->hw->regs;
3000 BUG_ON(regs->len < B3_RI_WTO_R1);
3002 memset(p, 0, regs->len);
3004 memcpy_fromio(p, io, B3_RAM_ADDR);
3006 memcpy_fromio(p + B3_RI_WTO_R1,
3008 regs->len - B3_RI_WTO_R1);
3011 static struct ethtool_ops sky2_ethtool_ops = {
3012 .get_settings = sky2_get_settings,
3013 .set_settings = sky2_set_settings,
3014 .get_drvinfo = sky2_get_drvinfo,
3015 .get_msglevel = sky2_get_msglevel,
3016 .set_msglevel = sky2_set_msglevel,
3017 .nway_reset = sky2_nway_reset,
3018 .get_regs_len = sky2_get_regs_len,
3019 .get_regs = sky2_get_regs,
3020 .get_link = ethtool_op_get_link,
3021 .get_sg = ethtool_op_get_sg,
3022 .set_sg = ethtool_op_set_sg,
3023 .get_tx_csum = ethtool_op_get_tx_csum,
3024 .set_tx_csum = ethtool_op_set_tx_csum,
3025 .get_tso = ethtool_op_get_tso,
3026 .set_tso = ethtool_op_set_tso,
3027 .get_rx_csum = sky2_get_rx_csum,
3028 .set_rx_csum = sky2_set_rx_csum,
3029 .get_strings = sky2_get_strings,
3030 .get_coalesce = sky2_get_coalesce,
3031 .set_coalesce = sky2_set_coalesce,
3032 .get_ringparam = sky2_get_ringparam,
3033 .set_ringparam = sky2_set_ringparam,
3034 .get_pauseparam = sky2_get_pauseparam,
3035 .set_pauseparam = sky2_set_pauseparam,
3036 .phys_id = sky2_phys_id,
3037 .get_stats_count = sky2_get_stats_count,
3038 .get_ethtool_stats = sky2_get_ethtool_stats,
3039 .get_perm_addr = ethtool_op_get_perm_addr,
3042 /* Initialize network device */
3043 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3044 unsigned port, int highmem)
3046 struct sky2_port *sky2;
3047 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3050 printk(KERN_ERR "sky2 etherdev alloc failed");
3054 SET_MODULE_OWNER(dev);
3055 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3056 dev->irq = hw->pdev->irq;
3057 dev->open = sky2_up;
3058 dev->stop = sky2_down;
3059 dev->do_ioctl = sky2_ioctl;
3060 dev->hard_start_xmit = sky2_xmit_frame;
3061 dev->get_stats = sky2_get_stats;
3062 dev->set_multicast_list = sky2_set_multicast;
3063 dev->set_mac_address = sky2_set_mac_address;
3064 dev->change_mtu = sky2_change_mtu;
3065 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3066 dev->tx_timeout = sky2_tx_timeout;
3067 dev->watchdog_timeo = TX_WATCHDOG;
3069 dev->poll = sky2_poll;
3070 dev->weight = NAPI_WEIGHT;
3071 #ifdef CONFIG_NET_POLL_CONTROLLER
3072 dev->poll_controller = sky2_netpoll;
3075 sky2 = netdev_priv(dev);
3078 sky2->msg_enable = netif_msg_init(debug, default_msg);
3080 spin_lock_init(&sky2->tx_lock);
3081 /* Auto speed and flow control */
3082 sky2->autoneg = AUTONEG_ENABLE;
3087 sky2->advertising = sky2_supported_modes(hw);
3090 spin_lock_init(&sky2->phy_lock);
3091 sky2->tx_pending = TX_DEF_PENDING;
3092 sky2->rx_pending = RX_DEF_PENDING;
3093 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3095 hw->dev[port] = dev;
3099 dev->features |= NETIF_F_LLTX;
3100 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3101 dev->features |= NETIF_F_TSO;
3103 dev->features |= NETIF_F_HIGHDMA;
3104 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3106 #ifdef SKY2_VLAN_TAG_USED
3107 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3108 dev->vlan_rx_register = sky2_vlan_rx_register;
3109 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3112 /* read the mac address */
3113 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3114 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3116 /* device is off until link detection */
3117 netif_carrier_off(dev);
3118 netif_stop_queue(dev);
3123 static void __devinit sky2_show_addr(struct net_device *dev)
3125 const struct sky2_port *sky2 = netdev_priv(dev);
3127 if (netif_msg_probe(sky2))
3128 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3130 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3131 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3134 /* Handle software interrupt used during MSI test */
3135 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3136 struct pt_regs *regs)
3138 struct sky2_hw *hw = dev_id;
3139 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3144 if (status & Y2_IS_IRQ_SW) {
3145 hw->msi_detected = 1;
3146 wake_up(&hw->msi_wait);
3147 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3149 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3154 /* Test interrupt path by forcing a a software IRQ */
3155 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3157 struct pci_dev *pdev = hw->pdev;
3160 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3162 err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
3164 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3165 pci_name(pdev), pdev->irq);
3169 init_waitqueue_head (&hw->msi_wait);
3171 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3174 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3176 if (!hw->msi_detected) {
3177 /* MSI test failed, go back to INTx mode */
3178 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
3179 "switching to INTx mode. Please report this failure to "
3180 "the PCI maintainer and include system chipset information.\n",
3184 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3187 sky2_write32(hw, B0_IMSK, 0);
3189 free_irq(pdev->irq, hw);
3194 static int __devinit sky2_probe(struct pci_dev *pdev,
3195 const struct pci_device_id *ent)
3197 struct net_device *dev, *dev1 = NULL;
3199 int err, pm_cap, using_dac = 0;
3201 err = pci_enable_device(pdev);
3203 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3208 err = pci_request_regions(pdev, DRV_NAME);
3210 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3215 pci_set_master(pdev);
3217 /* Find power-management capability. */
3218 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3220 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3223 goto err_out_free_regions;
3226 if (sizeof(dma_addr_t) > sizeof(u32) &&
3227 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3229 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3231 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3232 "for consistent allocations\n", pci_name(pdev));
3233 goto err_out_free_regions;
3237 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3239 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3241 goto err_out_free_regions;
3246 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3248 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3250 goto err_out_free_regions;
3255 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3257 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3259 goto err_out_free_hw;
3261 hw->pm_cap = pm_cap;
3264 /* byte swap descriptors in hardware */
3268 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3269 reg |= PCI_REV_DESC;
3270 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3274 /* ring for status responses */
3275 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3278 goto err_out_iounmap;
3280 err = sky2_reset(hw);
3282 goto err_out_iounmap;
3284 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3285 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3286 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3287 hw->chip_id, hw->chip_rev);
3289 dev = sky2_init_netdev(hw, 0, using_dac);
3291 goto err_out_free_pci;
3293 err = register_netdev(dev);
3295 printk(KERN_ERR PFX "%s: cannot register net device\n",
3297 goto err_out_free_netdev;
3300 sky2_show_addr(dev);
3302 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3303 if (register_netdev(dev1) == 0)
3304 sky2_show_addr(dev1);
3306 /* Failure to register second port need not be fatal */
3307 printk(KERN_WARNING PFX
3308 "register of second port failed\n");
3314 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3315 err = sky2_test_msi(hw);
3316 if (err == -EOPNOTSUPP)
3317 pci_disable_msi(pdev);
3319 goto err_out_unregister;
3322 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3324 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3325 pci_name(pdev), pdev->irq);
3326 goto err_out_unregister;
3329 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3331 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3332 if (idle_timeout > 0)
3333 mod_timer(&hw->idle_timer,
3334 jiffies + msecs_to_jiffies(idle_timeout));
3336 pci_set_drvdata(pdev, hw);
3341 pci_disable_msi(pdev);
3343 unregister_netdev(dev1);
3346 unregister_netdev(dev);
3347 err_out_free_netdev:
3350 sky2_write8(hw, B0_CTST, CS_RST_SET);
3351 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3356 err_out_free_regions:
3357 pci_release_regions(pdev);
3358 pci_disable_device(pdev);
3363 static void __devexit sky2_remove(struct pci_dev *pdev)
3365 struct sky2_hw *hw = pci_get_drvdata(pdev);
3366 struct net_device *dev0, *dev1;
3371 del_timer_sync(&hw->idle_timer);
3373 sky2_write32(hw, B0_IMSK, 0);
3374 synchronize_irq(hw->pdev->irq);
3379 unregister_netdev(dev1);
3380 unregister_netdev(dev0);
3382 sky2_set_power_state(hw, PCI_D3hot);
3383 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3384 sky2_write8(hw, B0_CTST, CS_RST_SET);
3385 sky2_read8(hw, B0_CTST);
3387 free_irq(pdev->irq, hw);
3388 pci_disable_msi(pdev);
3389 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3390 pci_release_regions(pdev);
3391 pci_disable_device(pdev);
3399 pci_set_drvdata(pdev, NULL);
3403 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3405 struct sky2_hw *hw = pci_get_drvdata(pdev);
3408 for (i = 0; i < 2; i++) {
3409 struct net_device *dev = hw->dev[i];
3412 if (!netif_running(dev))
3416 netif_device_detach(dev);
3420 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3423 static int sky2_resume(struct pci_dev *pdev)
3425 struct sky2_hw *hw = pci_get_drvdata(pdev);
3428 pci_restore_state(pdev);
3429 pci_enable_wake(pdev, PCI_D0, 0);
3430 err = sky2_set_power_state(hw, PCI_D0);
3434 err = sky2_reset(hw);
3438 for (i = 0; i < 2; i++) {
3439 struct net_device *dev = hw->dev[i];
3440 if (dev && netif_running(dev)) {
3441 netif_device_attach(dev);
3444 printk(KERN_ERR PFX "%s: could not up: %d\n",
3456 static struct pci_driver sky2_driver = {
3458 .id_table = sky2_id_table,
3459 .probe = sky2_probe,
3460 .remove = __devexit_p(sky2_remove),
3462 .suspend = sky2_suspend,
3463 .resume = sky2_resume,
3467 static int __init sky2_init_module(void)
3469 return pci_register_driver(&sky2_driver);
3472 static void __exit sky2_cleanup_module(void)
3474 pci_unregister_driver(&sky2_driver);
3477 module_init(sky2_init_module);
3478 module_exit(sky2_cleanup_module);
3480 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3481 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3482 MODULE_LICENSE("GPL");
3483 MODULE_VERSION(DRV_VERSION);